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ARM: rockchip: fix broken build
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_mbx.c
blobb2f713ad90346093b40b515b70be4062666c6b80
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8 #include "qla_target.h"
9
10 #include <linux/delay.h>
11 #include <linux/gfp.h>
12
13
14 /*
15 * qla2x00_mailbox_command
16 * Issue mailbox command and waits for completion.
17 *
18 * Input:
19 * ha = adapter block pointer.
20 * mcp = driver internal mbx struct pointer.
21 *
22 * Output:
23 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
24 *
25 * Returns:
26 * 0 : QLA_SUCCESS = cmd performed success
27 * 1 : QLA_FUNCTION_FAILED (error encountered)
28 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
29 *
30 * Context:
31 * Kernel context.
32 */
33 static int
34 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
35 {
36 int rval, i;
37 unsigned long flags = 0;
38 device_reg_t *reg;
39 uint8_t abort_active;
40 uint8_t io_lock_on;
41 uint16_t command = 0;
42 uint16_t *iptr;
43 uint16_t __iomem *optr;
44 uint32_t cnt;
45 uint32_t mboxes;
46 uint16_t __iomem *mbx_reg;
47 unsigned long wait_time;
48 struct qla_hw_data *ha = vha->hw;
49 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
50
51
52 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
53
54 if (ha->pdev->error_state > pci_channel_io_frozen) {
55 ql_log(ql_log_warn, vha, 0x1001,
56 "error_state is greater than pci_channel_io_frozen, "
57 "exiting.\n");
58 return QLA_FUNCTION_TIMEOUT;
59 }
60
61 if (vha->device_flags & DFLG_DEV_FAILED) {
62 ql_log(ql_log_warn, vha, 0x1002,
63 "Device in failed state, exiting.\n");
64 return QLA_FUNCTION_TIMEOUT;
65 }
66
67 reg = ha->iobase;
68 io_lock_on = base_vha->flags.init_done;
69
70 rval = QLA_SUCCESS;
71 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
72
73
74 if (ha->flags.pci_channel_io_perm_failure) {
75 ql_log(ql_log_warn, vha, 0x1003,
76 "Perm failure on EEH timeout MBX, exiting.\n");
77 return QLA_FUNCTION_TIMEOUT;
78 }
79
80 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
81 /* Setting Link-Down error */
82 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
83 ql_log(ql_log_warn, vha, 0x1004,
84 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
85 return QLA_FUNCTION_TIMEOUT;
86 }
87
88 /*
89 * Wait for active mailbox commands to finish by waiting at most tov
90 * seconds. This is to serialize actual issuing of mailbox cmds during
91 * non ISP abort time.
92 */
93 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
94 /* Timeout occurred. Return error. */
95 ql_log(ql_log_warn, vha, 0x1005,
96 "Cmd access timeout, cmd=0x%x, Exiting.\n",
97 mcp->mb[0]);
98 return QLA_FUNCTION_TIMEOUT;
99 }
100
101 ha->flags.mbox_busy = 1;
102 /* Save mailbox command for debug */
103 ha->mcp = mcp;
104
105 ql_dbg(ql_dbg_mbx, vha, 0x1006,
106 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
107
108 spin_lock_irqsave(&ha->hardware_lock, flags);
109
110 /* Load mailbox registers. */
111 if (IS_P3P_TYPE(ha))
112 optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
113 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
114 optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
115 else
116 optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
117
118 iptr = mcp->mb;
119 command = mcp->mb[0];
120 mboxes = mcp->out_mb;
121
122 ql_dbg(ql_dbg_mbx, vha, 0x1111,
123 "Mailbox registers (OUT):\n");
124 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
125 if (IS_QLA2200(ha) && cnt == 8)
126 optr =
127 (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
128 if (mboxes & BIT_0) {
129 ql_dbg(ql_dbg_mbx, vha, 0x1112,
130 "mbox[%d]<-0x%04x\n", cnt, *iptr);
131 WRT_REG_WORD(optr, *iptr);
132 }
133
134 mboxes >>= 1;
135 optr++;
136 iptr++;
137 }
138
139 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
140 "I/O Address = %p.\n", optr);
141
142 /* Issue set host interrupt command to send cmd out. */
143 ha->flags.mbox_int = 0;
144 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
145
146 /* Unlock mbx registers and wait for interrupt */
147 ql_dbg(ql_dbg_mbx, vha, 0x100f,
148 "Going to unlock irq & waiting for interrupts. "
149 "jiffies=%lx.\n", jiffies);
150
151 /* Wait for mbx cmd completion until timeout */
152
153 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
154 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
155
156 if (IS_P3P_TYPE(ha)) {
157 if (RD_REG_DWORD(&reg->isp82.hint) &
158 HINT_MBX_INT_PENDING) {
159 spin_unlock_irqrestore(&ha->hardware_lock,
160 flags);
161 ha->flags.mbox_busy = 0;
162 ql_dbg(ql_dbg_mbx, vha, 0x1010,
163 "Pending mailbox timeout, exiting.\n");
164 rval = QLA_FUNCTION_TIMEOUT;
165 goto premature_exit;
166 }
167 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
168 } else if (IS_FWI2_CAPABLE(ha))
169 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
170 else
171 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
172 spin_unlock_irqrestore(&ha->hardware_lock, flags);
173
174 if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
175 mcp->tov * HZ)) {
176 ql_dbg(ql_dbg_mbx, vha, 0x117a,
177 "cmd=%x Timeout.\n", command);
178 spin_lock_irqsave(&ha->hardware_lock, flags);
179 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
180 spin_unlock_irqrestore(&ha->hardware_lock, flags);
181 }
182 } else {
183 ql_dbg(ql_dbg_mbx, vha, 0x1011,
184 "Cmd=%x Polling Mode.\n", command);
185
186 if (IS_P3P_TYPE(ha)) {
187 if (RD_REG_DWORD(&reg->isp82.hint) &
188 HINT_MBX_INT_PENDING) {
189 spin_unlock_irqrestore(&ha->hardware_lock,
190 flags);
191 ha->flags.mbox_busy = 0;
192 ql_dbg(ql_dbg_mbx, vha, 0x1012,
193 "Pending mailbox timeout, exiting.\n");
194 rval = QLA_FUNCTION_TIMEOUT;
195 goto premature_exit;
196 }
197 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
198 } else if (IS_FWI2_CAPABLE(ha))
199 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
200 else
201 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
202 spin_unlock_irqrestore(&ha->hardware_lock, flags);
203
204 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
205 while (!ha->flags.mbox_int) {
206 if (time_after(jiffies, wait_time))
207 break;
208
209 /* Check for pending interrupts. */
210 qla2x00_poll(ha->rsp_q_map[0]);
211
212 if (!ha->flags.mbox_int &&
213 !(IS_QLA2200(ha) &&
214 command == MBC_LOAD_RISC_RAM_EXTENDED))
215 msleep(10);
216 } /* while */
217 ql_dbg(ql_dbg_mbx, vha, 0x1013,
218 "Waited %d sec.\n",
219 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
220 }
221
222 /* Check whether we timed out */
223 if (ha->flags.mbox_int) {
224 uint16_t *iptr2;
225
226 ql_dbg(ql_dbg_mbx, vha, 0x1014,
227 "Cmd=%x completed.\n", command);
228
229 /* Got interrupt. Clear the flag. */
230 ha->flags.mbox_int = 0;
231 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
232
233 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
234 ha->flags.mbox_busy = 0;
235 /* Setting Link-Down error */
236 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
237 ha->mcp = NULL;
238 rval = QLA_FUNCTION_FAILED;
239 ql_log(ql_log_warn, vha, 0x1015,
240 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
241 goto premature_exit;
242 }
243
244 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
245 rval = QLA_FUNCTION_FAILED;
246
247 /* Load return mailbox registers. */
248 iptr2 = mcp->mb;
249 iptr = (uint16_t *)&ha->mailbox_out[0];
250 mboxes = mcp->in_mb;
251
252 ql_dbg(ql_dbg_mbx, vha, 0x1113,
253 "Mailbox registers (IN):\n");
254 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
255 if (mboxes & BIT_0) {
256 *iptr2 = *iptr;
257 ql_dbg(ql_dbg_mbx, vha, 0x1114,
258 "mbox[%d]->0x%04x\n", cnt, *iptr2);
259 }
260
261 mboxes >>= 1;
262 iptr2++;
263 iptr++;
264 }
265 } else {
266
267 uint16_t mb0;
268 uint32_t ictrl;
269
270 if (IS_FWI2_CAPABLE(ha)) {
271 mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
272 ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
273 } else {
274 mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
275 ictrl = RD_REG_WORD(&reg->isp.ictrl);
276 }
277 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
278 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
279 "mb[0]=0x%x\n", command, ictrl, jiffies, mb0);
280 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
281
282 /*
283 * Attempt to capture a firmware dump for further analysis
284 * of the current firmware state. We do not need to do this
285 * if we are intentionally generating a dump.
286 */
287 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
288 ha->isp_ops->fw_dump(vha, 0);
289
290 rval = QLA_FUNCTION_TIMEOUT;
291 }
292
293 ha->flags.mbox_busy = 0;
294
295 /* Clean up */
296 ha->mcp = NULL;
297
298 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
299 ql_dbg(ql_dbg_mbx, vha, 0x101a,
300 "Checking for additional resp interrupt.\n");
301
302 /* polling mode for non isp_abort commands. */
303 qla2x00_poll(ha->rsp_q_map[0]);
304 }
305
306 if (rval == QLA_FUNCTION_TIMEOUT &&
307 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
308 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
309 ha->flags.eeh_busy) {
310 /* not in dpc. schedule it for dpc to take over. */
311 ql_dbg(ql_dbg_mbx, vha, 0x101b,
312 "Timeout, schedule isp_abort_needed.\n");
313
314 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
315 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
316 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
317 if (IS_QLA82XX(ha)) {
318 ql_dbg(ql_dbg_mbx, vha, 0x112a,
319 "disabling pause transmit on port "
320 "0 & 1.\n");
321 qla82xx_wr_32(ha,
322 QLA82XX_CRB_NIU + 0x98,
323 CRB_NIU_XG_PAUSE_CTL_P0|
324 CRB_NIU_XG_PAUSE_CTL_P1);
325 }
326 ql_log(ql_log_info, base_vha, 0x101c,
327 "Mailbox cmd timeout occurred, cmd=0x%x, "
328 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
329 "abort.\n", command, mcp->mb[0],
330 ha->flags.eeh_busy);
331 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
332 qla2xxx_wake_dpc(vha);
333 }
334 } else if (!abort_active) {
335 /* call abort directly since we are in the DPC thread */
336 ql_dbg(ql_dbg_mbx, vha, 0x101d,
337 "Timeout, calling abort_isp.\n");
338
339 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
340 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
341 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
342 if (IS_QLA82XX(ha)) {
343 ql_dbg(ql_dbg_mbx, vha, 0x112b,
344 "disabling pause transmit on port "
345 "0 & 1.\n");
346 qla82xx_wr_32(ha,
347 QLA82XX_CRB_NIU + 0x98,
348 CRB_NIU_XG_PAUSE_CTL_P0|
349 CRB_NIU_XG_PAUSE_CTL_P1);
350 }
351 ql_log(ql_log_info, base_vha, 0x101e,
352 "Mailbox cmd timeout occurred, cmd=0x%x, "
353 "mb[0]=0x%x. Scheduling ISP abort ",
354 command, mcp->mb[0]);
355 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
356 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
357 /* Allow next mbx cmd to come in. */
358 complete(&ha->mbx_cmd_comp);
359 if (ha->isp_ops->abort_isp(vha)) {
360 /* Failed. retry later. */
361 set_bit(ISP_ABORT_NEEDED,
362 &vha->dpc_flags);
363 }
364 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
365 ql_dbg(ql_dbg_mbx, vha, 0x101f,
366 "Finished abort_isp.\n");
367 goto mbx_done;
368 }
369 }
370 }
371
372 premature_exit:
373 /* Allow next mbx cmd to come in. */
374 complete(&ha->mbx_cmd_comp);
375
376 mbx_done:
377 if (rval) {
378 ql_dbg(ql_dbg_disc, base_vha, 0x1020,
379 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
380 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
381
382 ql_dbg(ql_dbg_disc, vha, 0x1115,
383 "host status: 0x%x, flags:0x%lx, intr ctrl reg:0x%x, intr status:0x%x\n",
384 RD_REG_DWORD(&reg->isp24.host_status),
385 ha->fw_dump_cap_flags,
386 RD_REG_DWORD(&reg->isp24.ictrl),
387 RD_REG_DWORD(&reg->isp24.istatus));
388
389 mbx_reg = &reg->isp24.mailbox0;
390 for (i = 0; i < 6; i++)
391 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x1116,
392 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
393 } else {
394 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
395 }
396
397 return rval;
398 }
399
400 int
401 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
402 uint32_t risc_code_size)
403 {
404 int rval;
405 struct qla_hw_data *ha = vha->hw;
406 mbx_cmd_t mc;
407 mbx_cmd_t *mcp = &mc;
408
409 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
410 "Entered %s.\n", __func__);
411
412 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
413 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
414 mcp->mb[8] = MSW(risc_addr);
415 mcp->out_mb = MBX_8|MBX_0;
416 } else {
417 mcp->mb[0] = MBC_LOAD_RISC_RAM;
418 mcp->out_mb = MBX_0;
419 }
420 mcp->mb[1] = LSW(risc_addr);
421 mcp->mb[2] = MSW(req_dma);
422 mcp->mb[3] = LSW(req_dma);
423 mcp->mb[6] = MSW(MSD(req_dma));
424 mcp->mb[7] = LSW(MSD(req_dma));
425 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
426 if (IS_FWI2_CAPABLE(ha)) {
427 mcp->mb[4] = MSW(risc_code_size);
428 mcp->mb[5] = LSW(risc_code_size);
429 mcp->out_mb |= MBX_5|MBX_4;
430 } else {
431 mcp->mb[4] = LSW(risc_code_size);
432 mcp->out_mb |= MBX_4;
433 }
434
435 mcp->in_mb = MBX_0;
436 mcp->tov = MBX_TOV_SECONDS;
437 mcp->flags = 0;
438 rval = qla2x00_mailbox_command(vha, mcp);
439
440 if (rval != QLA_SUCCESS) {
441 ql_dbg(ql_dbg_mbx, vha, 0x1023,
442 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
443 } else {
444 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
445 "Done %s.\n", __func__);
446 }
447
448 return rval;
449 }
450
451 #define EXTENDED_BB_CREDITS BIT_0
452 /*
453 * qla2x00_execute_fw
454 * Start adapter firmware.
455 *
456 * Input:
457 * ha = adapter block pointer.
458 * TARGET_QUEUE_LOCK must be released.
459 * ADAPTER_STATE_LOCK must be released.
460 *
461 * Returns:
462 * qla2x00 local function return status code.
463 *
464 * Context:
465 * Kernel context.
466 */
467 int
468 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
469 {
470 int rval;
471 struct qla_hw_data *ha = vha->hw;
472 mbx_cmd_t mc;
473 mbx_cmd_t *mcp = &mc;
474
475 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
476 "Entered %s.\n", __func__);
477
478 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
479 mcp->out_mb = MBX_0;
480 mcp->in_mb = MBX_0;
481 if (IS_FWI2_CAPABLE(ha)) {
482 mcp->mb[1] = MSW(risc_addr);
483 mcp->mb[2] = LSW(risc_addr);
484 mcp->mb[3] = 0;
485 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
486 IS_QLA27XX(ha)) {
487 struct nvram_81xx *nv = ha->nvram;
488 mcp->mb[4] = (nv->enhanced_features &
489 EXTENDED_BB_CREDITS);
490 } else
491 mcp->mb[4] = 0;
492 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
493 mcp->in_mb |= MBX_1;
494 } else {
495 mcp->mb[1] = LSW(risc_addr);
496 mcp->out_mb |= MBX_1;
497 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
498 mcp->mb[2] = 0;
499 mcp->out_mb |= MBX_2;
500 }
501 }
502
503 mcp->tov = MBX_TOV_SECONDS;
504 mcp->flags = 0;
505 rval = qla2x00_mailbox_command(vha, mcp);
506
507 if (rval != QLA_SUCCESS) {
508 ql_dbg(ql_dbg_mbx, vha, 0x1026,
509 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
510 } else {
511 if (IS_FWI2_CAPABLE(ha)) {
512 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
513 "Done exchanges=%x.\n", mcp->mb[1]);
514 } else {
515 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
516 "Done %s.\n", __func__);
517 }
518 }
519
520 return rval;
521 }
522
523 /*
524 * qla2x00_get_fw_version
525 * Get firmware version.
526 *
527 * Input:
528 * ha: adapter state pointer.
529 * major: pointer for major number.
530 * minor: pointer for minor number.
531 * subminor: pointer for subminor number.
532 *
533 * Returns:
534 * qla2x00 local function return status code.
535 *
536 * Context:
537 * Kernel context.
538 */
539 int
540 qla2x00_get_fw_version(scsi_qla_host_t *vha)
541 {
542 int rval;
543 mbx_cmd_t mc;
544 mbx_cmd_t *mcp = &mc;
545 struct qla_hw_data *ha = vha->hw;
546
547 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
548 "Entered %s.\n", __func__);
549
550 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
551 mcp->out_mb = MBX_0;
552 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
553 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
554 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
555 if (IS_FWI2_CAPABLE(ha))
556 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
557 if (IS_QLA27XX(ha))
558 mcp->in_mb |= MBX_21|MBX_20|MBX_19|MBX_18;
559 mcp->flags = 0;
560 mcp->tov = MBX_TOV_SECONDS;
561 rval = qla2x00_mailbox_command(vha, mcp);
562 if (rval != QLA_SUCCESS)
563 goto failed;
564
565 /* Return mailbox data. */
566 ha->fw_major_version = mcp->mb[1];
567 ha->fw_minor_version = mcp->mb[2];
568 ha->fw_subminor_version = mcp->mb[3];
569 ha->fw_attributes = mcp->mb[6];
570 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
571 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
572 else
573 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
574 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
575 ha->mpi_version[0] = mcp->mb[10] & 0xff;
576 ha->mpi_version[1] = mcp->mb[11] >> 8;
577 ha->mpi_version[2] = mcp->mb[11] & 0xff;
578 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
579 ha->phy_version[0] = mcp->mb[8] & 0xff;
580 ha->phy_version[1] = mcp->mb[9] >> 8;
581 ha->phy_version[2] = mcp->mb[9] & 0xff;
582 }
583 if (IS_FWI2_CAPABLE(ha)) {
584 ha->fw_attributes_h = mcp->mb[15];
585 ha->fw_attributes_ext[0] = mcp->mb[16];
586 ha->fw_attributes_ext[1] = mcp->mb[17];
587 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
588 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
589 __func__, mcp->mb[15], mcp->mb[6]);
590 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
591 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
592 __func__, mcp->mb[17], mcp->mb[16]);
593 }
594 if (IS_QLA27XX(ha)) {
595 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
596 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
597 }
598
599 failed:
600 if (rval != QLA_SUCCESS) {
601 /*EMPTY*/
602 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
603 } else {
604 /*EMPTY*/
605 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
606 "Done %s.\n", __func__);
607 }
608 return rval;
609 }
610
611 /*
612 * qla2x00_get_fw_options
613 * Set firmware options.
614 *
615 * Input:
616 * ha = adapter block pointer.
617 * fwopt = pointer for firmware options.
618 *
619 * Returns:
620 * qla2x00 local function return status code.
621 *
622 * Context:
623 * Kernel context.
624 */
625 int
626 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
627 {
628 int rval;
629 mbx_cmd_t mc;
630 mbx_cmd_t *mcp = &mc;
631
632 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
633 "Entered %s.\n", __func__);
634
635 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
636 mcp->out_mb = MBX_0;
637 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
638 mcp->tov = MBX_TOV_SECONDS;
639 mcp->flags = 0;
640 rval = qla2x00_mailbox_command(vha, mcp);
641
642 if (rval != QLA_SUCCESS) {
643 /*EMPTY*/
644 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
645 } else {
646 fwopts[0] = mcp->mb[0];
647 fwopts[1] = mcp->mb[1];
648 fwopts[2] = mcp->mb[2];
649 fwopts[3] = mcp->mb[3];
650
651 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
652 "Done %s.\n", __func__);
653 }
654
655 return rval;
656 }
657
658
659 /*
660 * qla2x00_set_fw_options
661 * Set firmware options.
662 *
663 * Input:
664 * ha = adapter block pointer.
665 * fwopt = pointer for firmware options.
666 *
667 * Returns:
668 * qla2x00 local function return status code.
669 *
670 * Context:
671 * Kernel context.
672 */
673 int
674 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
675 {
676 int rval;
677 mbx_cmd_t mc;
678 mbx_cmd_t *mcp = &mc;
679
680 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
681 "Entered %s.\n", __func__);
682
683 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
684 mcp->mb[1] = fwopts[1];
685 mcp->mb[2] = fwopts[2];
686 mcp->mb[3] = fwopts[3];
687 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
688 mcp->in_mb = MBX_0;
689 if (IS_FWI2_CAPABLE(vha->hw)) {
690 mcp->in_mb |= MBX_1;
691 } else {
692 mcp->mb[10] = fwopts[10];
693 mcp->mb[11] = fwopts[11];
694 mcp->mb[12] = 0; /* Undocumented, but used */
695 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
696 }
697 mcp->tov = MBX_TOV_SECONDS;
698 mcp->flags = 0;
699 rval = qla2x00_mailbox_command(vha, mcp);
700
701 fwopts[0] = mcp->mb[0];
702
703 if (rval != QLA_SUCCESS) {
704 /*EMPTY*/
705 ql_dbg(ql_dbg_mbx, vha, 0x1030,
706 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
707 } else {
708 /*EMPTY*/
709 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
710 "Done %s.\n", __func__);
711 }
712
713 return rval;
714 }
715
716 /*
717 * qla2x00_mbx_reg_test
718 * Mailbox register wrap test.
719 *
720 * Input:
721 * ha = adapter block pointer.
722 * TARGET_QUEUE_LOCK must be released.
723 * ADAPTER_STATE_LOCK must be released.
724 *
725 * Returns:
726 * qla2x00 local function return status code.
727 *
728 * Context:
729 * Kernel context.
730 */
731 int
732 qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
733 {
734 int rval;
735 mbx_cmd_t mc;
736 mbx_cmd_t *mcp = &mc;
737
738 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
739 "Entered %s.\n", __func__);
740
741 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
742 mcp->mb[1] = 0xAAAA;
743 mcp->mb[2] = 0x5555;
744 mcp->mb[3] = 0xAA55;
745 mcp->mb[4] = 0x55AA;
746 mcp->mb[5] = 0xA5A5;
747 mcp->mb[6] = 0x5A5A;
748 mcp->mb[7] = 0x2525;
749 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
750 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
751 mcp->tov = MBX_TOV_SECONDS;
752 mcp->flags = 0;
753 rval = qla2x00_mailbox_command(vha, mcp);
754
755 if (rval == QLA_SUCCESS) {
756 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
757 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
758 rval = QLA_FUNCTION_FAILED;
759 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
760 mcp->mb[7] != 0x2525)
761 rval = QLA_FUNCTION_FAILED;
762 }
763
764 if (rval != QLA_SUCCESS) {
765 /*EMPTY*/
766 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
767 } else {
768 /*EMPTY*/
769 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
770 "Done %s.\n", __func__);
771 }
772
773 return rval;
774 }
775
776 /*
777 * qla2x00_verify_checksum
778 * Verify firmware checksum.
779 *
780 * Input:
781 * ha = adapter block pointer.
782 * TARGET_QUEUE_LOCK must be released.
783 * ADAPTER_STATE_LOCK must be released.
784 *
785 * Returns:
786 * qla2x00 local function return status code.
787 *
788 * Context:
789 * Kernel context.
790 */
791 int
792 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
793 {
794 int rval;
795 mbx_cmd_t mc;
796 mbx_cmd_t *mcp = &mc;
797
798 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
799 "Entered %s.\n", __func__);
800
801 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
802 mcp->out_mb = MBX_0;
803 mcp->in_mb = MBX_0;
804 if (IS_FWI2_CAPABLE(vha->hw)) {
805 mcp->mb[1] = MSW(risc_addr);
806 mcp->mb[2] = LSW(risc_addr);
807 mcp->out_mb |= MBX_2|MBX_1;
808 mcp->in_mb |= MBX_2|MBX_1;
809 } else {
810 mcp->mb[1] = LSW(risc_addr);
811 mcp->out_mb |= MBX_1;
812 mcp->in_mb |= MBX_1;
813 }
814
815 mcp->tov = MBX_TOV_SECONDS;
816 mcp->flags = 0;
817 rval = qla2x00_mailbox_command(vha, mcp);
818
819 if (rval != QLA_SUCCESS) {
820 ql_dbg(ql_dbg_mbx, vha, 0x1036,
821 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
822 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
823 } else {
824 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
825 "Done %s.\n", __func__);
826 }
827
828 return rval;
829 }
830
831 /*
832 * qla2x00_issue_iocb
833 * Issue IOCB using mailbox command
834 *
835 * Input:
836 * ha = adapter state pointer.
837 * buffer = buffer pointer.
838 * phys_addr = physical address of buffer.
839 * size = size of buffer.
840 * TARGET_QUEUE_LOCK must be released.
841 * ADAPTER_STATE_LOCK must be released.
842 *
843 * Returns:
844 * qla2x00 local function return status code.
845 *
846 * Context:
847 * Kernel context.
848 */
849 int
850 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
851 dma_addr_t phys_addr, size_t size, uint32_t tov)
852 {
853 int rval;
854 mbx_cmd_t mc;
855 mbx_cmd_t *mcp = &mc;
856
857 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
858 "Entered %s.\n", __func__);
859
860 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
861 mcp->mb[1] = 0;
862 mcp->mb[2] = MSW(phys_addr);
863 mcp->mb[3] = LSW(phys_addr);
864 mcp->mb[6] = MSW(MSD(phys_addr));
865 mcp->mb[7] = LSW(MSD(phys_addr));
866 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
867 mcp->in_mb = MBX_2|MBX_0;
868 mcp->tov = tov;
869 mcp->flags = 0;
870 rval = qla2x00_mailbox_command(vha, mcp);
871
872 if (rval != QLA_SUCCESS) {
873 /*EMPTY*/
874 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
875 } else {
876 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
877
878 /* Mask reserved bits. */
879 sts_entry->entry_status &=
880 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
881 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
882 "Done %s.\n", __func__);
883 }
884
885 return rval;
886 }
887
888 int
889 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
890 size_t size)
891 {
892 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
893 MBX_TOV_SECONDS);
894 }
895
896 /*
897 * qla2x00_abort_command
898 * Abort command aborts a specified IOCB.
899 *
900 * Input:
901 * ha = adapter block pointer.
902 * sp = SB structure pointer.
903 *
904 * Returns:
905 * qla2x00 local function return status code.
906 *
907 * Context:
908 * Kernel context.
909 */
910 int
911 qla2x00_abort_command(srb_t *sp)
912 {
913 unsigned long flags = 0;
914 int rval;
915 uint32_t handle = 0;
916 mbx_cmd_t mc;
917 mbx_cmd_t *mcp = &mc;
918 fc_port_t *fcport = sp->fcport;
919 scsi_qla_host_t *vha = fcport->vha;
920 struct qla_hw_data *ha = vha->hw;
921 struct req_que *req = vha->req;
922 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
923
924 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
925 "Entered %s.\n", __func__);
926
927 spin_lock_irqsave(&ha->hardware_lock, flags);
928 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
929 if (req->outstanding_cmds[handle] == sp)
930 break;
931 }
932 spin_unlock_irqrestore(&ha->hardware_lock, flags);
933
934 if (handle == req->num_outstanding_cmds) {
935 /* command not found */
936 return QLA_FUNCTION_FAILED;
937 }
938
939 mcp->mb[0] = MBC_ABORT_COMMAND;
940 if (HAS_EXTENDED_IDS(ha))
941 mcp->mb[1] = fcport->loop_id;
942 else
943 mcp->mb[1] = fcport->loop_id << 8;
944 mcp->mb[2] = (uint16_t)handle;
945 mcp->mb[3] = (uint16_t)(handle >> 16);
946 mcp->mb[6] = (uint16_t)cmd->device->lun;
947 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
948 mcp->in_mb = MBX_0;
949 mcp->tov = MBX_TOV_SECONDS;
950 mcp->flags = 0;
951 rval = qla2x00_mailbox_command(vha, mcp);
952
953 if (rval != QLA_SUCCESS) {
954 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
955 } else {
956 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
957 "Done %s.\n", __func__);
958 }
959
960 return rval;
961 }
962
963 int
964 qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag)
965 {
966 int rval, rval2;
967 mbx_cmd_t mc;
968 mbx_cmd_t *mcp = &mc;
969 scsi_qla_host_t *vha;
970 struct req_que *req;
971 struct rsp_que *rsp;
972
973 l = l;
974 vha = fcport->vha;
975
976 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
977 "Entered %s.\n", __func__);
978
979 req = vha->hw->req_q_map[0];
980 rsp = req->rsp;
981 mcp->mb[0] = MBC_ABORT_TARGET;
982 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
983 if (HAS_EXTENDED_IDS(vha->hw)) {
984 mcp->mb[1] = fcport->loop_id;
985 mcp->mb[10] = 0;
986 mcp->out_mb |= MBX_10;
987 } else {
988 mcp->mb[1] = fcport->loop_id << 8;
989 }
990 mcp->mb[2] = vha->hw->loop_reset_delay;
991 mcp->mb[9] = vha->vp_idx;
992
993 mcp->in_mb = MBX_0;
994 mcp->tov = MBX_TOV_SECONDS;
995 mcp->flags = 0;
996 rval = qla2x00_mailbox_command(vha, mcp);
997 if (rval != QLA_SUCCESS) {
998 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
999 "Failed=%x.\n", rval);
1000 }
1001
1002 /* Issue marker IOCB. */
1003 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
1004 MK_SYNC_ID);
1005 if (rval2 != QLA_SUCCESS) {
1006 ql_dbg(ql_dbg_mbx, vha, 0x1040,
1007 "Failed to issue marker IOCB (%x).\n", rval2);
1008 } else {
1009 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
1010 "Done %s.\n", __func__);
1011 }
1012
1013 return rval;
1014 }
1015
1016 int
1017 qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
1018 {
1019 int rval, rval2;
1020 mbx_cmd_t mc;
1021 mbx_cmd_t *mcp = &mc;
1022 scsi_qla_host_t *vha;
1023 struct req_que *req;
1024 struct rsp_que *rsp;
1025
1026 vha = fcport->vha;
1027
1028 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1029 "Entered %s.\n", __func__);
1030
1031 req = vha->hw->req_q_map[0];
1032 rsp = req->rsp;
1033 mcp->mb[0] = MBC_LUN_RESET;
1034 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
1035 if (HAS_EXTENDED_IDS(vha->hw))
1036 mcp->mb[1] = fcport->loop_id;
1037 else
1038 mcp->mb[1] = fcport->loop_id << 8;
1039 mcp->mb[2] = (u32)l;
1040 mcp->mb[3] = 0;
1041 mcp->mb[9] = vha->vp_idx;
1042
1043 mcp->in_mb = MBX_0;
1044 mcp->tov = MBX_TOV_SECONDS;
1045 mcp->flags = 0;
1046 rval = qla2x00_mailbox_command(vha, mcp);
1047 if (rval != QLA_SUCCESS) {
1048 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
1049 }
1050
1051 /* Issue marker IOCB. */
1052 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
1053 MK_SYNC_ID_LUN);
1054 if (rval2 != QLA_SUCCESS) {
1055 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1056 "Failed to issue marker IOCB (%x).\n", rval2);
1057 } else {
1058 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1059 "Done %s.\n", __func__);
1060 }
1061
1062 return rval;
1063 }
1064
1065 /*
1066 * qla2x00_get_adapter_id
1067 * Get adapter ID and topology.
1068 *
1069 * Input:
1070 * ha = adapter block pointer.
1071 * id = pointer for loop ID.
1072 * al_pa = pointer for AL_PA.
1073 * area = pointer for area.
1074 * domain = pointer for domain.
1075 * top = pointer for topology.
1076 * TARGET_QUEUE_LOCK must be released.
1077 * ADAPTER_STATE_LOCK must be released.
1078 *
1079 * Returns:
1080 * qla2x00 local function return status code.
1081 *
1082 * Context:
1083 * Kernel context.
1084 */
1085 int
1086 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
1087 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1088 {
1089 int rval;
1090 mbx_cmd_t mc;
1091 mbx_cmd_t *mcp = &mc;
1092
1093 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1094 "Entered %s.\n", __func__);
1095
1096 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
1097 mcp->mb[9] = vha->vp_idx;
1098 mcp->out_mb = MBX_9|MBX_0;
1099 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1100 if (IS_CNA_CAPABLE(vha->hw))
1101 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
1102 if (IS_FWI2_CAPABLE(vha->hw))
1103 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16;
1104 mcp->tov = MBX_TOV_SECONDS;
1105 mcp->flags = 0;
1106 rval = qla2x00_mailbox_command(vha, mcp);
1107 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1108 rval = QLA_COMMAND_ERROR;
1109 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1110 rval = QLA_INVALID_COMMAND;
1111
1112 /* Return data. */
1113 *id = mcp->mb[1];
1114 *al_pa = LSB(mcp->mb[2]);
1115 *area = MSB(mcp->mb[2]);
1116 *domain = LSB(mcp->mb[3]);
1117 *top = mcp->mb[6];
1118 *sw_cap = mcp->mb[7];
1119
1120 if (rval != QLA_SUCCESS) {
1121 /*EMPTY*/
1122 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1123 } else {
1124 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1125 "Done %s.\n", __func__);
1126
1127 if (IS_CNA_CAPABLE(vha->hw)) {
1128 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1129 vha->fcoe_fcf_idx = mcp->mb[10];
1130 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1131 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1132 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1133 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1134 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1135 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1136 }
1137 /* If FA-WWN supported */
1138 if (mcp->mb[7] & BIT_14) {
1139 vha->port_name[0] = MSB(mcp->mb[16]);
1140 vha->port_name[1] = LSB(mcp->mb[16]);
1141 vha->port_name[2] = MSB(mcp->mb[17]);
1142 vha->port_name[3] = LSB(mcp->mb[17]);
1143 vha->port_name[4] = MSB(mcp->mb[18]);
1144 vha->port_name[5] = LSB(mcp->mb[18]);
1145 vha->port_name[6] = MSB(mcp->mb[19]);
1146 vha->port_name[7] = LSB(mcp->mb[19]);
1147 fc_host_port_name(vha->host) =
1148 wwn_to_u64(vha->port_name);
1149 ql_dbg(ql_dbg_mbx, vha, 0x10ca,
1150 "FA-WWN acquired %016llx\n",
1151 wwn_to_u64(vha->port_name));
1152 }
1153 }
1154
1155 return rval;
1156 }
1157
1158 /*
1159 * qla2x00_get_retry_cnt
1160 * Get current firmware login retry count and delay.
1161 *
1162 * Input:
1163 * ha = adapter block pointer.
1164 * retry_cnt = pointer to login retry count.
1165 * tov = pointer to login timeout value.
1166 *
1167 * Returns:
1168 * qla2x00 local function return status code.
1169 *
1170 * Context:
1171 * Kernel context.
1172 */
1173 int
1174 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1175 uint16_t *r_a_tov)
1176 {
1177 int rval;
1178 uint16_t ratov;
1179 mbx_cmd_t mc;
1180 mbx_cmd_t *mcp = &mc;
1181
1182 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1183 "Entered %s.\n", __func__);
1184
1185 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1186 mcp->out_mb = MBX_0;
1187 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1188 mcp->tov = MBX_TOV_SECONDS;
1189 mcp->flags = 0;
1190 rval = qla2x00_mailbox_command(vha, mcp);
1191
1192 if (rval != QLA_SUCCESS) {
1193 /*EMPTY*/
1194 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1195 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1196 } else {
1197 /* Convert returned data and check our values. */
1198 *r_a_tov = mcp->mb[3] / 2;
1199 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1200 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1201 /* Update to the larger values */
1202 *retry_cnt = (uint8_t)mcp->mb[1];
1203 *tov = ratov;
1204 }
1205
1206 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
1207 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1208 }
1209
1210 return rval;
1211 }
1212
1213 /*
1214 * qla2x00_init_firmware
1215 * Initialize adapter firmware.
1216 *
1217 * Input:
1218 * ha = adapter block pointer.
1219 * dptr = Initialization control block pointer.
1220 * size = size of initialization control block.
1221 * TARGET_QUEUE_LOCK must be released.
1222 * ADAPTER_STATE_LOCK must be released.
1223 *
1224 * Returns:
1225 * qla2x00 local function return status code.
1226 *
1227 * Context:
1228 * Kernel context.
1229 */
1230 int
1231 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1232 {
1233 int rval;
1234 mbx_cmd_t mc;
1235 mbx_cmd_t *mcp = &mc;
1236 struct qla_hw_data *ha = vha->hw;
1237
1238 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1239 "Entered %s.\n", __func__);
1240
1241 if (IS_P3P_TYPE(ha) && ql2xdbwr)
1242 qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
1243 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1244
1245 if (ha->flags.npiv_supported)
1246 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1247 else
1248 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1249
1250 mcp->mb[1] = 0;
1251 mcp->mb[2] = MSW(ha->init_cb_dma);
1252 mcp->mb[3] = LSW(ha->init_cb_dma);
1253 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1254 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
1255 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1256 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
1257 mcp->mb[1] = BIT_0;
1258 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1259 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1260 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1261 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1262 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1263 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1264 }
1265 /* 1 and 2 should normally be captured. */
1266 mcp->in_mb = MBX_2|MBX_1|MBX_0;
1267 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
1268 /* mb3 is additional info about the installed SFP. */
1269 mcp->in_mb |= MBX_3;
1270 mcp->buf_size = size;
1271 mcp->flags = MBX_DMA_OUT;
1272 mcp->tov = MBX_TOV_SECONDS;
1273 rval = qla2x00_mailbox_command(vha, mcp);
1274
1275 if (rval != QLA_SUCCESS) {
1276 /*EMPTY*/
1277 ql_dbg(ql_dbg_mbx, vha, 0x104d,
1278 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
1279 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
1280 } else {
1281 /*EMPTY*/
1282 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1283 "Done %s.\n", __func__);
1284 }
1285
1286 return rval;
1287 }
1288
1289 /*
1290 * qla2x00_get_node_name_list
1291 * Issue get node name list mailbox command, kmalloc()
1292 * and return the resulting list. Caller must kfree() it!
1293 *
1294 * Input:
1295 * ha = adapter state pointer.
1296 * out_data = resulting list
1297 * out_len = length of the resulting list
1298 *
1299 * Returns:
1300 * qla2x00 local function return status code.
1301 *
1302 * Context:
1303 * Kernel context.
1304 */
1305 int
1306 qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len)
1307 {
1308 struct qla_hw_data *ha = vha->hw;
1309 struct qla_port_24xx_data *list = NULL;
1310 void *pmap;
1311 mbx_cmd_t mc;
1312 dma_addr_t pmap_dma;
1313 ulong dma_size;
1314 int rval, left;
1315
1316 left = 1;
1317 while (left > 0) {
1318 dma_size = left * sizeof(*list);
1319 pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size,
1320 &pmap_dma, GFP_KERNEL);
1321 if (!pmap) {
1322 ql_log(ql_log_warn, vha, 0x113f,
1323 "%s(%ld): DMA Alloc failed of %ld\n",
1324 __func__, vha->host_no, dma_size);
1325 rval = QLA_MEMORY_ALLOC_FAILED;
1326 goto out;
1327 }
1328
1329 mc.mb[0] = MBC_PORT_NODE_NAME_LIST;
1330 mc.mb[1] = BIT_1 | BIT_3;
1331 mc.mb[2] = MSW(pmap_dma);
1332 mc.mb[3] = LSW(pmap_dma);
1333 mc.mb[6] = MSW(MSD(pmap_dma));
1334 mc.mb[7] = LSW(MSD(pmap_dma));
1335 mc.mb[8] = dma_size;
1336 mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8;
1337 mc.in_mb = MBX_0|MBX_1;
1338 mc.tov = 30;
1339 mc.flags = MBX_DMA_IN;
1340
1341 rval = qla2x00_mailbox_command(vha, &mc);
1342 if (rval != QLA_SUCCESS) {
1343 if ((mc.mb[0] == MBS_COMMAND_ERROR) &&
1344 (mc.mb[1] == 0xA)) {
1345 left += le16_to_cpu(mc.mb[2]) /
1346 sizeof(struct qla_port_24xx_data);
1347 goto restart;
1348 }
1349 goto out_free;
1350 }
1351
1352 left = 0;
1353
1354 list = kmemdup(pmap, dma_size, GFP_KERNEL);
1355 if (!list) {
1356 ql_log(ql_log_warn, vha, 0x1140,
1357 "%s(%ld): failed to allocate node names list "
1358 "structure.\n", __func__, vha->host_no);
1359 rval = QLA_MEMORY_ALLOC_FAILED;
1360 goto out_free;
1361 }
1362
1363 restart:
1364 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
1365 }
1366
1367 *out_data = list;
1368 *out_len = dma_size;
1369
1370 out:
1371 return rval;
1372
1373 out_free:
1374 dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
1375 return rval;
1376 }
1377
1378 /*
1379 * qla2x00_get_port_database
1380 * Issue normal/enhanced get port database mailbox command
1381 * and copy device name as necessary.
1382 *
1383 * Input:
1384 * ha = adapter state pointer.
1385 * dev = structure pointer.
1386 * opt = enhanced cmd option byte.
1387 *
1388 * Returns:
1389 * qla2x00 local function return status code.
1390 *
1391 * Context:
1392 * Kernel context.
1393 */
1394 int
1395 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1396 {
1397 int rval;
1398 mbx_cmd_t mc;
1399 mbx_cmd_t *mcp = &mc;
1400 port_database_t *pd;
1401 struct port_database_24xx *pd24;
1402 dma_addr_t pd_dma;
1403 struct qla_hw_data *ha = vha->hw;
1404
1405 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1406 "Entered %s.\n", __func__);
1407
1408 pd24 = NULL;
1409 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1410 if (pd == NULL) {
1411 ql_log(ql_log_warn, vha, 0x1050,
1412 "Failed to allocate port database structure.\n");
1413 return QLA_MEMORY_ALLOC_FAILED;
1414 }
1415 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
1416
1417 mcp->mb[0] = MBC_GET_PORT_DATABASE;
1418 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1419 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1420 mcp->mb[2] = MSW(pd_dma);
1421 mcp->mb[3] = LSW(pd_dma);
1422 mcp->mb[6] = MSW(MSD(pd_dma));
1423 mcp->mb[7] = LSW(MSD(pd_dma));
1424 mcp->mb[9] = vha->vp_idx;
1425 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1426 mcp->in_mb = MBX_0;
1427 if (IS_FWI2_CAPABLE(ha)) {
1428 mcp->mb[1] = fcport->loop_id;
1429 mcp->mb[10] = opt;
1430 mcp->out_mb |= MBX_10|MBX_1;
1431 mcp->in_mb |= MBX_1;
1432 } else if (HAS_EXTENDED_IDS(ha)) {
1433 mcp->mb[1] = fcport->loop_id;
1434 mcp->mb[10] = opt;
1435 mcp->out_mb |= MBX_10|MBX_1;
1436 } else {
1437 mcp->mb[1] = fcport->loop_id << 8 | opt;
1438 mcp->out_mb |= MBX_1;
1439 }
1440 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1441 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1442 mcp->flags = MBX_DMA_IN;
1443 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1444 rval = qla2x00_mailbox_command(vha, mcp);
1445 if (rval != QLA_SUCCESS)
1446 goto gpd_error_out;
1447
1448 if (IS_FWI2_CAPABLE(ha)) {
1449 uint64_t zero = 0;
1450 pd24 = (struct port_database_24xx *) pd;
1451
1452 /* Check for logged in state. */
1453 if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
1454 pd24->last_login_state != PDS_PRLI_COMPLETE) {
1455 ql_dbg(ql_dbg_mbx, vha, 0x1051,
1456 "Unable to verify login-state (%x/%x) for "
1457 "loop_id %x.\n", pd24->current_login_state,
1458 pd24->last_login_state, fcport->loop_id);
1459 rval = QLA_FUNCTION_FAILED;
1460 goto gpd_error_out;
1461 }
1462
1463 if (fcport->loop_id == FC_NO_LOOP_ID ||
1464 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1465 memcmp(fcport->port_name, pd24->port_name, 8))) {
1466 /* We lost the device mid way. */
1467 rval = QLA_NOT_LOGGED_IN;
1468 goto gpd_error_out;
1469 }
1470
1471 /* Names are little-endian. */
1472 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1473 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1474
1475 /* Get port_id of device. */
1476 fcport->d_id.b.domain = pd24->port_id[0];
1477 fcport->d_id.b.area = pd24->port_id[1];
1478 fcport->d_id.b.al_pa = pd24->port_id[2];
1479 fcport->d_id.b.rsvd_1 = 0;
1480
1481 /* If not target must be initiator or unknown type. */
1482 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
1483 fcport->port_type = FCT_INITIATOR;
1484 else
1485 fcport->port_type = FCT_TARGET;
1486
1487 /* Passback COS information. */
1488 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
1489 FC_COS_CLASS2 : FC_COS_CLASS3;
1490
1491 if (pd24->prli_svc_param_word_3[0] & BIT_7)
1492 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1493 } else {
1494 uint64_t zero = 0;
1495
1496 /* Check for logged in state. */
1497 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
1498 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
1499 ql_dbg(ql_dbg_mbx, vha, 0x100a,
1500 "Unable to verify login-state (%x/%x) - "
1501 "portid=%02x%02x%02x.\n", pd->master_state,
1502 pd->slave_state, fcport->d_id.b.domain,
1503 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1504 rval = QLA_FUNCTION_FAILED;
1505 goto gpd_error_out;
1506 }
1507
1508 if (fcport->loop_id == FC_NO_LOOP_ID ||
1509 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1510 memcmp(fcport->port_name, pd->port_name, 8))) {
1511 /* We lost the device mid way. */
1512 rval = QLA_NOT_LOGGED_IN;
1513 goto gpd_error_out;
1514 }
1515
1516 /* Names are little-endian. */
1517 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
1518 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
1519
1520 /* Get port_id of device. */
1521 fcport->d_id.b.domain = pd->port_id[0];
1522 fcport->d_id.b.area = pd->port_id[3];
1523 fcport->d_id.b.al_pa = pd->port_id[2];
1524 fcport->d_id.b.rsvd_1 = 0;
1525
1526 /* If not target must be initiator or unknown type. */
1527 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
1528 fcport->port_type = FCT_INITIATOR;
1529 else
1530 fcport->port_type = FCT_TARGET;
1531
1532 /* Passback COS information. */
1533 fcport->supported_classes = (pd->options & BIT_4) ?
1534 FC_COS_CLASS2: FC_COS_CLASS3;
1535 }
1536
1537 gpd_error_out:
1538 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1539
1540 if (rval != QLA_SUCCESS) {
1541 ql_dbg(ql_dbg_mbx, vha, 0x1052,
1542 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
1543 mcp->mb[0], mcp->mb[1]);
1544 } else {
1545 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
1546 "Done %s.\n", __func__);
1547 }
1548
1549 return rval;
1550 }
1551
1552 /*
1553 * qla2x00_get_firmware_state
1554 * Get adapter firmware state.
1555 *
1556 * Input:
1557 * ha = adapter block pointer.
1558 * dptr = pointer for firmware state.
1559 * TARGET_QUEUE_LOCK must be released.
1560 * ADAPTER_STATE_LOCK must be released.
1561 *
1562 * Returns:
1563 * qla2x00 local function return status code.
1564 *
1565 * Context:
1566 * Kernel context.
1567 */
1568 int
1569 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1570 {
1571 int rval;
1572 mbx_cmd_t mc;
1573 mbx_cmd_t *mcp = &mc;
1574
1575 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
1576 "Entered %s.\n", __func__);
1577
1578 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
1579 mcp->out_mb = MBX_0;
1580 if (IS_FWI2_CAPABLE(vha->hw))
1581 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1582 else
1583 mcp->in_mb = MBX_1|MBX_0;
1584 mcp->tov = MBX_TOV_SECONDS;
1585 mcp->flags = 0;
1586 rval = qla2x00_mailbox_command(vha, mcp);
1587
1588 /* Return firmware states. */
1589 states[0] = mcp->mb[1];
1590 if (IS_FWI2_CAPABLE(vha->hw)) {
1591 states[1] = mcp->mb[2];
1592 states[2] = mcp->mb[3];
1593 states[3] = mcp->mb[4];
1594 states[4] = mcp->mb[5];
1595 states[5] = mcp->mb[6]; /* DPORT status */
1596 }
1597
1598 if (rval != QLA_SUCCESS) {
1599 /*EMPTY*/
1600 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1601 } else {
1602 /*EMPTY*/
1603 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
1604 "Done %s.\n", __func__);
1605 }
1606
1607 return rval;
1608 }
1609
1610 /*
1611 * qla2x00_get_port_name
1612 * Issue get port name mailbox command.
1613 * Returned name is in big endian format.
1614 *
1615 * Input:
1616 * ha = adapter block pointer.
1617 * loop_id = loop ID of device.
1618 * name = pointer for name.
1619 * TARGET_QUEUE_LOCK must be released.
1620 * ADAPTER_STATE_LOCK must be released.
1621 *
1622 * Returns:
1623 * qla2x00 local function return status code.
1624 *
1625 * Context:
1626 * Kernel context.
1627 */
1628 int
1629 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1630 uint8_t opt)
1631 {
1632 int rval;
1633 mbx_cmd_t mc;
1634 mbx_cmd_t *mcp = &mc;
1635
1636 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
1637 "Entered %s.\n", __func__);
1638
1639 mcp->mb[0] = MBC_GET_PORT_NAME;
1640 mcp->mb[9] = vha->vp_idx;
1641 mcp->out_mb = MBX_9|MBX_1|MBX_0;
1642 if (HAS_EXTENDED_IDS(vha->hw)) {
1643 mcp->mb[1] = loop_id;
1644 mcp->mb[10] = opt;
1645 mcp->out_mb |= MBX_10;
1646 } else {
1647 mcp->mb[1] = loop_id << 8 | opt;
1648 }
1649
1650 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1651 mcp->tov = MBX_TOV_SECONDS;
1652 mcp->flags = 0;
1653 rval = qla2x00_mailbox_command(vha, mcp);
1654
1655 if (rval != QLA_SUCCESS) {
1656 /*EMPTY*/
1657 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
1658 } else {
1659 if (name != NULL) {
1660 /* This function returns name in big endian. */
1661 name[0] = MSB(mcp->mb[2]);
1662 name[1] = LSB(mcp->mb[2]);
1663 name[2] = MSB(mcp->mb[3]);
1664 name[3] = LSB(mcp->mb[3]);
1665 name[4] = MSB(mcp->mb[6]);
1666 name[5] = LSB(mcp->mb[6]);
1667 name[6] = MSB(mcp->mb[7]);
1668 name[7] = LSB(mcp->mb[7]);
1669 }
1670
1671 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
1672 "Done %s.\n", __func__);
1673 }
1674
1675 return rval;
1676 }
1677
1678 /*
1679 * qla24xx_link_initialization
1680 * Issue link initialization mailbox command.
1681 *
1682 * Input:
1683 * ha = adapter block pointer.
1684 * TARGET_QUEUE_LOCK must be released.
1685 * ADAPTER_STATE_LOCK must be released.
1686 *
1687 * Returns:
1688 * qla2x00 local function return status code.
1689 *
1690 * Context:
1691 * Kernel context.
1692 */
1693 int
1694 qla24xx_link_initialize(scsi_qla_host_t *vha)
1695 {
1696 int rval;
1697 mbx_cmd_t mc;
1698 mbx_cmd_t *mcp = &mc;
1699
1700 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
1701 "Entered %s.\n", __func__);
1702
1703 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
1704 return QLA_FUNCTION_FAILED;
1705
1706 mcp->mb[0] = MBC_LINK_INITIALIZATION;
1707 mcp->mb[1] = BIT_4;
1708 if (vha->hw->operating_mode == LOOP)
1709 mcp->mb[1] |= BIT_6;
1710 else
1711 mcp->mb[1] |= BIT_5;
1712 mcp->mb[2] = 0;
1713 mcp->mb[3] = 0;
1714 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1715 mcp->in_mb = MBX_0;
1716 mcp->tov = MBX_TOV_SECONDS;
1717 mcp->flags = 0;
1718 rval = qla2x00_mailbox_command(vha, mcp);
1719
1720 if (rval != QLA_SUCCESS) {
1721 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
1722 } else {
1723 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
1724 "Done %s.\n", __func__);
1725 }
1726
1727 return rval;
1728 }
1729
1730 /*
1731 * qla2x00_lip_reset
1732 * Issue LIP reset mailbox command.
1733 *
1734 * Input:
1735 * ha = adapter block pointer.
1736 * TARGET_QUEUE_LOCK must be released.
1737 * ADAPTER_STATE_LOCK must be released.
1738 *
1739 * Returns:
1740 * qla2x00 local function return status code.
1741 *
1742 * Context:
1743 * Kernel context.
1744 */
1745 int
1746 qla2x00_lip_reset(scsi_qla_host_t *vha)
1747 {
1748 int rval;
1749 mbx_cmd_t mc;
1750 mbx_cmd_t *mcp = &mc;
1751
1752 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
1753 "Entered %s.\n", __func__);
1754
1755 if (IS_CNA_CAPABLE(vha->hw)) {
1756 /* Logout across all FCFs. */
1757 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1758 mcp->mb[1] = BIT_1;
1759 mcp->mb[2] = 0;
1760 mcp->out_mb = MBX_2|MBX_1|MBX_0;
1761 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1762 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1763 mcp->mb[1] = BIT_6;
1764 mcp->mb[2] = 0;
1765 mcp->mb[3] = vha->hw->loop_reset_delay;
1766 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1767 } else {
1768 mcp->mb[0] = MBC_LIP_RESET;
1769 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1770 if (HAS_EXTENDED_IDS(vha->hw)) {
1771 mcp->mb[1] = 0x00ff;
1772 mcp->mb[10] = 0;
1773 mcp->out_mb |= MBX_10;
1774 } else {
1775 mcp->mb[1] = 0xff00;
1776 }
1777 mcp->mb[2] = vha->hw->loop_reset_delay;
1778 mcp->mb[3] = 0;
1779 }
1780 mcp->in_mb = MBX_0;
1781 mcp->tov = MBX_TOV_SECONDS;
1782 mcp->flags = 0;
1783 rval = qla2x00_mailbox_command(vha, mcp);
1784
1785 if (rval != QLA_SUCCESS) {
1786 /*EMPTY*/
1787 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
1788 } else {
1789 /*EMPTY*/
1790 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
1791 "Done %s.\n", __func__);
1792 }
1793
1794 return rval;
1795 }
1796
1797 /*
1798 * qla2x00_send_sns
1799 * Send SNS command.
1800 *
1801 * Input:
1802 * ha = adapter block pointer.
1803 * sns = pointer for command.
1804 * cmd_size = command size.
1805 * buf_size = response/command size.
1806 * TARGET_QUEUE_LOCK must be released.
1807 * ADAPTER_STATE_LOCK must be released.
1808 *
1809 * Returns:
1810 * qla2x00 local function return status code.
1811 *
1812 * Context:
1813 * Kernel context.
1814 */
1815 int
1816 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
1817 uint16_t cmd_size, size_t buf_size)
1818 {
1819 int rval;
1820 mbx_cmd_t mc;
1821 mbx_cmd_t *mcp = &mc;
1822
1823 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
1824 "Entered %s.\n", __func__);
1825
1826 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
1827 "Retry cnt=%d ratov=%d total tov=%d.\n",
1828 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
1829
1830 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
1831 mcp->mb[1] = cmd_size;
1832 mcp->mb[2] = MSW(sns_phys_address);
1833 mcp->mb[3] = LSW(sns_phys_address);
1834 mcp->mb[6] = MSW(MSD(sns_phys_address));
1835 mcp->mb[7] = LSW(MSD(sns_phys_address));
1836 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1837 mcp->in_mb = MBX_0|MBX_1;
1838 mcp->buf_size = buf_size;
1839 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
1840 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
1841 rval = qla2x00_mailbox_command(vha, mcp);
1842
1843 if (rval != QLA_SUCCESS) {
1844 /*EMPTY*/
1845 ql_dbg(ql_dbg_mbx, vha, 0x105f,
1846 "Failed=%x mb[0]=%x mb[1]=%x.\n",
1847 rval, mcp->mb[0], mcp->mb[1]);
1848 } else {
1849 /*EMPTY*/
1850 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
1851 "Done %s.\n", __func__);
1852 }
1853
1854 return rval;
1855 }
1856
1857 int
1858 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1859 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
1860 {
1861 int rval;
1862
1863 struct logio_entry_24xx *lg;
1864 dma_addr_t lg_dma;
1865 uint32_t iop[2];
1866 struct qla_hw_data *ha = vha->hw;
1867 struct req_que *req;
1868 struct rsp_que *rsp;
1869
1870 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
1871 "Entered %s.\n", __func__);
1872
1873 if (ha->flags.cpu_affinity_enabled)
1874 req = ha->req_q_map[0];
1875 else
1876 req = vha->req;
1877 rsp = req->rsp;
1878
1879 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1880 if (lg == NULL) {
1881 ql_log(ql_log_warn, vha, 0x1062,
1882 "Failed to allocate login IOCB.\n");
1883 return QLA_MEMORY_ALLOC_FAILED;
1884 }
1885 memset(lg, 0, sizeof(struct logio_entry_24xx));
1886
1887 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
1888 lg->entry_count = 1;
1889 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1890 lg->nport_handle = cpu_to_le16(loop_id);
1891 lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
1892 if (opt & BIT_0)
1893 lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
1894 if (opt & BIT_1)
1895 lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
1896 lg->port_id[0] = al_pa;
1897 lg->port_id[1] = area;
1898 lg->port_id[2] = domain;
1899 lg->vp_index = vha->vp_idx;
1900 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
1901 (ha->r_a_tov / 10 * 2) + 2);
1902 if (rval != QLA_SUCCESS) {
1903 ql_dbg(ql_dbg_mbx, vha, 0x1063,
1904 "Failed to issue login IOCB (%x).\n", rval);
1905 } else if (lg->entry_status != 0) {
1906 ql_dbg(ql_dbg_mbx, vha, 0x1064,
1907 "Failed to complete IOCB -- error status (%x).\n",
1908 lg->entry_status);
1909 rval = QLA_FUNCTION_FAILED;
1910 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
1911 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1912 iop[1] = le32_to_cpu(lg->io_parameter[1]);
1913
1914 ql_dbg(ql_dbg_mbx, vha, 0x1065,
1915 "Failed to complete IOCB -- completion status (%x) "
1916 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1917 iop[0], iop[1]);
1918
1919 switch (iop[0]) {
1920 case LSC_SCODE_PORTID_USED:
1921 mb[0] = MBS_PORT_ID_USED;
1922 mb[1] = LSW(iop[1]);
1923 break;
1924 case LSC_SCODE_NPORT_USED:
1925 mb[0] = MBS_LOOP_ID_USED;
1926 break;
1927 case LSC_SCODE_NOLINK:
1928 case LSC_SCODE_NOIOCB:
1929 case LSC_SCODE_NOXCB:
1930 case LSC_SCODE_CMD_FAILED:
1931 case LSC_SCODE_NOFABRIC:
1932 case LSC_SCODE_FW_NOT_READY:
1933 case LSC_SCODE_NOT_LOGGED_IN:
1934 case LSC_SCODE_NOPCB:
1935 case LSC_SCODE_ELS_REJECT:
1936 case LSC_SCODE_CMD_PARAM_ERR:
1937 case LSC_SCODE_NONPORT:
1938 case LSC_SCODE_LOGGED_IN:
1939 case LSC_SCODE_NOFLOGI_ACC:
1940 default:
1941 mb[0] = MBS_COMMAND_ERROR;
1942 break;
1943 }
1944 } else {
1945 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
1946 "Done %s.\n", __func__);
1947
1948 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1949
1950 mb[0] = MBS_COMMAND_COMPLETE;
1951 mb[1] = 0;
1952 if (iop[0] & BIT_4) {
1953 if (iop[0] & BIT_8)
1954 mb[1] |= BIT_1;
1955 } else
1956 mb[1] = BIT_0;
1957
1958 /* Passback COS information. */
1959 mb[10] = 0;
1960 if (lg->io_parameter[7] || lg->io_parameter[8])
1961 mb[10] |= BIT_0; /* Class 2. */
1962 if (lg->io_parameter[9] || lg->io_parameter[10])
1963 mb[10] |= BIT_1; /* Class 3. */
1964 if (lg->io_parameter[0] & __constant_cpu_to_le32(BIT_7))
1965 mb[10] |= BIT_7; /* Confirmed Completion
1966 * Allowed
1967 */
1968 }
1969
1970 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
1971
1972 return rval;
1973 }
1974
1975 /*
1976 * qla2x00_login_fabric
1977 * Issue login fabric port mailbox command.
1978 *
1979 * Input:
1980 * ha = adapter block pointer.
1981 * loop_id = device loop ID.
1982 * domain = device domain.
1983 * area = device area.
1984 * al_pa = device AL_PA.
1985 * status = pointer for return status.
1986 * opt = command options.
1987 * TARGET_QUEUE_LOCK must be released.
1988 * ADAPTER_STATE_LOCK must be released.
1989 *
1990 * Returns:
1991 * qla2x00 local function return status code.
1992 *
1993 * Context:
1994 * Kernel context.
1995 */
1996 int
1997 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1998 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
1999 {
2000 int rval;
2001 mbx_cmd_t mc;
2002 mbx_cmd_t *mcp = &mc;
2003 struct qla_hw_data *ha = vha->hw;
2004
2005 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
2006 "Entered %s.\n", __func__);
2007
2008 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
2009 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2010 if (HAS_EXTENDED_IDS(ha)) {
2011 mcp->mb[1] = loop_id;
2012 mcp->mb[10] = opt;
2013 mcp->out_mb |= MBX_10;
2014 } else {
2015 mcp->mb[1] = (loop_id << 8) | opt;
2016 }
2017 mcp->mb[2] = domain;
2018 mcp->mb[3] = area << 8 | al_pa;
2019
2020 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
2021 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2022 mcp->flags = 0;
2023 rval = qla2x00_mailbox_command(vha, mcp);
2024
2025 /* Return mailbox statuses. */
2026 if (mb != NULL) {
2027 mb[0] = mcp->mb[0];
2028 mb[1] = mcp->mb[1];
2029 mb[2] = mcp->mb[2];
2030 mb[6] = mcp->mb[6];
2031 mb[7] = mcp->mb[7];
2032 /* COS retrieved from Get-Port-Database mailbox command. */
2033 mb[10] = 0;
2034 }
2035
2036 if (rval != QLA_SUCCESS) {
2037 /* RLU tmp code: need to change main mailbox_command function to
2038 * return ok even when the mailbox completion value is not
2039 * SUCCESS. The caller needs to be responsible to interpret
2040 * the return values of this mailbox command if we're not
2041 * to change too much of the existing code.
2042 */
2043 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
2044 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
2045 mcp->mb[0] == 0x4006)
2046 rval = QLA_SUCCESS;
2047
2048 /*EMPTY*/
2049 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2050 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2051 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
2052 } else {
2053 /*EMPTY*/
2054 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2055 "Done %s.\n", __func__);
2056 }
2057
2058 return rval;
2059 }
2060
2061 /*
2062 * qla2x00_login_local_device
2063 * Issue login loop port mailbox command.
2064 *
2065 * Input:
2066 * ha = adapter block pointer.
2067 * loop_id = device loop ID.
2068 * opt = command options.
2069 *
2070 * Returns:
2071 * Return status code.
2072 *
2073 * Context:
2074 * Kernel context.
2075 *
2076 */
2077 int
2078 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
2079 uint16_t *mb_ret, uint8_t opt)
2080 {
2081 int rval;
2082 mbx_cmd_t mc;
2083 mbx_cmd_t *mcp = &mc;
2084 struct qla_hw_data *ha = vha->hw;
2085
2086 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2087 "Entered %s.\n", __func__);
2088
2089 if (IS_FWI2_CAPABLE(ha))
2090 return qla24xx_login_fabric(vha, fcport->loop_id,
2091 fcport->d_id.b.domain, fcport->d_id.b.area,
2092 fcport->d_id.b.al_pa, mb_ret, opt);
2093
2094 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2095 if (HAS_EXTENDED_IDS(ha))
2096 mcp->mb[1] = fcport->loop_id;
2097 else
2098 mcp->mb[1] = fcport->loop_id << 8;
2099 mcp->mb[2] = opt;
2100 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2101 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2102 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2103 mcp->flags = 0;
2104 rval = qla2x00_mailbox_command(vha, mcp);
2105
2106 /* Return mailbox statuses. */
2107 if (mb_ret != NULL) {
2108 mb_ret[0] = mcp->mb[0];
2109 mb_ret[1] = mcp->mb[1];
2110 mb_ret[6] = mcp->mb[6];
2111 mb_ret[7] = mcp->mb[7];
2112 }
2113
2114 if (rval != QLA_SUCCESS) {
2115 /* AV tmp code: need to change main mailbox_command function to
2116 * return ok even when the mailbox completion value is not
2117 * SUCCESS. The caller needs to be responsible to interpret
2118 * the return values of this mailbox command if we're not
2119 * to change too much of the existing code.
2120 */
2121 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2122 rval = QLA_SUCCESS;
2123
2124 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2125 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2126 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
2127 } else {
2128 /*EMPTY*/
2129 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2130 "Done %s.\n", __func__);
2131 }
2132
2133 return (rval);
2134 }
2135
2136 int
2137 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2138 uint8_t area, uint8_t al_pa)
2139 {
2140 int rval;
2141 struct logio_entry_24xx *lg;
2142 dma_addr_t lg_dma;
2143 struct qla_hw_data *ha = vha->hw;
2144 struct req_que *req;
2145 struct rsp_que *rsp;
2146
2147 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2148 "Entered %s.\n", __func__);
2149
2150 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2151 if (lg == NULL) {
2152 ql_log(ql_log_warn, vha, 0x106e,
2153 "Failed to allocate logout IOCB.\n");
2154 return QLA_MEMORY_ALLOC_FAILED;
2155 }
2156 memset(lg, 0, sizeof(struct logio_entry_24xx));
2157
2158 if (ql2xmaxqueues > 1)
2159 req = ha->req_q_map[0];
2160 else
2161 req = vha->req;
2162 rsp = req->rsp;
2163 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2164 lg->entry_count = 1;
2165 lg->handle = MAKE_HANDLE(req->id, lg->handle);
2166 lg->nport_handle = cpu_to_le16(loop_id);
2167 lg->control_flags =
2168 __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
2169 LCF_FREE_NPORT);
2170 lg->port_id[0] = al_pa;
2171 lg->port_id[1] = area;
2172 lg->port_id[2] = domain;
2173 lg->vp_index = vha->vp_idx;
2174 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2175 (ha->r_a_tov / 10 * 2) + 2);
2176 if (rval != QLA_SUCCESS) {
2177 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2178 "Failed to issue logout IOCB (%x).\n", rval);
2179 } else if (lg->entry_status != 0) {
2180 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2181 "Failed to complete IOCB -- error status (%x).\n",
2182 lg->entry_status);
2183 rval = QLA_FUNCTION_FAILED;
2184 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
2185 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2186 "Failed to complete IOCB -- completion status (%x) "
2187 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2188 le32_to_cpu(lg->io_parameter[0]),
2189 le32_to_cpu(lg->io_parameter[1]));
2190 } else {
2191 /*EMPTY*/
2192 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2193 "Done %s.\n", __func__);
2194 }
2195
2196 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2197
2198 return rval;
2199 }
2200
2201 /*
2202 * qla2x00_fabric_logout
2203 * Issue logout fabric port mailbox command.
2204 *
2205 * Input:
2206 * ha = adapter block pointer.
2207 * loop_id = device loop ID.
2208 * TARGET_QUEUE_LOCK must be released.
2209 * ADAPTER_STATE_LOCK must be released.
2210 *
2211 * Returns:
2212 * qla2x00 local function return status code.
2213 *
2214 * Context:
2215 * Kernel context.
2216 */
2217 int
2218 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
2219 uint8_t area, uint8_t al_pa)
2220 {
2221 int rval;
2222 mbx_cmd_t mc;
2223 mbx_cmd_t *mcp = &mc;
2224
2225 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2226 "Entered %s.\n", __func__);
2227
2228 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2229 mcp->out_mb = MBX_1|MBX_0;
2230 if (HAS_EXTENDED_IDS(vha->hw)) {
2231 mcp->mb[1] = loop_id;
2232 mcp->mb[10] = 0;
2233 mcp->out_mb |= MBX_10;
2234 } else {
2235 mcp->mb[1] = loop_id << 8;
2236 }
2237
2238 mcp->in_mb = MBX_1|MBX_0;
2239 mcp->tov = MBX_TOV_SECONDS;
2240 mcp->flags = 0;
2241 rval = qla2x00_mailbox_command(vha, mcp);
2242
2243 if (rval != QLA_SUCCESS) {
2244 /*EMPTY*/
2245 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2246 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
2247 } else {
2248 /*EMPTY*/
2249 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2250 "Done %s.\n", __func__);
2251 }
2252
2253 return rval;
2254 }
2255
2256 /*
2257 * qla2x00_full_login_lip
2258 * Issue full login LIP mailbox command.
2259 *
2260 * Input:
2261 * ha = adapter block pointer.
2262 * TARGET_QUEUE_LOCK must be released.
2263 * ADAPTER_STATE_LOCK must be released.
2264 *
2265 * Returns:
2266 * qla2x00 local function return status code.
2267 *
2268 * Context:
2269 * Kernel context.
2270 */
2271 int
2272 qla2x00_full_login_lip(scsi_qla_host_t *vha)
2273 {
2274 int rval;
2275 mbx_cmd_t mc;
2276 mbx_cmd_t *mcp = &mc;
2277
2278 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2279 "Entered %s.\n", __func__);
2280
2281 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2282 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
2283 mcp->mb[2] = 0;
2284 mcp->mb[3] = 0;
2285 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2286 mcp->in_mb = MBX_0;
2287 mcp->tov = MBX_TOV_SECONDS;
2288 mcp->flags = 0;
2289 rval = qla2x00_mailbox_command(vha, mcp);
2290
2291 if (rval != QLA_SUCCESS) {
2292 /*EMPTY*/
2293 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
2294 } else {
2295 /*EMPTY*/
2296 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2297 "Done %s.\n", __func__);
2298 }
2299
2300 return rval;
2301 }
2302
2303 /*
2304 * qla2x00_get_id_list
2305 *
2306 * Input:
2307 * ha = adapter block pointer.
2308 *
2309 * Returns:
2310 * qla2x00 local function return status code.
2311 *
2312 * Context:
2313 * Kernel context.
2314 */
2315 int
2316 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
2317 uint16_t *entries)
2318 {
2319 int rval;
2320 mbx_cmd_t mc;
2321 mbx_cmd_t *mcp = &mc;
2322
2323 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2324 "Entered %s.\n", __func__);
2325
2326 if (id_list == NULL)
2327 return QLA_FUNCTION_FAILED;
2328
2329 mcp->mb[0] = MBC_GET_ID_LIST;
2330 mcp->out_mb = MBX_0;
2331 if (IS_FWI2_CAPABLE(vha->hw)) {
2332 mcp->mb[2] = MSW(id_list_dma);
2333 mcp->mb[3] = LSW(id_list_dma);
2334 mcp->mb[6] = MSW(MSD(id_list_dma));
2335 mcp->mb[7] = LSW(MSD(id_list_dma));
2336 mcp->mb[8] = 0;
2337 mcp->mb[9] = vha->vp_idx;
2338 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
2339 } else {
2340 mcp->mb[1] = MSW(id_list_dma);
2341 mcp->mb[2] = LSW(id_list_dma);
2342 mcp->mb[3] = MSW(MSD(id_list_dma));
2343 mcp->mb[6] = LSW(MSD(id_list_dma));
2344 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2345 }
2346 mcp->in_mb = MBX_1|MBX_0;
2347 mcp->tov = MBX_TOV_SECONDS;
2348 mcp->flags = 0;
2349 rval = qla2x00_mailbox_command(vha, mcp);
2350
2351 if (rval != QLA_SUCCESS) {
2352 /*EMPTY*/
2353 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
2354 } else {
2355 *entries = mcp->mb[1];
2356 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2357 "Done %s.\n", __func__);
2358 }
2359
2360 return rval;
2361 }
2362
2363 /*
2364 * qla2x00_get_resource_cnts
2365 * Get current firmware resource counts.
2366 *
2367 * Input:
2368 * ha = adapter block pointer.
2369 *
2370 * Returns:
2371 * qla2x00 local function return status code.
2372 *
2373 * Context:
2374 * Kernel context.
2375 */
2376 int
2377 qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
2378 uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
2379 uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
2380 {
2381 int rval;
2382 mbx_cmd_t mc;
2383 mbx_cmd_t *mcp = &mc;
2384
2385 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2386 "Entered %s.\n", __func__);
2387
2388 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2389 mcp->out_mb = MBX_0;
2390 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2391 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw))
2392 mcp->in_mb |= MBX_12;
2393 mcp->tov = MBX_TOV_SECONDS;
2394 mcp->flags = 0;
2395 rval = qla2x00_mailbox_command(vha, mcp);
2396
2397 if (rval != QLA_SUCCESS) {
2398 /*EMPTY*/
2399 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2400 "Failed mb[0]=%x.\n", mcp->mb[0]);
2401 } else {
2402 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
2403 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2404 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2405 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2406 mcp->mb[11], mcp->mb[12]);
2407
2408 if (cur_xchg_cnt)
2409 *cur_xchg_cnt = mcp->mb[3];
2410 if (orig_xchg_cnt)
2411 *orig_xchg_cnt = mcp->mb[6];
2412 if (cur_iocb_cnt)
2413 *cur_iocb_cnt = mcp->mb[7];
2414 if (orig_iocb_cnt)
2415 *orig_iocb_cnt = mcp->mb[10];
2416 if (vha->hw->flags.npiv_supported && max_npiv_vports)
2417 *max_npiv_vports = mcp->mb[11];
2418 if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) ||
2419 IS_QLA27XX(vha->hw)) && max_fcfs)
2420 *max_fcfs = mcp->mb[12];
2421 }
2422
2423 return (rval);
2424 }
2425
2426 /*
2427 * qla2x00_get_fcal_position_map
2428 * Get FCAL (LILP) position map using mailbox command
2429 *
2430 * Input:
2431 * ha = adapter state pointer.
2432 * pos_map = buffer pointer (can be NULL).
2433 *
2434 * Returns:
2435 * qla2x00 local function return status code.
2436 *
2437 * Context:
2438 * Kernel context.
2439 */
2440 int
2441 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
2442 {
2443 int rval;
2444 mbx_cmd_t mc;
2445 mbx_cmd_t *mcp = &mc;
2446 char *pmap;
2447 dma_addr_t pmap_dma;
2448 struct qla_hw_data *ha = vha->hw;
2449
2450 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
2451 "Entered %s.\n", __func__);
2452
2453 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
2454 if (pmap == NULL) {
2455 ql_log(ql_log_warn, vha, 0x1080,
2456 "Memory alloc failed.\n");
2457 return QLA_MEMORY_ALLOC_FAILED;
2458 }
2459 memset(pmap, 0, FCAL_MAP_SIZE);
2460
2461 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
2462 mcp->mb[2] = MSW(pmap_dma);
2463 mcp->mb[3] = LSW(pmap_dma);
2464 mcp->mb[6] = MSW(MSD(pmap_dma));
2465 mcp->mb[7] = LSW(MSD(pmap_dma));
2466 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2467 mcp->in_mb = MBX_1|MBX_0;
2468 mcp->buf_size = FCAL_MAP_SIZE;
2469 mcp->flags = MBX_DMA_IN;
2470 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2471 rval = qla2x00_mailbox_command(vha, mcp);
2472
2473 if (rval == QLA_SUCCESS) {
2474 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
2475 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
2476 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
2477 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
2478 pmap, pmap[0] + 1);
2479
2480 if (pos_map)
2481 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
2482 }
2483 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2484
2485 if (rval != QLA_SUCCESS) {
2486 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
2487 } else {
2488 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
2489 "Done %s.\n", __func__);
2490 }
2491
2492 return rval;
2493 }
2494
2495 /*
2496 * qla2x00_get_link_status
2497 *
2498 * Input:
2499 * ha = adapter block pointer.
2500 * loop_id = device loop ID.
2501 * ret_buf = pointer to link status return buffer.
2502 *
2503 * Returns:
2504 * 0 = success.
2505 * BIT_0 = mem alloc error.
2506 * BIT_1 = mailbox error.
2507 */
2508 int
2509 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
2510 struct link_statistics *stats, dma_addr_t stats_dma)
2511 {
2512 int rval;
2513 mbx_cmd_t mc;
2514 mbx_cmd_t *mcp = &mc;
2515 uint32_t *siter, *diter, dwords;
2516 struct qla_hw_data *ha = vha->hw;
2517
2518 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
2519 "Entered %s.\n", __func__);
2520
2521 mcp->mb[0] = MBC_GET_LINK_STATUS;
2522 mcp->mb[2] = MSW(stats_dma);
2523 mcp->mb[3] = LSW(stats_dma);
2524 mcp->mb[6] = MSW(MSD(stats_dma));
2525 mcp->mb[7] = LSW(MSD(stats_dma));
2526 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2527 mcp->in_mb = MBX_0;
2528 if (IS_FWI2_CAPABLE(ha)) {
2529 mcp->mb[1] = loop_id;
2530 mcp->mb[4] = 0;
2531 mcp->mb[10] = 0;
2532 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
2533 mcp->in_mb |= MBX_1;
2534 } else if (HAS_EXTENDED_IDS(ha)) {
2535 mcp->mb[1] = loop_id;
2536 mcp->mb[10] = 0;
2537 mcp->out_mb |= MBX_10|MBX_1;
2538 } else {
2539 mcp->mb[1] = loop_id << 8;
2540 mcp->out_mb |= MBX_1;
2541 }
2542 mcp->tov = MBX_TOV_SECONDS;
2543 mcp->flags = IOCTL_CMD;
2544 rval = qla2x00_mailbox_command(vha, mcp);
2545
2546 if (rval == QLA_SUCCESS) {
2547 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
2548 ql_dbg(ql_dbg_mbx, vha, 0x1085,
2549 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2550 rval = QLA_FUNCTION_FAILED;
2551 } else {
2552 /* Copy over data -- firmware data is LE. */
2553 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
2554 "Done %s.\n", __func__);
2555 dwords = offsetof(struct link_statistics, unused1) / 4;
2556 siter = diter = &stats->link_fail_cnt;
2557 while (dwords--)
2558 *diter++ = le32_to_cpu(*siter++);
2559 }
2560 } else {
2561 /* Failed. */
2562 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
2563 }
2564
2565 return rval;
2566 }
2567
2568 int
2569 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
2570 dma_addr_t stats_dma)
2571 {
2572 int rval;
2573 mbx_cmd_t mc;
2574 mbx_cmd_t *mcp = &mc;
2575 uint32_t *siter, *diter, dwords;
2576
2577 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
2578 "Entered %s.\n", __func__);
2579
2580 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
2581 mcp->mb[2] = MSW(stats_dma);
2582 mcp->mb[3] = LSW(stats_dma);
2583 mcp->mb[6] = MSW(MSD(stats_dma));
2584 mcp->mb[7] = LSW(MSD(stats_dma));
2585 mcp->mb[8] = sizeof(struct link_statistics) / 4;
2586 mcp->mb[9] = vha->vp_idx;
2587 mcp->mb[10] = 0;
2588 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2589 mcp->in_mb = MBX_2|MBX_1|MBX_0;
2590 mcp->tov = MBX_TOV_SECONDS;
2591 mcp->flags = IOCTL_CMD;
2592 rval = qla2x00_mailbox_command(vha, mcp);
2593
2594 if (rval == QLA_SUCCESS) {
2595 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
2596 ql_dbg(ql_dbg_mbx, vha, 0x1089,
2597 "Failed mb[0]=%x.\n", mcp->mb[0]);
2598 rval = QLA_FUNCTION_FAILED;
2599 } else {
2600 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
2601 "Done %s.\n", __func__);
2602 /* Copy over data -- firmware data is LE. */
2603 dwords = sizeof(struct link_statistics) / 4;
2604 siter = diter = &stats->link_fail_cnt;
2605 while (dwords--)
2606 *diter++ = le32_to_cpu(*siter++);
2607 }
2608 } else {
2609 /* Failed. */
2610 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
2611 }
2612
2613 return rval;
2614 }
2615
2616 int
2617 qla24xx_abort_command(srb_t *sp)
2618 {
2619 int rval;
2620 unsigned long flags = 0;
2621
2622 struct abort_entry_24xx *abt;
2623 dma_addr_t abt_dma;
2624 uint32_t handle;
2625 fc_port_t *fcport = sp->fcport;
2626 struct scsi_qla_host *vha = fcport->vha;
2627 struct qla_hw_data *ha = vha->hw;
2628 struct req_que *req = vha->req;
2629
2630 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
2631 "Entered %s.\n", __func__);
2632
2633 if (ql2xasynctmfenable)
2634 return qla24xx_async_abort_command(sp);
2635
2636 spin_lock_irqsave(&ha->hardware_lock, flags);
2637 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
2638 if (req->outstanding_cmds[handle] == sp)
2639 break;
2640 }
2641 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2642 if (handle == req->num_outstanding_cmds) {
2643 /* Command not found. */
2644 return QLA_FUNCTION_FAILED;
2645 }
2646
2647 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
2648 if (abt == NULL) {
2649 ql_log(ql_log_warn, vha, 0x108d,
2650 "Failed to allocate abort IOCB.\n");
2651 return QLA_MEMORY_ALLOC_FAILED;
2652 }
2653 memset(abt, 0, sizeof(struct abort_entry_24xx));
2654
2655 abt->entry_type = ABORT_IOCB_TYPE;
2656 abt->entry_count = 1;
2657 abt->handle = MAKE_HANDLE(req->id, abt->handle);
2658 abt->nport_handle = cpu_to_le16(fcport->loop_id);
2659 abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
2660 abt->port_id[0] = fcport->d_id.b.al_pa;
2661 abt->port_id[1] = fcport->d_id.b.area;
2662 abt->port_id[2] = fcport->d_id.b.domain;
2663 abt->vp_index = fcport->vha->vp_idx;
2664
2665 abt->req_que_no = cpu_to_le16(req->id);
2666
2667 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
2668 if (rval != QLA_SUCCESS) {
2669 ql_dbg(ql_dbg_mbx, vha, 0x108e,
2670 "Failed to issue IOCB (%x).\n", rval);
2671 } else if (abt->entry_status != 0) {
2672 ql_dbg(ql_dbg_mbx, vha, 0x108f,
2673 "Failed to complete IOCB -- error status (%x).\n",
2674 abt->entry_status);
2675 rval = QLA_FUNCTION_FAILED;
2676 } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
2677 ql_dbg(ql_dbg_mbx, vha, 0x1090,
2678 "Failed to complete IOCB -- completion status (%x).\n",
2679 le16_to_cpu(abt->nport_handle));
2680 if (abt->nport_handle == CS_IOCB_ERROR)
2681 rval = QLA_FUNCTION_PARAMETER_ERROR;
2682 else
2683 rval = QLA_FUNCTION_FAILED;
2684 } else {
2685 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
2686 "Done %s.\n", __func__);
2687 }
2688
2689 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
2690
2691 return rval;
2692 }
2693
2694 struct tsk_mgmt_cmd {
2695 union {
2696 struct tsk_mgmt_entry tsk;
2697 struct sts_entry_24xx sts;
2698 } p;
2699 };
2700
2701 static int
2702 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
2703 uint64_t l, int tag)
2704 {
2705 int rval, rval2;
2706 struct tsk_mgmt_cmd *tsk;
2707 struct sts_entry_24xx *sts;
2708 dma_addr_t tsk_dma;
2709 scsi_qla_host_t *vha;
2710 struct qla_hw_data *ha;
2711 struct req_que *req;
2712 struct rsp_que *rsp;
2713
2714 vha = fcport->vha;
2715 ha = vha->hw;
2716 req = vha->req;
2717
2718 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
2719 "Entered %s.\n", __func__);
2720
2721 if (ha->flags.cpu_affinity_enabled)
2722 rsp = ha->rsp_q_map[tag + 1];
2723 else
2724 rsp = req->rsp;
2725 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
2726 if (tsk == NULL) {
2727 ql_log(ql_log_warn, vha, 0x1093,
2728 "Failed to allocate task management IOCB.\n");
2729 return QLA_MEMORY_ALLOC_FAILED;
2730 }
2731 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
2732
2733 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
2734 tsk->p.tsk.entry_count = 1;
2735 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
2736 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
2737 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
2738 tsk->p.tsk.control_flags = cpu_to_le32(type);
2739 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
2740 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
2741 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
2742 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
2743 if (type == TCF_LUN_RESET) {
2744 int_to_scsilun(l, &tsk->p.tsk.lun);
2745 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
2746 sizeof(tsk->p.tsk.lun));
2747 }
2748
2749 sts = &tsk->p.sts;
2750 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
2751 if (rval != QLA_SUCCESS) {
2752 ql_dbg(ql_dbg_mbx, vha, 0x1094,
2753 "Failed to issue %s reset IOCB (%x).\n", name, rval);
2754 } else if (sts->entry_status != 0) {
2755 ql_dbg(ql_dbg_mbx, vha, 0x1095,
2756 "Failed to complete IOCB -- error status (%x).\n",
2757 sts->entry_status);
2758 rval = QLA_FUNCTION_FAILED;
2759 } else if (sts->comp_status !=
2760 __constant_cpu_to_le16(CS_COMPLETE)) {
2761 ql_dbg(ql_dbg_mbx, vha, 0x1096,
2762 "Failed to complete IOCB -- completion status (%x).\n",
2763 le16_to_cpu(sts->comp_status));
2764 rval = QLA_FUNCTION_FAILED;
2765 } else if (le16_to_cpu(sts->scsi_status) &
2766 SS_RESPONSE_INFO_LEN_VALID) {
2767 if (le32_to_cpu(sts->rsp_data_len) < 4) {
2768 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
2769 "Ignoring inconsistent data length -- not enough "
2770 "response info (%d).\n",
2771 le32_to_cpu(sts->rsp_data_len));
2772 } else if (sts->data[3]) {
2773 ql_dbg(ql_dbg_mbx, vha, 0x1098,
2774 "Failed to complete IOCB -- response (%x).\n",
2775 sts->data[3]);
2776 rval = QLA_FUNCTION_FAILED;
2777 }
2778 }
2779
2780 /* Issue marker IOCB. */
2781 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
2782 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
2783 if (rval2 != QLA_SUCCESS) {
2784 ql_dbg(ql_dbg_mbx, vha, 0x1099,
2785 "Failed to issue marker IOCB (%x).\n", rval2);
2786 } else {
2787 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
2788 "Done %s.\n", __func__);
2789 }
2790
2791 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
2792
2793 return rval;
2794 }
2795
2796 int
2797 qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag)
2798 {
2799 struct qla_hw_data *ha = fcport->vha->hw;
2800
2801 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
2802 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
2803
2804 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
2805 }
2806
2807 int
2808 qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
2809 {
2810 struct qla_hw_data *ha = fcport->vha->hw;
2811
2812 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
2813 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
2814
2815 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
2816 }
2817
2818 int
2819 qla2x00_system_error(scsi_qla_host_t *vha)
2820 {
2821 int rval;
2822 mbx_cmd_t mc;
2823 mbx_cmd_t *mcp = &mc;
2824 struct qla_hw_data *ha = vha->hw;
2825
2826 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
2827 return QLA_FUNCTION_FAILED;
2828
2829 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
2830 "Entered %s.\n", __func__);
2831
2832 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
2833 mcp->out_mb = MBX_0;
2834 mcp->in_mb = MBX_0;
2835 mcp->tov = 5;
2836 mcp->flags = 0;
2837 rval = qla2x00_mailbox_command(vha, mcp);
2838
2839 if (rval != QLA_SUCCESS) {
2840 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
2841 } else {
2842 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
2843 "Done %s.\n", __func__);
2844 }
2845
2846 return rval;
2847 }
2848
2849 int
2850 qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
2851 {
2852 int rval;
2853 mbx_cmd_t mc;
2854 mbx_cmd_t *mcp = &mc;
2855
2856 if (!IS_QLA2031(vha->hw) && !IS_QLA27XX(vha->hw))
2857 return QLA_FUNCTION_FAILED;
2858
2859 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
2860 "Entered %s.\n", __func__);
2861
2862 mcp->mb[0] = MBC_WRITE_SERDES;
2863 mcp->mb[1] = addr;
2864 if (IS_QLA2031(vha->hw))
2865 mcp->mb[2] = data & 0xff;
2866 else
2867 mcp->mb[2] = data;
2868
2869 mcp->mb[3] = 0;
2870 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2871 mcp->in_mb = MBX_0;
2872 mcp->tov = MBX_TOV_SECONDS;
2873 mcp->flags = 0;
2874 rval = qla2x00_mailbox_command(vha, mcp);
2875
2876 if (rval != QLA_SUCCESS) {
2877 ql_dbg(ql_dbg_mbx, vha, 0x1183,
2878 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2879 } else {
2880 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
2881 "Done %s.\n", __func__);
2882 }
2883
2884 return rval;
2885 }
2886
2887 int
2888 qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
2889 {
2890 int rval;
2891 mbx_cmd_t mc;
2892 mbx_cmd_t *mcp = &mc;
2893
2894 if (!IS_QLA2031(vha->hw) && !IS_QLA27XX(vha->hw))
2895 return QLA_FUNCTION_FAILED;
2896
2897 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
2898 "Entered %s.\n", __func__);
2899
2900 mcp->mb[0] = MBC_READ_SERDES;
2901 mcp->mb[1] = addr;
2902 mcp->mb[3] = 0;
2903 mcp->out_mb = MBX_3|MBX_1|MBX_0;
2904 mcp->in_mb = MBX_1|MBX_0;
2905 mcp->tov = MBX_TOV_SECONDS;
2906 mcp->flags = 0;
2907 rval = qla2x00_mailbox_command(vha, mcp);
2908
2909 if (IS_QLA2031(vha->hw))
2910 *data = mcp->mb[1] & 0xff;
2911 else
2912 *data = mcp->mb[1];
2913
2914 if (rval != QLA_SUCCESS) {
2915 ql_dbg(ql_dbg_mbx, vha, 0x1186,
2916 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2917 } else {
2918 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
2919 "Done %s.\n", __func__);
2920 }
2921
2922 return rval;
2923 }
2924
2925 int
2926 qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
2927 {
2928 int rval;
2929 mbx_cmd_t mc;
2930 mbx_cmd_t *mcp = &mc;
2931
2932 if (!IS_QLA8044(vha->hw))
2933 return QLA_FUNCTION_FAILED;
2934
2935 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1186,
2936 "Entered %s.\n", __func__);
2937
2938 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
2939 mcp->mb[1] = HCS_WRITE_SERDES;
2940 mcp->mb[3] = LSW(addr);
2941 mcp->mb[4] = MSW(addr);
2942 mcp->mb[5] = LSW(data);
2943 mcp->mb[6] = MSW(data);
2944 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0;
2945 mcp->in_mb = MBX_0;
2946 mcp->tov = MBX_TOV_SECONDS;
2947 mcp->flags = 0;
2948 rval = qla2x00_mailbox_command(vha, mcp);
2949
2950 if (rval != QLA_SUCCESS) {
2951 ql_dbg(ql_dbg_mbx, vha, 0x1187,
2952 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2953 } else {
2954 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188,
2955 "Done %s.\n", __func__);
2956 }
2957
2958 return rval;
2959 }
2960
2961 int
2962 qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
2963 {
2964 int rval;
2965 mbx_cmd_t mc;
2966 mbx_cmd_t *mcp = &mc;
2967
2968 if (!IS_QLA8044(vha->hw))
2969 return QLA_FUNCTION_FAILED;
2970
2971 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189,
2972 "Entered %s.\n", __func__);
2973
2974 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
2975 mcp->mb[1] = HCS_READ_SERDES;
2976 mcp->mb[3] = LSW(addr);
2977 mcp->mb[4] = MSW(addr);
2978 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0;
2979 mcp->in_mb = MBX_2|MBX_1|MBX_0;
2980 mcp->tov = MBX_TOV_SECONDS;
2981 mcp->flags = 0;
2982 rval = qla2x00_mailbox_command(vha, mcp);
2983
2984 *data = mcp->mb[2] << 16 | mcp->mb[1];
2985
2986 if (rval != QLA_SUCCESS) {
2987 ql_dbg(ql_dbg_mbx, vha, 0x118a,
2988 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2989 } else {
2990 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b,
2991 "Done %s.\n", __func__);
2992 }
2993
2994 return rval;
2995 }
2996
2997 /**
2998 * qla2x00_set_serdes_params() -
2999 * @ha: HA context
3000 *
3001 * Returns
3002 */
3003 int
3004 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
3005 uint16_t sw_em_2g, uint16_t sw_em_4g)
3006 {
3007 int rval;
3008 mbx_cmd_t mc;
3009 mbx_cmd_t *mcp = &mc;
3010
3011 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
3012 "Entered %s.\n", __func__);
3013
3014 mcp->mb[0] = MBC_SERDES_PARAMS;
3015 mcp->mb[1] = BIT_0;
3016 mcp->mb[2] = sw_em_1g | BIT_15;
3017 mcp->mb[3] = sw_em_2g | BIT_15;
3018 mcp->mb[4] = sw_em_4g | BIT_15;
3019 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3020 mcp->in_mb = MBX_0;
3021 mcp->tov = MBX_TOV_SECONDS;
3022 mcp->flags = 0;
3023 rval = qla2x00_mailbox_command(vha, mcp);
3024
3025 if (rval != QLA_SUCCESS) {
3026 /*EMPTY*/
3027 ql_dbg(ql_dbg_mbx, vha, 0x109f,
3028 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3029 } else {
3030 /*EMPTY*/
3031 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
3032 "Done %s.\n", __func__);
3033 }
3034
3035 return rval;
3036 }
3037
3038 int
3039 qla2x00_stop_firmware(scsi_qla_host_t *vha)
3040 {
3041 int rval;
3042 mbx_cmd_t mc;
3043 mbx_cmd_t *mcp = &mc;
3044
3045 if (!IS_FWI2_CAPABLE(vha->hw))
3046 return QLA_FUNCTION_FAILED;
3047
3048 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
3049 "Entered %s.\n", __func__);
3050
3051 mcp->mb[0] = MBC_STOP_FIRMWARE;
3052 mcp->mb[1] = 0;
3053 mcp->out_mb = MBX_1|MBX_0;
3054 mcp->in_mb = MBX_0;
3055 mcp->tov = 5;
3056 mcp->flags = 0;
3057 rval = qla2x00_mailbox_command(vha, mcp);
3058
3059 if (rval != QLA_SUCCESS) {
3060 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
3061 if (mcp->mb[0] == MBS_INVALID_COMMAND)
3062 rval = QLA_INVALID_COMMAND;
3063 } else {
3064 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
3065 "Done %s.\n", __func__);
3066 }
3067
3068 return rval;
3069 }
3070
3071 int
3072 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
3073 uint16_t buffers)
3074 {
3075 int rval;
3076 mbx_cmd_t mc;
3077 mbx_cmd_t *mcp = &mc;
3078
3079 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
3080 "Entered %s.\n", __func__);
3081
3082 if (!IS_FWI2_CAPABLE(vha->hw))
3083 return QLA_FUNCTION_FAILED;
3084
3085 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3086 return QLA_FUNCTION_FAILED;
3087
3088 mcp->mb[0] = MBC_TRACE_CONTROL;
3089 mcp->mb[1] = TC_EFT_ENABLE;
3090 mcp->mb[2] = LSW(eft_dma);
3091 mcp->mb[3] = MSW(eft_dma);
3092 mcp->mb[4] = LSW(MSD(eft_dma));
3093 mcp->mb[5] = MSW(MSD(eft_dma));
3094 mcp->mb[6] = buffers;
3095 mcp->mb[7] = TC_AEN_DISABLE;
3096 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3097 mcp->in_mb = MBX_1|MBX_0;
3098 mcp->tov = MBX_TOV_SECONDS;
3099 mcp->flags = 0;
3100 rval = qla2x00_mailbox_command(vha, mcp);
3101 if (rval != QLA_SUCCESS) {
3102 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
3103 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3104 rval, mcp->mb[0], mcp->mb[1]);
3105 } else {
3106 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
3107 "Done %s.\n", __func__);
3108 }
3109
3110 return rval;
3111 }
3112
3113 int
3114 qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
3115 {
3116 int rval;
3117 mbx_cmd_t mc;
3118 mbx_cmd_t *mcp = &mc;
3119
3120 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
3121 "Entered %s.\n", __func__);
3122
3123 if (!IS_FWI2_CAPABLE(vha->hw))
3124 return QLA_FUNCTION_FAILED;
3125
3126 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3127 return QLA_FUNCTION_FAILED;
3128
3129 mcp->mb[0] = MBC_TRACE_CONTROL;
3130 mcp->mb[1] = TC_EFT_DISABLE;
3131 mcp->out_mb = MBX_1|MBX_0;
3132 mcp->in_mb = MBX_1|MBX_0;
3133 mcp->tov = MBX_TOV_SECONDS;
3134 mcp->flags = 0;
3135 rval = qla2x00_mailbox_command(vha, mcp);
3136 if (rval != QLA_SUCCESS) {
3137 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
3138 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3139 rval, mcp->mb[0], mcp->mb[1]);
3140 } else {
3141 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
3142 "Done %s.\n", __func__);
3143 }
3144
3145 return rval;
3146 }
3147
3148 int
3149 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
3150 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
3151 {
3152 int rval;
3153 mbx_cmd_t mc;
3154 mbx_cmd_t *mcp = &mc;
3155
3156 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
3157 "Entered %s.\n", __func__);
3158
3159 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
3160 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
3161 return QLA_FUNCTION_FAILED;
3162
3163 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3164 return QLA_FUNCTION_FAILED;
3165
3166 mcp->mb[0] = MBC_TRACE_CONTROL;
3167 mcp->mb[1] = TC_FCE_ENABLE;
3168 mcp->mb[2] = LSW(fce_dma);
3169 mcp->mb[3] = MSW(fce_dma);
3170 mcp->mb[4] = LSW(MSD(fce_dma));
3171 mcp->mb[5] = MSW(MSD(fce_dma));
3172 mcp->mb[6] = buffers;
3173 mcp->mb[7] = TC_AEN_DISABLE;
3174 mcp->mb[8] = 0;
3175 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
3176 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
3177 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3178 MBX_1|MBX_0;
3179 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3180 mcp->tov = MBX_TOV_SECONDS;
3181 mcp->flags = 0;
3182 rval = qla2x00_mailbox_command(vha, mcp);
3183 if (rval != QLA_SUCCESS) {
3184 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
3185 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3186 rval, mcp->mb[0], mcp->mb[1]);
3187 } else {
3188 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
3189 "Done %s.\n", __func__);
3190
3191 if (mb)
3192 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
3193 if (dwords)
3194 *dwords = buffers;
3195 }
3196
3197 return rval;
3198 }
3199
3200 int
3201 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
3202 {
3203 int rval;
3204 mbx_cmd_t mc;
3205 mbx_cmd_t *mcp = &mc;
3206
3207 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3208 "Entered %s.\n", __func__);
3209
3210 if (!IS_FWI2_CAPABLE(vha->hw))
3211 return QLA_FUNCTION_FAILED;
3212
3213 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3214 return QLA_FUNCTION_FAILED;
3215
3216 mcp->mb[0] = MBC_TRACE_CONTROL;
3217 mcp->mb[1] = TC_FCE_DISABLE;
3218 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3219 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3220 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3221 MBX_1|MBX_0;
3222 mcp->tov = MBX_TOV_SECONDS;
3223 mcp->flags = 0;
3224 rval = qla2x00_mailbox_command(vha, mcp);
3225 if (rval != QLA_SUCCESS) {
3226 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3227 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3228 rval, mcp->mb[0], mcp->mb[1]);
3229 } else {
3230 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3231 "Done %s.\n", __func__);
3232
3233 if (wr)
3234 *wr = (uint64_t) mcp->mb[5] << 48 |
3235 (uint64_t) mcp->mb[4] << 32 |
3236 (uint64_t) mcp->mb[3] << 16 |
3237 (uint64_t) mcp->mb[2];
3238 if (rd)
3239 *rd = (uint64_t) mcp->mb[9] << 48 |
3240 (uint64_t) mcp->mb[8] << 32 |
3241 (uint64_t) mcp->mb[7] << 16 |
3242 (uint64_t) mcp->mb[6];
3243 }
3244
3245 return rval;
3246 }
3247
3248 int
3249 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3250 uint16_t *port_speed, uint16_t *mb)
3251 {
3252 int rval;
3253 mbx_cmd_t mc;
3254 mbx_cmd_t *mcp = &mc;
3255
3256 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3257 "Entered %s.\n", __func__);
3258
3259 if (!IS_IIDMA_CAPABLE(vha->hw))
3260 return QLA_FUNCTION_FAILED;
3261
3262 mcp->mb[0] = MBC_PORT_PARAMS;
3263 mcp->mb[1] = loop_id;
3264 mcp->mb[2] = mcp->mb[3] = 0;
3265 mcp->mb[9] = vha->vp_idx;
3266 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3267 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3268 mcp->tov = MBX_TOV_SECONDS;
3269 mcp->flags = 0;
3270 rval = qla2x00_mailbox_command(vha, mcp);
3271
3272 /* Return mailbox statuses. */
3273 if (mb != NULL) {
3274 mb[0] = mcp->mb[0];
3275 mb[1] = mcp->mb[1];
3276 mb[3] = mcp->mb[3];
3277 }
3278
3279 if (rval != QLA_SUCCESS) {
3280 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
3281 } else {
3282 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3283 "Done %s.\n", __func__);
3284 if (port_speed)
3285 *port_speed = mcp->mb[3];
3286 }
3287
3288 return rval;
3289 }
3290
3291 int
3292 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3293 uint16_t port_speed, uint16_t *mb)
3294 {
3295 int rval;
3296 mbx_cmd_t mc;
3297 mbx_cmd_t *mcp = &mc;
3298
3299 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3300 "Entered %s.\n", __func__);
3301
3302 if (!IS_IIDMA_CAPABLE(vha->hw))
3303 return QLA_FUNCTION_FAILED;
3304
3305 mcp->mb[0] = MBC_PORT_PARAMS;
3306 mcp->mb[1] = loop_id;
3307 mcp->mb[2] = BIT_0;
3308 if (IS_CNA_CAPABLE(vha->hw))
3309 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
3310 else
3311 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
3312 mcp->mb[9] = vha->vp_idx;
3313 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3314 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3315 mcp->tov = MBX_TOV_SECONDS;
3316 mcp->flags = 0;
3317 rval = qla2x00_mailbox_command(vha, mcp);
3318
3319 /* Return mailbox statuses. */
3320 if (mb != NULL) {
3321 mb[0] = mcp->mb[0];
3322 mb[1] = mcp->mb[1];
3323 mb[3] = mcp->mb[3];
3324 }
3325
3326 if (rval != QLA_SUCCESS) {
3327 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3328 "Failed=%x.\n", rval);
3329 } else {
3330 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3331 "Done %s.\n", __func__);
3332 }
3333
3334 return rval;
3335 }
3336
3337 void
3338 qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
3339 struct vp_rpt_id_entry_24xx *rptid_entry)
3340 {
3341 uint8_t vp_idx;
3342 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
3343 struct qla_hw_data *ha = vha->hw;
3344 scsi_qla_host_t *vp;
3345 unsigned long flags;
3346 int found;
3347
3348 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3349 "Entered %s.\n", __func__);
3350
3351 if (rptid_entry->entry_status != 0)
3352 return;
3353
3354 if (rptid_entry->format == 0) {
3355 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7,
3356 "Format 0 : Number of VPs setup %d, number of "
3357 "VPs acquired %d.\n",
3358 MSB(le16_to_cpu(rptid_entry->vp_count)),
3359 LSB(le16_to_cpu(rptid_entry->vp_count)));
3360 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8,
3361 "Primary port id %02x%02x%02x.\n",
3362 rptid_entry->port_id[2], rptid_entry->port_id[1],
3363 rptid_entry->port_id[0]);
3364 } else if (rptid_entry->format == 1) {
3365 vp_idx = LSB(stat);
3366 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9,
3367 "Format 1: VP[%d] enabled - status %d - with "
3368 "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
3369 rptid_entry->port_id[2], rptid_entry->port_id[1],
3370 rptid_entry->port_id[0]);
3371
3372 /* FA-WWN is only for physical port */
3373 if (!vp_idx) {
3374 void *wwpn = ha->init_cb->port_name;
3375
3376 if (!MSB(stat)) {
3377 if (rptid_entry->vp_idx_map[1] & BIT_6)
3378 wwpn = rptid_entry->reserved_4 + 8;
3379 }
3380 memcpy(vha->port_name, wwpn, WWN_SIZE);
3381 fc_host_port_name(vha->host) =
3382 wwn_to_u64(vha->port_name);
3383 ql_dbg(ql_dbg_mbx, vha, 0x1018,
3384 "FA-WWN portname %016llx (%x)\n",
3385 fc_host_port_name(vha->host), MSB(stat));
3386 }
3387
3388 vp = vha;
3389 if (vp_idx == 0)
3390 goto reg_needed;
3391
3392 if (MSB(stat) != 0 && MSB(stat) != 2) {
3393 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
3394 "Could not acquire ID for VP[%d].\n", vp_idx);
3395 return;
3396 }
3397
3398 found = 0;
3399 spin_lock_irqsave(&ha->vport_slock, flags);
3400 list_for_each_entry(vp, &ha->vp_list, list) {
3401 if (vp_idx == vp->vp_idx) {
3402 found = 1;
3403 break;
3404 }
3405 }
3406 spin_unlock_irqrestore(&ha->vport_slock, flags);
3407
3408 if (!found)
3409 return;
3410
3411 vp->d_id.b.domain = rptid_entry->port_id[2];
3412 vp->d_id.b.area = rptid_entry->port_id[1];
3413 vp->d_id.b.al_pa = rptid_entry->port_id[0];
3414
3415 /*
3416 * Cannot configure here as we are still sitting on the
3417 * response queue. Handle it in dpc context.
3418 */
3419 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
3420
3421 reg_needed:
3422 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
3423 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
3424 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
3425 qla2xxx_wake_dpc(vha);
3426 }
3427 }
3428
3429 /*
3430 * qla24xx_modify_vp_config
3431 * Change VP configuration for vha
3432 *
3433 * Input:
3434 * vha = adapter block pointer.
3435 *
3436 * Returns:
3437 * qla2xxx local function return status code.
3438 *
3439 * Context:
3440 * Kernel context.
3441 */
3442 int
3443 qla24xx_modify_vp_config(scsi_qla_host_t *vha)
3444 {
3445 int rval;
3446 struct vp_config_entry_24xx *vpmod;
3447 dma_addr_t vpmod_dma;
3448 struct qla_hw_data *ha = vha->hw;
3449 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
3450
3451 /* This can be called by the parent */
3452
3453 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
3454 "Entered %s.\n", __func__);
3455
3456 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
3457 if (!vpmod) {
3458 ql_log(ql_log_warn, vha, 0x10bc,
3459 "Failed to allocate modify VP IOCB.\n");
3460 return QLA_MEMORY_ALLOC_FAILED;
3461 }
3462
3463 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
3464 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
3465 vpmod->entry_count = 1;
3466 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
3467 vpmod->vp_count = 1;
3468 vpmod->vp_index1 = vha->vp_idx;
3469 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
3470
3471 qlt_modify_vp_config(vha, vpmod);
3472
3473 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
3474 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
3475 vpmod->entry_count = 1;
3476
3477 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
3478 if (rval != QLA_SUCCESS) {
3479 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
3480 "Failed to issue VP config IOCB (%x).\n", rval);
3481 } else if (vpmod->comp_status != 0) {
3482 ql_dbg(ql_dbg_mbx, vha, 0x10be,
3483 "Failed to complete IOCB -- error status (%x).\n",
3484 vpmod->comp_status);
3485 rval = QLA_FUNCTION_FAILED;
3486 } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
3487 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
3488 "Failed to complete IOCB -- completion status (%x).\n",
3489 le16_to_cpu(vpmod->comp_status));
3490 rval = QLA_FUNCTION_FAILED;
3491 } else {
3492 /* EMPTY */
3493 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
3494 "Done %s.\n", __func__);
3495 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
3496 }
3497 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
3498
3499 return rval;
3500 }
3501
3502 /*
3503 * qla24xx_control_vp
3504 * Enable a virtual port for given host
3505 *
3506 * Input:
3507 * ha = adapter block pointer.
3508 * vhba = virtual adapter (unused)
3509 * index = index number for enabled VP
3510 *
3511 * Returns:
3512 * qla2xxx local function return status code.
3513 *
3514 * Context:
3515 * Kernel context.
3516 */
3517 int
3518 qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
3519 {
3520 int rval;
3521 int map, pos;
3522 struct vp_ctrl_entry_24xx *vce;
3523 dma_addr_t vce_dma;
3524 struct qla_hw_data *ha = vha->hw;
3525 int vp_index = vha->vp_idx;
3526 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
3527
3528 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
3529 "Entered %s enabling index %d.\n", __func__, vp_index);
3530
3531 if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
3532 return QLA_PARAMETER_ERROR;
3533
3534 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
3535 if (!vce) {
3536 ql_log(ql_log_warn, vha, 0x10c2,
3537 "Failed to allocate VP control IOCB.\n");
3538 return QLA_MEMORY_ALLOC_FAILED;
3539 }
3540 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
3541
3542 vce->entry_type = VP_CTRL_IOCB_TYPE;
3543 vce->entry_count = 1;
3544 vce->command = cpu_to_le16(cmd);
3545 vce->vp_count = __constant_cpu_to_le16(1);
3546
3547 /* index map in firmware starts with 1; decrement index
3548 * this is ok as we never use index 0
3549 */
3550 map = (vp_index - 1) / 8;
3551 pos = (vp_index - 1) & 7;
3552 mutex_lock(&ha->vport_lock);
3553 vce->vp_idx_map[map] |= 1 << pos;
3554 mutex_unlock(&ha->vport_lock);
3555
3556 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
3557 if (rval != QLA_SUCCESS) {
3558 ql_dbg(ql_dbg_mbx, vha, 0x10c3,
3559 "Failed to issue VP control IOCB (%x).\n", rval);
3560 } else if (vce->entry_status != 0) {
3561 ql_dbg(ql_dbg_mbx, vha, 0x10c4,
3562 "Failed to complete IOCB -- error status (%x).\n",
3563 vce->entry_status);
3564 rval = QLA_FUNCTION_FAILED;
3565 } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
3566 ql_dbg(ql_dbg_mbx, vha, 0x10c5,
3567 "Failed to complet IOCB -- completion status (%x).\n",
3568 le16_to_cpu(vce->comp_status));
3569 rval = QLA_FUNCTION_FAILED;
3570 } else {
3571 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
3572 "Done %s.\n", __func__);
3573 }
3574
3575 dma_pool_free(ha->s_dma_pool, vce, vce_dma);
3576
3577 return rval;
3578 }
3579
3580 /*
3581 * qla2x00_send_change_request
3582 * Receive or disable RSCN request from fabric controller
3583 *
3584 * Input:
3585 * ha = adapter block pointer
3586 * format = registration format:
3587 * 0 - Reserved
3588 * 1 - Fabric detected registration
3589 * 2 - N_port detected registration
3590 * 3 - Full registration
3591 * FF - clear registration
3592 * vp_idx = Virtual port index
3593 *
3594 * Returns:
3595 * qla2x00 local function return status code.
3596 *
3597 * Context:
3598 * Kernel Context
3599 */
3600
3601 int
3602 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
3603 uint16_t vp_idx)
3604 {
3605 int rval;
3606 mbx_cmd_t mc;
3607 mbx_cmd_t *mcp = &mc;
3608
3609 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
3610 "Entered %s.\n", __func__);
3611
3612 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
3613 mcp->mb[1] = format;
3614 mcp->mb[9] = vp_idx;
3615 mcp->out_mb = MBX_9|MBX_1|MBX_0;
3616 mcp->in_mb = MBX_0|MBX_1;
3617 mcp->tov = MBX_TOV_SECONDS;
3618 mcp->flags = 0;
3619 rval = qla2x00_mailbox_command(vha, mcp);
3620
3621 if (rval == QLA_SUCCESS) {
3622 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3623 rval = BIT_1;
3624 }
3625 } else
3626 rval = BIT_1;
3627
3628 return rval;
3629 }
3630
3631 int
3632 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
3633 uint32_t size)
3634 {
3635 int rval;
3636 mbx_cmd_t mc;
3637 mbx_cmd_t *mcp = &mc;
3638
3639 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
3640 "Entered %s.\n", __func__);
3641
3642 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
3643 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
3644 mcp->mb[8] = MSW(addr);
3645 mcp->out_mb = MBX_8|MBX_0;
3646 } else {
3647 mcp->mb[0] = MBC_DUMP_RISC_RAM;
3648 mcp->out_mb = MBX_0;
3649 }
3650 mcp->mb[1] = LSW(addr);
3651 mcp->mb[2] = MSW(req_dma);
3652 mcp->mb[3] = LSW(req_dma);
3653 mcp->mb[6] = MSW(MSD(req_dma));
3654 mcp->mb[7] = LSW(MSD(req_dma));
3655 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
3656 if (IS_FWI2_CAPABLE(vha->hw)) {
3657 mcp->mb[4] = MSW(size);
3658 mcp->mb[5] = LSW(size);
3659 mcp->out_mb |= MBX_5|MBX_4;
3660 } else {
3661 mcp->mb[4] = LSW(size);
3662 mcp->out_mb |= MBX_4;
3663 }
3664
3665 mcp->in_mb = MBX_0;
3666 mcp->tov = MBX_TOV_SECONDS;
3667 mcp->flags = 0;
3668 rval = qla2x00_mailbox_command(vha, mcp);
3669
3670 if (rval != QLA_SUCCESS) {
3671 ql_dbg(ql_dbg_mbx, vha, 0x1008,
3672 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3673 } else {
3674 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
3675 "Done %s.\n", __func__);
3676 }
3677
3678 return rval;
3679 }
3680 /* 84XX Support **************************************************************/
3681
3682 struct cs84xx_mgmt_cmd {
3683 union {
3684 struct verify_chip_entry_84xx req;
3685 struct verify_chip_rsp_84xx rsp;
3686 } p;
3687 };
3688
3689 int
3690 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
3691 {
3692 int rval, retry;
3693 struct cs84xx_mgmt_cmd *mn;
3694 dma_addr_t mn_dma;
3695 uint16_t options;
3696 unsigned long flags;
3697 struct qla_hw_data *ha = vha->hw;
3698
3699 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
3700 "Entered %s.\n", __func__);
3701
3702 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
3703 if (mn == NULL) {
3704 return QLA_MEMORY_ALLOC_FAILED;
3705 }
3706
3707 /* Force Update? */
3708 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
3709 /* Diagnostic firmware? */
3710 /* options |= MENLO_DIAG_FW; */
3711 /* We update the firmware with only one data sequence. */
3712 options |= VCO_END_OF_DATA;
3713
3714 do {
3715 retry = 0;
3716 memset(mn, 0, sizeof(*mn));
3717 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
3718 mn->p.req.entry_count = 1;
3719 mn->p.req.options = cpu_to_le16(options);
3720
3721 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
3722 "Dump of Verify Request.\n");
3723 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
3724 (uint8_t *)mn, sizeof(*mn));
3725
3726 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
3727 if (rval != QLA_SUCCESS) {
3728 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
3729 "Failed to issue verify IOCB (%x).\n", rval);
3730 goto verify_done;
3731 }
3732
3733 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
3734 "Dump of Verify Response.\n");
3735 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
3736 (uint8_t *)mn, sizeof(*mn));
3737
3738 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
3739 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
3740 le16_to_cpu(mn->p.rsp.failure_code) : 0;
3741 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
3742 "cs=%x fc=%x.\n", status[0], status[1]);
3743
3744 if (status[0] != CS_COMPLETE) {
3745 rval = QLA_FUNCTION_FAILED;
3746 if (!(options & VCO_DONT_UPDATE_FW)) {
3747 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
3748 "Firmware update failed. Retrying "
3749 "without update firmware.\n");
3750 options |= VCO_DONT_UPDATE_FW;
3751 options &= ~VCO_FORCE_UPDATE;
3752 retry = 1;
3753 }
3754 } else {
3755 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
3756 "Firmware updated to %x.\n",
3757 le32_to_cpu(mn->p.rsp.fw_ver));
3758
3759 /* NOTE: we only update OP firmware. */
3760 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
3761 ha->cs84xx->op_fw_version =
3762 le32_to_cpu(mn->p.rsp.fw_ver);
3763 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
3764 flags);
3765 }
3766 } while (retry);
3767
3768 verify_done:
3769 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
3770
3771 if (rval != QLA_SUCCESS) {
3772 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
3773 "Failed=%x.\n", rval);
3774 } else {
3775 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
3776 "Done %s.\n", __func__);
3777 }
3778
3779 return rval;
3780 }
3781
3782 int
3783 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
3784 {
3785 int rval;
3786 unsigned long flags;
3787 mbx_cmd_t mc;
3788 mbx_cmd_t *mcp = &mc;
3789 struct qla_hw_data *ha = vha->hw;
3790
3791 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
3792 "Entered %s.\n", __func__);
3793
3794 if (IS_SHADOW_REG_CAPABLE(ha))
3795 req->options |= BIT_13;
3796
3797 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
3798 mcp->mb[1] = req->options;
3799 mcp->mb[2] = MSW(LSD(req->dma));
3800 mcp->mb[3] = LSW(LSD(req->dma));
3801 mcp->mb[6] = MSW(MSD(req->dma));
3802 mcp->mb[7] = LSW(MSD(req->dma));
3803 mcp->mb[5] = req->length;
3804 if (req->rsp)
3805 mcp->mb[10] = req->rsp->id;
3806 mcp->mb[12] = req->qos;
3807 mcp->mb[11] = req->vp_idx;
3808 mcp->mb[13] = req->rid;
3809 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3810 mcp->mb[15] = 0;
3811
3812 mcp->mb[4] = req->id;
3813 /* que in ptr index */
3814 mcp->mb[8] = 0;
3815 /* que out ptr index */
3816 mcp->mb[9] = *req->out_ptr = 0;
3817 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
3818 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3819 mcp->in_mb = MBX_0;
3820 mcp->flags = MBX_DMA_OUT;
3821 mcp->tov = MBX_TOV_SECONDS * 2;
3822
3823 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
3824 mcp->in_mb |= MBX_1;
3825 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3826 mcp->out_mb |= MBX_15;
3827 /* debug q create issue in SR-IOV */
3828 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
3829 }
3830
3831 spin_lock_irqsave(&ha->hardware_lock, flags);
3832 if (!(req->options & BIT_0)) {
3833 WRT_REG_DWORD(req->req_q_in, 0);
3834 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
3835 WRT_REG_DWORD(req->req_q_out, 0);
3836 }
3837 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3838
3839 rval = qla2x00_mailbox_command(vha, mcp);
3840 if (rval != QLA_SUCCESS) {
3841 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
3842 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3843 } else {
3844 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
3845 "Done %s.\n", __func__);
3846 }
3847
3848 return rval;
3849 }
3850
3851 int
3852 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
3853 {
3854 int rval;
3855 unsigned long flags;
3856 mbx_cmd_t mc;
3857 mbx_cmd_t *mcp = &mc;
3858 struct qla_hw_data *ha = vha->hw;
3859
3860 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
3861 "Entered %s.\n", __func__);
3862
3863 if (IS_SHADOW_REG_CAPABLE(ha))
3864 rsp->options |= BIT_13;
3865
3866 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
3867 mcp->mb[1] = rsp->options;
3868 mcp->mb[2] = MSW(LSD(rsp->dma));
3869 mcp->mb[3] = LSW(LSD(rsp->dma));
3870 mcp->mb[6] = MSW(MSD(rsp->dma));
3871 mcp->mb[7] = LSW(MSD(rsp->dma));
3872 mcp->mb[5] = rsp->length;
3873 mcp->mb[14] = rsp->msix->entry;
3874 mcp->mb[13] = rsp->rid;
3875 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
3876 mcp->mb[15] = 0;
3877
3878 mcp->mb[4] = rsp->id;
3879 /* que in ptr index */
3880 mcp->mb[8] = *rsp->in_ptr = 0;
3881 /* que out ptr index */
3882 mcp->mb[9] = 0;
3883 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
3884 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3885 mcp->in_mb = MBX_0;
3886 mcp->flags = MBX_DMA_OUT;
3887 mcp->tov = MBX_TOV_SECONDS * 2;
3888
3889 if (IS_QLA81XX(ha)) {
3890 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
3891 mcp->in_mb |= MBX_1;
3892 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3893 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
3894 mcp->in_mb |= MBX_1;
3895 /* debug q create issue in SR-IOV */
3896 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
3897 }
3898
3899 spin_lock_irqsave(&ha->hardware_lock, flags);
3900 if (!(rsp->options & BIT_0)) {
3901 WRT_REG_DWORD(rsp->rsp_q_out, 0);
3902 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
3903 WRT_REG_DWORD(rsp->rsp_q_in, 0);
3904 }
3905
3906 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3907
3908 rval = qla2x00_mailbox_command(vha, mcp);
3909 if (rval != QLA_SUCCESS) {
3910 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
3911 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3912 } else {
3913 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
3914 "Done %s.\n", __func__);
3915 }
3916
3917 return rval;
3918 }
3919
3920 int
3921 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
3922 {
3923 int rval;
3924 mbx_cmd_t mc;
3925 mbx_cmd_t *mcp = &mc;
3926
3927 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
3928 "Entered %s.\n", __func__);
3929
3930 mcp->mb[0] = MBC_IDC_ACK;
3931 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3932 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3933 mcp->in_mb = MBX_0;
3934 mcp->tov = MBX_TOV_SECONDS;
3935 mcp->flags = 0;
3936 rval = qla2x00_mailbox_command(vha, mcp);
3937
3938 if (rval != QLA_SUCCESS) {
3939 ql_dbg(ql_dbg_mbx, vha, 0x10da,
3940 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3941 } else {
3942 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
3943 "Done %s.\n", __func__);
3944 }
3945
3946 return rval;
3947 }
3948
3949 int
3950 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
3951 {
3952 int rval;
3953 mbx_cmd_t mc;
3954 mbx_cmd_t *mcp = &mc;
3955
3956 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
3957 "Entered %s.\n", __func__);
3958
3959 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
3960 !IS_QLA27XX(vha->hw))
3961 return QLA_FUNCTION_FAILED;
3962
3963 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3964 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
3965 mcp->out_mb = MBX_1|MBX_0;
3966 mcp->in_mb = MBX_1|MBX_0;
3967 mcp->tov = MBX_TOV_SECONDS;
3968 mcp->flags = 0;
3969 rval = qla2x00_mailbox_command(vha, mcp);
3970
3971 if (rval != QLA_SUCCESS) {
3972 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
3973 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3974 rval, mcp->mb[0], mcp->mb[1]);
3975 } else {
3976 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
3977 "Done %s.\n", __func__);
3978 *sector_size = mcp->mb[1];
3979 }
3980
3981 return rval;
3982 }
3983
3984 int
3985 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
3986 {
3987 int rval;
3988 mbx_cmd_t mc;
3989 mbx_cmd_t *mcp = &mc;
3990
3991 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
3992 !IS_QLA27XX(vha->hw))
3993 return QLA_FUNCTION_FAILED;
3994
3995 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
3996 "Entered %s.\n", __func__);
3997
3998 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3999 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
4000 FAC_OPT_CMD_WRITE_PROTECT;
4001 mcp->out_mb = MBX_1|MBX_0;
4002 mcp->in_mb = MBX_1|MBX_0;
4003 mcp->tov = MBX_TOV_SECONDS;
4004 mcp->flags = 0;
4005 rval = qla2x00_mailbox_command(vha, mcp);
4006
4007 if (rval != QLA_SUCCESS) {
4008 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
4009 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4010 rval, mcp->mb[0], mcp->mb[1]);
4011 } else {
4012 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
4013 "Done %s.\n", __func__);
4014 }
4015
4016 return rval;
4017 }
4018
4019 int
4020 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
4021 {
4022 int rval;
4023 mbx_cmd_t mc;
4024 mbx_cmd_t *mcp = &mc;
4025
4026 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4027 !IS_QLA27XX(vha->hw))
4028 return QLA_FUNCTION_FAILED;
4029
4030 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4031 "Entered %s.\n", __func__);
4032
4033 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4034 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
4035 mcp->mb[2] = LSW(start);
4036 mcp->mb[3] = MSW(start);
4037 mcp->mb[4] = LSW(finish);
4038 mcp->mb[5] = MSW(finish);
4039 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4040 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4041 mcp->tov = MBX_TOV_SECONDS;
4042 mcp->flags = 0;
4043 rval = qla2x00_mailbox_command(vha, mcp);
4044
4045 if (rval != QLA_SUCCESS) {
4046 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4047 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4048 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4049 } else {
4050 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4051 "Done %s.\n", __func__);
4052 }
4053
4054 return rval;
4055 }
4056
4057 int
4058 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
4059 {
4060 int rval = 0;
4061 mbx_cmd_t mc;
4062 mbx_cmd_t *mcp = &mc;
4063
4064 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
4065 "Entered %s.\n", __func__);
4066
4067 mcp->mb[0] = MBC_RESTART_MPI_FW;
4068 mcp->out_mb = MBX_0;
4069 mcp->in_mb = MBX_0|MBX_1;
4070 mcp->tov = MBX_TOV_SECONDS;
4071 mcp->flags = 0;
4072 rval = qla2x00_mailbox_command(vha, mcp);
4073
4074 if (rval != QLA_SUCCESS) {
4075 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
4076 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4077 rval, mcp->mb[0], mcp->mb[1]);
4078 } else {
4079 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
4080 "Done %s.\n", __func__);
4081 }
4082
4083 return rval;
4084 }
4085
4086 int
4087 qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4088 {
4089 int rval;
4090 mbx_cmd_t mc;
4091 mbx_cmd_t *mcp = &mc;
4092 int i;
4093 int len;
4094 uint16_t *str;
4095 struct qla_hw_data *ha = vha->hw;
4096
4097 if (!IS_P3P_TYPE(ha))
4098 return QLA_FUNCTION_FAILED;
4099
4100 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
4101 "Entered %s.\n", __func__);
4102
4103 str = (void *)version;
4104 len = strlen(version);
4105
4106 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4107 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
4108 mcp->out_mb = MBX_1|MBX_0;
4109 for (i = 4; i < 16 && len; i++, str++, len -= 2) {
4110 mcp->mb[i] = cpu_to_le16p(str);
4111 mcp->out_mb |= 1<<i;
4112 }
4113 for (; i < 16; i++) {
4114 mcp->mb[i] = 0;
4115 mcp->out_mb |= 1<<i;
4116 }
4117 mcp->in_mb = MBX_1|MBX_0;
4118 mcp->tov = MBX_TOV_SECONDS;
4119 mcp->flags = 0;
4120 rval = qla2x00_mailbox_command(vha, mcp);
4121
4122 if (rval != QLA_SUCCESS) {
4123 ql_dbg(ql_dbg_mbx, vha, 0x117c,
4124 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4125 } else {
4126 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
4127 "Done %s.\n", __func__);
4128 }
4129
4130 return rval;
4131 }
4132
4133 int
4134 qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4135 {
4136 int rval;
4137 mbx_cmd_t mc;
4138 mbx_cmd_t *mcp = &mc;
4139 int len;
4140 uint16_t dwlen;
4141 uint8_t *str;
4142 dma_addr_t str_dma;
4143 struct qla_hw_data *ha = vha->hw;
4144
4145 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
4146 IS_P3P_TYPE(ha))
4147 return QLA_FUNCTION_FAILED;
4148
4149 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
4150 "Entered %s.\n", __func__);
4151
4152 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
4153 if (!str) {
4154 ql_log(ql_log_warn, vha, 0x117f,
4155 "Failed to allocate driver version param.\n");
4156 return QLA_MEMORY_ALLOC_FAILED;
4157 }
4158
4159 memcpy(str, "\x7\x3\x11\x0", 4);
4160 dwlen = str[0];
4161 len = dwlen * 4 - 4;
4162 memset(str + 4, 0, len);
4163 if (len > strlen(version))
4164 len = strlen(version);
4165 memcpy(str + 4, version, len);
4166
4167 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4168 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
4169 mcp->mb[2] = MSW(LSD(str_dma));
4170 mcp->mb[3] = LSW(LSD(str_dma));
4171 mcp->mb[6] = MSW(MSD(str_dma));
4172 mcp->mb[7] = LSW(MSD(str_dma));
4173 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4174 mcp->in_mb = MBX_1|MBX_0;
4175 mcp->tov = MBX_TOV_SECONDS;
4176 mcp->flags = 0;
4177 rval = qla2x00_mailbox_command(vha, mcp);
4178
4179 if (rval != QLA_SUCCESS) {
4180 ql_dbg(ql_dbg_mbx, vha, 0x1180,
4181 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4182 } else {
4183 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
4184 "Done %s.\n", __func__);
4185 }
4186
4187 dma_pool_free(ha->s_dma_pool, str, str_dma);
4188
4189 return rval;
4190 }
4191
4192 static int
4193 qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
4194 {
4195 int rval;
4196 mbx_cmd_t mc;
4197 mbx_cmd_t *mcp = &mc;
4198
4199 if (!IS_FWI2_CAPABLE(vha->hw))
4200 return QLA_FUNCTION_FAILED;
4201
4202 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4203 "Entered %s.\n", __func__);
4204
4205 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4206 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
4207 mcp->out_mb = MBX_1|MBX_0;
4208 mcp->in_mb = MBX_1|MBX_0;
4209 mcp->tov = MBX_TOV_SECONDS;
4210 mcp->flags = 0;
4211 rval = qla2x00_mailbox_command(vha, mcp);
4212 *temp = mcp->mb[1];
4213
4214 if (rval != QLA_SUCCESS) {
4215 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4216 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4217 } else {
4218 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4219 "Done %s.\n", __func__);
4220 }
4221
4222 return rval;
4223 }
4224
4225 int
4226 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4227 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
4228 {
4229 int rval;
4230 mbx_cmd_t mc;
4231 mbx_cmd_t *mcp = &mc;
4232 struct qla_hw_data *ha = vha->hw;
4233
4234 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
4235 "Entered %s.\n", __func__);
4236
4237 if (!IS_FWI2_CAPABLE(ha))
4238 return QLA_FUNCTION_FAILED;
4239
4240 if (len == 1)
4241 opt |= BIT_0;
4242
4243 mcp->mb[0] = MBC_READ_SFP;
4244 mcp->mb[1] = dev;
4245 mcp->mb[2] = MSW(sfp_dma);
4246 mcp->mb[3] = LSW(sfp_dma);
4247 mcp->mb[6] = MSW(MSD(sfp_dma));
4248 mcp->mb[7] = LSW(MSD(sfp_dma));
4249 mcp->mb[8] = len;
4250 mcp->mb[9] = off;
4251 mcp->mb[10] = opt;
4252 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4253 mcp->in_mb = MBX_1|MBX_0;
4254 mcp->tov = MBX_TOV_SECONDS;
4255 mcp->flags = 0;
4256 rval = qla2x00_mailbox_command(vha, mcp);
4257
4258 if (opt & BIT_0)
4259 *sfp = mcp->mb[1];
4260
4261 if (rval != QLA_SUCCESS) {
4262 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
4263 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4264 } else {
4265 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
4266 "Done %s.\n", __func__);
4267 }
4268
4269 return rval;
4270 }
4271
4272 int
4273 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4274 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
4275 {
4276 int rval;
4277 mbx_cmd_t mc;
4278 mbx_cmd_t *mcp = &mc;
4279 struct qla_hw_data *ha = vha->hw;
4280
4281 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
4282 "Entered %s.\n", __func__);
4283
4284 if (!IS_FWI2_CAPABLE(ha))
4285 return QLA_FUNCTION_FAILED;
4286
4287 if (len == 1)
4288 opt |= BIT_0;
4289
4290 if (opt & BIT_0)
4291 len = *sfp;
4292
4293 mcp->mb[0] = MBC_WRITE_SFP;
4294 mcp->mb[1] = dev;
4295 mcp->mb[2] = MSW(sfp_dma);
4296 mcp->mb[3] = LSW(sfp_dma);
4297 mcp->mb[6] = MSW(MSD(sfp_dma));
4298 mcp->mb[7] = LSW(MSD(sfp_dma));
4299 mcp->mb[8] = len;
4300 mcp->mb[9] = off;
4301 mcp->mb[10] = opt;
4302 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4303 mcp->in_mb = MBX_1|MBX_0;
4304 mcp->tov = MBX_TOV_SECONDS;
4305 mcp->flags = 0;
4306 rval = qla2x00_mailbox_command(vha, mcp);
4307
4308 if (rval != QLA_SUCCESS) {
4309 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
4310 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4311 } else {
4312 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
4313 "Done %s.\n", __func__);
4314 }
4315
4316 return rval;
4317 }
4318
4319 int
4320 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
4321 uint16_t size_in_bytes, uint16_t *actual_size)
4322 {
4323 int rval;
4324 mbx_cmd_t mc;
4325 mbx_cmd_t *mcp = &mc;
4326
4327 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
4328 "Entered %s.\n", __func__);
4329
4330 if (!IS_CNA_CAPABLE(vha->hw))
4331 return QLA_FUNCTION_FAILED;
4332
4333 mcp->mb[0] = MBC_GET_XGMAC_STATS;
4334 mcp->mb[2] = MSW(stats_dma);
4335 mcp->mb[3] = LSW(stats_dma);
4336 mcp->mb[6] = MSW(MSD(stats_dma));
4337 mcp->mb[7] = LSW(MSD(stats_dma));
4338 mcp->mb[8] = size_in_bytes >> 2;
4339 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
4340 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4341 mcp->tov = MBX_TOV_SECONDS;
4342 mcp->flags = 0;
4343 rval = qla2x00_mailbox_command(vha, mcp);
4344
4345 if (rval != QLA_SUCCESS) {
4346 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
4347 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4348 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4349 } else {
4350 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
4351 "Done %s.\n", __func__);
4352
4353
4354 *actual_size = mcp->mb[2] << 2;
4355 }
4356
4357 return rval;
4358 }
4359
4360 int
4361 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
4362 uint16_t size)
4363 {
4364 int rval;
4365 mbx_cmd_t mc;
4366 mbx_cmd_t *mcp = &mc;
4367
4368 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
4369 "Entered %s.\n", __func__);
4370
4371 if (!IS_CNA_CAPABLE(vha->hw))
4372 return QLA_FUNCTION_FAILED;
4373
4374 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
4375 mcp->mb[1] = 0;
4376 mcp->mb[2] = MSW(tlv_dma);
4377 mcp->mb[3] = LSW(tlv_dma);
4378 mcp->mb[6] = MSW(MSD(tlv_dma));
4379 mcp->mb[7] = LSW(MSD(tlv_dma));
4380 mcp->mb[8] = size;
4381 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4382 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4383 mcp->tov = MBX_TOV_SECONDS;
4384 mcp->flags = 0;
4385 rval = qla2x00_mailbox_command(vha, mcp);
4386
4387 if (rval != QLA_SUCCESS) {
4388 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
4389 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4390 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
4391 } else {
4392 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
4393 "Done %s.\n", __func__);
4394 }
4395
4396 return rval;
4397 }
4398
4399 int
4400 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
4401 {
4402 int rval;
4403 mbx_cmd_t mc;
4404 mbx_cmd_t *mcp = &mc;
4405
4406 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
4407 "Entered %s.\n", __func__);
4408
4409 if (!IS_FWI2_CAPABLE(vha->hw))
4410 return QLA_FUNCTION_FAILED;
4411
4412 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
4413 mcp->mb[1] = LSW(risc_addr);
4414 mcp->mb[8] = MSW(risc_addr);
4415 mcp->out_mb = MBX_8|MBX_1|MBX_0;
4416 mcp->in_mb = MBX_3|MBX_2|MBX_0;
4417 mcp->tov = 30;
4418 mcp->flags = 0;
4419 rval = qla2x00_mailbox_command(vha, mcp);
4420 if (rval != QLA_SUCCESS) {
4421 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
4422 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4423 } else {
4424 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
4425 "Done %s.\n", __func__);
4426 *data = mcp->mb[3] << 16 | mcp->mb[2];
4427 }
4428
4429 return rval;
4430 }
4431
4432 int
4433 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4434 uint16_t *mresp)
4435 {
4436 int rval;
4437 mbx_cmd_t mc;
4438 mbx_cmd_t *mcp = &mc;
4439
4440 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
4441 "Entered %s.\n", __func__);
4442
4443 memset(mcp->mb, 0 , sizeof(mcp->mb));
4444 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
4445 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
4446
4447 /* transfer count */
4448 mcp->mb[10] = LSW(mreq->transfer_size);
4449 mcp->mb[11] = MSW(mreq->transfer_size);
4450
4451 /* send data address */
4452 mcp->mb[14] = LSW(mreq->send_dma);
4453 mcp->mb[15] = MSW(mreq->send_dma);
4454 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4455 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4456
4457 /* receive data address */
4458 mcp->mb[16] = LSW(mreq->rcv_dma);
4459 mcp->mb[17] = MSW(mreq->rcv_dma);
4460 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4461 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4462
4463 /* Iteration count */
4464 mcp->mb[18] = LSW(mreq->iteration_count);
4465 mcp->mb[19] = MSW(mreq->iteration_count);
4466
4467 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
4468 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
4469 if (IS_CNA_CAPABLE(vha->hw))
4470 mcp->out_mb |= MBX_2;
4471 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
4472
4473 mcp->buf_size = mreq->transfer_size;
4474 mcp->tov = MBX_TOV_SECONDS;
4475 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4476
4477 rval = qla2x00_mailbox_command(vha, mcp);
4478
4479 if (rval != QLA_SUCCESS) {
4480 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
4481 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
4482 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
4483 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
4484 } else {
4485 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
4486 "Done %s.\n", __func__);
4487 }
4488
4489 /* Copy mailbox information */
4490 memcpy( mresp, mcp->mb, 64);
4491 return rval;
4492 }
4493
4494 int
4495 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4496 uint16_t *mresp)
4497 {
4498 int rval;
4499 mbx_cmd_t mc;
4500 mbx_cmd_t *mcp = &mc;
4501 struct qla_hw_data *ha = vha->hw;
4502
4503 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
4504 "Entered %s.\n", __func__);
4505
4506 memset(mcp->mb, 0 , sizeof(mcp->mb));
4507 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
4508 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
4509 if (IS_CNA_CAPABLE(ha)) {
4510 mcp->mb[1] |= BIT_15;
4511 mcp->mb[2] = vha->fcoe_fcf_idx;
4512 }
4513 mcp->mb[16] = LSW(mreq->rcv_dma);
4514 mcp->mb[17] = MSW(mreq->rcv_dma);
4515 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4516 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4517
4518 mcp->mb[10] = LSW(mreq->transfer_size);
4519
4520 mcp->mb[14] = LSW(mreq->send_dma);
4521 mcp->mb[15] = MSW(mreq->send_dma);
4522 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4523 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4524
4525 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
4526 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
4527 if (IS_CNA_CAPABLE(ha))
4528 mcp->out_mb |= MBX_2;
4529
4530 mcp->in_mb = MBX_0;
4531 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
4532 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
4533 mcp->in_mb |= MBX_1;
4534 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
4535 mcp->in_mb |= MBX_3;
4536
4537 mcp->tov = MBX_TOV_SECONDS;
4538 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4539 mcp->buf_size = mreq->transfer_size;
4540
4541 rval = qla2x00_mailbox_command(vha, mcp);
4542
4543 if (rval != QLA_SUCCESS) {
4544 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
4545 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4546 rval, mcp->mb[0], mcp->mb[1]);
4547 } else {
4548 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
4549 "Done %s.\n", __func__);
4550 }
4551
4552 /* Copy mailbox information */
4553 memcpy(mresp, mcp->mb, 64);
4554 return rval;
4555 }
4556
4557 int
4558 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
4559 {
4560 int rval;
4561 mbx_cmd_t mc;
4562 mbx_cmd_t *mcp = &mc;
4563
4564 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
4565 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
4566
4567 mcp->mb[0] = MBC_ISP84XX_RESET;
4568 mcp->mb[1] = enable_diagnostic;
4569 mcp->out_mb = MBX_1|MBX_0;
4570 mcp->in_mb = MBX_1|MBX_0;
4571 mcp->tov = MBX_TOV_SECONDS;
4572 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4573 rval = qla2x00_mailbox_command(vha, mcp);
4574
4575 if (rval != QLA_SUCCESS)
4576 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
4577 else
4578 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
4579 "Done %s.\n", __func__);
4580
4581 return rval;
4582 }
4583
4584 int
4585 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
4586 {
4587 int rval;
4588 mbx_cmd_t mc;
4589 mbx_cmd_t *mcp = &mc;
4590
4591 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
4592 "Entered %s.\n", __func__);
4593
4594 if (!IS_FWI2_CAPABLE(vha->hw))
4595 return QLA_FUNCTION_FAILED;
4596
4597 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
4598 mcp->mb[1] = LSW(risc_addr);
4599 mcp->mb[2] = LSW(data);
4600 mcp->mb[3] = MSW(data);
4601 mcp->mb[8] = MSW(risc_addr);
4602 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
4603 mcp->in_mb = MBX_0;
4604 mcp->tov = 30;
4605 mcp->flags = 0;
4606 rval = qla2x00_mailbox_command(vha, mcp);
4607 if (rval != QLA_SUCCESS) {
4608 ql_dbg(ql_dbg_mbx, vha, 0x1101,
4609 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4610 } else {
4611 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
4612 "Done %s.\n", __func__);
4613 }
4614
4615 return rval;
4616 }
4617
4618 int
4619 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
4620 {
4621 int rval;
4622 uint32_t stat, timer;
4623 uint16_t mb0 = 0;
4624 struct qla_hw_data *ha = vha->hw;
4625 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4626
4627 rval = QLA_SUCCESS;
4628
4629 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
4630 "Entered %s.\n", __func__);
4631
4632 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
4633
4634 /* Write the MBC data to the registers */
4635 WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
4636 WRT_REG_WORD(&reg->mailbox1, mb[0]);
4637 WRT_REG_WORD(&reg->mailbox2, mb[1]);
4638 WRT_REG_WORD(&reg->mailbox3, mb[2]);
4639 WRT_REG_WORD(&reg->mailbox4, mb[3]);
4640
4641 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
4642
4643 /* Poll for MBC interrupt */
4644 for (timer = 6000000; timer; timer--) {
4645 /* Check for pending interrupts. */
4646 stat = RD_REG_DWORD(&reg->host_status);
4647 if (stat & HSRX_RISC_INT) {
4648 stat &= 0xff;
4649
4650 if (stat == 0x1 || stat == 0x2 ||
4651 stat == 0x10 || stat == 0x11) {
4652 set_bit(MBX_INTERRUPT,
4653 &ha->mbx_cmd_flags);
4654 mb0 = RD_REG_WORD(&reg->mailbox0);
4655 WRT_REG_DWORD(&reg->hccr,
4656 HCCRX_CLR_RISC_INT);
4657 RD_REG_DWORD(&reg->hccr);
4658 break;
4659 }
4660 }
4661 udelay(5);
4662 }
4663
4664 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
4665 rval = mb0 & MBS_MASK;
4666 else
4667 rval = QLA_FUNCTION_FAILED;
4668
4669 if (rval != QLA_SUCCESS) {
4670 ql_dbg(ql_dbg_mbx, vha, 0x1104,
4671 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
4672 } else {
4673 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
4674 "Done %s.\n", __func__);
4675 }
4676
4677 return rval;
4678 }
4679
4680 int
4681 qla2x00_get_data_rate(scsi_qla_host_t *vha)
4682 {
4683 int rval;
4684 mbx_cmd_t mc;
4685 mbx_cmd_t *mcp = &mc;
4686 struct qla_hw_data *ha = vha->hw;
4687
4688 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
4689 "Entered %s.\n", __func__);
4690
4691 if (!IS_FWI2_CAPABLE(ha))
4692 return QLA_FUNCTION_FAILED;
4693
4694 mcp->mb[0] = MBC_DATA_RATE;
4695 mcp->mb[1] = 0;
4696 mcp->out_mb = MBX_1|MBX_0;
4697 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4698 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
4699 mcp->in_mb |= MBX_3;
4700 mcp->tov = MBX_TOV_SECONDS;
4701 mcp->flags = 0;
4702 rval = qla2x00_mailbox_command(vha, mcp);
4703 if (rval != QLA_SUCCESS) {
4704 ql_dbg(ql_dbg_mbx, vha, 0x1107,
4705 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4706 } else {
4707 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
4708 "Done %s.\n", __func__);
4709 if (mcp->mb[1] != 0x7)
4710 ha->link_data_rate = mcp->mb[1];
4711 }
4712
4713 return rval;
4714 }
4715
4716 int
4717 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
4718 {
4719 int rval;
4720 mbx_cmd_t mc;
4721 mbx_cmd_t *mcp = &mc;
4722 struct qla_hw_data *ha = vha->hw;
4723
4724 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
4725 "Entered %s.\n", __func__);
4726
4727 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
4728 !IS_QLA27XX(ha))
4729 return QLA_FUNCTION_FAILED;
4730 mcp->mb[0] = MBC_GET_PORT_CONFIG;
4731 mcp->out_mb = MBX_0;
4732 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4733 mcp->tov = MBX_TOV_SECONDS;
4734 mcp->flags = 0;
4735
4736 rval = qla2x00_mailbox_command(vha, mcp);
4737
4738 if (rval != QLA_SUCCESS) {
4739 ql_dbg(ql_dbg_mbx, vha, 0x110a,
4740 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4741 } else {
4742 /* Copy all bits to preserve original value */
4743 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
4744
4745 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
4746 "Done %s.\n", __func__);
4747 }
4748 return rval;
4749 }
4750
4751 int
4752 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
4753 {
4754 int rval;
4755 mbx_cmd_t mc;
4756 mbx_cmd_t *mcp = &mc;
4757
4758 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
4759 "Entered %s.\n", __func__);
4760
4761 mcp->mb[0] = MBC_SET_PORT_CONFIG;
4762 /* Copy all bits to preserve original setting */
4763 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
4764 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4765 mcp->in_mb = MBX_0;
4766 mcp->tov = MBX_TOV_SECONDS;
4767 mcp->flags = 0;
4768 rval = qla2x00_mailbox_command(vha, mcp);
4769
4770 if (rval != QLA_SUCCESS) {
4771 ql_dbg(ql_dbg_mbx, vha, 0x110d,
4772 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4773 } else
4774 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
4775 "Done %s.\n", __func__);
4776
4777 return rval;
4778 }
4779
4780
4781 int
4782 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
4783 uint16_t *mb)
4784 {
4785 int rval;
4786 mbx_cmd_t mc;
4787 mbx_cmd_t *mcp = &mc;
4788 struct qla_hw_data *ha = vha->hw;
4789
4790 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
4791 "Entered %s.\n", __func__);
4792
4793 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
4794 return QLA_FUNCTION_FAILED;
4795
4796 mcp->mb[0] = MBC_PORT_PARAMS;
4797 mcp->mb[1] = loop_id;
4798 if (ha->flags.fcp_prio_enabled)
4799 mcp->mb[2] = BIT_1;
4800 else
4801 mcp->mb[2] = BIT_2;
4802 mcp->mb[4] = priority & 0xf;
4803 mcp->mb[9] = vha->vp_idx;
4804 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4805 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
4806 mcp->tov = 30;
4807 mcp->flags = 0;
4808 rval = qla2x00_mailbox_command(vha, mcp);
4809 if (mb != NULL) {
4810 mb[0] = mcp->mb[0];
4811 mb[1] = mcp->mb[1];
4812 mb[3] = mcp->mb[3];
4813 mb[4] = mcp->mb[4];
4814 }
4815
4816 if (rval != QLA_SUCCESS) {
4817 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
4818 } else {
4819 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
4820 "Done %s.\n", __func__);
4821 }
4822
4823 return rval;
4824 }
4825
4826 int
4827 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
4828 {
4829 int rval = QLA_FUNCTION_FAILED;
4830 struct qla_hw_data *ha = vha->hw;
4831 uint8_t byte;
4832
4833 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
4834 ql_dbg(ql_dbg_mbx, vha, 0x1150,
4835 "Thermal not supported by this card.\n");
4836 return rval;
4837 }
4838
4839 if (IS_QLA25XX(ha)) {
4840 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
4841 ha->pdev->subsystem_device == 0x0175) {
4842 rval = qla2x00_read_sfp(vha, 0, &byte,
4843 0x98, 0x1, 1, BIT_13|BIT_0);
4844 *temp = byte;
4845 return rval;
4846 }
4847 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
4848 ha->pdev->subsystem_device == 0x338e) {
4849 rval = qla2x00_read_sfp(vha, 0, &byte,
4850 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
4851 *temp = byte;
4852 return rval;
4853 }
4854 ql_dbg(ql_dbg_mbx, vha, 0x10c9,
4855 "Thermal not supported by this card.\n");
4856 return rval;
4857 }
4858
4859 if (IS_QLA82XX(ha)) {
4860 *temp = qla82xx_read_temperature(vha);
4861 rval = QLA_SUCCESS;
4862 return rval;
4863 } else if (IS_QLA8044(ha)) {
4864 *temp = qla8044_read_temperature(vha);
4865 rval = QLA_SUCCESS;
4866 return rval;
4867 }
4868
4869 rval = qla2x00_read_asic_temperature(vha, temp);
4870 return rval;
4871 }
4872
4873 int
4874 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
4875 {
4876 int rval;
4877 struct qla_hw_data *ha = vha->hw;
4878 mbx_cmd_t mc;
4879 mbx_cmd_t *mcp = &mc;
4880
4881 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
4882 "Entered %s.\n", __func__);
4883
4884 if (!IS_FWI2_CAPABLE(ha))
4885 return QLA_FUNCTION_FAILED;
4886
4887 memset(mcp, 0, sizeof(mbx_cmd_t));
4888 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
4889 mcp->mb[1] = 1;
4890
4891 mcp->out_mb = MBX_1|MBX_0;
4892 mcp->in_mb = MBX_0;
4893 mcp->tov = 30;
4894 mcp->flags = 0;
4895
4896 rval = qla2x00_mailbox_command(vha, mcp);
4897 if (rval != QLA_SUCCESS) {
4898 ql_dbg(ql_dbg_mbx, vha, 0x1016,
4899 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4900 } else {
4901 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
4902 "Done %s.\n", __func__);
4903 }
4904
4905 return rval;
4906 }
4907
4908 int
4909 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
4910 {
4911 int rval;
4912 struct qla_hw_data *ha = vha->hw;
4913 mbx_cmd_t mc;
4914 mbx_cmd_t *mcp = &mc;
4915
4916 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
4917 "Entered %s.\n", __func__);
4918
4919 if (!IS_P3P_TYPE(ha))
4920 return QLA_FUNCTION_FAILED;
4921
4922 memset(mcp, 0, sizeof(mbx_cmd_t));
4923 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
4924 mcp->mb[1] = 0;
4925
4926 mcp->out_mb = MBX_1|MBX_0;
4927 mcp->in_mb = MBX_0;
4928 mcp->tov = 30;
4929 mcp->flags = 0;
4930
4931 rval = qla2x00_mailbox_command(vha, mcp);
4932 if (rval != QLA_SUCCESS) {
4933 ql_dbg(ql_dbg_mbx, vha, 0x100c,
4934 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4935 } else {
4936 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
4937 "Done %s.\n", __func__);
4938 }
4939
4940 return rval;
4941 }
4942
4943 int
4944 qla82xx_md_get_template_size(scsi_qla_host_t *vha)
4945 {
4946 struct qla_hw_data *ha = vha->hw;
4947 mbx_cmd_t mc;
4948 mbx_cmd_t *mcp = &mc;
4949 int rval = QLA_FUNCTION_FAILED;
4950
4951 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
4952 "Entered %s.\n", __func__);
4953
4954 memset(mcp->mb, 0 , sizeof(mcp->mb));
4955 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4956 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4957 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
4958 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
4959
4960 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4961 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
4962 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4963
4964 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4965 mcp->tov = MBX_TOV_SECONDS;
4966 rval = qla2x00_mailbox_command(vha, mcp);
4967
4968 /* Always copy back return mailbox values. */
4969 if (rval != QLA_SUCCESS) {
4970 ql_dbg(ql_dbg_mbx, vha, 0x1120,
4971 "mailbox command FAILED=0x%x, subcode=%x.\n",
4972 (mcp->mb[1] << 16) | mcp->mb[0],
4973 (mcp->mb[3] << 16) | mcp->mb[2]);
4974 } else {
4975 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
4976 "Done %s.\n", __func__);
4977 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
4978 if (!ha->md_template_size) {
4979 ql_dbg(ql_dbg_mbx, vha, 0x1122,
4980 "Null template size obtained.\n");
4981 rval = QLA_FUNCTION_FAILED;
4982 }
4983 }
4984 return rval;
4985 }
4986
4987 int
4988 qla82xx_md_get_template(scsi_qla_host_t *vha)
4989 {
4990 struct qla_hw_data *ha = vha->hw;
4991 mbx_cmd_t mc;
4992 mbx_cmd_t *mcp = &mc;
4993 int rval = QLA_FUNCTION_FAILED;
4994
4995 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
4996 "Entered %s.\n", __func__);
4997
4998 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
4999 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5000 if (!ha->md_tmplt_hdr) {
5001 ql_log(ql_log_warn, vha, 0x1124,
5002 "Unable to allocate memory for Minidump template.\n");
5003 return rval;
5004 }
5005
5006 memset(mcp->mb, 0 , sizeof(mcp->mb));
5007 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5008 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5009 mcp->mb[2] = LSW(RQST_TMPLT);
5010 mcp->mb[3] = MSW(RQST_TMPLT);
5011 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
5012 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
5013 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
5014 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
5015 mcp->mb[8] = LSW(ha->md_template_size);
5016 mcp->mb[9] = MSW(ha->md_template_size);
5017
5018 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5019 mcp->tov = MBX_TOV_SECONDS;
5020 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5021 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5022 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5023 rval = qla2x00_mailbox_command(vha, mcp);
5024
5025 if (rval != QLA_SUCCESS) {
5026 ql_dbg(ql_dbg_mbx, vha, 0x1125,
5027 "mailbox command FAILED=0x%x, subcode=%x.\n",
5028 ((mcp->mb[1] << 16) | mcp->mb[0]),
5029 ((mcp->mb[3] << 16) | mcp->mb[2]));
5030 } else
5031 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
5032 "Done %s.\n", __func__);
5033 return rval;
5034 }
5035
5036 int
5037 qla8044_md_get_template(scsi_qla_host_t *vha)
5038 {
5039 struct qla_hw_data *ha = vha->hw;
5040 mbx_cmd_t mc;
5041 mbx_cmd_t *mcp = &mc;
5042 int rval = QLA_FUNCTION_FAILED;
5043 int offset = 0, size = MINIDUMP_SIZE_36K;
5044 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
5045 "Entered %s.\n", __func__);
5046
5047 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5048 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5049 if (!ha->md_tmplt_hdr) {
5050 ql_log(ql_log_warn, vha, 0xb11b,
5051 "Unable to allocate memory for Minidump template.\n");
5052 return rval;
5053 }
5054
5055 memset(mcp->mb, 0 , sizeof(mcp->mb));
5056 while (offset < ha->md_template_size) {
5057 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5058 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5059 mcp->mb[2] = LSW(RQST_TMPLT);
5060 mcp->mb[3] = MSW(RQST_TMPLT);
5061 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
5062 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
5063 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
5064 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
5065 mcp->mb[8] = LSW(size);
5066 mcp->mb[9] = MSW(size);
5067 mcp->mb[10] = offset & 0x0000FFFF;
5068 mcp->mb[11] = offset & 0xFFFF0000;
5069 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5070 mcp->tov = MBX_TOV_SECONDS;
5071 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5072 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5073 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5074 rval = qla2x00_mailbox_command(vha, mcp);
5075
5076 if (rval != QLA_SUCCESS) {
5077 ql_dbg(ql_dbg_mbx, vha, 0xb11c,
5078 "mailbox command FAILED=0x%x, subcode=%x.\n",
5079 ((mcp->mb[1] << 16) | mcp->mb[0]),
5080 ((mcp->mb[3] << 16) | mcp->mb[2]));
5081 return rval;
5082 } else
5083 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
5084 "Done %s.\n", __func__);
5085 offset = offset + size;
5086 }
5087 return rval;
5088 }
5089
5090 int
5091 qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5092 {
5093 int rval;
5094 struct qla_hw_data *ha = vha->hw;
5095 mbx_cmd_t mc;
5096 mbx_cmd_t *mcp = &mc;
5097
5098 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5099 return QLA_FUNCTION_FAILED;
5100
5101 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
5102 "Entered %s.\n", __func__);
5103
5104 memset(mcp, 0, sizeof(mbx_cmd_t));
5105 mcp->mb[0] = MBC_SET_LED_CONFIG;
5106 mcp->mb[1] = led_cfg[0];
5107 mcp->mb[2] = led_cfg[1];
5108 if (IS_QLA8031(ha)) {
5109 mcp->mb[3] = led_cfg[2];
5110 mcp->mb[4] = led_cfg[3];
5111 mcp->mb[5] = led_cfg[4];
5112 mcp->mb[6] = led_cfg[5];
5113 }
5114
5115 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5116 if (IS_QLA8031(ha))
5117 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5118 mcp->in_mb = MBX_0;
5119 mcp->tov = 30;
5120 mcp->flags = 0;
5121
5122 rval = qla2x00_mailbox_command(vha, mcp);
5123 if (rval != QLA_SUCCESS) {
5124 ql_dbg(ql_dbg_mbx, vha, 0x1134,
5125 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5126 } else {
5127 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
5128 "Done %s.\n", __func__);
5129 }
5130
5131 return rval;
5132 }
5133
5134 int
5135 qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5136 {
5137 int rval;
5138 struct qla_hw_data *ha = vha->hw;
5139 mbx_cmd_t mc;
5140 mbx_cmd_t *mcp = &mc;
5141
5142 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5143 return QLA_FUNCTION_FAILED;
5144
5145 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
5146 "Entered %s.\n", __func__);
5147
5148 memset(mcp, 0, sizeof(mbx_cmd_t));
5149 mcp->mb[0] = MBC_GET_LED_CONFIG;
5150
5151 mcp->out_mb = MBX_0;
5152 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5153 if (IS_QLA8031(ha))
5154 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5155 mcp->tov = 30;
5156 mcp->flags = 0;
5157
5158 rval = qla2x00_mailbox_command(vha, mcp);
5159 if (rval != QLA_SUCCESS) {
5160 ql_dbg(ql_dbg_mbx, vha, 0x1137,
5161 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5162 } else {
5163 led_cfg[0] = mcp->mb[1];
5164 led_cfg[1] = mcp->mb[2];
5165 if (IS_QLA8031(ha)) {
5166 led_cfg[2] = mcp->mb[3];
5167 led_cfg[3] = mcp->mb[4];
5168 led_cfg[4] = mcp->mb[5];
5169 led_cfg[5] = mcp->mb[6];
5170 }
5171 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
5172 "Done %s.\n", __func__);
5173 }
5174
5175 return rval;
5176 }
5177
5178 int
5179 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
5180 {
5181 int rval;
5182 struct qla_hw_data *ha = vha->hw;
5183 mbx_cmd_t mc;
5184 mbx_cmd_t *mcp = &mc;
5185
5186 if (!IS_P3P_TYPE(ha))
5187 return QLA_FUNCTION_FAILED;
5188
5189 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
5190 "Entered %s.\n", __func__);
5191
5192 memset(mcp, 0, sizeof(mbx_cmd_t));
5193 mcp->mb[0] = MBC_SET_LED_CONFIG;
5194 if (enable)
5195 mcp->mb[7] = 0xE;
5196 else
5197 mcp->mb[7] = 0xD;
5198
5199 mcp->out_mb = MBX_7|MBX_0;
5200 mcp->in_mb = MBX_0;
5201 mcp->tov = MBX_TOV_SECONDS;
5202 mcp->flags = 0;
5203
5204 rval = qla2x00_mailbox_command(vha, mcp);
5205 if (rval != QLA_SUCCESS) {
5206 ql_dbg(ql_dbg_mbx, vha, 0x1128,
5207 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5208 } else {
5209 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
5210 "Done %s.\n", __func__);
5211 }
5212
5213 return rval;
5214 }
5215
5216 int
5217 qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
5218 {
5219 int rval;
5220 struct qla_hw_data *ha = vha->hw;
5221 mbx_cmd_t mc;
5222 mbx_cmd_t *mcp = &mc;
5223
5224 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
5225 return QLA_FUNCTION_FAILED;
5226
5227 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
5228 "Entered %s.\n", __func__);
5229
5230 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
5231 mcp->mb[1] = LSW(reg);
5232 mcp->mb[2] = MSW(reg);
5233 mcp->mb[3] = LSW(data);
5234 mcp->mb[4] = MSW(data);
5235 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5236
5237 mcp->in_mb = MBX_1|MBX_0;
5238 mcp->tov = MBX_TOV_SECONDS;
5239 mcp->flags = 0;
5240 rval = qla2x00_mailbox_command(vha, mcp);
5241
5242 if (rval != QLA_SUCCESS) {
5243 ql_dbg(ql_dbg_mbx, vha, 0x1131,
5244 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5245 } else {
5246 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
5247 "Done %s.\n", __func__);
5248 }
5249
5250 return rval;
5251 }
5252
5253 int
5254 qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
5255 {
5256 int rval;
5257 struct qla_hw_data *ha = vha->hw;
5258 mbx_cmd_t mc;
5259 mbx_cmd_t *mcp = &mc;
5260
5261 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
5262 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
5263 "Implicit LOGO Unsupported.\n");
5264 return QLA_FUNCTION_FAILED;
5265 }
5266
5267
5268 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
5269 "Entering %s.\n", __func__);
5270
5271 /* Perform Implicit LOGO. */
5272 mcp->mb[0] = MBC_PORT_LOGOUT;
5273 mcp->mb[1] = fcport->loop_id;
5274 mcp->mb[10] = BIT_15;
5275 mcp->out_mb = MBX_10|MBX_1|MBX_0;
5276 mcp->in_mb = MBX_0;
5277 mcp->tov = MBX_TOV_SECONDS;
5278 mcp->flags = 0;
5279 rval = qla2x00_mailbox_command(vha, mcp);
5280 if (rval != QLA_SUCCESS)
5281 ql_dbg(ql_dbg_mbx, vha, 0x113d,
5282 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5283 else
5284 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
5285 "Done %s.\n", __func__);
5286
5287 return rval;
5288 }
5289
5290 int
5291 qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
5292 {
5293 int rval;
5294 mbx_cmd_t mc;
5295 mbx_cmd_t *mcp = &mc;
5296 struct qla_hw_data *ha = vha->hw;
5297 unsigned long retry_max_time = jiffies + (2 * HZ);
5298
5299 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
5300 return QLA_FUNCTION_FAILED;
5301
5302 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
5303
5304 retry_rd_reg:
5305 mcp->mb[0] = MBC_READ_REMOTE_REG;
5306 mcp->mb[1] = LSW(reg);
5307 mcp->mb[2] = MSW(reg);
5308 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5309 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5310 mcp->tov = MBX_TOV_SECONDS;
5311 mcp->flags = 0;
5312 rval = qla2x00_mailbox_command(vha, mcp);
5313
5314 if (rval != QLA_SUCCESS) {
5315 ql_dbg(ql_dbg_mbx, vha, 0x114c,
5316 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5317 rval, mcp->mb[0], mcp->mb[1]);
5318 } else {
5319 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
5320 if (*data == QLA8XXX_BAD_VALUE) {
5321 /*
5322 * During soft-reset CAMRAM register reads might
5323 * return 0xbad0bad0. So retry for MAX of 2 sec
5324 * while reading camram registers.
5325 */
5326 if (time_after(jiffies, retry_max_time)) {
5327 ql_dbg(ql_dbg_mbx, vha, 0x1141,
5328 "Failure to read CAMRAM register. "
5329 "data=0x%x.\n", *data);
5330 return QLA_FUNCTION_FAILED;
5331 }
5332 msleep(100);
5333 goto retry_rd_reg;
5334 }
5335 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
5336 }
5337
5338 return rval;
5339 }
5340
5341 int
5342 qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
5343 {
5344 int rval;
5345 mbx_cmd_t mc;
5346 mbx_cmd_t *mcp = &mc;
5347 struct qla_hw_data *ha = vha->hw;
5348
5349 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
5350 return QLA_FUNCTION_FAILED;
5351
5352 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
5353
5354 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
5355 mcp->out_mb = MBX_0;
5356 mcp->in_mb = MBX_1|MBX_0;
5357 mcp->tov = MBX_TOV_SECONDS;
5358 mcp->flags = 0;
5359 rval = qla2x00_mailbox_command(vha, mcp);
5360
5361 if (rval != QLA_SUCCESS) {
5362 ql_dbg(ql_dbg_mbx, vha, 0x1144,
5363 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5364 rval, mcp->mb[0], mcp->mb[1]);
5365 ha->isp_ops->fw_dump(vha, 0);
5366 } else {
5367 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
5368 }
5369
5370 return rval;
5371 }
5372
5373 int
5374 qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
5375 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
5376 {
5377 int rval;
5378 mbx_cmd_t mc;
5379 mbx_cmd_t *mcp = &mc;
5380 uint8_t subcode = (uint8_t)options;
5381 struct qla_hw_data *ha = vha->hw;
5382
5383 if (!IS_QLA8031(ha))
5384 return QLA_FUNCTION_FAILED;
5385
5386 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
5387
5388 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
5389 mcp->mb[1] = options;
5390 mcp->out_mb = MBX_1|MBX_0;
5391 if (subcode & BIT_2) {
5392 mcp->mb[2] = LSW(start_addr);
5393 mcp->mb[3] = MSW(start_addr);
5394 mcp->mb[4] = LSW(end_addr);
5395 mcp->mb[5] = MSW(end_addr);
5396 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
5397 }
5398 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5399 if (!(subcode & (BIT_2 | BIT_5)))
5400 mcp->in_mb |= MBX_4|MBX_3;
5401 mcp->tov = MBX_TOV_SECONDS;
5402 mcp->flags = 0;
5403 rval = qla2x00_mailbox_command(vha, mcp);
5404
5405 if (rval != QLA_SUCCESS) {
5406 ql_dbg(ql_dbg_mbx, vha, 0x1147,
5407 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
5408 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
5409 mcp->mb[4]);
5410 ha->isp_ops->fw_dump(vha, 0);
5411 } else {
5412 if (subcode & BIT_5)
5413 *sector_size = mcp->mb[1];
5414 else if (subcode & (BIT_6 | BIT_7)) {
5415 ql_dbg(ql_dbg_mbx, vha, 0x1148,
5416 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5417 } else if (subcode & (BIT_3 | BIT_4)) {
5418 ql_dbg(ql_dbg_mbx, vha, 0x1149,
5419 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5420 }
5421 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
5422 }
5423
5424 return rval;
5425 }
5426
5427 int
5428 qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
5429 uint32_t size)
5430 {
5431 int rval;
5432 mbx_cmd_t mc;
5433 mbx_cmd_t *mcp = &mc;
5434
5435 if (!IS_MCTP_CAPABLE(vha->hw))
5436 return QLA_FUNCTION_FAILED;
5437
5438 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
5439 "Entered %s.\n", __func__);
5440
5441 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
5442 mcp->mb[1] = LSW(addr);
5443 mcp->mb[2] = MSW(req_dma);
5444 mcp->mb[3] = LSW(req_dma);
5445 mcp->mb[4] = MSW(size);
5446 mcp->mb[5] = LSW(size);
5447 mcp->mb[6] = MSW(MSD(req_dma));
5448 mcp->mb[7] = LSW(MSD(req_dma));
5449 mcp->mb[8] = MSW(addr);
5450 /* Setting RAM ID to valid */
5451 mcp->mb[10] |= BIT_7;
5452 /* For MCTP RAM ID is 0x40 */
5453 mcp->mb[10] |= 0x40;
5454
5455 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
5456 MBX_0;
5457
5458 mcp->in_mb = MBX_0;
5459 mcp->tov = MBX_TOV_SECONDS;
5460 mcp->flags = 0;
5461 rval = qla2x00_mailbox_command(vha, mcp);
5462
5463 if (rval != QLA_SUCCESS) {
5464 ql_dbg(ql_dbg_mbx, vha, 0x114e,
5465 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5466 } else {
5467 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
5468 "Done %s.\n", __func__);
5469 }
5470
5471 return rval;
5472 }
Linux with added FPC-III support