arch/powerpc/include/asm/io.h

   1 #ifndef _ASM_POWERPC_IO_H
   2 #define _ASM_POWERPC_IO_H
   3 #ifdef __KERNEL__
   4
   5 #define ARCH_HAS_IOREMAP_WC
   6
   7 /*
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  */
  13
  14 /* Check of existence of legacy devices */
  15 extern int check_legacy_ioport(unsigned long base_port);
  16 #define I8042_DATA_REG  0x60
  17 #define FDC_BASE        0x3f0
  18
  19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
  20 extern struct pci_dev *isa_bridge_pcidev;
  21 /*
  22  * has legacy ISA devices ?
  23  */
  24 #define arch_has_dev_port()     (isa_bridge_pcidev != NULL || isa_io_special)
  25 #endif
  26
  27 #include <linux/device.h>
  28 #include <linux/compiler.h>
  29 #include <asm/page.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/synch.h>
  32 #include <asm/delay.h>
  33 #include <asm/mmu.h>
  34 #include <asm/ppc_asm.h>
  35
  36 #include <asm-generic/iomap.h>
  37
  38 #ifdef CONFIG_PPC64
  39 #include <asm/paca.h>
  40 #endif
  41
  42 #define SIO_CONFIG_RA   0x398
  43 #define SIO_CONFIG_RD   0x399
  44
  45 #define SLOW_DOWN_IO
  46
  47 /* 32 bits uses slightly different variables for the various IO
  48  * bases. Most of this file only uses _IO_BASE though which we
  49  * define properly based on the platform
  50  */
  51 #ifndef CONFIG_PCI
  52 #define _IO_BASE        0
  53 #define _ISA_MEM_BASE   0
  54 #define PCI_DRAM_OFFSET 0
  55 #elif defined(CONFIG_PPC32)
  56 #define _IO_BASE        isa_io_base
  57 #define _ISA_MEM_BASE   isa_mem_base
  58 #define PCI_DRAM_OFFSET pci_dram_offset
  59 #else
  60 #define _IO_BASE        pci_io_base
  61 #define _ISA_MEM_BASE   isa_mem_base
  62 #define PCI_DRAM_OFFSET 0
  63 #endif
  64
  65 extern unsigned long isa_io_base;
  66 extern unsigned long pci_io_base;
  67 extern unsigned long pci_dram_offset;
  68
  69 extern resource_size_t isa_mem_base;
  70
  71 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
  72  * is not set or addresses cannot be translated to MMIO. This is typically
  73  * set when the platform supports "special" PIO accesses via a non memory
  74  * mapped mechanism, and allows things like the early udbg UART code to
  75  * function.
  76  */
  77 extern bool isa_io_special;
  78
  79 #ifdef CONFIG_PPC32
  80 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
  81 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
  82 #endif
  83 #endif
  84
  85 /*
  86  *
  87  * Low level MMIO accessors
  88  *
  89  * This provides the non-bus specific accessors to MMIO. Those are PowerPC
  90  * specific and thus shouldn't be used in generic code. The accessors
  91  * provided here are:
  92  *
  93  *      in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
  94  *      out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
  95  *      _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
  96  *
  97  * Those operate directly on a kernel virtual address. Note that the prototype
  98  * for the out_* accessors has the arguments in opposite order from the usual
  99  * linux PCI accessors. Unlike those, they take the address first and the value
 100  * next.
 101  *
 102  * Note: I might drop the _ns suffix on the stream operations soon as it is
 103  * simply normal for stream operations to not swap in the first place.
 104  *
 105  */
 106
 107 #ifdef CONFIG_PPC64
 108 #define IO_SET_SYNC_FLAG()      do { local_paca->io_sync = 1; } while(0)
 109 #else
 110 #define IO_SET_SYNC_FLAG()
 111 #endif
 112
 113 /* gcc 4.0 and older doesn't have 'Z' constraint */
 114 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
 115 #define DEF_MMIO_IN_X(name, size, insn)                         \
 116 static inline u##size name(const volatile u##size __iomem *addr)        \
 117 {                                                                       \
 118         u##size ret;                                                    \
 119         __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync"    \
 120                 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory");     \
 121         return ret;                                                     \
 122 }
 123
 124 #define DEF_MMIO_OUT_X(name, size, insn)                                \
 125 static inline void name(volatile u##size __iomem *addr, u##size val)    \
 126 {                                                                       \
 127         __asm__ __volatile__("sync;"#insn" %1,0,%2"                     \
 128                 : "=m" (*addr) : "r" (val), "r" (addr) : "memory");     \
 129         IO_SET_SYNC_FLAG();                                             \
 130 }
 131 #else /* newer gcc */
 132 #define DEF_MMIO_IN_X(name, size, insn)                         \
 133 static inline u##size name(const volatile u##size __iomem *addr)        \
 134 {                                                                       \
 135         u##size ret;                                                    \
 136         __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync"     \
 137                 : "=r" (ret) : "Z" (*addr) : "memory");                 \
 138         return ret;                                                     \
 139 }
 140
 141 #define DEF_MMIO_OUT_X(name, size, insn)                                \
 142 static inline void name(volatile u##size __iomem *addr, u##size val)    \
 143 {                                                                       \
 144         __asm__ __volatile__("sync;"#insn" %1,%y0"                      \
 145                 : "=Z" (*addr) : "r" (val) : "memory");                 \
 146         IO_SET_SYNC_FLAG();                                             \
 147 }
 148 #endif
 149
 150 #define DEF_MMIO_IN_D(name, size, insn)                         \
 151 static inline u##size name(const volatile u##size __iomem *addr)        \
 152 {                                                                       \
 153         u##size ret;                                                    \
 154         __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
 155                 : "=r" (ret) : "m" (*addr) : "memory");                 \
 156         return ret;                                                     \
 157 }
 158
 159 #define DEF_MMIO_OUT_D(name, size, insn)                                \
 160 static inline void name(volatile u##size __iomem *addr, u##size val)    \
 161 {                                                                       \
 162         __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0"                 \
 163                 : "=m" (*addr) : "r" (val) : "memory");                 \
 164         IO_SET_SYNC_FLAG();                                             \
 165 }
 166
 167 DEF_MMIO_IN_D(in_8,     8, lbz);
 168 DEF_MMIO_OUT_D(out_8,   8, stb);
 169
 170 #ifdef __BIG_ENDIAN__
 171 DEF_MMIO_IN_D(in_be16, 16, lhz);
 172 DEF_MMIO_IN_D(in_be32, 32, lwz);
 173 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
 174 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
 175
 176 DEF_MMIO_OUT_D(out_be16, 16, sth);
 177 DEF_MMIO_OUT_D(out_be32, 32, stw);
 178 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
 179 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
 180 #else
 181 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
 182 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
 183 DEF_MMIO_IN_D(in_le16, 16, lhz);
 184 DEF_MMIO_IN_D(in_le32, 32, lwz);
 185
 186 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
 187 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
 188 DEF_MMIO_OUT_D(out_le16, 16, sth);
 189 DEF_MMIO_OUT_D(out_le32, 32, stw);
 190
 191 #endif /* __BIG_ENDIAN */
 192
 193 #ifdef __powerpc64__
 194
 195 #ifdef __BIG_ENDIAN__
 196 DEF_MMIO_OUT_D(out_be64, 64, std);
 197 DEF_MMIO_IN_D(in_be64, 64, ld);
 198
 199 /* There is no asm instructions for 64 bits reverse loads and stores */
 200 static inline u64 in_le64(const volatile u64 __iomem *addr)
 201 {
 202         return swab64(in_be64(addr));
 203 }
 204
 205 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
 206 {
 207         out_be64(addr, swab64(val));
 208 }
 209 #else
 210 DEF_MMIO_OUT_D(out_le64, 64, std);
 211 DEF_MMIO_IN_D(in_le64, 64, ld);
 212
 213 /* There is no asm instructions for 64 bits reverse loads and stores */
 214 static inline u64 in_be64(const volatile u64 __iomem *addr)
 215 {
 216         return swab64(in_le64(addr));
 217 }
 218
 219 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
 220 {
 221         out_le64(addr, swab64(val));
 222 }
 223
 224 #endif
 225 #endif /* __powerpc64__ */
 226
 227 /*
 228  * Low level IO stream instructions are defined out of line for now
 229  */
 230 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
 231 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
 232 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
 233 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
 234 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
 235 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
 236
 237 /* The _ns naming is historical and will be removed. For now, just #define
 238  * the non _ns equivalent names
 239  */
 240 #define _insw   _insw_ns
 241 #define _insl   _insl_ns
 242 #define _outsw  _outsw_ns
 243 #define _outsl  _outsl_ns
 244
 245
 246 /*
 247  * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
 248  */
 249
 250 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
 251 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
 252                            unsigned long n);
 253 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
 254                          unsigned long n);
 255
 256 /*
 257  *
 258  * PCI and standard ISA accessors
 259  *
 260  * Those are globally defined linux accessors for devices on PCI or ISA
 261  * busses. They follow the Linux defined semantics. The current implementation
 262  * for PowerPC is as close as possible to the x86 version of these, and thus
 263  * provides fairly heavy weight barriers for the non-raw versions
 264  *
 265  * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
 266  * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
 267  * own implementation of some or all of the accessors.
 268  */
 269
 270 /*
 271  * Include the EEH definitions when EEH is enabled only so they don't get
 272  * in the way when building for 32 bits
 273  */
 274 #ifdef CONFIG_EEH
 275 #include <asm/eeh.h>
 276 #endif
 277
 278 /* Shortcut to the MMIO argument pointer */
 279 #define PCI_IO_ADDR     volatile void __iomem *
 280
 281 /* Indirect IO address tokens:
 282  *
 283  * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
 284  * on all MMIOs. (Note that this is all 64 bits only for now)
 285  *
 286  * To help platforms who may need to differentiate MMIO addresses in
 287  * their hooks, a bitfield is reserved for use by the platform near the
 288  * top of MMIO addresses (not PIO, those have to cope the hard way).
 289  *
 290  * This bit field is 12 bits and is at the top of the IO virtual
 291  * addresses PCI_IO_INDIRECT_TOKEN_MASK.
 292  *
 293  * The kernel virtual space is thus:
 294  *
 295  *  0xD000000000000000          : vmalloc
 296  *  0xD000080000000000          : PCI PHB IO space
 297  *  0xD000080080000000          : ioremap
 298  *  0xD0000fffffffffff          : end of ioremap region
 299  *
 300  * Since the top 4 bits are reserved as the region ID, we use thus
 301  * the next 12 bits and keep 4 bits available for the future if the
 302  * virtual address space is ever to be extended.
 303  *
 304  * The direct IO mapping operations will then mask off those bits
 305  * before doing the actual access, though that only happen when
 306  * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
 307  * mechanism
 308  *
 309  * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
 310  * all PIO functions call through a hook.
 311  */
 312
 313 #ifdef CONFIG_PPC_INDIRECT_MMIO
 314 #define PCI_IO_IND_TOKEN_MASK   0x0fff000000000000ul
 315 #define PCI_IO_IND_TOKEN_SHIFT  48
 316 #define PCI_FIX_ADDR(addr)                                              \
 317         ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
 318 #define PCI_GET_ADDR_TOKEN(addr)                                        \
 319         (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >>             \
 320                 PCI_IO_IND_TOKEN_SHIFT)
 321 #define PCI_SET_ADDR_TOKEN(addr, token)                                 \
 322 do {                                                                    \
 323         unsigned long __a = (unsigned long)(addr);                      \
 324         __a &= ~PCI_IO_IND_TOKEN_MASK;                                  \
 325         __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT;      \
 326         (addr) = (void __iomem *)__a;                                   \
 327 } while(0)
 328 #else
 329 #define PCI_FIX_ADDR(addr) (addr)
 330 #endif
 331
 332
 333 /*
 334  * Non ordered and non-swapping "raw" accessors
 335  */
 336
 337 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
 338 {
 339         return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
 340 }
 341 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
 342 {
 343         return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
 344 }
 345 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
 346 {
 347         return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
 348 }
 349 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
 350 {
 351         *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
 352 }
 353 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
 354 {
 355         *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
 356 }
 357 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
 358 {
 359         *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
 360 }
 361
 362 #ifdef __powerpc64__
 363 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
 364 {
 365         return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
 366 }
 367 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
 368 {
 369         *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
 370 }
 371
 372 /*
 373  * Real mode versions of the above. Those instructions are only supposed
 374  * to be used in hypervisor real mode as per the architecture spec.
 375  */
 376 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
 377 {
 378         __asm__ __volatile__("stbcix %0,0,%1"
 379                 : : "r" (val), "r" (paddr) : "memory");
 380 }
 381
 382 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
 383 {
 384         __asm__ __volatile__("sthcix %0,0,%1"
 385                 : : "r" (val), "r" (paddr) : "memory");
 386 }
 387
 388 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
 389 {
 390         __asm__ __volatile__("stwcix %0,0,%1"
 391                 : : "r" (val), "r" (paddr) : "memory");
 392 }
 393
 394 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
 395 {
 396         __asm__ __volatile__("stdcix %0,0,%1"
 397                 : : "r" (val), "r" (paddr) : "memory");
 398 }
 399
 400 static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
 401 {
 402         u8 ret;
 403         __asm__ __volatile__("lbzcix %0,0, %1"
 404                              : "=r" (ret) : "r" (paddr) : "memory");
 405         return ret;
 406 }
 407
 408 static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
 409 {
 410         u16 ret;
 411         __asm__ __volatile__("lhzcix %0,0, %1"
 412                              : "=r" (ret) : "r" (paddr) : "memory");
 413         return ret;
 414 }
 415
 416 static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
 417 {
 418         u32 ret;
 419         __asm__ __volatile__("lwzcix %0,0, %1"
 420                              : "=r" (ret) : "r" (paddr) : "memory");
 421         return ret;
 422 }
 423
 424 static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
 425 {
 426         u64 ret;
 427         __asm__ __volatile__("ldcix %0,0, %1"
 428                              : "=r" (ret) : "r" (paddr) : "memory");
 429         return ret;
 430 }
 431 #endif /* __powerpc64__ */
 432
 433 /*
 434  *
 435  * PCI PIO and MMIO accessors.
 436  *
 437  *
 438  * On 32 bits, PIO operations have a recovery mechanism in case they trigger
 439  * machine checks (which they occasionally do when probing non existing
 440  * IO ports on some platforms, like PowerMac and 8xx).
 441  * I always found it to be of dubious reliability and I am tempted to get
 442  * rid of it one of these days. So if you think it's important to keep it,
 443  * please voice up asap. We never had it for 64 bits and I do not intend
 444  * to port it over
 445  */
 446
 447 #ifdef CONFIG_PPC32
 448
 449 #define __do_in_asm(name, op)                           \
 450 static inline unsigned int name(unsigned int port)      \
 451 {                                                       \
 452         unsigned int x;                                 \
 453         __asm__ __volatile__(                           \
 454                 "sync\n"                                \
 455                 "0:"    op "    %0,0,%1\n"              \
 456                 "1:     twi     0,%0,0\n"               \
 457                 "2:     isync\n"                        \
 458                 "3:     nop\n"                          \
 459                 "4:\n"                                  \
 460                 ".section .fixup,\"ax\"\n"              \
 461                 "5:     li      %0,-1\n"                \
 462                 "       b       4b\n"                   \
 463                 ".previous\n"                           \
 464                 EX_TABLE(0b, 5b)                        \
 465                 EX_TABLE(1b, 5b)                        \
 466                 EX_TABLE(2b, 5b)                        \
 467                 EX_TABLE(3b, 5b)                        \
 468                 : "=&r" (x)                             \
 469                 : "r" (port + _IO_BASE)                 \
 470                 : "memory");                            \
 471         return x;                                       \
 472 }
 473
 474 #define __do_out_asm(name, op)                          \
 475 static inline void name(unsigned int val, unsigned int port) \
 476 {                                                       \
 477         __asm__ __volatile__(                           \
 478                 "sync\n"                                \
 479                 "0:" op " %0,0,%1\n"                    \
 480                 "1:     sync\n"                         \
 481                 "2:\n"                                  \
 482                 EX_TABLE(0b, 2b)                        \
 483                 EX_TABLE(1b, 2b)                        \
 484                 : : "r" (val), "r" (port + _IO_BASE)    \
 485                 : "memory");                            \
 486 }
 487
 488 __do_in_asm(_rec_inb, "lbzx")
 489 __do_in_asm(_rec_inw, "lhbrx")
 490 __do_in_asm(_rec_inl, "lwbrx")
 491 __do_out_asm(_rec_outb, "stbx")
 492 __do_out_asm(_rec_outw, "sthbrx")
 493 __do_out_asm(_rec_outl, "stwbrx")
 494
 495 #endif /* CONFIG_PPC32 */
 496
 497 /* The "__do_*" operations below provide the actual "base" implementation
 498  * for each of the defined accessors. Some of them use the out_* functions
 499  * directly, some of them still use EEH, though we might change that in the
 500  * future. Those macros below provide the necessary argument swapping and
 501  * handling of the IO base for PIO.
 502  *
 503  * They are themselves used by the macros that define the actual accessors
 504  * and can be used by the hooks if any.
 505  *
 506  * Note that PIO operations are always defined in terms of their corresonding
 507  * MMIO operations. That allows platforms like iSeries who want to modify the
 508  * behaviour of both to only hook on the MMIO version and get both. It's also
 509  * possible to hook directly at the toplevel PIO operation if they have to
 510  * be handled differently
 511  */
 512 #define __do_writeb(val, addr)  out_8(PCI_FIX_ADDR(addr), val)
 513 #define __do_writew(val, addr)  out_le16(PCI_FIX_ADDR(addr), val)
 514 #define __do_writel(val, addr)  out_le32(PCI_FIX_ADDR(addr), val)
 515 #define __do_writeq(val, addr)  out_le64(PCI_FIX_ADDR(addr), val)
 516 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
 517 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
 518 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
 519
 520 #ifdef CONFIG_EEH
 521 #define __do_readb(addr)        eeh_readb(PCI_FIX_ADDR(addr))
 522 #define __do_readw(addr)        eeh_readw(PCI_FIX_ADDR(addr))
 523 #define __do_readl(addr)        eeh_readl(PCI_FIX_ADDR(addr))
 524 #define __do_readq(addr)        eeh_readq(PCI_FIX_ADDR(addr))
 525 #define __do_readw_be(addr)     eeh_readw_be(PCI_FIX_ADDR(addr))
 526 #define __do_readl_be(addr)     eeh_readl_be(PCI_FIX_ADDR(addr))
 527 #define __do_readq_be(addr)     eeh_readq_be(PCI_FIX_ADDR(addr))
 528 #else /* CONFIG_EEH */
 529 #define __do_readb(addr)        in_8(PCI_FIX_ADDR(addr))
 530 #define __do_readw(addr)        in_le16(PCI_FIX_ADDR(addr))
 531 #define __do_readl(addr)        in_le32(PCI_FIX_ADDR(addr))
 532 #define __do_readq(addr)        in_le64(PCI_FIX_ADDR(addr))
 533 #define __do_readw_be(addr)     in_be16(PCI_FIX_ADDR(addr))
 534 #define __do_readl_be(addr)     in_be32(PCI_FIX_ADDR(addr))
 535 #define __do_readq_be(addr)     in_be64(PCI_FIX_ADDR(addr))
 536 #endif /* !defined(CONFIG_EEH) */
 537
 538 #ifdef CONFIG_PPC32
 539 #define __do_outb(val, port)    _rec_outb(val, port)
 540 #define __do_outw(val, port)    _rec_outw(val, port)
 541 #define __do_outl(val, port)    _rec_outl(val, port)
 542 #define __do_inb(port)          _rec_inb(port)
 543 #define __do_inw(port)          _rec_inw(port)
 544 #define __do_inl(port)          _rec_inl(port)
 545 #else /* CONFIG_PPC32 */
 546 #define __do_outb(val, port)    writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
 547 #define __do_outw(val, port)    writew(val,(PCI_IO_ADDR)_IO_BASE+port);
 548 #define __do_outl(val, port)    writel(val,(PCI_IO_ADDR)_IO_BASE+port);
 549 #define __do_inb(port)          readb((PCI_IO_ADDR)_IO_BASE + port);
 550 #define __do_inw(port)          readw((PCI_IO_ADDR)_IO_BASE + port);
 551 #define __do_inl(port)          readl((PCI_IO_ADDR)_IO_BASE + port);
 552 #endif /* !CONFIG_PPC32 */
 553
 554 #ifdef CONFIG_EEH
 555 #define __do_readsb(a, b, n)    eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
 556 #define __do_readsw(a, b, n)    eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
 557 #define __do_readsl(a, b, n)    eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
 558 #else /* CONFIG_EEH */
 559 #define __do_readsb(a, b, n)    _insb(PCI_FIX_ADDR(a), (b), (n))
 560 #define __do_readsw(a, b, n)    _insw(PCI_FIX_ADDR(a), (b), (n))
 561 #define __do_readsl(a, b, n)    _insl(PCI_FIX_ADDR(a), (b), (n))
 562 #endif /* !CONFIG_EEH */
 563 #define __do_writesb(a, b, n)   _outsb(PCI_FIX_ADDR(a),(b),(n))
 564 #define __do_writesw(a, b, n)   _outsw(PCI_FIX_ADDR(a),(b),(n))
 565 #define __do_writesl(a, b, n)   _outsl(PCI_FIX_ADDR(a),(b),(n))
 566
 567 #define __do_insb(p, b, n)      readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 568 #define __do_insw(p, b, n)      readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 569 #define __do_insl(p, b, n)      readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 570 #define __do_outsb(p, b, n)     writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 571 #define __do_outsw(p, b, n)     writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 572 #define __do_outsl(p, b, n)     writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 573
 574 #define __do_memset_io(addr, c, n)      \
 575                                 _memset_io(PCI_FIX_ADDR(addr), c, n)
 576 #define __do_memcpy_toio(dst, src, n)   \
 577                                 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
 578
 579 #ifdef CONFIG_EEH
 580 #define __do_memcpy_fromio(dst, src, n) \
 581                                 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
 582 #else /* CONFIG_EEH */
 583 #define __do_memcpy_fromio(dst, src, n) \
 584                                 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
 585 #endif /* !CONFIG_EEH */
 586
 587 #ifdef CONFIG_PPC_INDIRECT_PIO
 588 #define DEF_PCI_HOOK_pio(x)     x
 589 #else
 590 #define DEF_PCI_HOOK_pio(x)     NULL
 591 #endif
 592
 593 #ifdef CONFIG_PPC_INDIRECT_MMIO
 594 #define DEF_PCI_HOOK_mem(x)     x
 595 #else
 596 #define DEF_PCI_HOOK_mem(x)     NULL
 597 #endif
 598
 599 /* Structure containing all the hooks */
 600 extern struct ppc_pci_io {
 601
 602 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)    ret (*name) at;
 603 #define DEF_PCI_AC_NORET(name, at, al, space, aa)       void (*name) at;
 604
 605 #include <asm/io-defs.h>
 606
 607 #undef DEF_PCI_AC_RET
 608 #undef DEF_PCI_AC_NORET
 609
 610 } ppc_pci_io;
 611
 612 /* The inline wrappers */
 613 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)            \
 614 static inline ret name at                                       \
 615 {                                                               \
 616         if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)      \
 617                 return ppc_pci_io.name al;                      \
 618         return __do_##name al;                                  \
 619 }
 620
 621 #define DEF_PCI_AC_NORET(name, at, al, space, aa)               \
 622 static inline void name at                                      \
 623 {                                                               \
 624         if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)              \
 625                 ppc_pci_io.name al;                             \
 626         else                                                    \
 627                 __do_##name al;                                 \
 628 }
 629
 630 #include <asm/io-defs.h>
 631
 632 #undef DEF_PCI_AC_RET
 633 #undef DEF_PCI_AC_NORET
 634
 635 /* Some drivers check for the presence of readq & writeq with
 636  * a #ifdef, so we make them happy here.
 637  */
 638 #ifdef __powerpc64__
 639 #define readq   readq
 640 #define writeq  writeq
 641 #endif
 642
 643 /*
 644  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 645  * access
 646  */
 647 #define xlate_dev_mem_ptr(p)    __va(p)
 648
 649 /*
 650  * Convert a virtual cached pointer to an uncached pointer
 651  */
 652 #define xlate_dev_kmem_ptr(p)   p
 653
 654 /*
 655  * We don't do relaxed operations yet, at least not with this semantic
 656  */
 657 #define readb_relaxed(addr)     readb(addr)
 658 #define readw_relaxed(addr)     readw(addr)
 659 #define readl_relaxed(addr)     readl(addr)
 660 #define readq_relaxed(addr)     readq(addr)
 661 #define writeb_relaxed(v, addr) writeb(v, addr)
 662 #define writew_relaxed(v, addr) writew(v, addr)
 663 #define writel_relaxed(v, addr) writel(v, addr)
 664 #define writeq_relaxed(v, addr) writeq(v, addr)
 665
 666 #ifdef CONFIG_PPC32
 667 #define mmiowb()
 668 #else
 669 /*
 670  * Enforce synchronisation of stores vs. spin_unlock
 671  * (this does it explicitly, though our implementation of spin_unlock
 672  * does it implicitely too)
 673  */
 674 static inline void mmiowb(void)
 675 {
 676         unsigned long tmp;
 677
 678         __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
 679         : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
 680         : "memory");
 681 }
 682 #endif /* !CONFIG_PPC32 */
 683
 684 static inline void iosync(void)
 685 {
 686         __asm__ __volatile__ ("sync" : : : "memory");
 687 }
 688
 689 /* Enforce in-order execution of data I/O.
 690  * No distinction between read/write on PPC; use eieio for all three.
 691  * Those are fairly week though. They don't provide a barrier between
 692  * MMIO and cacheable storage nor do they provide a barrier vs. locks,
 693  * they only provide barriers between 2 __raw MMIO operations and
 694  * possibly break write combining.
 695  */
 696 #define iobarrier_rw() eieio()
 697 #define iobarrier_r()  eieio()
 698 #define iobarrier_w()  eieio()
 699
 700
 701 /*
 702  * output pause versions need a delay at least for the
 703  * w83c105 ide controller in a p610.
 704  */
 705 #define inb_p(port)             inb(port)
 706 #define outb_p(val, port)       (udelay(1), outb((val), (port)))
 707 #define inw_p(port)             inw(port)
 708 #define outw_p(val, port)       (udelay(1), outw((val), (port)))
 709 #define inl_p(port)             inl(port)
 710 #define outl_p(val, port)       (udelay(1), outl((val), (port)))
 711
 712
 713 #define IO_SPACE_LIMIT ~(0UL)
 714
 715
 716 /**
 717  * ioremap     -   map bus memory into CPU space
 718  * @address:   bus address of the memory
 719  * @size:      size of the resource to map
 720  *
 721  * ioremap performs a platform specific sequence of operations to
 722  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 723  * writew/writel functions and the other mmio helpers. The returned
 724  * address is not guaranteed to be usable directly as a virtual
 725  * address.
 726  *
 727  * We provide a few variations of it:
 728  *
 729  * * ioremap is the standard one and provides non-cacheable guarded mappings
 730  *   and can be hooked by the platform via ppc_md
 731  *
 732  * * ioremap_prot allows to specify the page flags as an argument and can
 733  *   also be hooked by the platform via ppc_md.
 734  *
 735  * * ioremap_nocache is identical to ioremap
 736  *
 737  * * ioremap_wc enables write combining
 738  *
 739  * * iounmap undoes such a mapping and can be hooked
 740  *
 741  * * __ioremap_at (and the pending __iounmap_at) are low level functions to
 742  *   create hand-made mappings for use only by the PCI code and cannot
 743  *   currently be hooked. Must be page aligned.
 744  *
 745  * * __ioremap is the low level implementation used by ioremap and
 746  *   ioremap_prot and cannot be hooked (but can be used by a hook on one
 747  *   of the previous ones)
 748  *
 749  * * __ioremap_caller is the same as above but takes an explicit caller
 750  *   reference rather than using __builtin_return_address(0)
 751  *
 752  * * __iounmap, is the low level implementation used by iounmap and cannot
 753  *   be hooked (but can be used by a hook on iounmap)
 754  *
 755  */
 756 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
 757 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
 758                                   unsigned long flags);
 759 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
 760 #define ioremap_nocache(addr, size)     ioremap((addr), (size))
 761 #define ioremap_uc(addr, size)          ioremap((addr), (size))
 762 #define ioremap_cache(addr, size) \
 763         ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
 764
 765 extern void iounmap(volatile void __iomem *addr);
 766
 767 extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
 768                                unsigned long flags);
 769 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
 770                                       unsigned long flags, void *caller);
 771
 772 extern void __iounmap(volatile void __iomem *addr);
 773
 774 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
 775                                    unsigned long size, unsigned long flags);
 776 extern void __iounmap_at(void *ea, unsigned long size);
 777
 778 /*
 779  * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
 780  * which needs some additional definitions here. They basically allow PIO
 781  * space overall to be 1GB. This will work as long as we never try to use
 782  * iomap to map MMIO below 1GB which should be fine on ppc64
 783  */
 784 #define HAVE_ARCH_PIO_SIZE              1
 785 #define PIO_OFFSET                      0x00000000UL
 786 #define PIO_MASK                        (FULL_IO_SIZE - 1)
 787 #define PIO_RESERVED                    (FULL_IO_SIZE)
 788
 789 #define mmio_read16be(addr)             readw_be(addr)
 790 #define mmio_read32be(addr)             readl_be(addr)
 791 #define mmio_write16be(val, addr)       writew_be(val, addr)
 792 #define mmio_write32be(val, addr)       writel_be(val, addr)
 793 #define mmio_insb(addr, dst, count)     readsb(addr, dst, count)
 794 #define mmio_insw(addr, dst, count)     readsw(addr, dst, count)
 795 #define mmio_insl(addr, dst, count)     readsl(addr, dst, count)
 796 #define mmio_outsb(addr, src, count)    writesb(addr, src, count)
 797 #define mmio_outsw(addr, src, count)    writesw(addr, src, count)
 798 #define mmio_outsl(addr, src, count)    writesl(addr, src, count)
 799
 800 /**
 801  *      virt_to_phys    -       map virtual addresses to physical
 802  *      @address: address to remap
 803  *
 804  *      The returned physical address is the physical (CPU) mapping for
 805  *      the memory address given. It is only valid to use this function on
 806  *      addresses directly mapped or allocated via kmalloc.
 807  *
 808  *      This function does not give bus mappings for DMA transfers. In
 809  *      almost all conceivable cases a device driver should not be using
 810  *      this function
 811  */
 812 static inline unsigned long virt_to_phys(volatile void * address)
 813 {
 814         return __pa((unsigned long)address);
 815 }
 816
 817 /**
 818  *      phys_to_virt    -       map physical address to virtual
 819  *      @address: address to remap
 820  *
 821  *      The returned virtual address is a current CPU mapping for
 822  *      the memory address given. It is only valid to use this function on
 823  *      addresses that have a kernel mapping
 824  *
 825  *      This function does not handle bus mappings for DMA transfers. In
 826  *      almost all conceivable cases a device driver should not be using
 827  *      this function
 828  */
 829 static inline void * phys_to_virt(unsigned long address)
 830 {
 831         return (void *)__va(address);
 832 }
 833
 834 /*
 835  * Change "struct page" to physical address.
 836  */
 837 #define page_to_phys(page)      ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 838
 839 /*
 840  * 32 bits still uses virt_to_bus() for it's implementation of DMA
 841  * mappings se we have to keep it defined here. We also have some old
 842  * drivers (shame shame shame) that use bus_to_virt() and haven't been
 843  * fixed yet so I need to define it here.
 844  */
 845 #ifdef CONFIG_PPC32
 846
 847 static inline unsigned long virt_to_bus(volatile void * address)
 848 {
 849         if (address == NULL)
 850                 return 0;
 851         return __pa(address) + PCI_DRAM_OFFSET;
 852 }
 853
 854 static inline void * bus_to_virt(unsigned long address)
 855 {
 856         if (address == 0)
 857                 return NULL;
 858         return __va(address - PCI_DRAM_OFFSET);
 859 }
 860
 861 #define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
 862
 863 #endif /* CONFIG_PPC32 */
 864
 865 /* access ports */
 866 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
 867 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
 868
 869 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
 870 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
 871
 872 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) |  (_v))
 873 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
 874
 875 /* Clear and set bits in one shot.  These macros can be used to clear and
 876  * set multiple bits in a register using a single read-modify-write.  These
 877  * macros can also be used to set a multiple-bit bit pattern using a mask,
 878  * by specifying the mask in the 'clear' parameter and the new bit pattern
 879  * in the 'set' parameter.
 880  */
 881
 882 #define clrsetbits(type, addr, clear, set) \
 883         out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
 884
 885 #ifdef __powerpc64__
 886 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
 887 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
 888 #endif
 889
 890 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
 891 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
 892
 893 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
 894 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
 895
 896 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
 897
 898 #endif /* __KERNEL__ */
 899
 900 #endif /* _ASM_POWERPC_IO_H */