arch/powerpc/include/asm/mmu-8xx.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_MMU_8XX_H_
   3 #define _ASM_POWERPC_MMU_8XX_H_
   4 /*
   5  * PPC8xx support
   6  */
   7
   8 /* Control/status registers for the MPC8xx.
   9  * A write operation to these registers causes serialized access.
  10  * During software tablewalk, the registers used perform mask/shift-add
  11  * operations when written/read.  A TLB entry is created when the Mx_RPN
  12  * is written, and the contents of several registers are used to
  13  * create the entry.
  14  */
  15 #define SPRN_MI_CTR     784     /* Instruction TLB control register */
  16 #define MI_GPM          0x80000000      /* Set domain manager mode */
  17 #define MI_PPM          0x40000000      /* Set subpage protection */
  18 #define MI_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
  19 #define MI_RSV4I        0x08000000      /* Reserve 4 TLB entries */
  20 #define MI_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
  21 #define MI_IDXMASK      0x00001f00      /* TLB index to be loaded */
  22 #define MI_RESETVAL     0x00000000      /* Value of register at reset */
  23
  24 /* These are the Ks and Kp from the PowerPC books.  For proper operation,
  25  * Ks = 0, Kp = 1.
  26  */
  27 #define SPRN_MI_AP      786
  28 #define MI_Ks           0x80000000      /* Should not be set */
  29 #define MI_Kp           0x40000000      /* Should always be set */
  30
  31 /*
  32  * All pages' PP data bits are set to either 001 or 011 by copying _PAGE_EXEC
  33  * into bit 21 in the ITLBmiss handler (bit 21 is the middle bit), which means
  34  * respectively NA for All or X for Supervisor and no access for User.
  35  * Then we use the APG to say whether accesses are according to Page rules or
  36  * "all Supervisor" rules (Access to all)
  37  * We also use the 2nd APG bit for _PAGE_ACCESSED when having SWAP:
  38  * When that bit is not set access is done iaw "all user"
  39  * which means no access iaw page rules.
  40  * Therefore, we define 4 APG groups. lsb is _PMD_USER, 2nd is _PAGE_ACCESSED
  41  * 0x => No access => 11 (all accesses performed as user iaw page definition)
  42  * 10 => No user => 01 (all accesses performed according to page definition)
  43  * 11 => User => 00 (all accesses performed as supervisor iaw page definition)
  44  * We define all 16 groups so that all other bits of APG can take any value
  45  */
  46 #ifdef CONFIG_SWAP
  47 #define MI_APG_INIT     0xf4f4f4f4
  48 #else
  49 #define MI_APG_INIT     0x44444444
  50 #endif
  51
  52 /* The effective page number register.  When read, contains the information
  53  * about the last instruction TLB miss.  When MI_RPN is written, bits in
  54  * this register are used to create the TLB entry.
  55  */
  56 #define SPRN_MI_EPN     787
  57 #define MI_EPNMASK      0xfffff000      /* Effective page number for entry */
  58 #define MI_EVALID       0x00000200      /* Entry is valid */
  59 #define MI_ASIDMASK     0x0000000f      /* ASID match value */
  60                                         /* Reset value is undefined */
  61
  62 /* A "level 1" or "segment" or whatever you want to call it register.
  63  * For the instruction TLB, it contains bits that get loaded into the
  64  * TLB entry when the MI_RPN is written.
  65  */
  66 #define SPRN_MI_TWC     789
  67 #define MI_APG          0x000001e0      /* Access protection group (0) */
  68 #define MI_GUARDED      0x00000010      /* Guarded storage */
  69 #define MI_PSMASK       0x0000000c      /* Mask of page size bits */
  70 #define MI_PS8MEG       0x0000000c      /* 8M page size */
  71 #define MI_PS512K       0x00000004      /* 512K page size */
  72 #define MI_PS4K_16K     0x00000000      /* 4K or 16K page size */
  73 #define MI_SVALID       0x00000001      /* Segment entry is valid */
  74                                         /* Reset value is undefined */
  75
  76 /* Real page number.  Defined by the pte.  Writing this register
  77  * causes a TLB entry to be created for the instruction TLB, using
  78  * additional information from the MI_EPN, and MI_TWC registers.
  79  */
  80 #define SPRN_MI_RPN     790
  81 #define MI_SPS16K       0x00000008      /* Small page size (0 = 4k, 1 = 16k) */
  82
  83 /* Define an RPN value for mapping kernel memory to large virtual
  84  * pages for boot initialization.  This has real page number of 0,
  85  * large page size, shared page, cache enabled, and valid.
  86  * Also mark all subpages valid and write access.
  87  */
  88 #define MI_BOOTINIT     0x000001fd
  89
  90 #define SPRN_MD_CTR     792     /* Data TLB control register */
  91 #define MD_GPM          0x80000000      /* Set domain manager mode */
  92 #define MD_PPM          0x40000000      /* Set subpage protection */
  93 #define MD_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
  94 #define MD_WTDEF        0x10000000      /* Set writethrough when MMU dis */
  95 #define MD_RSV4I        0x08000000      /* Reserve 4 TLB entries */
  96 #define MD_TWAM         0x04000000      /* Use 4K page hardware assist */
  97 #define MD_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
  98 #define MD_IDXMASK      0x00001f00      /* TLB index to be loaded */
  99 #define MD_RESETVAL     0x04000000      /* Value of register at reset */
 100
 101 #define SPRN_M_CASID    793     /* Address space ID (context) to match */
 102 #define MC_ASIDMASK     0x0000000f      /* Bits used for ASID value */
 103
 104
 105 /* These are the Ks and Kp from the PowerPC books.  For proper operation,
 106  * Ks = 0, Kp = 1.
 107  */
 108 #define SPRN_MD_AP      794
 109 #define MD_Ks           0x80000000      /* Should not be set */
 110 #define MD_Kp           0x40000000      /* Should always be set */
 111
 112 /*
 113  * All pages' PP data bits are set to either 000 or 011 or 001, which means
 114  * respectively RW for Supervisor and no access for User, or RO for
 115  * Supervisor and no access for user and NA for ALL.
 116  * Then we use the APG to say whether accesses are according to Page rules or
 117  * "all Supervisor" rules (Access to all)
 118  * We also use the 2nd APG bit for _PAGE_ACCESSED when having SWAP:
 119  * When that bit is not set access is done iaw "all user"
 120  * which means no access iaw page rules.
 121  * Therefore, we define 4 APG groups. lsb is _PMD_USER, 2nd is _PAGE_ACCESSED
 122  * 0x => No access => 11 (all accesses performed as user iaw page definition)
 123  * 10 => No user => 01 (all accesses performed according to page definition)
 124  * 11 => User => 00 (all accesses performed as supervisor iaw page definition)
 125  * We define all 16 groups so that all other bits of APG can take any value
 126  */
 127 #ifdef CONFIG_SWAP
 128 #define MD_APG_INIT     0xf4f4f4f4
 129 #else
 130 #define MD_APG_INIT     0x44444444
 131 #endif
 132
 133 /* The effective page number register.  When read, contains the information
 134  * about the last instruction TLB miss.  When MD_RPN is written, bits in
 135  * this register are used to create the TLB entry.
 136  */
 137 #define SPRN_MD_EPN     795
 138 #define MD_EPNMASK      0xfffff000      /* Effective page number for entry */
 139 #define MD_EVALID       0x00000200      /* Entry is valid */
 140 #define MD_ASIDMASK     0x0000000f      /* ASID match value */
 141                                         /* Reset value is undefined */
 142
 143 /* The pointer to the base address of the first level page table.
 144  * During a software tablewalk, reading this register provides the address
 145  * of the entry associated with MD_EPN.
 146  */
 147 #define SPRN_M_TWB      796
 148 #define M_L1TB          0xfffff000      /* Level 1 table base address */
 149 #define M_L1INDX        0x00000ffc      /* Level 1 index, when read */
 150                                         /* Reset value is undefined */
 151
 152 /* A "level 1" or "segment" or whatever you want to call it register.
 153  * For the data TLB, it contains bits that get loaded into the TLB entry
 154  * when the MD_RPN is written.  It is also provides the hardware assist
 155  * for finding the PTE address during software tablewalk.
 156  */
 157 #define SPRN_MD_TWC     797
 158 #define MD_L2TB         0xfffff000      /* Level 2 table base address */
 159 #define MD_L2INDX       0xfffffe00      /* Level 2 index (*pte), when read */
 160 #define MD_APG          0x000001e0      /* Access protection group (0) */
 161 #define MD_GUARDED      0x00000010      /* Guarded storage */
 162 #define MD_PSMASK       0x0000000c      /* Mask of page size bits */
 163 #define MD_PS8MEG       0x0000000c      /* 8M page size */
 164 #define MD_PS512K       0x00000004      /* 512K page size */
 165 #define MD_PS4K_16K     0x00000000      /* 4K or 16K page size */
 166 #define MD_WT           0x00000002      /* Use writethrough page attribute */
 167 #define MD_SVALID       0x00000001      /* Segment entry is valid */
 168                                         /* Reset value is undefined */
 169
 170
 171 /* Real page number.  Defined by the pte.  Writing this register
 172  * causes a TLB entry to be created for the data TLB, using
 173  * additional information from the MD_EPN, and MD_TWC registers.
 174  */
 175 #define SPRN_MD_RPN     798
 176 #define MD_SPS16K       0x00000008      /* Small page size (0 = 4k, 1 = 16k) */
 177
 178 /* This is a temporary storage register that could be used to save
 179  * a processor working register during a tablewalk.
 180  */
 181 #define SPRN_M_TW       799
 182
 183 /* APGs */
 184 #define M_APG0          0x00000000
 185 #define M_APG1          0x00000020
 186 #define M_APG2          0x00000040
 187 #define M_APG3          0x00000060
 188
 189 #ifndef __ASSEMBLY__
 190 typedef struct {
 191         unsigned int id;
 192         unsigned int active;
 193         unsigned long vdso_base;
 194 } mm_context_t;
 195
 196 #define PHYS_IMMR_BASE (mfspr(SPRN_IMMR) & 0xfff80000)
 197 #define VIRT_IMMR_BASE (__fix_to_virt(FIX_IMMR_BASE))
 198
 199 /* Page size definitions, common between 32 and 64-bit
 200  *
 201  *    shift : is the "PAGE_SHIFT" value for that page size
 202  *    penc  : is the pte encoding mask
 203  *
 204  */
 205 struct mmu_psize_def {
 206         unsigned int    shift;  /* number of bits */
 207         unsigned int    enc;    /* PTE encoding */
 208         unsigned int    ind;    /* Corresponding indirect page size shift */
 209         unsigned int    flags;
 210 #define MMU_PAGE_SIZE_DIRECT    0x1     /* Supported as a direct size */
 211 #define MMU_PAGE_SIZE_INDIRECT  0x2     /* Supported as an indirect size */
 212 };
 213
 214 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 215
 216 static inline int shift_to_mmu_psize(unsigned int shift)
 217 {
 218         int psize;
 219
 220         for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
 221                 if (mmu_psize_defs[psize].shift == shift)
 222                         return psize;
 223         return -1;
 224 }
 225
 226 static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
 227 {
 228         if (mmu_psize_defs[mmu_psize].shift)
 229                 return mmu_psize_defs[mmu_psize].shift;
 230         BUG();
 231 }
 232
 233 #endif /* !__ASSEMBLY__ */
 234
 235 #if defined(CONFIG_PPC_4K_PAGES)
 236 #define mmu_virtual_psize       MMU_PAGE_4K
 237 #elif defined(CONFIG_PPC_16K_PAGES)
 238 #define mmu_virtual_psize       MMU_PAGE_16K
 239 #else
 240 #error "Unsupported PAGE_SIZE"
 241 #endif
 242
 243 #define mmu_linear_psize        MMU_PAGE_8M
 244
 245 #endif /* _ASM_POWERPC_MMU_8XX_H_ */