arch/powerpc/include/asm/nohash/pgtable.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_NOHASH_PGTABLE_H
   3 #define _ASM_POWERPC_NOHASH_PGTABLE_H
   4
   5 #if defined(CONFIG_PPC64)
   6 #include <asm/nohash/64/pgtable.h>
   7 #else
   8 #include <asm/nohash/32/pgtable.h>
   9 #endif
  10
  11 #ifndef __ASSEMBLY__
  12
  13 /* Generic accessors to PTE bits */
  14 static inline int pte_write(pte_t pte)
  15 {
  16         return (pte_val(pte) & (_PAGE_RW | _PAGE_RO)) != _PAGE_RO;
  17 }
  18 static inline int pte_read(pte_t pte)           { return 1; }
  19 static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
  20 static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
  21 static inline int pte_special(pte_t pte)        { return pte_val(pte) & _PAGE_SPECIAL; }
  22 static inline int pte_none(pte_t pte)           { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
  23 static inline pgprot_t pte_pgprot(pte_t pte)    { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
  24
  25 #ifdef CONFIG_NUMA_BALANCING
  26 /*
  27  * These work without NUMA balancing but the kernel does not care. See the
  28  * comment in include/asm-generic/pgtable.h . On powerpc, this will only
  29  * work for user pages and always return true for kernel pages.
  30  */
  31 static inline int pte_protnone(pte_t pte)
  32 {
  33         return (pte_val(pte) &
  34                 (_PAGE_PRESENT | _PAGE_USER)) == _PAGE_PRESENT;
  35 }
  36
  37 static inline int pmd_protnone(pmd_t pmd)
  38 {
  39         return pte_protnone(pmd_pte(pmd));
  40 }
  41 #endif /* CONFIG_NUMA_BALANCING */
  42
  43 static inline int pte_present(pte_t pte)
  44 {
  45         return pte_val(pte) & _PAGE_PRESENT;
  46 }
  47
  48 /*
  49  * We only find page table entry in the last level
  50  * Hence no need for other accessors
  51  */
  52 #define pte_access_permitted pte_access_permitted
  53 static inline bool pte_access_permitted(pte_t pte, bool write)
  54 {
  55         unsigned long pteval = pte_val(pte);
  56         /*
  57          * A read-only access is controlled by _PAGE_USER bit.
  58          * We have _PAGE_READ set for WRITE and EXECUTE
  59          */
  60         unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_USER;
  61
  62         if (write)
  63                 need_pte_bits |= _PAGE_WRITE;
  64
  65         if ((pteval & need_pte_bits) != need_pte_bits)
  66                 return false;
  67
  68         return true;
  69 }
  70
  71 /* Conversion functions: convert a page and protection to a page entry,
  72  * and a page entry and page directory to the page they refer to.
  73  *
  74  * Even if PTEs can be unsigned long long, a PFN is always an unsigned
  75  * long for now.
  76  */
  77 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) {
  78         return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
  79                      pgprot_val(pgprot)); }
  80 static inline unsigned long pte_pfn(pte_t pte)  {
  81         return pte_val(pte) >> PTE_RPN_SHIFT; }
  82
  83 /* Generic modifiers for PTE bits */
  84 static inline pte_t pte_wrprotect(pte_t pte)
  85 {
  86         pte_basic_t ptev;
  87
  88         ptev = pte_val(pte) & ~(_PAGE_RW | _PAGE_HWWRITE);
  89         ptev |= _PAGE_RO;
  90         return __pte(ptev);
  91 }
  92
  93 static inline pte_t pte_mkclean(pte_t pte)
  94 {
  95         return __pte(pte_val(pte) & ~(_PAGE_DIRTY | _PAGE_HWWRITE));
  96 }
  97
  98 static inline pte_t pte_mkold(pte_t pte)
  99 {
 100         return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
 101 }
 102
 103 static inline pte_t pte_mkwrite(pte_t pte)
 104 {
 105         pte_basic_t ptev;
 106
 107         ptev = pte_val(pte) & ~_PAGE_RO;
 108         ptev |= _PAGE_RW;
 109         return __pte(ptev);
 110 }
 111
 112 static inline pte_t pte_mkdirty(pte_t pte)
 113 {
 114         return __pte(pte_val(pte) | _PAGE_DIRTY);
 115 }
 116
 117 static inline pte_t pte_mkyoung(pte_t pte)
 118 {
 119         return __pte(pte_val(pte) | _PAGE_ACCESSED);
 120 }
 121
 122 static inline pte_t pte_mkspecial(pte_t pte)
 123 {
 124         return __pte(pte_val(pte) | _PAGE_SPECIAL);
 125 }
 126
 127 static inline pte_t pte_mkhuge(pte_t pte)
 128 {
 129         return __pte(pte_val(pte) | _PAGE_HUGE);
 130 }
 131
 132 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 133 {
 134         return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
 135 }
 136
 137 /* Insert a PTE, top-level function is out of line. It uses an inline
 138  * low level function in the respective pgtable-* files
 139  */
 140 extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
 141                        pte_t pte);
 142
 143 /* This low level function performs the actual PTE insertion
 144  * Setting the PTE depends on the MMU type and other factors. It's
 145  * an horrible mess that I'm not going to try to clean up now but
 146  * I'm keeping it in one place rather than spread around
 147  */
 148 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
 149                                 pte_t *ptep, pte_t pte, int percpu)
 150 {
 151 #if defined(CONFIG_PPC_STD_MMU_32) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
 152         /* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the
 153          * helper pte_update() which does an atomic update. We need to do that
 154          * because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a
 155          * per-CPU PTE such as a kmap_atomic, we do a simple update preserving
 156          * the hash bits instead (ie, same as the non-SMP case)
 157          */
 158         if (percpu)
 159                 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
 160                               | (pte_val(pte) & ~_PAGE_HASHPTE));
 161         else
 162                 pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
 163
 164 #elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
 165         /* Second case is 32-bit with 64-bit PTE.  In this case, we
 166          * can just store as long as we do the two halves in the right order
 167          * with a barrier in between. This is possible because we take care,
 168          * in the hash code, to pre-invalidate if the PTE was already hashed,
 169          * which synchronizes us with any concurrent invalidation.
 170          * In the percpu case, we also fallback to the simple update preserving
 171          * the hash bits
 172          */
 173         if (percpu) {
 174                 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
 175                               | (pte_val(pte) & ~_PAGE_HASHPTE));
 176                 return;
 177         }
 178 #if _PAGE_HASHPTE != 0
 179         if (pte_val(*ptep) & _PAGE_HASHPTE)
 180                 flush_hash_entry(mm, ptep, addr);
 181 #endif
 182         __asm__ __volatile__("\
 183                 stw%U0%X0 %2,%0\n\
 184                 eieio\n\
 185                 stw%U0%X0 %L2,%1"
 186         : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
 187         : "r" (pte) : "memory");
 188
 189 #elif defined(CONFIG_PPC_STD_MMU_32)
 190         /* Third case is 32-bit hash table in UP mode, we need to preserve
 191          * the _PAGE_HASHPTE bit since we may not have invalidated the previous
 192          * translation in the hash yet (done in a subsequent flush_tlb_xxx())
 193          * and see we need to keep track that this PTE needs invalidating
 194          */
 195         *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
 196                       | (pte_val(pte) & ~_PAGE_HASHPTE));
 197
 198 #else
 199         /* Anything else just stores the PTE normally. That covers all 64-bit
 200          * cases, and 32-bit non-hash with 32-bit PTEs.
 201          */
 202         *ptep = pte;
 203
 204 #ifdef CONFIG_PPC_BOOK3E_64
 205         /*
 206          * With hardware tablewalk, a sync is needed to ensure that
 207          * subsequent accesses see the PTE we just wrote.  Unlike userspace
 208          * mappings, we can't tolerate spurious faults, so make sure
 209          * the new PTE will be seen the first time.
 210          */
 211         if (is_kernel_addr(addr))
 212                 mb();
 213 #endif
 214 #endif
 215 }
 216
 217
 218 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 219 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
 220                                  pte_t *ptep, pte_t entry, int dirty);
 221
 222 /*
 223  * Macro to mark a page protection value as "uncacheable".
 224  */
 225
 226 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
 227                          _PAGE_WRITETHRU)
 228
 229 #define pgprot_noncached(prot)    (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
 230                                             _PAGE_NO_CACHE | _PAGE_GUARDED))
 231
 232 #define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
 233                                             _PAGE_NO_CACHE))
 234
 235 #define pgprot_cached(prot)       (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
 236                                             _PAGE_COHERENT))
 237
 238 #if _PAGE_WRITETHRU != 0
 239 #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
 240                                             _PAGE_COHERENT | _PAGE_WRITETHRU))
 241 #endif
 242
 243 #define pgprot_cached_noncoherent(prot) \
 244                 (__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL))
 245
 246 #define pgprot_writecombine pgprot_noncached_wc
 247
 248 struct file;
 249 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 250                                      unsigned long size, pgprot_t vma_prot);
 251 #define __HAVE_PHYS_MEM_ACCESS_PROT
 252
 253 #ifdef CONFIG_HUGETLB_PAGE
 254 static inline int hugepd_ok(hugepd_t hpd)
 255 {
 256 #ifdef CONFIG_PPC_8xx
 257         return ((hpd_val(hpd) & 0x4) != 0);
 258 #else
 259         /* We clear the top bit to indicate hugepd */
 260         return (hpd_val(hpd) && (hpd_val(hpd) & PD_HUGE) == 0);
 261 #endif
 262 }
 263
 264 static inline int pmd_huge(pmd_t pmd)
 265 {
 266         return 0;
 267 }
 268
 269 static inline int pud_huge(pud_t pud)
 270 {
 271         return 0;
 272 }
 273
 274 static inline int pgd_huge(pgd_t pgd)
 275 {
 276         return 0;
 277 }
 278 #define pgd_huge                pgd_huge
 279
 280 #define is_hugepd(hpd)          (hugepd_ok(hpd))
 281 #endif
 282
 283 #endif /* __ASSEMBLY__ */
 284 #endif