arch/powerpc/include/asm/nohash/pte-book3e.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_POWERPC_NOHASH_PTE_BOOK3E_H
   3 #define _ASM_POWERPC_NOHASH_PTE_BOOK3E_H
   4 #ifdef __KERNEL__
   5
   6 /* PTE bit definitions for processors compliant to the Book3E
   7  * architecture 2.06 or later. The position of the PTE bits
   8  * matches the HW definition of the optional Embedded Page Table
   9  * category.
  10  */
  11
  12 /* Architected bits */
  13 #define _PAGE_PRESENT   0x000001 /* software: pte contains a translation */
  14 #define _PAGE_SW1       0x000002
  15 #define _PAGE_BIT_SWAP_TYPE     2
  16 #define _PAGE_BAP_SR    0x000004
  17 #define _PAGE_BAP_UR    0x000008
  18 #define _PAGE_BAP_SW    0x000010
  19 #define _PAGE_BAP_UW    0x000020
  20 #define _PAGE_BAP_SX    0x000040
  21 #define _PAGE_BAP_UX    0x000080
  22 #define _PAGE_PSIZE_MSK 0x000f00
  23 #define _PAGE_PSIZE_4K  0x000200
  24 #define _PAGE_PSIZE_8K  0x000300
  25 #define _PAGE_PSIZE_16K 0x000400
  26 #define _PAGE_PSIZE_32K 0x000500
  27 #define _PAGE_PSIZE_64K 0x000600
  28 #define _PAGE_PSIZE_128K        0x000700
  29 #define _PAGE_PSIZE_256K        0x000800
  30 #define _PAGE_PSIZE_512K        0x000900
  31 #define _PAGE_PSIZE_1M  0x000a00
  32 #define _PAGE_PSIZE_2M  0x000b00
  33 #define _PAGE_PSIZE_4M  0x000c00
  34 #define _PAGE_PSIZE_8M  0x000d00
  35 #define _PAGE_PSIZE_16M 0x000e00
  36 #define _PAGE_PSIZE_32M 0x000f00
  37 #define _PAGE_DIRTY     0x001000 /* C: page changed */
  38 #define _PAGE_SW0       0x002000
  39 #define _PAGE_U3        0x004000
  40 #define _PAGE_U2        0x008000
  41 #define _PAGE_U1        0x010000
  42 #define _PAGE_U0        0x020000
  43 #define _PAGE_ACCESSED  0x040000
  44 #define _PAGE_ENDIAN    0x080000
  45 #define _PAGE_GUARDED   0x100000
  46 #define _PAGE_COHERENT  0x200000 /* M: enforce memory coherence */
  47 #define _PAGE_NO_CACHE  0x400000 /* I: cache inhibit */
  48 #define _PAGE_WRITETHRU 0x800000 /* W: cache write-through */
  49
  50 /* "Higher level" linux bit combinations */
  51 #define _PAGE_EXEC              _PAGE_BAP_UX /* .. and was cache cleaned */
  52 #define _PAGE_RW                (_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */
  53 #define _PAGE_KERNEL_RW         (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY)
  54 #define _PAGE_KERNEL_RO         (_PAGE_BAP_SR)
  55 #define _PAGE_KERNEL_RWX        (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY | _PAGE_BAP_SX)
  56 #define _PAGE_KERNEL_ROX        (_PAGE_BAP_SR | _PAGE_BAP_SX)
  57 #define _PAGE_USER              (_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
  58 #define _PAGE_PRIVILEGED        (_PAGE_BAP_SR)
  59
  60 #define _PAGE_HASHPTE   0
  61 #define _PAGE_BUSY      0
  62
  63 #define _PAGE_SPECIAL   _PAGE_SW0
  64
  65 /* Flags to be preserved on PTE modifications */
  66 #define _PAGE_HPTEFLAGS _PAGE_BUSY
  67
  68 /* Base page size */
  69 #ifdef CONFIG_PPC_64K_PAGES
  70 #define _PAGE_PSIZE     _PAGE_PSIZE_64K
  71 #define PTE_RPN_SHIFT   (28)
  72 #else
  73 #define _PAGE_PSIZE     _PAGE_PSIZE_4K
  74 #define PTE_RPN_SHIFT   (24)
  75 #endif
  76
  77 #define PTE_WIMGE_SHIFT (19)
  78 #define PTE_BAP_SHIFT   (2)
  79
  80 /* On 32-bit, we never clear the top part of the PTE */
  81 #ifdef CONFIG_PPC32
  82 #define _PTE_NONE_MASK  0xffffffff00000000ULL
  83 #define _PMD_PRESENT    0
  84 #define _PMD_PRESENT_MASK (PAGE_MASK)
  85 #define _PMD_BAD        (~PAGE_MASK)
  86 #endif
  87
  88 #endif /* __KERNEL__ */
  89 #endif /*  _ASM_POWERPC_NOHASH_PTE_BOOK3E_H */