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ARM: amba: Make driver_override output consistent with other buses
[linux/fpc-iii.git] / arch / powerpc / include / asm / opal-api.h
blob94bd1bf2c8732cbd6119bab581f1cffcfb7316b8
1 /*
2 * OPAL API definitions.
3 *
4 * Copyright 2011-2015 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #ifndef __OPAL_API_H
13 #define __OPAL_API_H
14
15 /****** OPAL APIs ******/
16
17 /* Return codes */
18 #define OPAL_SUCCESS 0
19 #define OPAL_PARAMETER -1
20 #define OPAL_BUSY -2
21 #define OPAL_PARTIAL -3
22 #define OPAL_CONSTRAINED -4
23 #define OPAL_CLOSED -5
24 #define OPAL_HARDWARE -6
25 #define OPAL_UNSUPPORTED -7
26 #define OPAL_PERMISSION -8
27 #define OPAL_NO_MEM -9
28 #define OPAL_RESOURCE -10
29 #define OPAL_INTERNAL_ERROR -11
30 #define OPAL_BUSY_EVENT -12
31 #define OPAL_HARDWARE_FROZEN -13
32 #define OPAL_WRONG_STATE -14
33 #define OPAL_ASYNC_COMPLETION -15
34 #define OPAL_EMPTY -16
35 #define OPAL_I2C_TIMEOUT -17
36 #define OPAL_I2C_INVALID_CMD -18
37 #define OPAL_I2C_LBUS_PARITY -19
38 #define OPAL_I2C_BKEND_OVERRUN -20
39 #define OPAL_I2C_BKEND_ACCESS -21
40 #define OPAL_I2C_ARBT_LOST -22
41 #define OPAL_I2C_NACK_RCVD -23
42 #define OPAL_I2C_STOP_ERR -24
43 #define OPAL_XIVE_PROVISIONING -31
44 #define OPAL_XIVE_FREE_ACTIVE -32
45 #define OPAL_TIMEOUT -33
46
47 /* API Tokens (in r0) */
48 #define OPAL_INVALID_CALL -1
49 #define OPAL_TEST 0
50 #define OPAL_CONSOLE_WRITE 1
51 #define OPAL_CONSOLE_READ 2
52 #define OPAL_RTC_READ 3
53 #define OPAL_RTC_WRITE 4
54 #define OPAL_CEC_POWER_DOWN 5
55 #define OPAL_CEC_REBOOT 6
56 #define OPAL_READ_NVRAM 7
57 #define OPAL_WRITE_NVRAM 8
58 #define OPAL_HANDLE_INTERRUPT 9
59 #define OPAL_POLL_EVENTS 10
60 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
61 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
62 #define OPAL_PCI_CONFIG_READ_BYTE 13
63 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
64 #define OPAL_PCI_CONFIG_READ_WORD 15
65 #define OPAL_PCI_CONFIG_WRITE_BYTE 16
66 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
67 #define OPAL_PCI_CONFIG_WRITE_WORD 18
68 #define OPAL_SET_XIVE 19
69 #define OPAL_GET_XIVE 20
70 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
71 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
72 #define OPAL_PCI_EEH_FREEZE_STATUS 23
73 #define OPAL_PCI_SHPC 24
74 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
75 #define OPAL_PCI_EEH_FREEZE_CLEAR 26
76 #define OPAL_PCI_PHB_MMIO_ENABLE 27
77 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
78 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
79 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
80 #define OPAL_PCI_SET_PE 31
81 #define OPAL_PCI_SET_PELTV 32
82 #define OPAL_PCI_SET_MVE 33
83 #define OPAL_PCI_SET_MVE_ENABLE 34
84 #define OPAL_PCI_GET_XIVE_REISSUE 35
85 #define OPAL_PCI_SET_XIVE_REISSUE 36
86 #define OPAL_PCI_SET_XIVE_PE 37
87 #define OPAL_GET_XIVE_SOURCE 38
88 #define OPAL_GET_MSI_32 39
89 #define OPAL_GET_MSI_64 40
90 #define OPAL_START_CPU 41
91 #define OPAL_QUERY_CPU_STATUS 42
92 #define OPAL_WRITE_OPPANEL 43 /* unimplemented */
93 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
94 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
95 #define OPAL_PCI_RESET 49
96 #define OPAL_PCI_GET_HUB_DIAG_DATA 50
97 #define OPAL_PCI_GET_PHB_DIAG_DATA 51
98 #define OPAL_PCI_FENCE_PHB 52
99 #define OPAL_PCI_REINIT 53
100 #define OPAL_PCI_MASK_PE_ERROR 54
101 #define OPAL_SET_SLOT_LED_STATUS 55
102 #define OPAL_GET_EPOW_STATUS 56
103 #define OPAL_SET_SYSTEM_ATTENTION_LED 57
104 #define OPAL_RESERVED1 58
105 #define OPAL_RESERVED2 59
106 #define OPAL_PCI_NEXT_ERROR 60
107 #define OPAL_PCI_EEH_FREEZE_STATUS2 61
108 #define OPAL_PCI_POLL 62
109 #define OPAL_PCI_MSI_EOI 63
110 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
111 #define OPAL_XSCOM_READ 65
112 #define OPAL_XSCOM_WRITE 66
113 #define OPAL_LPC_READ 67
114 #define OPAL_LPC_WRITE 68
115 #define OPAL_RETURN_CPU 69
116 #define OPAL_REINIT_CPUS 70
117 #define OPAL_ELOG_READ 71
118 #define OPAL_ELOG_WRITE 72
119 #define OPAL_ELOG_ACK 73
120 #define OPAL_ELOG_RESEND 74
121 #define OPAL_ELOG_SIZE 75
122 #define OPAL_FLASH_VALIDATE 76
123 #define OPAL_FLASH_MANAGE 77
124 #define OPAL_FLASH_UPDATE 78
125 #define OPAL_RESYNC_TIMEBASE 79
126 #define OPAL_CHECK_TOKEN 80
127 #define OPAL_DUMP_INIT 81
128 #define OPAL_DUMP_INFO 82
129 #define OPAL_DUMP_READ 83
130 #define OPAL_DUMP_ACK 84
131 #define OPAL_GET_MSG 85
132 #define OPAL_CHECK_ASYNC_COMPLETION 86
133 #define OPAL_SYNC_HOST_REBOOT 87
134 #define OPAL_SENSOR_READ 88
135 #define OPAL_GET_PARAM 89
136 #define OPAL_SET_PARAM 90
137 #define OPAL_DUMP_RESEND 91
138 #define OPAL_ELOG_SEND 92 /* Deprecated */
139 #define OPAL_PCI_SET_PHB_CAPI_MODE 93
140 #define OPAL_DUMP_INFO2 94
141 #define OPAL_WRITE_OPPANEL_ASYNC 95
142 #define OPAL_PCI_ERR_INJECT 96
143 #define OPAL_PCI_EEH_FREEZE_SET 97
144 #define OPAL_HANDLE_HMI 98
145 #define OPAL_CONFIG_CPU_IDLE_STATE 99
146 #define OPAL_SLW_SET_REG 100
147 #define OPAL_REGISTER_DUMP_REGION 101
148 #define OPAL_UNREGISTER_DUMP_REGION 102
149 #define OPAL_WRITE_TPO 103
150 #define OPAL_READ_TPO 104
151 #define OPAL_GET_DPO_STATUS 105
152 #define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */
153 #define OPAL_IPMI_SEND 107
154 #define OPAL_IPMI_RECV 108
155 #define OPAL_I2C_REQUEST 109
156 #define OPAL_FLASH_READ 110
157 #define OPAL_FLASH_WRITE 111
158 #define OPAL_FLASH_ERASE 112
159 #define OPAL_PRD_MSG 113
160 #define OPAL_LEDS_GET_INDICATOR 114
161 #define OPAL_LEDS_SET_INDICATOR 115
162 #define OPAL_CEC_REBOOT2 116
163 #define OPAL_CONSOLE_FLUSH 117
164 #define OPAL_GET_DEVICE_TREE 118
165 #define OPAL_PCI_GET_PRESENCE_STATE 119
166 #define OPAL_PCI_GET_POWER_STATE 120
167 #define OPAL_PCI_SET_POWER_STATE 121
168 #define OPAL_INT_GET_XIRR 122
169 #define OPAL_INT_SET_CPPR 123
170 #define OPAL_INT_EOI 124
171 #define OPAL_INT_SET_MFRR 125
172 #define OPAL_PCI_TCE_KILL 126
173 #define OPAL_NMMU_SET_PTCR 127
174 #define OPAL_XIVE_RESET 128
175 #define OPAL_XIVE_GET_IRQ_INFO 129
176 #define OPAL_XIVE_GET_IRQ_CONFIG 130
177 #define OPAL_XIVE_SET_IRQ_CONFIG 131
178 #define OPAL_XIVE_GET_QUEUE_INFO 132
179 #define OPAL_XIVE_SET_QUEUE_INFO 133
180 #define OPAL_XIVE_DONATE_PAGE 134
181 #define OPAL_XIVE_ALLOCATE_VP_BLOCK 135
182 #define OPAL_XIVE_FREE_VP_BLOCK 136
183 #define OPAL_XIVE_GET_VP_INFO 137
184 #define OPAL_XIVE_SET_VP_INFO 138
185 #define OPAL_XIVE_ALLOCATE_IRQ 139
186 #define OPAL_XIVE_FREE_IRQ 140
187 #define OPAL_XIVE_SYNC 141
188 #define OPAL_XIVE_DUMP 142
189 #define OPAL_XIVE_RESERVED3 143
190 #define OPAL_XIVE_RESERVED4 144
191 #define OPAL_SIGNAL_SYSTEM_RESET 145
192 #define OPAL_NPU_INIT_CONTEXT 146
193 #define OPAL_NPU_DESTROY_CONTEXT 147
194 #define OPAL_NPU_MAP_LPAR 148
195 #define OPAL_IMC_COUNTERS_INIT 149
196 #define OPAL_IMC_COUNTERS_START 150
197 #define OPAL_IMC_COUNTERS_STOP 151
198 #define OPAL_GET_POWERCAP 152
199 #define OPAL_SET_POWERCAP 153
200 #define OPAL_GET_POWER_SHIFT_RATIO 154
201 #define OPAL_SET_POWER_SHIFT_RATIO 155
202 #define OPAL_SENSOR_GROUP_CLEAR 156
203 #define OPAL_PCI_SET_P2P 157
204 #define OPAL_NPU_SPA_SETUP 159
205 #define OPAL_NPU_SPA_CLEAR_CACHE 160
206 #define OPAL_NPU_TL_SET 161
207 #define OPAL_LAST 161
208
209 /* Device tree flags */
210
211 /*
212 * Flags set in power-mgmt nodes in device tree describing
213 * idle states that are supported in the platform.
214 */
215
216 #define OPAL_PM_TIMEBASE_STOP 0x00000002
217 #define OPAL_PM_LOSE_HYP_CONTEXT 0x00002000
218 #define OPAL_PM_LOSE_FULL_CONTEXT 0x00004000
219 #define OPAL_PM_NAP_ENABLED 0x00010000
220 #define OPAL_PM_SLEEP_ENABLED 0x00020000
221 #define OPAL_PM_WINKLE_ENABLED 0x00040000
222 #define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */
223 #define OPAL_PM_STOP_INST_FAST 0x00100000
224 #define OPAL_PM_STOP_INST_DEEP 0x00200000
225
226 /*
227 * OPAL_CONFIG_CPU_IDLE_STATE parameters
228 */
229 #define OPAL_CONFIG_IDLE_FASTSLEEP 1
230 #define OPAL_CONFIG_IDLE_UNDO 0
231 #define OPAL_CONFIG_IDLE_APPLY 1
232
233 #ifndef __ASSEMBLY__
234
235 /* Other enums */
236 enum OpalFreezeState {
237 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
238 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
239 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
240 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
241 OPAL_EEH_STOPPED_RESET = 4,
242 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
243 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
244 };
245
246 enum OpalEehFreezeActionToken {
247 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
248 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
249 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
250
251 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
252 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2,
253 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3
254 };
255
256 enum OpalPciStatusToken {
257 OPAL_EEH_NO_ERROR = 0,
258 OPAL_EEH_IOC_ERROR = 1,
259 OPAL_EEH_PHB_ERROR = 2,
260 OPAL_EEH_PE_ERROR = 3,
261 OPAL_EEH_PE_MMIO_ERROR = 4,
262 OPAL_EEH_PE_DMA_ERROR = 5
263 };
264
265 enum OpalPciErrorSeverity {
266 OPAL_EEH_SEV_NO_ERROR = 0,
267 OPAL_EEH_SEV_IOC_DEAD = 1,
268 OPAL_EEH_SEV_PHB_DEAD = 2,
269 OPAL_EEH_SEV_PHB_FENCED = 3,
270 OPAL_EEH_SEV_PE_ER = 4,
271 OPAL_EEH_SEV_INF = 5
272 };
273
274 enum OpalErrinjectType {
275 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0,
276 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1,
277 };
278
279 enum OpalErrinjectFunc {
280 /* IOA bus specific errors */
281 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0,
282 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1,
283 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2,
284 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3,
285 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4,
286 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5,
287 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6,
288 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7,
289 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8,
290 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9,
291 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10,
292 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11,
293 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12,
294 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13,
295 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14,
296 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15,
297 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16,
298 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17,
299 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18,
300 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19,
301 };
302
303 enum OpalMmioWindowType {
304 OPAL_M32_WINDOW_TYPE = 1,
305 OPAL_M64_WINDOW_TYPE = 2,
306 OPAL_IO_WINDOW_TYPE = 3
307 };
308
309 enum OpalExceptionHandler {
310 OPAL_MACHINE_CHECK_HANDLER = 1,
311 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
312 OPAL_SOFTPATCH_HANDLER = 3
313 };
314
315 enum OpalPendingState {
316 OPAL_EVENT_OPAL_INTERNAL = 0x1,
317 OPAL_EVENT_NVRAM = 0x2,
318 OPAL_EVENT_RTC = 0x4,
319 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
320 OPAL_EVENT_CONSOLE_INPUT = 0x10,
321 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
322 OPAL_EVENT_ERROR_LOG = 0x40,
323 OPAL_EVENT_EPOW = 0x80,
324 OPAL_EVENT_LED_STATUS = 0x100,
325 OPAL_EVENT_PCI_ERROR = 0x200,
326 OPAL_EVENT_DUMP_AVAIL = 0x400,
327 OPAL_EVENT_MSG_PENDING = 0x800,
328 };
329
330 enum OpalThreadStatus {
331 OPAL_THREAD_INACTIVE = 0x0,
332 OPAL_THREAD_STARTED = 0x1,
333 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
334 };
335
336 enum OpalPciBusCompare {
337 OpalPciBusAny = 0, /* Any bus number match */
338 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
339 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
340 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
341 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
342 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
343 OpalPciBusAll = 7, /* Match bus number exactly */
344 };
345
346 enum OpalDeviceCompare {
347 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
348 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
349 };
350
351 enum OpalFuncCompare {
352 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
353 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
354 };
355
356 enum OpalPeAction {
357 OPAL_UNMAP_PE = 0,
358 OPAL_MAP_PE = 1
359 };
360
361 enum OpalPeltvAction {
362 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
363 OPAL_ADD_PE_TO_DOMAIN = 1
364 };
365
366 enum OpalMveEnableAction {
367 OPAL_DISABLE_MVE = 0,
368 OPAL_ENABLE_MVE = 1
369 };
370
371 enum OpalM64Action {
372 OPAL_DISABLE_M64 = 0,
373 OPAL_ENABLE_M64_SPLIT = 1,
374 OPAL_ENABLE_M64_NON_SPLIT = 2
375 };
376
377 enum OpalPciResetScope {
378 OPAL_RESET_PHB_COMPLETE = 1,
379 OPAL_RESET_PCI_LINK = 2,
380 OPAL_RESET_PHB_ERROR = 3,
381 OPAL_RESET_PCI_HOT = 4,
382 OPAL_RESET_PCI_FUNDAMENTAL = 5,
383 OPAL_RESET_PCI_IODA_TABLE = 6
384 };
385
386 enum OpalPciReinitScope {
387 /*
388 * Note: we chose values that do not overlap
389 * OpalPciResetScope as OPAL v2 used the same
390 * enum for both
391 */
392 OPAL_REINIT_PCI_DEV = 1000
393 };
394
395 enum OpalPciResetState {
396 OPAL_DEASSERT_RESET = 0,
397 OPAL_ASSERT_RESET = 1
398 };
399
400 enum OpalPciSlotPresence {
401 OPAL_PCI_SLOT_EMPTY = 0,
402 OPAL_PCI_SLOT_PRESENT = 1
403 };
404
405 enum OpalPciSlotPower {
406 OPAL_PCI_SLOT_POWER_OFF = 0,
407 OPAL_PCI_SLOT_POWER_ON = 1,
408 OPAL_PCI_SLOT_OFFLINE = 2,
409 OPAL_PCI_SLOT_ONLINE = 3
410 };
411
412 enum OpalSlotLedType {
413 OPAL_SLOT_LED_TYPE_ID = 0, /* IDENTIFY LED */
414 OPAL_SLOT_LED_TYPE_FAULT = 1, /* FAULT LED */
415 OPAL_SLOT_LED_TYPE_ATTN = 2, /* System Attention LED */
416 OPAL_SLOT_LED_TYPE_MAX = 3
417 };
418
419 enum OpalSlotLedState {
420 OPAL_SLOT_LED_STATE_OFF = 0, /* LED is OFF */
421 OPAL_SLOT_LED_STATE_ON = 1 /* LED is ON */
422 };
423
424 /*
425 * Address cycle types for LPC accesses. These also correspond
426 * to the content of the first cell of the "reg" property for
427 * device nodes on the LPC bus
428 */
429 enum OpalLPCAddressType {
430 OPAL_LPC_MEM = 0,
431 OPAL_LPC_IO = 1,
432 OPAL_LPC_FW = 2,
433 };
434
435 enum opal_msg_type {
436 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
437 * additional params function-specific
438 */
439 OPAL_MSG_MEM_ERR = 1,
440 OPAL_MSG_EPOW = 2,
441 OPAL_MSG_SHUTDOWN = 3, /* params[0] = 1 reboot, 0 shutdown */
442 OPAL_MSG_HMI_EVT = 4,
443 OPAL_MSG_DPO = 5,
444 OPAL_MSG_PRD = 6,
445 OPAL_MSG_OCC = 7,
446 OPAL_MSG_TYPE_MAX,
447 };
448
449 struct opal_msg {
450 __be32 msg_type;
451 __be32 reserved;
452 __be64 params[8];
453 };
454
455 /* System parameter permission */
456 enum OpalSysparamPerm {
457 OPAL_SYSPARAM_READ = 0x1,
458 OPAL_SYSPARAM_WRITE = 0x2,
459 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
460 };
461
462 enum {
463 OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
464 };
465
466 struct opal_ipmi_msg {
467 uint8_t version;
468 uint8_t netfn;
469 uint8_t cmd;
470 uint8_t data[];
471 };
472
473 /* FSP memory errors handling */
474 enum OpalMemErr_Version {
475 OpalMemErr_V1 = 1,
476 };
477
478 enum OpalMemErrType {
479 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
480 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
481 };
482
483 /* Memory Reilience error type */
484 enum OpalMemErr_ResilErrType {
485 OPAL_MEM_RESILIENCE_CE = 0,
486 OPAL_MEM_RESILIENCE_UE,
487 OPAL_MEM_RESILIENCE_UE_SCRUB,
488 };
489
490 /* Dynamic Memory Deallocation type */
491 enum OpalMemErr_DynErrType {
492 OPAL_MEM_DYNAMIC_DEALLOC = 0,
493 };
494
495 struct OpalMemoryErrorData {
496 enum OpalMemErr_Version version:8; /* 0x00 */
497 enum OpalMemErrType type:8; /* 0x01 */
498 __be16 flags; /* 0x02 */
499 uint8_t reserved_1[4]; /* 0x04 */
500
501 union {
502 /* Memory Resilience corrected/uncorrected error info */
503 struct {
504 enum OpalMemErr_ResilErrType resil_err_type:8;
505 uint8_t reserved_1[7];
506 __be64 physical_address_start;
507 __be64 physical_address_end;
508 } resilience;
509 /* Dynamic memory deallocation error info */
510 struct {
511 enum OpalMemErr_DynErrType dyn_err_type:8;
512 uint8_t reserved_1[7];
513 __be64 physical_address_start;
514 __be64 physical_address_end;
515 } dyn_dealloc;
516 } u;
517 };
518
519 /* HMI interrupt event */
520 enum OpalHMI_Version {
521 OpalHMIEvt_V1 = 1,
522 OpalHMIEvt_V2 = 2,
523 };
524
525 enum OpalHMI_Severity {
526 OpalHMI_SEV_NO_ERROR = 0,
527 OpalHMI_SEV_WARNING = 1,
528 OpalHMI_SEV_ERROR_SYNC = 2,
529 OpalHMI_SEV_FATAL = 3,
530 };
531
532 enum OpalHMI_Disposition {
533 OpalHMI_DISPOSITION_RECOVERED = 0,
534 OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
535 };
536
537 enum OpalHMI_ErrType {
538 OpalHMI_ERROR_MALFUNC_ALERT = 0,
539 OpalHMI_ERROR_PROC_RECOV_DONE,
540 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
541 OpalHMI_ERROR_PROC_RECOV_MASKED,
542 OpalHMI_ERROR_TFAC,
543 OpalHMI_ERROR_TFMR_PARITY,
544 OpalHMI_ERROR_HA_OVERFLOW_WARN,
545 OpalHMI_ERROR_XSCOM_FAIL,
546 OpalHMI_ERROR_XSCOM_DONE,
547 OpalHMI_ERROR_SCOM_FIR,
548 OpalHMI_ERROR_DEBUG_TRIG_FIR,
549 OpalHMI_ERROR_HYP_RESOURCE,
550 OpalHMI_ERROR_CAPP_RECOVERY,
551 };
552
553 enum OpalHMI_XstopType {
554 CHECKSTOP_TYPE_UNKNOWN = 0,
555 CHECKSTOP_TYPE_CORE = 1,
556 CHECKSTOP_TYPE_NX = 2,
557 };
558
559 enum OpalHMI_CoreXstopReason {
560 CORE_CHECKSTOP_IFU_REGFILE = 0x00000001,
561 CORE_CHECKSTOP_IFU_LOGIC = 0x00000002,
562 CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004,
563 CORE_CHECKSTOP_ISU_REGFILE = 0x00000008,
564 CORE_CHECKSTOP_ISU_LOGIC = 0x00000010,
565 CORE_CHECKSTOP_FXU_LOGIC = 0x00000020,
566 CORE_CHECKSTOP_VSU_LOGIC = 0x00000040,
567 CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080,
568 CORE_CHECKSTOP_LSU_REGFILE = 0x00000100,
569 CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200,
570 CORE_CHECKSTOP_LSU_LOGIC = 0x00000400,
571 CORE_CHECKSTOP_PC_LOGIC = 0x00000800,
572 CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000,
573 CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000,
574 CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000,
575 CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000,
576 CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000,
577 };
578
579 enum OpalHMI_NestAccelXstopReason {
580 NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001,
581 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002,
582 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004,
583 NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008,
584 NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010,
585 NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020,
586 NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040,
587 NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080,
588 NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100,
589 NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200,
590 NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400,
591 NX_CHECKSTOP_DMA_CRB_UE = 0x00000800,
592 NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000,
593 NX_CHECKSTOP_PBI_ISN_UE = 0x00002000,
594 };
595
596 struct OpalHMIEvent {
597 uint8_t version; /* 0x00 */
598 uint8_t severity; /* 0x01 */
599 uint8_t type; /* 0x02 */
600 uint8_t disposition; /* 0x03 */
601 uint8_t reserved_1[4]; /* 0x04 */
602
603 __be64 hmer;
604 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
605 __be64 tfmr;
606
607 /* version 2 and later */
608 union {
609 /*
610 * checkstop info (Core/NX).
611 * Valid for OpalHMI_ERROR_MALFUNC_ALERT.
612 */
613 struct {
614 uint8_t xstop_type; /* enum OpalHMI_XstopType */
615 uint8_t reserved_1[3];
616 __be32 xstop_reason;
617 union {
618 __be32 pir; /* for CHECKSTOP_TYPE_CORE */
619 __be32 chip_id; /* for CHECKSTOP_TYPE_NX */
620 } u;
621 } xstop_error;
622 } u;
623 };
624
625 enum {
626 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
627 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
628 OPAL_P7IOC_DIAG_TYPE_BI = 2,
629 OPAL_P7IOC_DIAG_TYPE_CI = 3,
630 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
631 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
632 OPAL_P7IOC_DIAG_TYPE_LAST = 6
633 };
634
635 struct OpalIoP7IOCErrorData {
636 __be16 type;
637
638 /* GEM */
639 __be64 gemXfir;
640 __be64 gemRfir;
641 __be64 gemRirqfir;
642 __be64 gemMask;
643 __be64 gemRwof;
644
645 /* LEM */
646 __be64 lemFir;
647 __be64 lemErrMask;
648 __be64 lemAction0;
649 __be64 lemAction1;
650 __be64 lemWof;
651
652 union {
653 struct OpalIoP7IOCRgcErrorData {
654 __be64 rgcStatus; /* 3E1C10 */
655 __be64 rgcLdcp; /* 3E1C18 */
656 }rgc;
657 struct OpalIoP7IOCBiErrorData {
658 __be64 biLdcp0; /* 3C0100, 3C0118 */
659 __be64 biLdcp1; /* 3C0108, 3C0120 */
660 __be64 biLdcp2; /* 3C0110, 3C0128 */
661 __be64 biFenceStatus; /* 3C0130, 3C0130 */
662
663 uint8_t biDownbound; /* BI Downbound or Upbound */
664 }bi;
665 struct OpalIoP7IOCCiErrorData {
666 __be64 ciPortStatus; /* 3Dn008 */
667 __be64 ciPortLdcp; /* 3Dn010 */
668
669 uint8_t ciPort; /* Index of CI port: 0/1 */
670 }ci;
671 };
672 };
673
674 /**
675 * This structure defines the overlay which will be used to store PHB error
676 * data upon request.
677 */
678 enum {
679 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
680 };
681
682 enum {
683 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
684 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2,
685 OPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3
686 };
687
688 enum {
689 OPAL_P7IOC_NUM_PEST_REGS = 128,
690 OPAL_PHB3_NUM_PEST_REGS = 256,
691 OPAL_PHB4_NUM_PEST_REGS = 512
692 };
693
694 struct OpalIoPhbErrorCommon {
695 __be32 version;
696 __be32 ioType;
697 __be32 len;
698 };
699
700 struct OpalIoP7IOCPhbErrorData {
701 struct OpalIoPhbErrorCommon common;
702
703 __be32 brdgCtl;
704
705 // P7IOC utl regs
706 __be32 portStatusReg;
707 __be32 rootCmplxStatus;
708 __be32 busAgentStatus;
709
710 // P7IOC cfg regs
711 __be32 deviceStatus;
712 __be32 slotStatus;
713 __be32 linkStatus;
714 __be32 devCmdStatus;
715 __be32 devSecStatus;
716
717 // cfg AER regs
718 __be32 rootErrorStatus;
719 __be32 uncorrErrorStatus;
720 __be32 corrErrorStatus;
721 __be32 tlpHdr1;
722 __be32 tlpHdr2;
723 __be32 tlpHdr3;
724 __be32 tlpHdr4;
725 __be32 sourceId;
726
727 __be32 rsv3;
728
729 // Record data about the call to allocate a buffer.
730 __be64 errorClass;
731 __be64 correlator;
732
733 //P7IOC MMIO Error Regs
734 __be64 p7iocPlssr; // n120
735 __be64 p7iocCsr; // n110
736 __be64 lemFir; // nC00
737 __be64 lemErrorMask; // nC18
738 __be64 lemWOF; // nC40
739 __be64 phbErrorStatus; // nC80
740 __be64 phbFirstErrorStatus; // nC88
741 __be64 phbErrorLog0; // nCC0
742 __be64 phbErrorLog1; // nCC8
743 __be64 mmioErrorStatus; // nD00
744 __be64 mmioFirstErrorStatus; // nD08
745 __be64 mmioErrorLog0; // nD40
746 __be64 mmioErrorLog1; // nD48
747 __be64 dma0ErrorStatus; // nD80
748 __be64 dma0FirstErrorStatus; // nD88
749 __be64 dma0ErrorLog0; // nDC0
750 __be64 dma0ErrorLog1; // nDC8
751 __be64 dma1ErrorStatus; // nE00
752 __be64 dma1FirstErrorStatus; // nE08
753 __be64 dma1ErrorLog0; // nE40
754 __be64 dma1ErrorLog1; // nE48
755 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
756 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
757 };
758
759 struct OpalIoPhb3ErrorData {
760 struct OpalIoPhbErrorCommon common;
761
762 __be32 brdgCtl;
763
764 /* PHB3 UTL regs */
765 __be32 portStatusReg;
766 __be32 rootCmplxStatus;
767 __be32 busAgentStatus;
768
769 /* PHB3 cfg regs */
770 __be32 deviceStatus;
771 __be32 slotStatus;
772 __be32 linkStatus;
773 __be32 devCmdStatus;
774 __be32 devSecStatus;
775
776 /* cfg AER regs */
777 __be32 rootErrorStatus;
778 __be32 uncorrErrorStatus;
779 __be32 corrErrorStatus;
780 __be32 tlpHdr1;
781 __be32 tlpHdr2;
782 __be32 tlpHdr3;
783 __be32 tlpHdr4;
784 __be32 sourceId;
785
786 __be32 rsv3;
787
788 /* Record data about the call to allocate a buffer */
789 __be64 errorClass;
790 __be64 correlator;
791
792 /* PHB3 MMIO Error Regs */
793 __be64 nFir; /* 000 */
794 __be64 nFirMask; /* 003 */
795 __be64 nFirWOF; /* 008 */
796 __be64 phbPlssr; /* 120 */
797 __be64 phbCsr; /* 110 */
798 __be64 lemFir; /* C00 */
799 __be64 lemErrorMask; /* C18 */
800 __be64 lemWOF; /* C40 */
801 __be64 phbErrorStatus; /* C80 */
802 __be64 phbFirstErrorStatus; /* C88 */
803 __be64 phbErrorLog0; /* CC0 */
804 __be64 phbErrorLog1; /* CC8 */
805 __be64 mmioErrorStatus; /* D00 */
806 __be64 mmioFirstErrorStatus; /* D08 */
807 __be64 mmioErrorLog0; /* D40 */
808 __be64 mmioErrorLog1; /* D48 */
809 __be64 dma0ErrorStatus; /* D80 */
810 __be64 dma0FirstErrorStatus; /* D88 */
811 __be64 dma0ErrorLog0; /* DC0 */
812 __be64 dma0ErrorLog1; /* DC8 */
813 __be64 dma1ErrorStatus; /* E00 */
814 __be64 dma1FirstErrorStatus; /* E08 */
815 __be64 dma1ErrorLog0; /* E40 */
816 __be64 dma1ErrorLog1; /* E48 */
817 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
818 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
819 };
820
821 struct OpalIoPhb4ErrorData {
822 struct OpalIoPhbErrorCommon common;
823
824 __be32 brdgCtl;
825
826 /* PHB4 cfg regs */
827 __be32 deviceStatus;
828 __be32 slotStatus;
829 __be32 linkStatus;
830 __be32 devCmdStatus;
831 __be32 devSecStatus;
832
833 /* cfg AER regs */
834 __be32 rootErrorStatus;
835 __be32 uncorrErrorStatus;
836 __be32 corrErrorStatus;
837 __be32 tlpHdr1;
838 __be32 tlpHdr2;
839 __be32 tlpHdr3;
840 __be32 tlpHdr4;
841 __be32 sourceId;
842
843 /* PHB4 ETU Error Regs */
844 __be64 nFir; /* 000 */
845 __be64 nFirMask; /* 003 */
846 __be64 nFirWOF; /* 008 */
847 __be64 phbPlssr; /* 120 */
848 __be64 phbCsr; /* 110 */
849 __be64 lemFir; /* C00 */
850 __be64 lemErrorMask; /* C18 */
851 __be64 lemWOF; /* C40 */
852 __be64 phbErrorStatus; /* C80 */
853 __be64 phbFirstErrorStatus; /* C88 */
854 __be64 phbErrorLog0; /* CC0 */
855 __be64 phbErrorLog1; /* CC8 */
856 __be64 phbTxeErrorStatus; /* D00 */
857 __be64 phbTxeFirstErrorStatus; /* D08 */
858 __be64 phbTxeErrorLog0; /* D40 */
859 __be64 phbTxeErrorLog1; /* D48 */
860 __be64 phbRxeArbErrorStatus; /* D80 */
861 __be64 phbRxeArbFirstErrorStatus; /* D88 */
862 __be64 phbRxeArbErrorLog0; /* DC0 */
863 __be64 phbRxeArbErrorLog1; /* DC8 */
864 __be64 phbRxeMrgErrorStatus; /* E00 */
865 __be64 phbRxeMrgFirstErrorStatus; /* E08 */
866 __be64 phbRxeMrgErrorLog0; /* E40 */
867 __be64 phbRxeMrgErrorLog1; /* E48 */
868 __be64 phbRxeTceErrorStatus; /* E80 */
869 __be64 phbRxeTceFirstErrorStatus; /* E88 */
870 __be64 phbRxeTceErrorLog0; /* EC0 */
871 __be64 phbRxeTceErrorLog1; /* EC8 */
872
873 /* PHB4 REGB Error Regs */
874 __be64 phbPblErrorStatus; /* 1900 */
875 __be64 phbPblFirstErrorStatus; /* 1908 */
876 __be64 phbPblErrorLog0; /* 1940 */
877 __be64 phbPblErrorLog1; /* 1948 */
878 __be64 phbPcieDlpErrorLog1; /* 1AA0 */
879 __be64 phbPcieDlpErrorLog2; /* 1AA8 */
880 __be64 phbPcieDlpErrorStatus; /* 1AB0 */
881 __be64 phbRegbErrorStatus; /* 1C00 */
882 __be64 phbRegbFirstErrorStatus; /* 1C08 */
883 __be64 phbRegbErrorLog0; /* 1C40 */
884 __be64 phbRegbErrorLog1; /* 1C48 */
885
886 __be64 pestA[OPAL_PHB4_NUM_PEST_REGS];
887 __be64 pestB[OPAL_PHB4_NUM_PEST_REGS];
888 };
889
890 enum {
891 OPAL_REINIT_CPUS_HILE_BE = (1 << 0),
892 OPAL_REINIT_CPUS_HILE_LE = (1 << 1),
893
894 /* These two define the base MMU mode of the host on P9
895 *
896 * On P9 Nimbus DD2.0 and Cumlus (and later), KVM can still
897 * create hash guests in "radix" mode with care (full core
898 * switch only).
899 */
900 OPAL_REINIT_CPUS_MMU_HASH = (1 << 2),
901 OPAL_REINIT_CPUS_MMU_RADIX = (1 << 3),
902
903 OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED = (1 << 4),
904 };
905
906 typedef struct oppanel_line {
907 __be64 line;
908 __be64 line_len;
909 } oppanel_line_t;
910
911 enum opal_prd_msg_type {
912 OPAL_PRD_MSG_TYPE_INIT = 0, /* HBRT --> OPAL */
913 OPAL_PRD_MSG_TYPE_FINI, /* HBRT/kernel --> OPAL */
914 OPAL_PRD_MSG_TYPE_ATTN, /* HBRT <-- OPAL */
915 OPAL_PRD_MSG_TYPE_ATTN_ACK, /* HBRT --> OPAL */
916 OPAL_PRD_MSG_TYPE_OCC_ERROR, /* HBRT <-- OPAL */
917 OPAL_PRD_MSG_TYPE_OCC_RESET, /* HBRT <-- OPAL */
918 };
919
920 struct opal_prd_msg_header {
921 uint8_t type;
922 uint8_t pad[1];
923 __be16 size;
924 };
925
926 struct opal_prd_msg;
927
928 #define OCC_RESET 0
929 #define OCC_LOAD 1
930 #define OCC_THROTTLE 2
931 #define OCC_MAX_THROTTLE_STATUS 5
932
933 struct opal_occ_msg {
934 __be64 type;
935 __be64 chip;
936 __be64 throttle_status;
937 };
938
939 /*
940 * SG entries
941 *
942 * WARNING: The current implementation requires each entry
943 * to represent a block that is 4k aligned *and* each block
944 * size except the last one in the list to be as well.
945 */
946 struct opal_sg_entry {
947 __be64 data;
948 __be64 length;
949 };
950
951 /*
952 * Candidate image SG list.
953 *
954 * length = VER | length
955 */
956 struct opal_sg_list {
957 __be64 length;
958 __be64 next;
959 struct opal_sg_entry entry[];
960 };
961
962 /*
963 * Dump region ID range usable by the OS
964 */
965 #define OPAL_DUMP_REGION_HOST_START 0x80
966 #define OPAL_DUMP_REGION_LOG_BUF 0x80
967 #define OPAL_DUMP_REGION_HOST_END 0xFF
968
969 /* CAPI modes for PHB */
970 enum {
971 OPAL_PHB_CAPI_MODE_PCIE = 0,
972 OPAL_PHB_CAPI_MODE_CAPI = 1,
973 OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2,
974 OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
975 OPAL_PHB_CAPI_MODE_DMA = 4,
976 OPAL_PHB_CAPI_MODE_DMA_TVT1 = 5,
977 };
978
979 /* OPAL I2C request */
980 struct opal_i2c_request {
981 uint8_t type;
982 #define OPAL_I2C_RAW_READ 0
983 #define OPAL_I2C_RAW_WRITE 1
984 #define OPAL_I2C_SM_READ 2
985 #define OPAL_I2C_SM_WRITE 3
986 uint8_t flags;
987 #define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */
988 uint8_t subaddr_sz; /* Max 4 */
989 uint8_t reserved;
990 __be16 addr; /* 7 or 10 bit address */
991 __be16 reserved2;
992 __be32 subaddr; /* Sub-address if any */
993 __be32 size; /* Data size */
994 __be64 buffer_ra; /* Buffer real address */
995 };
996
997 /*
998 * EPOW status sharing (OPAL and the host)
999 *
1000 * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
1001 * with individual elements being 16 bits wide to fetch the system
1002 * wide EPOW status. Each element in the buffer will contain the
1003 * EPOW status in it's bit representation for a particular EPOW sub
1004 * class as defined here. So multiple detailed EPOW status bits
1005 * specific for any sub class can be represented in a single buffer
1006 * element as it's bit representation.
1007 */
1008
1009 /* System EPOW type */
1010 enum OpalSysEpow {
1011 OPAL_SYSEPOW_POWER = 0, /* Power EPOW */
1012 OPAL_SYSEPOW_TEMP = 1, /* Temperature EPOW */
1013 OPAL_SYSEPOW_COOLING = 2, /* Cooling EPOW */
1014 OPAL_SYSEPOW_MAX = 3, /* Max EPOW categories */
1015 };
1016
1017 /* Power EPOW */
1018 enum OpalSysPower {
1019 OPAL_SYSPOWER_UPS = 0x0001, /* System on UPS power */
1020 OPAL_SYSPOWER_CHNG = 0x0002, /* System power config change */
1021 OPAL_SYSPOWER_FAIL = 0x0004, /* System impending power failure */
1022 OPAL_SYSPOWER_INCL = 0x0008, /* System incomplete power */
1023 };
1024
1025 /* Temperature EPOW */
1026 enum OpalSysTemp {
1027 OPAL_SYSTEMP_AMB = 0x0001, /* System over ambient temperature */
1028 OPAL_SYSTEMP_INT = 0x0002, /* System over internal temperature */
1029 OPAL_SYSTEMP_HMD = 0x0004, /* System over ambient humidity */
1030 };
1031
1032 /* Cooling EPOW */
1033 enum OpalSysCooling {
1034 OPAL_SYSCOOL_INSF = 0x0001, /* System insufficient cooling */
1035 };
1036
1037 /* Argument to OPAL_CEC_REBOOT2() */
1038 enum {
1039 OPAL_REBOOT_NORMAL = 0,
1040 OPAL_REBOOT_PLATFORM_ERROR = 1,
1041 };
1042
1043 /* Argument to OPAL_PCI_TCE_KILL */
1044 enum {
1045 OPAL_PCI_TCE_KILL_PAGES,
1046 OPAL_PCI_TCE_KILL_PE,
1047 OPAL_PCI_TCE_KILL_ALL,
1048 };
1049
1050 /* The xive operation mode indicates the active "API" and
1051 * corresponds to the "mode" parameter of the opal_xive_reset()
1052 * call
1053 */
1054 enum {
1055 OPAL_XIVE_MODE_EMU = 0,
1056 OPAL_XIVE_MODE_EXPL = 1,
1057 };
1058
1059 /* Flags for OPAL_XIVE_GET_IRQ_INFO */
1060 enum {
1061 OPAL_XIVE_IRQ_TRIGGER_PAGE = 0x00000001,
1062 OPAL_XIVE_IRQ_STORE_EOI = 0x00000002,
1063 OPAL_XIVE_IRQ_LSI = 0x00000004,
1064 OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008,
1065 OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010,
1066 OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020,
1067 };
1068
1069 /* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */
1070 enum {
1071 OPAL_XIVE_EQ_ENABLED = 0x00000001,
1072 OPAL_XIVE_EQ_ALWAYS_NOTIFY = 0x00000002,
1073 OPAL_XIVE_EQ_ESCALATE = 0x00000004,
1074 };
1075
1076 /* Flags for OPAL_XIVE_GET/SET_VP_INFO */
1077 enum {
1078 OPAL_XIVE_VP_ENABLED = 0x00000001,
1079 OPAL_XIVE_VP_SINGLE_ESCALATION = 0x00000002,
1080 };
1081
1082 /* "Any chip" replacement for chip ID for allocation functions */
1083 enum {
1084 OPAL_XIVE_ANY_CHIP = 0xffffffff,
1085 };
1086
1087 /* Xive sync options */
1088 enum {
1089 /* This bits are cumulative, arg is a girq */
1090 XIVE_SYNC_EAS = 0x00000001, /* Sync irq source */
1091 XIVE_SYNC_QUEUE = 0x00000002, /* Sync irq target */
1092 };
1093
1094 /* Dump options */
1095 enum {
1096 XIVE_DUMP_TM_HYP = 0,
1097 XIVE_DUMP_TM_POOL = 1,
1098 XIVE_DUMP_TM_OS = 2,
1099 XIVE_DUMP_TM_USER = 3,
1100 XIVE_DUMP_VP = 4,
1101 XIVE_DUMP_EMU_STATE = 5,
1102 };
1103
1104 /* "type" argument options for OPAL_IMC_COUNTERS_* calls */
1105 enum {
1106 OPAL_IMC_COUNTERS_NEST = 1,
1107 OPAL_IMC_COUNTERS_CORE = 2,
1108 };
1109
1110
1111 /* PCI p2p descriptor */
1112 #define OPAL_PCI_P2P_ENABLE 0x1
1113 #define OPAL_PCI_P2P_LOAD 0x2
1114 #define OPAL_PCI_P2P_STORE 0x4
1115
1116 #endif /* __ASSEMBLY__ */
1117
1118 #endif /* __OPAL_API_H */
Linux with added FPC-III support