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ARM: amba: Make driver_override output consistent with other buses
[linux/fpc-iii.git] / arch / powerpc / kvm / book3s_hv_rm_mmu.c
blob78e6a392330f78b8407f8f7102762944c39c7d1f
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * Copyright 2010-2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
7 */
8
9 #include <linux/types.h>
10 #include <linux/string.h>
11 #include <linux/kvm.h>
12 #include <linux/kvm_host.h>
13 #include <linux/hugetlb.h>
14 #include <linux/module.h>
15 #include <linux/log2.h>
16
17 #include <asm/tlbflush.h>
18 #include <asm/trace.h>
19 #include <asm/kvm_ppc.h>
20 #include <asm/kvm_book3s.h>
21 #include <asm/book3s/64/mmu-hash.h>
22 #include <asm/hvcall.h>
23 #include <asm/synch.h>
24 #include <asm/ppc-opcode.h>
25 #include <asm/pte-walk.h>
26
27 /* Translate address of a vmalloc'd thing to a linear map address */
28 static void *real_vmalloc_addr(void *x)
29 {
30 unsigned long addr = (unsigned long) x;
31 pte_t *p;
32 /*
33 * assume we don't have huge pages in vmalloc space...
34 * So don't worry about THP collapse/split. Called
35 * Only in realmode with MSR_EE = 0, hence won't need irq_save/restore.
36 */
37 p = find_init_mm_pte(addr, NULL);
38 if (!p || !pte_present(*p))
39 return NULL;
40 addr = (pte_pfn(*p) << PAGE_SHIFT) | (addr & ~PAGE_MASK);
41 return __va(addr);
42 }
43
44 /* Return 1 if we need to do a global tlbie, 0 if we can use tlbiel */
45 static int global_invalidates(struct kvm *kvm)
46 {
47 int global;
48 int cpu;
49
50 /*
51 * If there is only one vcore, and it's currently running,
52 * as indicated by local_paca->kvm_hstate.kvm_vcpu being set,
53 * we can use tlbiel as long as we mark all other physical
54 * cores as potentially having stale TLB entries for this lpid.
55 * Otherwise, don't use tlbiel.
56 */
57 if (kvm->arch.online_vcores == 1 && local_paca->kvm_hstate.kvm_vcpu)
58 global = 0;
59 else
60 global = 1;
61
62 if (!global) {
63 /* any other core might now have stale TLB entries... */
64 smp_wmb();
65 cpumask_setall(&kvm->arch.need_tlb_flush);
66 cpu = local_paca->kvm_hstate.kvm_vcore->pcpu;
67 /*
68 * On POWER9, threads are independent but the TLB is shared,
69 * so use the bit for the first thread to represent the core.
70 */
71 if (cpu_has_feature(CPU_FTR_ARCH_300))
72 cpu = cpu_first_thread_sibling(cpu);
73 cpumask_clear_cpu(cpu, &kvm->arch.need_tlb_flush);
74 }
75
76 return global;
77 }
78
79 /*
80 * Add this HPTE into the chain for the real page.
81 * Must be called with the chain locked; it unlocks the chain.
82 */
83 void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev,
84 unsigned long *rmap, long pte_index, int realmode)
85 {
86 struct revmap_entry *head, *tail;
87 unsigned long i;
88
89 if (*rmap & KVMPPC_RMAP_PRESENT) {
90 i = *rmap & KVMPPC_RMAP_INDEX;
91 head = &kvm->arch.hpt.rev[i];
92 if (realmode)
93 head = real_vmalloc_addr(head);
94 tail = &kvm->arch.hpt.rev[head->back];
95 if (realmode)
96 tail = real_vmalloc_addr(tail);
97 rev->forw = i;
98 rev->back = head->back;
99 tail->forw = pte_index;
100 head->back = pte_index;
101 } else {
102 rev->forw = rev->back = pte_index;
103 *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) |
104 pte_index | KVMPPC_RMAP_PRESENT;
105 }
106 unlock_rmap(rmap);
107 }
108 EXPORT_SYMBOL_GPL(kvmppc_add_revmap_chain);
109
110 /* Update the dirty bitmap of a memslot */
111 void kvmppc_update_dirty_map(struct kvm_memory_slot *memslot,
112 unsigned long gfn, unsigned long psize)
113 {
114 unsigned long npages;
115
116 if (!psize || !memslot->dirty_bitmap)
117 return;
118 npages = (psize + PAGE_SIZE - 1) / PAGE_SIZE;
119 gfn -= memslot->base_gfn;
120 set_dirty_bits_atomic(memslot->dirty_bitmap, gfn, npages);
121 }
122 EXPORT_SYMBOL_GPL(kvmppc_update_dirty_map);
123
124 static void kvmppc_set_dirty_from_hpte(struct kvm *kvm,
125 unsigned long hpte_v, unsigned long hpte_gr)
126 {
127 struct kvm_memory_slot *memslot;
128 unsigned long gfn;
129 unsigned long psize;
130
131 psize = kvmppc_actual_pgsz(hpte_v, hpte_gr);
132 gfn = hpte_rpn(hpte_gr, psize);
133 memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
134 if (memslot && memslot->dirty_bitmap)
135 kvmppc_update_dirty_map(memslot, gfn, psize);
136 }
137
138 /* Returns a pointer to the revmap entry for the page mapped by a HPTE */
139 static unsigned long *revmap_for_hpte(struct kvm *kvm, unsigned long hpte_v,
140 unsigned long hpte_gr,
141 struct kvm_memory_slot **memslotp,
142 unsigned long *gfnp)
143 {
144 struct kvm_memory_slot *memslot;
145 unsigned long *rmap;
146 unsigned long gfn;
147
148 gfn = hpte_rpn(hpte_gr, kvmppc_actual_pgsz(hpte_v, hpte_gr));
149 memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
150 if (memslotp)
151 *memslotp = memslot;
152 if (gfnp)
153 *gfnp = gfn;
154 if (!memslot)
155 return NULL;
156
157 rmap = real_vmalloc_addr(&memslot->arch.rmap[gfn - memslot->base_gfn]);
158 return rmap;
159 }
160
161 /* Remove this HPTE from the chain for a real page */
162 static void remove_revmap_chain(struct kvm *kvm, long pte_index,
163 struct revmap_entry *rev,
164 unsigned long hpte_v, unsigned long hpte_r)
165 {
166 struct revmap_entry *next, *prev;
167 unsigned long ptel, head;
168 unsigned long *rmap;
169 unsigned long rcbits;
170 struct kvm_memory_slot *memslot;
171 unsigned long gfn;
172
173 rcbits = hpte_r & (HPTE_R_R | HPTE_R_C);
174 ptel = rev->guest_rpte |= rcbits;
175 rmap = revmap_for_hpte(kvm, hpte_v, ptel, &memslot, &gfn);
176 if (!rmap)
177 return;
178 lock_rmap(rmap);
179
180 head = *rmap & KVMPPC_RMAP_INDEX;
181 next = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->forw]);
182 prev = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->back]);
183 next->back = rev->back;
184 prev->forw = rev->forw;
185 if (head == pte_index) {
186 head = rev->forw;
187 if (head == pte_index)
188 *rmap &= ~(KVMPPC_RMAP_PRESENT | KVMPPC_RMAP_INDEX);
189 else
190 *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) | head;
191 }
192 *rmap |= rcbits << KVMPPC_RMAP_RC_SHIFT;
193 if (rcbits & HPTE_R_C)
194 kvmppc_update_dirty_map(memslot, gfn,
195 kvmppc_actual_pgsz(hpte_v, hpte_r));
196 unlock_rmap(rmap);
197 }
198
199 long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags,
200 long pte_index, unsigned long pteh, unsigned long ptel,
201 pgd_t *pgdir, bool realmode, unsigned long *pte_idx_ret)
202 {
203 unsigned long i, pa, gpa, gfn, psize;
204 unsigned long slot_fn, hva;
205 __be64 *hpte;
206 struct revmap_entry *rev;
207 unsigned long g_ptel;
208 struct kvm_memory_slot *memslot;
209 unsigned hpage_shift;
210 bool is_ci;
211 unsigned long *rmap;
212 pte_t *ptep;
213 unsigned int writing;
214 unsigned long mmu_seq;
215 unsigned long rcbits, irq_flags = 0;
216
217 if (kvm_is_radix(kvm))
218 return H_FUNCTION;
219 psize = kvmppc_actual_pgsz(pteh, ptel);
220 if (!psize)
221 return H_PARAMETER;
222 writing = hpte_is_writable(ptel);
223 pteh &= ~(HPTE_V_HVLOCK | HPTE_V_ABSENT | HPTE_V_VALID);
224 ptel &= ~HPTE_GR_RESERVED;
225 g_ptel = ptel;
226
227 /* used later to detect if we might have been invalidated */
228 mmu_seq = kvm->mmu_notifier_seq;
229 smp_rmb();
230
231 /* Find the memslot (if any) for this address */
232 gpa = (ptel & HPTE_R_RPN) & ~(psize - 1);
233 gfn = gpa >> PAGE_SHIFT;
234 memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
235 pa = 0;
236 is_ci = false;
237 rmap = NULL;
238 if (!(memslot && !(memslot->flags & KVM_MEMSLOT_INVALID))) {
239 /* Emulated MMIO - mark this with key=31 */
240 pteh |= HPTE_V_ABSENT;
241 ptel |= HPTE_R_KEY_HI | HPTE_R_KEY_LO;
242 goto do_insert;
243 }
244
245 /* Check if the requested page fits entirely in the memslot. */
246 if (!slot_is_aligned(memslot, psize))
247 return H_PARAMETER;
248 slot_fn = gfn - memslot->base_gfn;
249 rmap = &memslot->arch.rmap[slot_fn];
250
251 /* Translate to host virtual address */
252 hva = __gfn_to_hva_memslot(memslot, gfn);
253 /*
254 * If we had a page table table change after lookup, we would
255 * retry via mmu_notifier_retry.
256 */
257 if (!realmode)
258 local_irq_save(irq_flags);
259 /*
260 * If called in real mode we have MSR_EE = 0. Otherwise
261 * we disable irq above.
262 */
263 ptep = __find_linux_pte(pgdir, hva, NULL, &hpage_shift);
264 if (ptep) {
265 pte_t pte;
266 unsigned int host_pte_size;
267
268 if (hpage_shift)
269 host_pte_size = 1ul << hpage_shift;
270 else
271 host_pte_size = PAGE_SIZE;
272 /*
273 * We should always find the guest page size
274 * to <= host page size, if host is using hugepage
275 */
276 if (host_pte_size < psize) {
277 if (!realmode)
278 local_irq_restore(flags);
279 return H_PARAMETER;
280 }
281 pte = kvmppc_read_update_linux_pte(ptep, writing);
282 if (pte_present(pte) && !pte_protnone(pte)) {
283 if (writing && !__pte_write(pte))
284 /* make the actual HPTE be read-only */
285 ptel = hpte_make_readonly(ptel);
286 is_ci = pte_ci(pte);
287 pa = pte_pfn(pte) << PAGE_SHIFT;
288 pa |= hva & (host_pte_size - 1);
289 pa |= gpa & ~PAGE_MASK;
290 }
291 }
292 if (!realmode)
293 local_irq_restore(irq_flags);
294
295 ptel &= HPTE_R_KEY | HPTE_R_PP0 | (psize-1);
296 ptel |= pa;
297
298 if (pa)
299 pteh |= HPTE_V_VALID;
300 else {
301 pteh |= HPTE_V_ABSENT;
302 ptel &= ~(HPTE_R_KEY_HI | HPTE_R_KEY_LO);
303 }
304
305 /*If we had host pte mapping then Check WIMG */
306 if (ptep && !hpte_cache_flags_ok(ptel, is_ci)) {
307 if (is_ci)
308 return H_PARAMETER;
309 /*
310 * Allow guest to map emulated device memory as
311 * uncacheable, but actually make it cacheable.
312 */
313 ptel &= ~(HPTE_R_W|HPTE_R_I|HPTE_R_G);
314 ptel |= HPTE_R_M;
315 }
316
317 /* Find and lock the HPTEG slot to use */
318 do_insert:
319 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
320 return H_PARAMETER;
321 if (likely((flags & H_EXACT) == 0)) {
322 pte_index &= ~7UL;
323 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
324 for (i = 0; i < 8; ++i) {
325 if ((be64_to_cpu(*hpte) & HPTE_V_VALID) == 0 &&
326 try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
327 HPTE_V_ABSENT))
328 break;
329 hpte += 2;
330 }
331 if (i == 8) {
332 /*
333 * Since try_lock_hpte doesn't retry (not even stdcx.
334 * failures), it could be that there is a free slot
335 * but we transiently failed to lock it. Try again,
336 * actually locking each slot and checking it.
337 */
338 hpte -= 16;
339 for (i = 0; i < 8; ++i) {
340 u64 pte;
341 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
342 cpu_relax();
343 pte = be64_to_cpu(hpte[0]);
344 if (!(pte & (HPTE_V_VALID | HPTE_V_ABSENT)))
345 break;
346 __unlock_hpte(hpte, pte);
347 hpte += 2;
348 }
349 if (i == 8)
350 return H_PTEG_FULL;
351 }
352 pte_index += i;
353 } else {
354 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
355 if (!try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
356 HPTE_V_ABSENT)) {
357 /* Lock the slot and check again */
358 u64 pte;
359
360 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
361 cpu_relax();
362 pte = be64_to_cpu(hpte[0]);
363 if (pte & (HPTE_V_VALID | HPTE_V_ABSENT)) {
364 __unlock_hpte(hpte, pte);
365 return H_PTEG_FULL;
366 }
367 }
368 }
369
370 /* Save away the guest's idea of the second HPTE dword */
371 rev = &kvm->arch.hpt.rev[pte_index];
372 if (realmode)
373 rev = real_vmalloc_addr(rev);
374 if (rev) {
375 rev->guest_rpte = g_ptel;
376 note_hpte_modification(kvm, rev);
377 }
378
379 /* Link HPTE into reverse-map chain */
380 if (pteh & HPTE_V_VALID) {
381 if (realmode)
382 rmap = real_vmalloc_addr(rmap);
383 lock_rmap(rmap);
384 /* Check for pending invalidations under the rmap chain lock */
385 if (mmu_notifier_retry(kvm, mmu_seq)) {
386 /* inval in progress, write a non-present HPTE */
387 pteh |= HPTE_V_ABSENT;
388 pteh &= ~HPTE_V_VALID;
389 ptel &= ~(HPTE_R_KEY_HI | HPTE_R_KEY_LO);
390 unlock_rmap(rmap);
391 } else {
392 kvmppc_add_revmap_chain(kvm, rev, rmap, pte_index,
393 realmode);
394 /* Only set R/C in real HPTE if already set in *rmap */
395 rcbits = *rmap >> KVMPPC_RMAP_RC_SHIFT;
396 ptel &= rcbits | ~(HPTE_R_R | HPTE_R_C);
397 }
398 }
399
400 /* Convert to new format on P9 */
401 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
402 ptel = hpte_old_to_new_r(pteh, ptel);
403 pteh = hpte_old_to_new_v(pteh);
404 }
405 hpte[1] = cpu_to_be64(ptel);
406
407 /* Write the first HPTE dword, unlocking the HPTE and making it valid */
408 eieio();
409 __unlock_hpte(hpte, pteh);
410 asm volatile("ptesync" : : : "memory");
411
412 *pte_idx_ret = pte_index;
413 return H_SUCCESS;
414 }
415 EXPORT_SYMBOL_GPL(kvmppc_do_h_enter);
416
417 long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
418 long pte_index, unsigned long pteh, unsigned long ptel)
419 {
420 return kvmppc_do_h_enter(vcpu->kvm, flags, pte_index, pteh, ptel,
421 vcpu->arch.pgdir, true, &vcpu->arch.gpr[4]);
422 }
423
424 #ifdef __BIG_ENDIAN__
425 #define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
426 #else
427 #define LOCK_TOKEN (*(u32 *)(&get_paca()->paca_index))
428 #endif
429
430 static inline int is_mmio_hpte(unsigned long v, unsigned long r)
431 {
432 return ((v & HPTE_V_ABSENT) &&
433 (r & (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) ==
434 (HPTE_R_KEY_HI | HPTE_R_KEY_LO));
435 }
436
437 static inline int try_lock_tlbie(unsigned int *lock)
438 {
439 unsigned int tmp, old;
440 unsigned int token = LOCK_TOKEN;
441
442 asm volatile("1:lwarx %1,0,%2\n"
443 " cmpwi cr0,%1,0\n"
444 " bne 2f\n"
445 " stwcx. %3,0,%2\n"
446 " bne- 1b\n"
447 " isync\n"
448 "2:"
449 : "=&r" (tmp), "=&r" (old)
450 : "r" (lock), "r" (token)
451 : "cc", "memory");
452 return old == 0;
453 }
454
455 static void do_tlbies(struct kvm *kvm, unsigned long *rbvalues,
456 long npages, int global, bool need_sync)
457 {
458 long i;
459
460 /*
461 * We use the POWER9 5-operand versions of tlbie and tlbiel here.
462 * Since we are using RIC=0 PRS=0 R=0, and P7/P8 tlbiel ignores
463 * the RS field, this is backwards-compatible with P7 and P8.
464 */
465 if (global) {
466 while (!try_lock_tlbie(&kvm->arch.tlbie_lock))
467 cpu_relax();
468 if (need_sync)
469 asm volatile("ptesync" : : : "memory");
470 for (i = 0; i < npages; ++i) {
471 asm volatile(PPC_TLBIE_5(%0,%1,0,0,0) : :
472 "r" (rbvalues[i]), "r" (kvm->arch.lpid));
473 }
474
475 if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) {
476 /*
477 * Need the extra ptesync to make sure we don't
478 * re-order the tlbie
479 */
480 asm volatile("ptesync": : :"memory");
481 asm volatile(PPC_TLBIE_5(%0,%1,0,0,0) : :
482 "r" (rbvalues[0]), "r" (kvm->arch.lpid));
483 }
484
485 asm volatile("eieio; tlbsync; ptesync" : : : "memory");
486 kvm->arch.tlbie_lock = 0;
487 } else {
488 if (need_sync)
489 asm volatile("ptesync" : : : "memory");
490 for (i = 0; i < npages; ++i) {
491 asm volatile(PPC_TLBIEL(%0,%1,0,0,0) : :
492 "r" (rbvalues[i]), "r" (0));
493 }
494 asm volatile("ptesync" : : : "memory");
495 }
496 }
497
498 long kvmppc_do_h_remove(struct kvm *kvm, unsigned long flags,
499 unsigned long pte_index, unsigned long avpn,
500 unsigned long *hpret)
501 {
502 __be64 *hpte;
503 unsigned long v, r, rb;
504 struct revmap_entry *rev;
505 u64 pte, orig_pte, pte_r;
506
507 if (kvm_is_radix(kvm))
508 return H_FUNCTION;
509 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
510 return H_PARAMETER;
511 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
512 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
513 cpu_relax();
514 pte = orig_pte = be64_to_cpu(hpte[0]);
515 pte_r = be64_to_cpu(hpte[1]);
516 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
517 pte = hpte_new_to_old_v(pte, pte_r);
518 pte_r = hpte_new_to_old_r(pte_r);
519 }
520 if ((pte & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
521 ((flags & H_AVPN) && (pte & ~0x7fUL) != avpn) ||
522 ((flags & H_ANDCOND) && (pte & avpn) != 0)) {
523 __unlock_hpte(hpte, orig_pte);
524 return H_NOT_FOUND;
525 }
526
527 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
528 v = pte & ~HPTE_V_HVLOCK;
529 if (v & HPTE_V_VALID) {
530 hpte[0] &= ~cpu_to_be64(HPTE_V_VALID);
531 rb = compute_tlbie_rb(v, pte_r, pte_index);
532 do_tlbies(kvm, &rb, 1, global_invalidates(kvm), true);
533 /*
534 * The reference (R) and change (C) bits in a HPT
535 * entry can be set by hardware at any time up until
536 * the HPTE is invalidated and the TLB invalidation
537 * sequence has completed. This means that when
538 * removing a HPTE, we need to re-read the HPTE after
539 * the invalidation sequence has completed in order to
540 * obtain reliable values of R and C.
541 */
542 remove_revmap_chain(kvm, pte_index, rev, v,
543 be64_to_cpu(hpte[1]));
544 }
545 r = rev->guest_rpte & ~HPTE_GR_RESERVED;
546 note_hpte_modification(kvm, rev);
547 unlock_hpte(hpte, 0);
548
549 if (is_mmio_hpte(v, pte_r))
550 atomic64_inc(&kvm->arch.mmio_update);
551
552 if (v & HPTE_V_ABSENT)
553 v = (v & ~HPTE_V_ABSENT) | HPTE_V_VALID;
554 hpret[0] = v;
555 hpret[1] = r;
556 return H_SUCCESS;
557 }
558 EXPORT_SYMBOL_GPL(kvmppc_do_h_remove);
559
560 long kvmppc_h_remove(struct kvm_vcpu *vcpu, unsigned long flags,
561 unsigned long pte_index, unsigned long avpn)
562 {
563 return kvmppc_do_h_remove(vcpu->kvm, flags, pte_index, avpn,
564 &vcpu->arch.gpr[4]);
565 }
566
567 long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
568 {
569 struct kvm *kvm = vcpu->kvm;
570 unsigned long *args = &vcpu->arch.gpr[4];
571 __be64 *hp, *hptes[4];
572 unsigned long tlbrb[4];
573 long int i, j, k, n, found, indexes[4];
574 unsigned long flags, req, pte_index, rcbits;
575 int global;
576 long int ret = H_SUCCESS;
577 struct revmap_entry *rev, *revs[4];
578 u64 hp0, hp1;
579
580 if (kvm_is_radix(kvm))
581 return H_FUNCTION;
582 global = global_invalidates(kvm);
583 for (i = 0; i < 4 && ret == H_SUCCESS; ) {
584 n = 0;
585 for (; i < 4; ++i) {
586 j = i * 2;
587 pte_index = args[j];
588 flags = pte_index >> 56;
589 pte_index &= ((1ul << 56) - 1);
590 req = flags >> 6;
591 flags &= 3;
592 if (req == 3) { /* no more requests */
593 i = 4;
594 break;
595 }
596 if (req != 1 || flags == 3 ||
597 pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt)) {
598 /* parameter error */
599 args[j] = ((0xa0 | flags) << 56) + pte_index;
600 ret = H_PARAMETER;
601 break;
602 }
603 hp = (__be64 *) (kvm->arch.hpt.virt + (pte_index << 4));
604 /* to avoid deadlock, don't spin except for first */
605 if (!try_lock_hpte(hp, HPTE_V_HVLOCK)) {
606 if (n)
607 break;
608 while (!try_lock_hpte(hp, HPTE_V_HVLOCK))
609 cpu_relax();
610 }
611 found = 0;
612 hp0 = be64_to_cpu(hp[0]);
613 hp1 = be64_to_cpu(hp[1]);
614 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
615 hp0 = hpte_new_to_old_v(hp0, hp1);
616 hp1 = hpte_new_to_old_r(hp1);
617 }
618 if (hp0 & (HPTE_V_ABSENT | HPTE_V_VALID)) {
619 switch (flags & 3) {
620 case 0: /* absolute */
621 found = 1;
622 break;
623 case 1: /* andcond */
624 if (!(hp0 & args[j + 1]))
625 found = 1;
626 break;
627 case 2: /* AVPN */
628 if ((hp0 & ~0x7fUL) == args[j + 1])
629 found = 1;
630 break;
631 }
632 }
633 if (!found) {
634 hp[0] &= ~cpu_to_be64(HPTE_V_HVLOCK);
635 args[j] = ((0x90 | flags) << 56) + pte_index;
636 continue;
637 }
638
639 args[j] = ((0x80 | flags) << 56) + pte_index;
640 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
641 note_hpte_modification(kvm, rev);
642
643 if (!(hp0 & HPTE_V_VALID)) {
644 /* insert R and C bits from PTE */
645 rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
646 args[j] |= rcbits << (56 - 5);
647 hp[0] = 0;
648 if (is_mmio_hpte(hp0, hp1))
649 atomic64_inc(&kvm->arch.mmio_update);
650 continue;
651 }
652
653 /* leave it locked */
654 hp[0] &= ~cpu_to_be64(HPTE_V_VALID);
655 tlbrb[n] = compute_tlbie_rb(hp0, hp1, pte_index);
656 indexes[n] = j;
657 hptes[n] = hp;
658 revs[n] = rev;
659 ++n;
660 }
661
662 if (!n)
663 break;
664
665 /* Now that we've collected a batch, do the tlbies */
666 do_tlbies(kvm, tlbrb, n, global, true);
667
668 /* Read PTE low words after tlbie to get final R/C values */
669 for (k = 0; k < n; ++k) {
670 j = indexes[k];
671 pte_index = args[j] & ((1ul << 56) - 1);
672 hp = hptes[k];
673 rev = revs[k];
674 remove_revmap_chain(kvm, pte_index, rev,
675 be64_to_cpu(hp[0]), be64_to_cpu(hp[1]));
676 rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
677 args[j] |= rcbits << (56 - 5);
678 __unlock_hpte(hp, 0);
679 }
680 }
681
682 return ret;
683 }
684
685 long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
686 unsigned long pte_index, unsigned long avpn,
687 unsigned long va)
688 {
689 struct kvm *kvm = vcpu->kvm;
690 __be64 *hpte;
691 struct revmap_entry *rev;
692 unsigned long v, r, rb, mask, bits;
693 u64 pte_v, pte_r;
694
695 if (kvm_is_radix(kvm))
696 return H_FUNCTION;
697 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
698 return H_PARAMETER;
699
700 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
701 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
702 cpu_relax();
703 v = pte_v = be64_to_cpu(hpte[0]);
704 if (cpu_has_feature(CPU_FTR_ARCH_300))
705 v = hpte_new_to_old_v(v, be64_to_cpu(hpte[1]));
706 if ((v & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
707 ((flags & H_AVPN) && (v & ~0x7fUL) != avpn)) {
708 __unlock_hpte(hpte, pte_v);
709 return H_NOT_FOUND;
710 }
711
712 pte_r = be64_to_cpu(hpte[1]);
713 bits = (flags << 55) & HPTE_R_PP0;
714 bits |= (flags << 48) & HPTE_R_KEY_HI;
715 bits |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
716
717 /* Update guest view of 2nd HPTE dword */
718 mask = HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
719 HPTE_R_KEY_HI | HPTE_R_KEY_LO;
720 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
721 if (rev) {
722 r = (rev->guest_rpte & ~mask) | bits;
723 rev->guest_rpte = r;
724 note_hpte_modification(kvm, rev);
725 }
726
727 /* Update HPTE */
728 if (v & HPTE_V_VALID) {
729 /*
730 * If the page is valid, don't let it transition from
731 * readonly to writable. If it should be writable, we'll
732 * take a trap and let the page fault code sort it out.
733 */
734 r = (pte_r & ~mask) | bits;
735 if (hpte_is_writable(r) && !hpte_is_writable(pte_r))
736 r = hpte_make_readonly(r);
737 /* If the PTE is changing, invalidate it first */
738 if (r != pte_r) {
739 rb = compute_tlbie_rb(v, r, pte_index);
740 hpte[0] = cpu_to_be64((pte_v & ~HPTE_V_VALID) |
741 HPTE_V_ABSENT);
742 do_tlbies(kvm, &rb, 1, global_invalidates(kvm), true);
743 /* Don't lose R/C bit updates done by hardware */
744 r |= be64_to_cpu(hpte[1]) & (HPTE_R_R | HPTE_R_C);
745 hpte[1] = cpu_to_be64(r);
746 }
747 }
748 unlock_hpte(hpte, pte_v & ~HPTE_V_HVLOCK);
749 asm volatile("ptesync" : : : "memory");
750 if (is_mmio_hpte(v, pte_r))
751 atomic64_inc(&kvm->arch.mmio_update);
752
753 return H_SUCCESS;
754 }
755
756 long kvmppc_h_read(struct kvm_vcpu *vcpu, unsigned long flags,
757 unsigned long pte_index)
758 {
759 struct kvm *kvm = vcpu->kvm;
760 __be64 *hpte;
761 unsigned long v, r;
762 int i, n = 1;
763 struct revmap_entry *rev = NULL;
764
765 if (kvm_is_radix(kvm))
766 return H_FUNCTION;
767 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
768 return H_PARAMETER;
769 if (flags & H_READ_4) {
770 pte_index &= ~3;
771 n = 4;
772 }
773 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
774 for (i = 0; i < n; ++i, ++pte_index) {
775 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
776 v = be64_to_cpu(hpte[0]) & ~HPTE_V_HVLOCK;
777 r = be64_to_cpu(hpte[1]);
778 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
779 v = hpte_new_to_old_v(v, r);
780 r = hpte_new_to_old_r(r);
781 }
782 if (v & HPTE_V_ABSENT) {
783 v &= ~HPTE_V_ABSENT;
784 v |= HPTE_V_VALID;
785 }
786 if (v & HPTE_V_VALID) {
787 r = rev[i].guest_rpte | (r & (HPTE_R_R | HPTE_R_C));
788 r &= ~HPTE_GR_RESERVED;
789 }
790 vcpu->arch.gpr[4 + i * 2] = v;
791 vcpu->arch.gpr[5 + i * 2] = r;
792 }
793 return H_SUCCESS;
794 }
795
796 long kvmppc_h_clear_ref(struct kvm_vcpu *vcpu, unsigned long flags,
797 unsigned long pte_index)
798 {
799 struct kvm *kvm = vcpu->kvm;
800 __be64 *hpte;
801 unsigned long v, r, gr;
802 struct revmap_entry *rev;
803 unsigned long *rmap;
804 long ret = H_NOT_FOUND;
805
806 if (kvm_is_radix(kvm))
807 return H_FUNCTION;
808 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
809 return H_PARAMETER;
810
811 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
812 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
813 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
814 cpu_relax();
815 v = be64_to_cpu(hpte[0]);
816 r = be64_to_cpu(hpte[1]);
817 if (!(v & (HPTE_V_VALID | HPTE_V_ABSENT)))
818 goto out;
819
820 gr = rev->guest_rpte;
821 if (rev->guest_rpte & HPTE_R_R) {
822 rev->guest_rpte &= ~HPTE_R_R;
823 note_hpte_modification(kvm, rev);
824 }
825 if (v & HPTE_V_VALID) {
826 gr |= r & (HPTE_R_R | HPTE_R_C);
827 if (r & HPTE_R_R) {
828 kvmppc_clear_ref_hpte(kvm, hpte, pte_index);
829 rmap = revmap_for_hpte(kvm, v, gr, NULL, NULL);
830 if (rmap) {
831 lock_rmap(rmap);
832 *rmap |= KVMPPC_RMAP_REFERENCED;
833 unlock_rmap(rmap);
834 }
835 }
836 }
837 vcpu->arch.gpr[4] = gr;
838 ret = H_SUCCESS;
839 out:
840 unlock_hpte(hpte, v & ~HPTE_V_HVLOCK);
841 return ret;
842 }
843
844 long kvmppc_h_clear_mod(struct kvm_vcpu *vcpu, unsigned long flags,
845 unsigned long pte_index)
846 {
847 struct kvm *kvm = vcpu->kvm;
848 __be64 *hpte;
849 unsigned long v, r, gr;
850 struct revmap_entry *rev;
851 long ret = H_NOT_FOUND;
852
853 if (kvm_is_radix(kvm))
854 return H_FUNCTION;
855 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
856 return H_PARAMETER;
857
858 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
859 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
860 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
861 cpu_relax();
862 v = be64_to_cpu(hpte[0]);
863 r = be64_to_cpu(hpte[1]);
864 if (!(v & (HPTE_V_VALID | HPTE_V_ABSENT)))
865 goto out;
866
867 gr = rev->guest_rpte;
868 if (gr & HPTE_R_C) {
869 rev->guest_rpte &= ~HPTE_R_C;
870 note_hpte_modification(kvm, rev);
871 }
872 if (v & HPTE_V_VALID) {
873 /* need to make it temporarily absent so C is stable */
874 hpte[0] |= cpu_to_be64(HPTE_V_ABSENT);
875 kvmppc_invalidate_hpte(kvm, hpte, pte_index);
876 r = be64_to_cpu(hpte[1]);
877 gr |= r & (HPTE_R_R | HPTE_R_C);
878 if (r & HPTE_R_C) {
879 hpte[1] = cpu_to_be64(r & ~HPTE_R_C);
880 eieio();
881 kvmppc_set_dirty_from_hpte(kvm, v, gr);
882 }
883 }
884 vcpu->arch.gpr[4] = gr;
885 ret = H_SUCCESS;
886 out:
887 unlock_hpte(hpte, v & ~HPTE_V_HVLOCK);
888 return ret;
889 }
890
891 void kvmppc_invalidate_hpte(struct kvm *kvm, __be64 *hptep,
892 unsigned long pte_index)
893 {
894 unsigned long rb;
895 u64 hp0, hp1;
896
897 hptep[0] &= ~cpu_to_be64(HPTE_V_VALID);
898 hp0 = be64_to_cpu(hptep[0]);
899 hp1 = be64_to_cpu(hptep[1]);
900 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
901 hp0 = hpte_new_to_old_v(hp0, hp1);
902 hp1 = hpte_new_to_old_r(hp1);
903 }
904 rb = compute_tlbie_rb(hp0, hp1, pte_index);
905 do_tlbies(kvm, &rb, 1, 1, true);
906 }
907 EXPORT_SYMBOL_GPL(kvmppc_invalidate_hpte);
908
909 void kvmppc_clear_ref_hpte(struct kvm *kvm, __be64 *hptep,
910 unsigned long pte_index)
911 {
912 unsigned long rb;
913 unsigned char rbyte;
914 u64 hp0, hp1;
915
916 hp0 = be64_to_cpu(hptep[0]);
917 hp1 = be64_to_cpu(hptep[1]);
918 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
919 hp0 = hpte_new_to_old_v(hp0, hp1);
920 hp1 = hpte_new_to_old_r(hp1);
921 }
922 rb = compute_tlbie_rb(hp0, hp1, pte_index);
923 rbyte = (be64_to_cpu(hptep[1]) & ~HPTE_R_R) >> 8;
924 /* modify only the second-last byte, which contains the ref bit */
925 *((char *)hptep + 14) = rbyte;
926 do_tlbies(kvm, &rb, 1, 1, false);
927 }
928 EXPORT_SYMBOL_GPL(kvmppc_clear_ref_hpte);
929
930 static int slb_base_page_shift[4] = {
931 24, /* 16M */
932 16, /* 64k */
933 34, /* 16G */
934 20, /* 1M, unsupported */
935 };
936
937 static struct mmio_hpte_cache_entry *mmio_cache_search(struct kvm_vcpu *vcpu,
938 unsigned long eaddr, unsigned long slb_v, long mmio_update)
939 {
940 struct mmio_hpte_cache_entry *entry = NULL;
941 unsigned int pshift;
942 unsigned int i;
943
944 for (i = 0; i < MMIO_HPTE_CACHE_SIZE; i++) {
945 entry = &vcpu->arch.mmio_cache.entry[i];
946 if (entry->mmio_update == mmio_update) {
947 pshift = entry->slb_base_pshift;
948 if ((entry->eaddr >> pshift) == (eaddr >> pshift) &&
949 entry->slb_v == slb_v)
950 return entry;
951 }
952 }
953 return NULL;
954 }
955
956 static struct mmio_hpte_cache_entry *
957 next_mmio_cache_entry(struct kvm_vcpu *vcpu)
958 {
959 unsigned int index = vcpu->arch.mmio_cache.index;
960
961 vcpu->arch.mmio_cache.index++;
962 if (vcpu->arch.mmio_cache.index == MMIO_HPTE_CACHE_SIZE)
963 vcpu->arch.mmio_cache.index = 0;
964
965 return &vcpu->arch.mmio_cache.entry[index];
966 }
967
968 /* When called from virtmode, this func should be protected by
969 * preempt_disable(), otherwise, the holding of HPTE_V_HVLOCK
970 * can trigger deadlock issue.
971 */
972 long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr, unsigned long slb_v,
973 unsigned long valid)
974 {
975 unsigned int i;
976 unsigned int pshift;
977 unsigned long somask;
978 unsigned long vsid, hash;
979 unsigned long avpn;
980 __be64 *hpte;
981 unsigned long mask, val;
982 unsigned long v, r, orig_v;
983
984 /* Get page shift, work out hash and AVPN etc. */
985 mask = SLB_VSID_B | HPTE_V_AVPN | HPTE_V_SECONDARY;
986 val = 0;
987 pshift = 12;
988 if (slb_v & SLB_VSID_L) {
989 mask |= HPTE_V_LARGE;
990 val |= HPTE_V_LARGE;
991 pshift = slb_base_page_shift[(slb_v & SLB_VSID_LP) >> 4];
992 }
993 if (slb_v & SLB_VSID_B_1T) {
994 somask = (1UL << 40) - 1;
995 vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT_1T;
996 vsid ^= vsid << 25;
997 } else {
998 somask = (1UL << 28) - 1;
999 vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT;
1000 }
1001 hash = (vsid ^ ((eaddr & somask) >> pshift)) & kvmppc_hpt_mask(&kvm->arch.hpt);
1002 avpn = slb_v & ~(somask >> 16); /* also includes B */
1003 avpn |= (eaddr & somask) >> 16;
1004
1005 if (pshift >= 24)
1006 avpn &= ~((1UL << (pshift - 16)) - 1);
1007 else
1008 avpn &= ~0x7fUL;
1009 val |= avpn;
1010
1011 for (;;) {
1012 hpte = (__be64 *)(kvm->arch.hpt.virt + (hash << 7));
1013
1014 for (i = 0; i < 16; i += 2) {
1015 /* Read the PTE racily */
1016 v = be64_to_cpu(hpte[i]) & ~HPTE_V_HVLOCK;
1017 if (cpu_has_feature(CPU_FTR_ARCH_300))
1018 v = hpte_new_to_old_v(v, be64_to_cpu(hpte[i+1]));
1019
1020 /* Check valid/absent, hash, segment size and AVPN */
1021 if (!(v & valid) || (v & mask) != val)
1022 continue;
1023
1024 /* Lock the PTE and read it under the lock */
1025 while (!try_lock_hpte(&hpte[i], HPTE_V_HVLOCK))
1026 cpu_relax();
1027 v = orig_v = be64_to_cpu(hpte[i]) & ~HPTE_V_HVLOCK;
1028 r = be64_to_cpu(hpte[i+1]);
1029 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1030 v = hpte_new_to_old_v(v, r);
1031 r = hpte_new_to_old_r(r);
1032 }
1033
1034 /*
1035 * Check the HPTE again, including base page size
1036 */
1037 if ((v & valid) && (v & mask) == val &&
1038 kvmppc_hpte_base_page_shift(v, r) == pshift)
1039 /* Return with the HPTE still locked */
1040 return (hash << 3) + (i >> 1);
1041
1042 __unlock_hpte(&hpte[i], orig_v);
1043 }
1044
1045 if (val & HPTE_V_SECONDARY)
1046 break;
1047 val |= HPTE_V_SECONDARY;
1048 hash = hash ^ kvmppc_hpt_mask(&kvm->arch.hpt);
1049 }
1050 return -1;
1051 }
1052 EXPORT_SYMBOL(kvmppc_hv_find_lock_hpte);
1053
1054 /*
1055 * Called in real mode to check whether an HPTE not found fault
1056 * is due to accessing a paged-out page or an emulated MMIO page,
1057 * or if a protection fault is due to accessing a page that the
1058 * guest wanted read/write access to but which we made read-only.
1059 * Returns a possibly modified status (DSISR) value if not
1060 * (i.e. pass the interrupt to the guest),
1061 * -1 to pass the fault up to host kernel mode code, -2 to do that
1062 * and also load the instruction word (for MMIO emulation),
1063 * or 0 if we should make the guest retry the access.
1064 */
1065 long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned long addr,
1066 unsigned long slb_v, unsigned int status, bool data)
1067 {
1068 struct kvm *kvm = vcpu->kvm;
1069 long int index;
1070 unsigned long v, r, gr, orig_v;
1071 __be64 *hpte;
1072 unsigned long valid;
1073 struct revmap_entry *rev;
1074 unsigned long pp, key;
1075 struct mmio_hpte_cache_entry *cache_entry = NULL;
1076 long mmio_update = 0;
1077
1078 /* For protection fault, expect to find a valid HPTE */
1079 valid = HPTE_V_VALID;
1080 if (status & DSISR_NOHPTE) {
1081 valid |= HPTE_V_ABSENT;
1082 mmio_update = atomic64_read(&kvm->arch.mmio_update);
1083 cache_entry = mmio_cache_search(vcpu, addr, slb_v, mmio_update);
1084 }
1085 if (cache_entry) {
1086 index = cache_entry->pte_index;
1087 v = cache_entry->hpte_v;
1088 r = cache_entry->hpte_r;
1089 gr = cache_entry->rpte;
1090 } else {
1091 index = kvmppc_hv_find_lock_hpte(kvm, addr, slb_v, valid);
1092 if (index < 0) {
1093 if (status & DSISR_NOHPTE)
1094 return status; /* there really was no HPTE */
1095 return 0; /* for prot fault, HPTE disappeared */
1096 }
1097 hpte = (__be64 *)(kvm->arch.hpt.virt + (index << 4));
1098 v = orig_v = be64_to_cpu(hpte[0]) & ~HPTE_V_HVLOCK;
1099 r = be64_to_cpu(hpte[1]);
1100 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1101 v = hpte_new_to_old_v(v, r);
1102 r = hpte_new_to_old_r(r);
1103 }
1104 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[index]);
1105 gr = rev->guest_rpte;
1106
1107 unlock_hpte(hpte, orig_v);
1108 }
1109
1110 /* For not found, if the HPTE is valid by now, retry the instruction */
1111 if ((status & DSISR_NOHPTE) && (v & HPTE_V_VALID))
1112 return 0;
1113
1114 /* Check access permissions to the page */
1115 pp = gr & (HPTE_R_PP0 | HPTE_R_PP);
1116 key = (vcpu->arch.shregs.msr & MSR_PR) ? SLB_VSID_KP : SLB_VSID_KS;
1117 status &= ~DSISR_NOHPTE; /* DSISR_NOHPTE == SRR1_ISI_NOPT */
1118 if (!data) {
1119 if (gr & (HPTE_R_N | HPTE_R_G))
1120 return status | SRR1_ISI_N_OR_G;
1121 if (!hpte_read_permission(pp, slb_v & key))
1122 return status | SRR1_ISI_PROT;
1123 } else if (status & DSISR_ISSTORE) {
1124 /* check write permission */
1125 if (!hpte_write_permission(pp, slb_v & key))
1126 return status | DSISR_PROTFAULT;
1127 } else {
1128 if (!hpte_read_permission(pp, slb_v & key))
1129 return status | DSISR_PROTFAULT;
1130 }
1131
1132 /* Check storage key, if applicable */
1133 if (data && (vcpu->arch.shregs.msr & MSR_DR)) {
1134 unsigned int perm = hpte_get_skey_perm(gr, vcpu->arch.amr);
1135 if (status & DSISR_ISSTORE)
1136 perm >>= 1;
1137 if (perm & 1)
1138 return status | DSISR_KEYFAULT;
1139 }
1140
1141 /* Save HPTE info for virtual-mode handler */
1142 vcpu->arch.pgfault_addr = addr;
1143 vcpu->arch.pgfault_index = index;
1144 vcpu->arch.pgfault_hpte[0] = v;
1145 vcpu->arch.pgfault_hpte[1] = r;
1146 vcpu->arch.pgfault_cache = cache_entry;
1147
1148 /* Check the storage key to see if it is possibly emulated MMIO */
1149 if ((r & (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) ==
1150 (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) {
1151 if (!cache_entry) {
1152 unsigned int pshift = 12;
1153 unsigned int pshift_index;
1154
1155 if (slb_v & SLB_VSID_L) {
1156 pshift_index = ((slb_v & SLB_VSID_LP) >> 4);
1157 pshift = slb_base_page_shift[pshift_index];
1158 }
1159 cache_entry = next_mmio_cache_entry(vcpu);
1160 cache_entry->eaddr = addr;
1161 cache_entry->slb_base_pshift = pshift;
1162 cache_entry->pte_index = index;
1163 cache_entry->hpte_v = v;
1164 cache_entry->hpte_r = r;
1165 cache_entry->rpte = gr;
1166 cache_entry->slb_v = slb_v;
1167 cache_entry->mmio_update = mmio_update;
1168 }
1169 if (data && (vcpu->arch.shregs.msr & MSR_IR))
1170 return -2; /* MMIO emulation - load instr word */
1171 }
1172
1173 return -1; /* send fault up to host kernel mode */
1174 }
Linux with added FPC-III support