arch/arm/mach-nomadik/include/mach/mtu.h

   1 #ifndef __ASM_ARCH_MTU_H
   2 #define __ASM_ARCH_MTU_H
   3
   4 /*
   5  * The MTU device hosts four different counters, with 4 set of
   6  * registers. These are register names.
   7  */
   8
   9 #define MTU_IMSC        0x00    /* Interrupt mask set/clear */
  10 #define MTU_RIS         0x04    /* Raw interrupt status */
  11 #define MTU_MIS         0x08    /* Masked interrupt status */
  12 #define MTU_ICR         0x0C    /* Interrupt clear register */
  13
  14 /* per-timer registers take 0..3 as argument */
  15 #define MTU_LR(x)       (0x10 + 0x10 * (x) + 0x00)      /* Load value */
  16 #define MTU_VAL(x)      (0x10 + 0x10 * (x) + 0x04)      /* Current value */
  17 #define MTU_CR(x)       (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
  18 #define MTU_BGLR(x)     (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
  19
  20 /* bits for the control register */
  21 #define MTU_CRn_ENA             0x80
  22 #define MTU_CRn_PERIODIC        0x40    /* if 0 = free-running */
  23 #define MTU_CRn_PRESCALE_MASK   0x0c
  24 #define MTU_CRn_PRESCALE_1              0x00
  25 #define MTU_CRn_PRESCALE_16             0x04
  26 #define MTU_CRn_PRESCALE_256            0x08
  27 #define MTU_CRn_32BITS          0x02
  28 #define MTU_CRn_ONESHOT         0x01    /* if 0 = wraps reloading from BGLR*/
  29
  30 /* Other registers are usual amba/primecell registers, currently not used */
  31 #define MTU_ITCR        0xff0
  32 #define MTU_ITOP        0xff4
  33
  34 #define MTU_PERIPH_ID0  0xfe0
  35 #define MTU_PERIPH_ID1  0xfe4
  36 #define MTU_PERIPH_ID2  0xfe8
  37 #define MTU_PERIPH_ID3  0xfeC
  38
  39 #define MTU_PCELL0      0xff0
  40 #define MTU_PCELL1      0xff4
  41 #define MTU_PCELL2      0xff8
  42 #define MTU_PCELL3      0xffC
  43
  44 #endif /* __ASM_ARCH_MTU_H */
  45