arch/arm/mach-omap2/iommu2.c

   1 /*
   2  * omap iommu: omap2/3 architecture specific functions
   3  *
   4  * Copyright (C) 2008-2009 Nokia Corporation
   5  *
   6  * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
   7  *              Paul Mundt and Toshihiro Kobayashi
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/err.h>
  15 #include <linux/device.h>
  16 #include <linux/jiffies.h>
  17 #include <linux/module.h>
  18 #include <linux/stringify.h>
  19
  20 #include <mach/iommu.h>
  21
  22 /*
  23  * omap2 architecture specific register bit definitions
  24  */
  25 #define IOMMU_ARCH_VERSION      0x00000011
  26
  27 /* SYSCONF */
  28 #define MMU_SYS_IDLE_SHIFT      3
  29 #define MMU_SYS_IDLE_FORCE      (0 << MMU_SYS_IDLE_SHIFT)
  30 #define MMU_SYS_IDLE_NONE       (1 << MMU_SYS_IDLE_SHIFT)
  31 #define MMU_SYS_IDLE_SMART      (2 << MMU_SYS_IDLE_SHIFT)
  32 #define MMU_SYS_IDLE_MASK       (3 << MMU_SYS_IDLE_SHIFT)
  33
  34 #define MMU_SYS_SOFTRESET       (1 << 1)
  35 #define MMU_SYS_AUTOIDLE        1
  36
  37 /* SYSSTATUS */
  38 #define MMU_SYS_RESETDONE       1
  39
  40 /* IRQSTATUS & IRQENABLE */
  41 #define MMU_IRQ_MULTIHITFAULT   (1 << 4)
  42 #define MMU_IRQ_TABLEWALKFAULT  (1 << 3)
  43 #define MMU_IRQ_EMUMISS         (1 << 2)
  44 #define MMU_IRQ_TRANSLATIONFAULT        (1 << 1)
  45 #define MMU_IRQ_TLBMISS         (1 << 0)
  46 #define MMU_IRQ_MASK    \
  47         (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \
  48          MMU_IRQ_TRANSLATIONFAULT)
  49
  50 /* MMU_CNTL */
  51 #define MMU_CNTL_SHIFT          1
  52 #define MMU_CNTL_MASK           (7 << MMU_CNTL_SHIFT)
  53 #define MMU_CNTL_EML_TLB        (1 << 3)
  54 #define MMU_CNTL_TWL_EN         (1 << 2)
  55 #define MMU_CNTL_MMU_EN         (1 << 1)
  56
  57 #define get_cam_va_mask(pgsz)                           \
  58         (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 :    \
  59          ((pgsz) == MMU_CAM_PGSZ_1M)  ? 0xfff00000 :    \
  60          ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :    \
  61          ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
  62
  63 static int omap2_iommu_enable(struct iommu *obj)
  64 {
  65         u32 l, pa;
  66         unsigned long timeout;
  67
  68         if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd,  SZ_16K))
  69                 return -EINVAL;
  70
  71         pa = virt_to_phys(obj->iopgd);
  72         if (!IS_ALIGNED(pa, SZ_16K))
  73                 return -EINVAL;
  74
  75         iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG);
  76
  77         timeout = jiffies + msecs_to_jiffies(20);
  78         do {
  79                 l = iommu_read_reg(obj, MMU_SYSSTATUS);
  80                 if (l & MMU_SYS_RESETDONE)
  81                         break;
  82         } while (!time_after(jiffies, timeout));
  83
  84         if (!(l & MMU_SYS_RESETDONE)) {
  85                 dev_err(obj->dev, "can't take mmu out of reset\n");
  86                 return -ENODEV;
  87         }
  88
  89         l = iommu_read_reg(obj, MMU_REVISION);
  90         dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
  91                  (l >> 4) & 0xf, l & 0xf);
  92
  93         l = iommu_read_reg(obj, MMU_SYSCONFIG);
  94         l &= ~MMU_SYS_IDLE_MASK;
  95         l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
  96         iommu_write_reg(obj, l, MMU_SYSCONFIG);
  97
  98         iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE);
  99         iommu_write_reg(obj, pa, MMU_TTB);
 100
 101         l = iommu_read_reg(obj, MMU_CNTL);
 102         l &= ~MMU_CNTL_MASK;
 103         l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
 104         iommu_write_reg(obj, l, MMU_CNTL);
 105
 106         return 0;
 107 }
 108
 109 static void omap2_iommu_disable(struct iommu *obj)
 110 {
 111         u32 l = iommu_read_reg(obj, MMU_CNTL);
 112
 113         l &= ~MMU_CNTL_MASK;
 114         iommu_write_reg(obj, l, MMU_CNTL);
 115         iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG);
 116
 117         dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
 118 }
 119
 120 static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
 121 {
 122         int i;
 123         u32 stat, da;
 124         const char *err_msg[] = {
 125                 "tlb miss",
 126                 "translation fault",
 127                 "emulation miss",
 128                 "table walk fault",
 129                 "multi hit fault",
 130         };
 131
 132         stat = iommu_read_reg(obj, MMU_IRQSTATUS);
 133         stat &= MMU_IRQ_MASK;
 134         if (!stat)
 135                 return 0;
 136
 137         da = iommu_read_reg(obj, MMU_FAULT_AD);
 138         *ra = da;
 139
 140         dev_err(obj->dev, "%s:\tda:%08x ", __func__, da);
 141
 142         for (i = 0; i < ARRAY_SIZE(err_msg); i++) {
 143                 if (stat & (1 << i))
 144                         printk("%s ", err_msg[i]);
 145         }
 146         printk("\n");
 147
 148         iommu_write_reg(obj, stat, MMU_IRQSTATUS);
 149         return stat;
 150 }
 151
 152 static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr)
 153 {
 154         cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
 155         cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
 156 }
 157
 158 static void omap2_tlb_load_cr(struct iommu *obj, struct cr_regs *cr)
 159 {
 160         iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
 161         iommu_write_reg(obj, cr->ram, MMU_RAM);
 162 }
 163
 164 static u32 omap2_cr_to_virt(struct cr_regs *cr)
 165 {
 166         u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
 167         u32 mask = get_cam_va_mask(cr->cam & page_size);
 168
 169         return cr->cam & mask;
 170 }
 171
 172 static struct cr_regs *omap2_alloc_cr(struct iommu *obj, struct iotlb_entry *e)
 173 {
 174         struct cr_regs *cr;
 175
 176         if (e->da & ~(get_cam_va_mask(e->pgsz))) {
 177                 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
 178                         e->da);
 179                 return ERR_PTR(-EINVAL);
 180         }
 181
 182         cr = kmalloc(sizeof(*cr), GFP_KERNEL);
 183         if (!cr)
 184                 return ERR_PTR(-ENOMEM);
 185
 186         cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz;
 187         cr->ram = e->pa | e->endian | e->elsz | e->mixed;
 188
 189         return cr;
 190 }
 191
 192 static inline int omap2_cr_valid(struct cr_regs *cr)
 193 {
 194         return cr->cam & MMU_CAM_V;
 195 }
 196
 197 static u32 omap2_get_pte_attr(struct iotlb_entry *e)
 198 {
 199         u32 attr;
 200
 201         attr = e->mixed << 5;
 202         attr |= e->endian;
 203         attr |= e->elsz >> 3;
 204         attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6);
 205
 206         return attr;
 207 }
 208
 209 static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf)
 210 {
 211         char *p = buf;
 212
 213         /* FIXME: Need more detail analysis of cam/ram */
 214         p += sprintf(p, "%08x %08x\n", cr->cam, cr->ram);
 215
 216         return p - buf;
 217 }
 218
 219 #define pr_reg(name)                                                    \
 220         do {                                                            \
 221                 ssize_t bytes;                                          \
 222                 const char *str = "%20s: %08x\n";                       \
 223                 const int maxcol = 32;                                  \
 224                 bytes = snprintf(p, maxcol, str, __stringify(name),     \
 225                                  iommu_read_reg(obj, MMU_##name));      \
 226                 p += bytes;                                             \
 227                 len -= bytes;                                           \
 228                 if (len < maxcol)                                       \
 229                         goto out;                                       \
 230         } while (0)
 231
 232 static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len)
 233 {
 234         char *p = buf;
 235
 236         pr_reg(REVISION);
 237         pr_reg(SYSCONFIG);
 238         pr_reg(SYSSTATUS);
 239         pr_reg(IRQSTATUS);
 240         pr_reg(IRQENABLE);
 241         pr_reg(WALKING_ST);
 242         pr_reg(CNTL);
 243         pr_reg(FAULT_AD);
 244         pr_reg(TTB);
 245         pr_reg(LOCK);
 246         pr_reg(LD_TLB);
 247         pr_reg(CAM);
 248         pr_reg(RAM);
 249         pr_reg(GFLUSH);
 250         pr_reg(FLUSH_ENTRY);
 251         pr_reg(READ_CAM);
 252         pr_reg(READ_RAM);
 253         pr_reg(EMU_FAULT_AD);
 254 out:
 255         return p - buf;
 256 }
 257
 258 static void omap2_iommu_save_ctx(struct iommu *obj)
 259 {
 260         int i;
 261         u32 *p = obj->ctx;
 262
 263         for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
 264                 p[i] = iommu_read_reg(obj, i * sizeof(u32));
 265                 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
 266         }
 267
 268         BUG_ON(p[0] != IOMMU_ARCH_VERSION);
 269 }
 270
 271 static void omap2_iommu_restore_ctx(struct iommu *obj)
 272 {
 273         int i;
 274         u32 *p = obj->ctx;
 275
 276         for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
 277                 iommu_write_reg(obj, p[i], i * sizeof(u32));
 278                 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i, p[i]);
 279         }
 280
 281         BUG_ON(p[0] != IOMMU_ARCH_VERSION);
 282 }
 283
 284 static void omap2_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
 285 {
 286         e->da           = cr->cam & MMU_CAM_VATAG_MASK;
 287         e->pa           = cr->ram & MMU_RAM_PADDR_MASK;
 288         e->valid        = cr->cam & MMU_CAM_V;
 289         e->pgsz         = cr->cam & MMU_CAM_PGSZ_MASK;
 290         e->endian       = cr->ram & MMU_RAM_ENDIAN_MASK;
 291         e->elsz         = cr->ram & MMU_RAM_ELSZ_MASK;
 292         e->mixed        = cr->ram & MMU_RAM_MIXED;
 293 }
 294
 295 static const struct iommu_functions omap2_iommu_ops = {
 296         .version        = IOMMU_ARCH_VERSION,
 297
 298         .enable         = omap2_iommu_enable,
 299         .disable        = omap2_iommu_disable,
 300         .fault_isr      = omap2_iommu_fault_isr,
 301
 302         .tlb_read_cr    = omap2_tlb_read_cr,
 303         .tlb_load_cr    = omap2_tlb_load_cr,
 304
 305         .cr_to_e        = omap2_cr_to_e,
 306         .cr_to_virt     = omap2_cr_to_virt,
 307         .alloc_cr       = omap2_alloc_cr,
 308         .cr_valid       = omap2_cr_valid,
 309         .dump_cr        = omap2_dump_cr,
 310
 311         .get_pte_attr   = omap2_get_pte_attr,
 312
 313         .save_ctx       = omap2_iommu_save_ctx,
 314         .restore_ctx    = omap2_iommu_restore_ctx,
 315         .dump_ctx       = omap2_iommu_dump_ctx,
 316 };
 317
 318 static int __init omap2_iommu_init(void)
 319 {
 320         return install_iommu_arch(&omap2_iommu_ops);
 321 }
 322 module_init(omap2_iommu_init);
 323
 324 static void __exit omap2_iommu_exit(void)
 325 {
 326         uninstall_iommu_arch(&omap2_iommu_ops);
 327 }
 328 module_exit(omap2_iommu_exit);
 329
 330 MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
 331 MODULE_DESCRIPTION("omap iommu: omap2/3 architecture specific functions");
 332 MODULE_LICENSE("GPL v2");