arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2005 Texas Instruments, Inc.
   9  * Richard Woodruff <r-woodruff2@ti.com>
  10  *
  11  * Based on pm.c for omap1
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17
  18 #include <linux/pm.h>
  19 #include <linux/suspend.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/list.h>
  23 #include <linux/err.h>
  24 #include <linux/gpio.h>
  25
  26 #include <mach/sram.h>
  27 #include <mach/clockdomain.h>
  28 #include <mach/powerdomain.h>
  29 #include <mach/control.h>
  30 #include <mach/serial.h>
  31
  32 #include "cm.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "prm-regbits-34xx.h"
  35
  36 #include "prm.h"
  37 #include "pm.h"
  38
  39 struct power_state {
  40         struct powerdomain *pwrdm;
  41         u32 next_state;
  42 #ifdef CONFIG_SUSPEND
  43         u32 saved_state;
  44 #endif
  45         struct list_head node;
  46 };
  47
  48 static LIST_HEAD(pwrst_list);
  49
  50 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  51
  52 static struct powerdomain *mpu_pwrdm;
  53
  54 /*
  55  * PRCM Interrupt Handler Helper Function
  56  *
  57  * The purpose of this function is to clear any wake-up events latched
  58  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
  59  * may occur whilst attempting to clear a PM_WKST_x register and thus
  60  * set another bit in this register. A while loop is used to ensure
  61  * that any peripheral wake-up events occurring while attempting to
  62  * clear the PM_WKST_x are detected and cleared.
  63  */
  64 static int prcm_clear_mod_irqs(s16 module, u8 regs)
  65 {
  66         u32 wkst, fclk, iclk, clken;
  67         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
  68         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
  69         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
  70         u16 grpsel_off = (regs == 3) ?
  71                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
  72         int c = 0;
  73
  74         wkst = prm_read_mod_reg(module, wkst_off);
  75         wkst &= prm_read_mod_reg(module, grpsel_off);
  76         if (wkst) {
  77                 iclk = cm_read_mod_reg(module, iclk_off);
  78                 fclk = cm_read_mod_reg(module, fclk_off);
  79                 while (wkst) {
  80                         clken = wkst;
  81                         cm_set_mod_reg_bits(clken, module, iclk_off);
  82                         /*
  83                          * For USBHOST, we don't know whether HOST1 or
  84                          * HOST2 woke us up, so enable both f-clocks
  85                          */
  86                         if (module == OMAP3430ES2_USBHOST_MOD)
  87                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
  88                         cm_set_mod_reg_bits(clken, module, fclk_off);
  89                         prm_write_mod_reg(wkst, module, wkst_off);
  90                         wkst = prm_read_mod_reg(module, wkst_off);
  91                         c++;
  92                 }
  93                 cm_write_mod_reg(iclk, module, iclk_off);
  94                 cm_write_mod_reg(fclk, module, fclk_off);
  95         }
  96
  97         return c;
  98 }
  99
 100 static int _prcm_int_handle_wakeup(void)
 101 {
 102         int c;
 103
 104         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 105         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 106         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 107         if (omap_rev() > OMAP3430_REV_ES1_0) {
 108                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 109                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 110         }
 111
 112         return c;
 113 }
 114
 115 /*
 116  * PRCM Interrupt Handler
 117  *
 118  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 119  * interrupts from the PRCM for the MPU. These bits must be cleared in
 120  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 121  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 122  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 123  * register indicates that a wake-up event is pending for the MPU and
 124  * this bit can only be cleared if the all the wake-up events latched
 125  * in the various PM_WKST_x registers have been cleared. The interrupt
 126  * handler is implemented using a do-while loop so that if a wake-up
 127  * event occurred during the processing of the prcm interrupt handler
 128  * (setting a bit in the corresponding PM_WKST_x register and thus
 129  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 130  * this would be handled.
 131  */
 132 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 133 {
 134         u32 irqstatus_mpu;
 135         int c = 0;
 136
 137         do {
 138                 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 139                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 140
 141                 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
 142                         c = _prcm_int_handle_wakeup();
 143
 144                         /*
 145                          * Is the MPU PRCM interrupt handler racing with the
 146                          * IVA2 PRCM interrupt handler ?
 147                          */
 148                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 149                              "but no wakeup sources are marked\n");
 150                 } else {
 151                         /* XXX we need to expand our PRCM interrupt handler */
 152                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 153                              "no code to handle it (%08x)\n", irqstatus_mpu);
 154                 }
 155
 156                 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 157                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 158
 159         } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
 160
 161         return IRQ_HANDLED;
 162 }
 163
 164 static void omap_sram_idle(void)
 165 {
 166         /* Variable to tell what needs to be saved and restored
 167          * in omap_sram_idle*/
 168         /* save_state = 0 => Nothing to save and restored */
 169         /* save_state = 1 => Only L1 and logic lost */
 170         /* save_state = 2 => Only L2 lost */
 171         /* save_state = 3 => L1, L2 and logic lost */
 172         int save_state = 0, mpu_next_state;
 173
 174         if (!_omap_sram_idle)
 175                 return;
 176
 177         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 178         switch (mpu_next_state) {
 179         case PWRDM_POWER_RET:
 180                 /* No need to save context */
 181                 save_state = 0;
 182                 break;
 183         default:
 184                 /* Invalid state */
 185                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 186                 return;
 187         }
 188         pwrdm_pre_transition();
 189
 190         omap2_gpio_prepare_for_retention();
 191         omap_uart_prepare_idle(0);
 192         omap_uart_prepare_idle(1);
 193         omap_uart_prepare_idle(2);
 194
 195         _omap_sram_idle(NULL, save_state);
 196         cpu_init();
 197
 198         omap_uart_resume_idle(2);
 199         omap_uart_resume_idle(1);
 200         omap_uart_resume_idle(0);
 201         omap2_gpio_resume_after_retention();
 202
 203         pwrdm_post_transition();
 204
 205 }
 206
 207 /*
 208  * Check if functional clocks are enabled before entering
 209  * sleep. This function could be behind CONFIG_PM_DEBUG
 210  * when all drivers are configuring their sysconfig registers
 211  * properly and using their clocks properly.
 212  */
 213 static int omap3_fclks_active(void)
 214 {
 215         u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
 216                 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
 217
 218         fck_core1 = cm_read_mod_reg(CORE_MOD,
 219                                     CM_FCLKEN1);
 220         if (omap_rev() > OMAP3430_REV_ES1_0) {
 221                 fck_core3 = cm_read_mod_reg(CORE_MOD,
 222                                             OMAP3430ES2_CM_FCLKEN3);
 223                 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 224                                           CM_FCLKEN);
 225                 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 226                                               CM_FCLKEN);
 227         } else
 228                 fck_sgx = cm_read_mod_reg(GFX_MOD,
 229                                           OMAP3430ES2_CM_FCLKEN3);
 230         fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
 231                                   CM_FCLKEN);
 232         fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
 233                                   CM_FCLKEN);
 234         fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
 235                                   CM_FCLKEN);
 236
 237         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
 238         fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
 239         fck_per &= ~OMAP3430_EN_UART3;
 240
 241         if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
 242             fck_cam | fck_per | fck_usbhost)
 243                 return 1;
 244         return 0;
 245 }
 246
 247 static int omap3_can_sleep(void)
 248 {
 249         if (!omap_uart_can_sleep())
 250                 return 0;
 251         if (omap3_fclks_active())
 252                 return 0;
 253         return 1;
 254 }
 255
 256 /* This sets pwrdm state (other than mpu & core. Currently only ON &
 257  * RET are supported. Function is assuming that clkdm doesn't have
 258  * hw_sup mode enabled. */
 259 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 260 {
 261         u32 cur_state;
 262         int sleep_switch = 0;
 263         int ret = 0;
 264
 265         if (pwrdm == NULL || IS_ERR(pwrdm))
 266                 return -EINVAL;
 267
 268         while (!(pwrdm->pwrsts & (1 << state))) {
 269                 if (state == PWRDM_POWER_OFF)
 270                         return ret;
 271                 state--;
 272         }
 273
 274         cur_state = pwrdm_read_next_pwrst(pwrdm);
 275         if (cur_state == state)
 276                 return ret;
 277
 278         if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
 279                 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
 280                 sleep_switch = 1;
 281                 pwrdm_wait_transition(pwrdm);
 282         }
 283
 284         ret = pwrdm_set_next_pwrst(pwrdm, state);
 285         if (ret) {
 286                 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
 287                        pwrdm->name);
 288                 goto err;
 289         }
 290
 291         if (sleep_switch) {
 292                 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
 293                 pwrdm_wait_transition(pwrdm);
 294                 pwrdm_state_switch(pwrdm);
 295         }
 296
 297 err:
 298         return ret;
 299 }
 300
 301 static void omap3_pm_idle(void)
 302 {
 303         local_irq_disable();
 304         local_fiq_disable();
 305
 306         if (!omap3_can_sleep())
 307                 goto out;
 308
 309         if (omap_irq_pending())
 310                 goto out;
 311
 312         omap_sram_idle();
 313
 314 out:
 315         local_fiq_enable();
 316         local_irq_enable();
 317 }
 318
 319 #ifdef CONFIG_SUSPEND
 320 static suspend_state_t suspend_state;
 321
 322 static int omap3_pm_prepare(void)
 323 {
 324         disable_hlt();
 325         return 0;
 326 }
 327
 328 static int omap3_pm_suspend(void)
 329 {
 330         struct power_state *pwrst;
 331         int state, ret = 0;
 332
 333         /* Read current next_pwrsts */
 334         list_for_each_entry(pwrst, &pwrst_list, node)
 335                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 336         /* Set ones wanted by suspend */
 337         list_for_each_entry(pwrst, &pwrst_list, node) {
 338                 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 339                         goto restore;
 340                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 341                         goto restore;
 342         }
 343
 344         omap_uart_prepare_suspend();
 345         omap_sram_idle();
 346
 347 restore:
 348         /* Restore next_pwrsts */
 349         list_for_each_entry(pwrst, &pwrst_list, node) {
 350                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 351                 if (state > pwrst->next_state) {
 352                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 353                                "target state %d\n",
 354                                pwrst->pwrdm->name, pwrst->next_state);
 355                         ret = -1;
 356                 }
 357                 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 358         }
 359         if (ret)
 360                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 361         else
 362                 printk(KERN_INFO "Successfully put all powerdomains "
 363                        "to target state\n");
 364
 365         return ret;
 366 }
 367
 368 static int omap3_pm_enter(suspend_state_t unused)
 369 {
 370         int ret = 0;
 371
 372         switch (suspend_state) {
 373         case PM_SUSPEND_STANDBY:
 374         case PM_SUSPEND_MEM:
 375                 ret = omap3_pm_suspend();
 376                 break;
 377         default:
 378                 ret = -EINVAL;
 379         }
 380
 381         return ret;
 382 }
 383
 384 static void omap3_pm_finish(void)
 385 {
 386         enable_hlt();
 387 }
 388
 389 /* Hooks to enable / disable UART interrupts during suspend */
 390 static int omap3_pm_begin(suspend_state_t state)
 391 {
 392         suspend_state = state;
 393         omap_uart_enable_irqs(0);
 394         return 0;
 395 }
 396
 397 static void omap3_pm_end(void)
 398 {
 399         suspend_state = PM_SUSPEND_ON;
 400         omap_uart_enable_irqs(1);
 401         return;
 402 }
 403
 404 static struct platform_suspend_ops omap_pm_ops = {
 405         .begin          = omap3_pm_begin,
 406         .end            = omap3_pm_end,
 407         .prepare        = omap3_pm_prepare,
 408         .enter          = omap3_pm_enter,
 409         .finish         = omap3_pm_finish,
 410         .valid          = suspend_valid_only_mem,
 411 };
 412 #endif /* CONFIG_SUSPEND */
 413
 414
 415 /**
 416  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 417  *                   retention
 418  *
 419  * In cases where IVA2 is activated by bootcode, it may prevent
 420  * full-chip retention or off-mode because it is not idle.  This
 421  * function forces the IVA2 into idle state so it can go
 422  * into retention/off and thus allow full-chip retention/off.
 423  *
 424  **/
 425 static void __init omap3_iva_idle(void)
 426 {
 427         /* ensure IVA2 clock is disabled */
 428         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 429
 430         /* if no clock activity, nothing else to do */
 431         if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 432               OMAP3430_CLKACTIVITY_IVA2_MASK))
 433                 return;
 434
 435         /* Reset IVA2 */
 436         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 437                           OMAP3430_RST2_IVA2 |
 438                           OMAP3430_RST3_IVA2,
 439                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 440
 441         /* Enable IVA2 clock */
 442         cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
 443                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 444
 445         /* Set IVA2 boot mode to 'idle' */
 446         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 447                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 448
 449         /* Un-reset IVA2 */
 450         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
 451
 452         /* Disable IVA2 clock */
 453         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 454
 455         /* Reset IVA2 */
 456         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 457                           OMAP3430_RST2_IVA2 |
 458                           OMAP3430_RST3_IVA2,
 459                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 460 }
 461
 462 static void __init omap3_d2d_idle(void)
 463 {
 464         u16 mask, padconf;
 465
 466         /* In a stand alone OMAP3430 where there is not a stacked
 467          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 468          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 469          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 470         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 471         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 472         padconf |= mask;
 473         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 474
 475         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 476         padconf |= mask;
 477         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 478
 479         /* reset modem */
 480         prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
 481                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
 482                           CORE_MOD, RM_RSTCTRL);
 483         prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
 484 }
 485
 486 static void __init prcm_setup_regs(void)
 487 {
 488         /* XXX Reset all wkdeps. This should be done when initializing
 489          * powerdomains */
 490         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 491         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 492         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 493         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 494         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 495         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 496         if (omap_rev() > OMAP3430_REV_ES1_0) {
 497                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 498                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 499         } else
 500                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 501
 502         /*
 503          * Enable interface clock autoidle for all modules.
 504          * Note that in the long run this should be done by clockfw
 505          */
 506         cm_write_mod_reg(
 507                 OMAP3430_AUTO_MODEM |
 508                 OMAP3430ES2_AUTO_MMC3 |
 509                 OMAP3430ES2_AUTO_ICR |
 510                 OMAP3430_AUTO_AES2 |
 511                 OMAP3430_AUTO_SHA12 |
 512                 OMAP3430_AUTO_DES2 |
 513                 OMAP3430_AUTO_MMC2 |
 514                 OMAP3430_AUTO_MMC1 |
 515                 OMAP3430_AUTO_MSPRO |
 516                 OMAP3430_AUTO_HDQ |
 517                 OMAP3430_AUTO_MCSPI4 |
 518                 OMAP3430_AUTO_MCSPI3 |
 519                 OMAP3430_AUTO_MCSPI2 |
 520                 OMAP3430_AUTO_MCSPI1 |
 521                 OMAP3430_AUTO_I2C3 |
 522                 OMAP3430_AUTO_I2C2 |
 523                 OMAP3430_AUTO_I2C1 |
 524                 OMAP3430_AUTO_UART2 |
 525                 OMAP3430_AUTO_UART1 |
 526                 OMAP3430_AUTO_GPT11 |
 527                 OMAP3430_AUTO_GPT10 |
 528                 OMAP3430_AUTO_MCBSP5 |
 529                 OMAP3430_AUTO_MCBSP1 |
 530                 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
 531                 OMAP3430_AUTO_MAILBOXES |
 532                 OMAP3430_AUTO_OMAPCTRL |
 533                 OMAP3430ES1_AUTO_FSHOSTUSB |
 534                 OMAP3430_AUTO_HSOTGUSB |
 535                 OMAP3430_AUTO_SAD2D |
 536                 OMAP3430_AUTO_SSI,
 537                 CORE_MOD, CM_AUTOIDLE1);
 538
 539         cm_write_mod_reg(
 540                 OMAP3430_AUTO_PKA |
 541                 OMAP3430_AUTO_AES1 |
 542                 OMAP3430_AUTO_RNG |
 543                 OMAP3430_AUTO_SHA11 |
 544                 OMAP3430_AUTO_DES1,
 545                 CORE_MOD, CM_AUTOIDLE2);
 546
 547         if (omap_rev() > OMAP3430_REV_ES1_0) {
 548                 cm_write_mod_reg(
 549                         OMAP3430_AUTO_MAD2D |
 550                         OMAP3430ES2_AUTO_USBTLL,
 551                         CORE_MOD, CM_AUTOIDLE3);
 552         }
 553
 554         cm_write_mod_reg(
 555                 OMAP3430_AUTO_WDT2 |
 556                 OMAP3430_AUTO_WDT1 |
 557                 OMAP3430_AUTO_GPIO1 |
 558                 OMAP3430_AUTO_32KSYNC |
 559                 OMAP3430_AUTO_GPT12 |
 560                 OMAP3430_AUTO_GPT1 ,
 561                 WKUP_MOD, CM_AUTOIDLE);
 562
 563         cm_write_mod_reg(
 564                 OMAP3430_AUTO_DSS,
 565                 OMAP3430_DSS_MOD,
 566                 CM_AUTOIDLE);
 567
 568         cm_write_mod_reg(
 569                 OMAP3430_AUTO_CAM,
 570                 OMAP3430_CAM_MOD,
 571                 CM_AUTOIDLE);
 572
 573         cm_write_mod_reg(
 574                 OMAP3430_AUTO_GPIO6 |
 575                 OMAP3430_AUTO_GPIO5 |
 576                 OMAP3430_AUTO_GPIO4 |
 577                 OMAP3430_AUTO_GPIO3 |
 578                 OMAP3430_AUTO_GPIO2 |
 579                 OMAP3430_AUTO_WDT3 |
 580                 OMAP3430_AUTO_UART3 |
 581                 OMAP3430_AUTO_GPT9 |
 582                 OMAP3430_AUTO_GPT8 |
 583                 OMAP3430_AUTO_GPT7 |
 584                 OMAP3430_AUTO_GPT6 |
 585                 OMAP3430_AUTO_GPT5 |
 586                 OMAP3430_AUTO_GPT4 |
 587                 OMAP3430_AUTO_GPT3 |
 588                 OMAP3430_AUTO_GPT2 |
 589                 OMAP3430_AUTO_MCBSP4 |
 590                 OMAP3430_AUTO_MCBSP3 |
 591                 OMAP3430_AUTO_MCBSP2,
 592                 OMAP3430_PER_MOD,
 593                 CM_AUTOIDLE);
 594
 595         if (omap_rev() > OMAP3430_REV_ES1_0) {
 596                 cm_write_mod_reg(
 597                         OMAP3430ES2_AUTO_USBHOST,
 598                         OMAP3430ES2_USBHOST_MOD,
 599                         CM_AUTOIDLE);
 600         }
 601
 602         /*
 603          * Set all plls to autoidle. This is needed until autoidle is
 604          * enabled by clockfw
 605          */
 606         cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 607                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 608         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 609                          MPU_MOD,
 610                          CM_AUTOIDLE2);
 611         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 612                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 613                          PLL_MOD,
 614                          CM_AUTOIDLE);
 615         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 616                          PLL_MOD,
 617                          CM_AUTOIDLE2);
 618
 619         /*
 620          * Enable control of expternal oscillator through
 621          * sys_clkreq. In the long run clock framework should
 622          * take care of this.
 623          */
 624         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 625                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 626                              OMAP3430_GR_MOD,
 627                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 628
 629         /* setup wakup source */
 630         prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
 631                           OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
 632                           WKUP_MOD, PM_WKEN);
 633         /* No need to write EN_IO, that is always enabled */
 634         prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
 635                           OMAP3430_EN_GPT12,
 636                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 637         /* For some reason IO doesn't generate wakeup event even if
 638          * it is selected to mpu wakeup goup */
 639         prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
 640                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 641
 642         /* Enable wakeups in PER */
 643         prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
 644                           OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
 645                           OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
 646                           OMAP3430_PER_MOD, PM_WKEN);
 647         /* and allow them to wake up MPU */
 648         prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
 649                           OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
 650                           OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
 651                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 652
 653         /* Don't attach IVA interrupts */
 654         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 655         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 656         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 657         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 658
 659         /* Clear any pending 'reset' flags */
 660         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 661         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 662         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 663         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 664         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 665         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 666         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 667
 668         /* Clear any pending PRCM interrupts */
 669         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 670
 671         /* Don't attach IVA interrupts */
 672         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 673         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 674         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 675         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 676
 677         /* Clear any pending 'reset' flags */
 678         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 679         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 680         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 681         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 682         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 683         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 684         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 685
 686         /* Clear any pending PRCM interrupts */
 687         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 688
 689         omap3_iva_idle();
 690         omap3_d2d_idle();
 691 }
 692
 693 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 694 {
 695         struct power_state *pwrst;
 696
 697         list_for_each_entry(pwrst, &pwrst_list, node) {
 698                 if (pwrst->pwrdm == pwrdm)
 699                         return pwrst->next_state;
 700         }
 701         return -EINVAL;
 702 }
 703
 704 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 705 {
 706         struct power_state *pwrst;
 707
 708         list_for_each_entry(pwrst, &pwrst_list, node) {
 709                 if (pwrst->pwrdm == pwrdm) {
 710                         pwrst->next_state = state;
 711                         return 0;
 712                 }
 713         }
 714         return -EINVAL;
 715 }
 716
 717 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 718 {
 719         struct power_state *pwrst;
 720
 721         if (!pwrdm->pwrsts)
 722                 return 0;
 723
 724         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 725         if (!pwrst)
 726                 return -ENOMEM;
 727         pwrst->pwrdm = pwrdm;
 728         pwrst->next_state = PWRDM_POWER_RET;
 729         list_add(&pwrst->node, &pwrst_list);
 730
 731         if (pwrdm_has_hdwr_sar(pwrdm))
 732                 pwrdm_enable_hdwr_sar(pwrdm);
 733
 734         return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 735 }
 736
 737 /*
 738  * Enable hw supervised mode for all clockdomains if it's
 739  * supported. Initiate sleep transition for other clockdomains, if
 740  * they are not used
 741  */
 742 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 743 {
 744         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 745                 omap2_clkdm_allow_idle(clkdm);
 746         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 747                  atomic_read(&clkdm->usecount) == 0)
 748                 omap2_clkdm_sleep(clkdm);
 749         return 0;
 750 }
 751
 752 static int __init omap3_pm_init(void)
 753 {
 754         struct power_state *pwrst, *tmp;
 755         int ret;
 756
 757         if (!cpu_is_omap34xx())
 758                 return -ENODEV;
 759
 760         printk(KERN_ERR "Power Management for TI OMAP3.\n");
 761
 762         /* XXX prcm_setup_regs needs to be before enabling hw
 763          * supervised mode for powerdomains */
 764         prcm_setup_regs();
 765
 766         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 767                           (irq_handler_t)prcm_interrupt_handler,
 768                           IRQF_DISABLED, "prcm", NULL);
 769         if (ret) {
 770                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 771                        INT_34XX_PRCM_MPU_IRQ);
 772                 goto err1;
 773         }
 774
 775         ret = pwrdm_for_each(pwrdms_setup, NULL);
 776         if (ret) {
 777                 printk(KERN_ERR "Failed to setup powerdomains\n");
 778                 goto err2;
 779         }
 780
 781         (void) clkdm_for_each(clkdms_setup, NULL);
 782
 783         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 784         if (mpu_pwrdm == NULL) {
 785                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 786                 goto err2;
 787         }
 788
 789         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 790                                          omap34xx_cpu_suspend_sz);
 791
 792 #ifdef CONFIG_SUSPEND
 793         suspend_set_ops(&omap_pm_ops);
 794 #endif /* CONFIG_SUSPEND */
 795
 796         pm_idle = omap3_pm_idle;
 797
 798 err1:
 799         return ret;
 800 err2:
 801         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 802         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 803                 list_del(&pwrst->node);
 804                 kfree(pwrst);
 805         }
 806         return ret;
 807 }
 808
 809 late_initcall(omap3_pm_init);