drivers/net/davinci_emac.c

   1 /*
   2  * DaVinci Ethernet Medium Access Controller
   3  *
   4  * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
   5  *
   6  * Copyright (C) 2009 Texas Instruments.
   7  *
   8  * ---------------------------------------------------------------------------
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  * ---------------------------------------------------------------------------
  24  * History:
  25  * 0-5 A number of folks worked on this driver in bits and pieces but the major
  26  *     contribution came from Suraj Iyer and Anant Gole
  27  * 6.0 Anant Gole - rewrote the driver as per Linux conventions
  28  * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
  29  *     PHY layer usage
  30  */
  31
  32 #include <linux/module.h>
  33 #include <linux/kernel.h>
  34 #include <linux/sched.h>
  35 #include <linux/string.h>
  36 #include <linux/timer.h>
  37 #include <linux/errno.h>
  38 #include <linux/in.h>
  39 #include <linux/ioport.h>
  40 #include <linux/slab.h>
  41 #include <linux/mm.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/init.h>
  44 #include <linux/netdevice.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/skbuff.h>
  47 #include <linux/ethtool.h>
  48 #include <linux/highmem.h>
  49 #include <linux/proc_fs.h>
  50 #include <linux/ctype.h>
  51 #include <linux/version.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/dma-mapping.h>
  54 #include <linux/clk.h>
  55 #include <linux/platform_device.h>
  56 #include <linux/semaphore.h>
  57 #include <linux/phy.h>
  58 #include <linux/bitops.h>
  59 #include <linux/io.h>
  60 #include <linux/uaccess.h>
  61 #include <linux/davinci_emac.h>
  62
  63 #include <asm/irq.h>
  64 #include <asm/page.h>
  65
  66 static int debug_level;
  67 module_param(debug_level, int, 0);
  68 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
  69
  70 /* Netif debug messages possible */
  71 #define DAVINCI_EMAC_DEBUG      (NETIF_MSG_DRV | \
  72                                 NETIF_MSG_PROBE | \
  73                                 NETIF_MSG_LINK | \
  74                                 NETIF_MSG_TIMER | \
  75                                 NETIF_MSG_IFDOWN | \
  76                                 NETIF_MSG_IFUP | \
  77                                 NETIF_MSG_RX_ERR | \
  78                                 NETIF_MSG_TX_ERR | \
  79                                 NETIF_MSG_TX_QUEUED | \
  80                                 NETIF_MSG_INTR | \
  81                                 NETIF_MSG_TX_DONE | \
  82                                 NETIF_MSG_RX_STATUS | \
  83                                 NETIF_MSG_PKTDATA | \
  84                                 NETIF_MSG_HW | \
  85                                 NETIF_MSG_WOL)
  86
  87 /* version info */
  88 #define EMAC_MAJOR_VERSION      6
  89 #define EMAC_MINOR_VERSION      1
  90 #define EMAC_MODULE_VERSION     "6.1"
  91 MODULE_VERSION(EMAC_MODULE_VERSION);
  92 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
  93
  94 /* Configuration items */
  95 #define EMAC_DEF_PASS_CRC               (0) /* Do not pass CRC upto frames */
  96 #define EMAC_DEF_QOS_EN                 (0) /* EMAC proprietary QoS disabled */
  97 #define EMAC_DEF_NO_BUFF_CHAIN          (0) /* No buffer chain */
  98 #define EMAC_DEF_MACCTRL_FRAME_EN       (0) /* Discard Maccontrol frames */
  99 #define EMAC_DEF_SHORT_FRAME_EN         (0) /* Discard short frames */
 100 #define EMAC_DEF_ERROR_FRAME_EN         (0) /* Discard error frames */
 101 #define EMAC_DEF_PROM_EN                (0) /* Promiscous disabled */
 102 #define EMAC_DEF_PROM_CH                (0) /* Promiscous channel is 0 */
 103 #define EMAC_DEF_BCAST_EN               (1) /* Broadcast enabled */
 104 #define EMAC_DEF_BCAST_CH               (0) /* Broadcast channel is 0 */
 105 #define EMAC_DEF_MCAST_EN               (1) /* Multicast enabled */
 106 #define EMAC_DEF_MCAST_CH               (0) /* Multicast channel is 0 */
 107
 108 #define EMAC_DEF_TXPRIO_FIXED           (1) /* TX Priority is fixed */
 109 #define EMAC_DEF_TXPACING_EN            (0) /* TX pacing NOT supported*/
 110
 111 #define EMAC_DEF_BUFFER_OFFSET          (0) /* Buffer offset to DMA (future) */
 112 #define EMAC_DEF_MIN_ETHPKTSIZE         (60) /* Minimum ethernet pkt size */
 113 #define EMAC_DEF_MAX_FRAME_SIZE         (1500 + 14 + 4 + 4)
 114 #define EMAC_DEF_TX_CH                  (0) /* Default 0th channel */
 115 #define EMAC_DEF_RX_CH                  (0) /* Default 0th channel */
 116 #define EMAC_DEF_MDIO_TICK_MS           (10) /* typically 1 tick=1 ms) */
 117 #define EMAC_DEF_MAX_TX_CH              (1) /* Max TX channels configured */
 118 #define EMAC_DEF_MAX_RX_CH              (1) /* Max RX channels configured */
 119 #define EMAC_POLL_WEIGHT                (64) /* Default NAPI poll weight */
 120
 121 /* Buffer descriptor parameters */
 122 #define EMAC_DEF_TX_MAX_SERVICE         (32) /* TX max service BD's */
 123 #define EMAC_DEF_RX_MAX_SERVICE         (64) /* should = netdev->weight */
 124
 125 /* EMAC register related defines */
 126 #define EMAC_ALL_MULTI_REG_VALUE        (0xFFFFFFFF)
 127 #define EMAC_NUM_MULTICAST_BITS         (64)
 128 #define EMAC_TEARDOWN_VALUE             (0xFFFFFFFC)
 129 #define EMAC_TX_CONTROL_TX_ENABLE_VAL   (0x1)
 130 #define EMAC_RX_CONTROL_RX_ENABLE_VAL   (0x1)
 131 #define EMAC_MAC_HOST_ERR_INTMASK_VAL   (0x2)
 132 #define EMAC_RX_UNICAST_CLEAR_ALL       (0xFF)
 133 #define EMAC_INT_MASK_CLEAR             (0xFF)
 134
 135 /* RX MBP register bit positions */
 136 #define EMAC_RXMBP_PASSCRC_MASK         BIT(30)
 137 #define EMAC_RXMBP_QOSEN_MASK           BIT(29)
 138 #define EMAC_RXMBP_NOCHAIN_MASK         BIT(28)
 139 #define EMAC_RXMBP_CMFEN_MASK           BIT(24)
 140 #define EMAC_RXMBP_CSFEN_MASK           BIT(23)
 141 #define EMAC_RXMBP_CEFEN_MASK           BIT(22)
 142 #define EMAC_RXMBP_CAFEN_MASK           BIT(21)
 143 #define EMAC_RXMBP_PROMCH_SHIFT         (16)
 144 #define EMAC_RXMBP_PROMCH_MASK          (0x7 << 16)
 145 #define EMAC_RXMBP_BROADEN_MASK         BIT(13)
 146 #define EMAC_RXMBP_BROADCH_SHIFT        (8)
 147 #define EMAC_RXMBP_BROADCH_MASK         (0x7 << 8)
 148 #define EMAC_RXMBP_MULTIEN_MASK         BIT(5)
 149 #define EMAC_RXMBP_MULTICH_SHIFT        (0)
 150 #define EMAC_RXMBP_MULTICH_MASK         (0x7)
 151 #define EMAC_RXMBP_CHMASK               (0x7)
 152
 153 /* EMAC register definitions/bit maps used */
 154 # define EMAC_MBP_RXPROMISC             (0x00200000)
 155 # define EMAC_MBP_PROMISCCH(ch)         (((ch) & 0x7) << 16)
 156 # define EMAC_MBP_RXBCAST               (0x00002000)
 157 # define EMAC_MBP_BCASTCHAN(ch)         (((ch) & 0x7) << 8)
 158 # define EMAC_MBP_RXMCAST               (0x00000020)
 159 # define EMAC_MBP_MCASTCHAN(ch)         ((ch) & 0x7)
 160
 161 /* EMAC mac_control register */
 162 #define EMAC_MACCONTROL_TXPTYPE         BIT(9)
 163 #define EMAC_MACCONTROL_TXPACEEN        BIT(6)
 164 #define EMAC_MACCONTROL_GMIIEN          BIT(5)
 165 #define EMAC_MACCONTROL_GIGABITEN       BIT(7)
 166 #define EMAC_MACCONTROL_FULLDUPLEXEN    BIT(0)
 167 #define EMAC_MACCONTROL_RMIISPEED_MASK  BIT(15)
 168
 169 /* GIGABIT MODE related bits */
 170 #define EMAC_DM646X_MACCONTORL_GIG      BIT(7)
 171 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
 172
 173 /* EMAC mac_status register */
 174 #define EMAC_MACSTATUS_TXERRCODE_MASK   (0xF00000)
 175 #define EMAC_MACSTATUS_TXERRCODE_SHIFT  (20)
 176 #define EMAC_MACSTATUS_TXERRCH_MASK     (0x7)
 177 #define EMAC_MACSTATUS_TXERRCH_SHIFT    (16)
 178 #define EMAC_MACSTATUS_RXERRCODE_MASK   (0xF000)
 179 #define EMAC_MACSTATUS_RXERRCODE_SHIFT  (12)
 180 #define EMAC_MACSTATUS_RXERRCH_MASK     (0x7)
 181 #define EMAC_MACSTATUS_RXERRCH_SHIFT    (8)
 182
 183 /* EMAC RX register masks */
 184 #define EMAC_RX_MAX_LEN_MASK            (0xFFFF)
 185 #define EMAC_RX_BUFFER_OFFSET_MASK      (0xFFFF)
 186
 187 /* MAC_IN_VECTOR (0x180) register bit fields */
 188 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT      BIT(17)
 189 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT  BIT(16)
 190 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC    BIT(8)
 191 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC    BIT(0)
 192
 193 /** NOTE:: For DM646x the IN_VECTOR has changed */
 194 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC    BIT(EMAC_DEF_RX_CH)
 195 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC    BIT(16 + EMAC_DEF_TX_CH)
 196 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT      BIT(26)
 197 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT  BIT(27)
 198
 199 /* CPPI bit positions */
 200 #define EMAC_CPPI_SOP_BIT               BIT(31)
 201 #define EMAC_CPPI_EOP_BIT               BIT(30)
 202 #define EMAC_CPPI_OWNERSHIP_BIT         BIT(29)
 203 #define EMAC_CPPI_EOQ_BIT               BIT(28)
 204 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
 205 #define EMAC_CPPI_PASS_CRC_BIT          BIT(26)
 206 #define EMAC_RX_BD_BUF_SIZE             (0xFFFF)
 207 #define EMAC_BD_LENGTH_FOR_CACHE        (16) /* only CPPI bytes */
 208 #define EMAC_RX_BD_PKT_LENGTH_MASK      (0xFFFF)
 209
 210 /* Max hardware defines */
 211 #define EMAC_MAX_TXRX_CHANNELS           (8)  /* Max hardware channels */
 212 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
 213
 214 /* EMAC Peripheral Device Register Memory Layout structure */
 215 #define EMAC_TXIDVER            0x0
 216 #define EMAC_TXCONTROL          0x4
 217 #define EMAC_TXTEARDOWN         0x8
 218 #define EMAC_RXIDVER            0x10
 219 #define EMAC_RXCONTROL          0x14
 220 #define EMAC_RXTEARDOWN         0x18
 221 #define EMAC_TXINTSTATRAW       0x80
 222 #define EMAC_TXINTSTATMASKED    0x84
 223 #define EMAC_TXINTMASKSET       0x88
 224 #define EMAC_TXINTMASKCLEAR     0x8C
 225 #define EMAC_MACINVECTOR        0x90
 226
 227 #define EMAC_DM646X_MACEOIVECTOR        0x94
 228
 229 #define EMAC_RXINTSTATRAW       0xA0
 230 #define EMAC_RXINTSTATMASKED    0xA4
 231 #define EMAC_RXINTMASKSET       0xA8
 232 #define EMAC_RXINTMASKCLEAR     0xAC
 233 #define EMAC_MACINTSTATRAW      0xB0
 234 #define EMAC_MACINTSTATMASKED   0xB4
 235 #define EMAC_MACINTMASKSET      0xB8
 236 #define EMAC_MACINTMASKCLEAR    0xBC
 237
 238 #define EMAC_RXMBPENABLE        0x100
 239 #define EMAC_RXUNICASTSET       0x104
 240 #define EMAC_RXUNICASTCLEAR     0x108
 241 #define EMAC_RXMAXLEN           0x10C
 242 #define EMAC_RXBUFFEROFFSET     0x110
 243 #define EMAC_RXFILTERLOWTHRESH  0x114
 244
 245 #define EMAC_MACCONTROL         0x160
 246 #define EMAC_MACSTATUS          0x164
 247 #define EMAC_EMCONTROL          0x168
 248 #define EMAC_FIFOCONTROL        0x16C
 249 #define EMAC_MACCONFIG          0x170
 250 #define EMAC_SOFTRESET          0x174
 251 #define EMAC_MACSRCADDRLO       0x1D0
 252 #define EMAC_MACSRCADDRHI       0x1D4
 253 #define EMAC_MACHASH1           0x1D8
 254 #define EMAC_MACHASH2           0x1DC
 255 #define EMAC_MACADDRLO          0x500
 256 #define EMAC_MACADDRHI          0x504
 257 #define EMAC_MACINDEX           0x508
 258
 259 /* EMAC HDP and Completion registors */
 260 #define EMAC_TXHDP(ch)          (0x600 + (ch * 4))
 261 #define EMAC_RXHDP(ch)          (0x620 + (ch * 4))
 262 #define EMAC_TXCP(ch)           (0x640 + (ch * 4))
 263 #define EMAC_RXCP(ch)           (0x660 + (ch * 4))
 264
 265 /* EMAC statistics registers */
 266 #define EMAC_RXGOODFRAMES       0x200
 267 #define EMAC_RXBCASTFRAMES      0x204
 268 #define EMAC_RXMCASTFRAMES      0x208
 269 #define EMAC_RXPAUSEFRAMES      0x20C
 270 #define EMAC_RXCRCERRORS        0x210
 271 #define EMAC_RXALIGNCODEERRORS  0x214
 272 #define EMAC_RXOVERSIZED        0x218
 273 #define EMAC_RXJABBER           0x21C
 274 #define EMAC_RXUNDERSIZED       0x220
 275 #define EMAC_RXFRAGMENTS        0x224
 276 #define EMAC_RXFILTERED         0x228
 277 #define EMAC_RXQOSFILTERED      0x22C
 278 #define EMAC_RXOCTETS           0x230
 279 #define EMAC_TXGOODFRAMES       0x234
 280 #define EMAC_TXBCASTFRAMES      0x238
 281 #define EMAC_TXMCASTFRAMES      0x23C
 282 #define EMAC_TXPAUSEFRAMES      0x240
 283 #define EMAC_TXDEFERRED         0x244
 284 #define EMAC_TXCOLLISION        0x248
 285 #define EMAC_TXSINGLECOLL       0x24C
 286 #define EMAC_TXMULTICOLL        0x250
 287 #define EMAC_TXEXCESSIVECOLL    0x254
 288 #define EMAC_TXLATECOLL         0x258
 289 #define EMAC_TXUNDERRUN         0x25C
 290 #define EMAC_TXCARRIERSENSE     0x260
 291 #define EMAC_TXOCTETS           0x264
 292 #define EMAC_NETOCTETS          0x280
 293 #define EMAC_RXSOFOVERRUNS      0x284
 294 #define EMAC_RXMOFOVERRUNS      0x288
 295 #define EMAC_RXDMAOVERRUNS      0x28C
 296
 297 /* EMAC DM644x control registers */
 298 #define EMAC_CTRL_EWCTL         (0x4)
 299 #define EMAC_CTRL_EWINTTCNT     (0x8)
 300
 301 /* EMAC DM644x control module masks */
 302 #define EMAC_DM644X_EWINTCNT_MASK       0x1FFFF
 303 #define EMAC_DM644X_INTMIN_INTVL        0x1
 304 #define EMAC_DM644X_INTMAX_INTVL        (EMAC_DM644X_EWINTCNT_MASK)
 305
 306 /* EMAC MDIO related */
 307 /* Mask & Control defines */
 308 #define MDIO_CONTROL_CLKDIV     (0xFF)
 309 #define MDIO_CONTROL_ENABLE     BIT(30)
 310 #define MDIO_USERACCESS_GO      BIT(31)
 311 #define MDIO_USERACCESS_WRITE   BIT(30)
 312 #define MDIO_USERACCESS_READ    (0)
 313 #define MDIO_USERACCESS_REGADR  (0x1F << 21)
 314 #define MDIO_USERACCESS_PHYADR  (0x1F << 16)
 315 #define MDIO_USERACCESS_DATA    (0xFFFF)
 316 #define MDIO_USERPHYSEL_LINKSEL BIT(7)
 317 #define MDIO_VER_MODID          (0xFFFF << 16)
 318 #define MDIO_VER_REVMAJ         (0xFF   << 8)
 319 #define MDIO_VER_REVMIN         (0xFF)
 320
 321 #define MDIO_USERACCESS(inst)   (0x80 + (inst * 8))
 322 #define MDIO_USERPHYSEL(inst)   (0x84 + (inst * 8))
 323 #define MDIO_CONTROL            (0x04)
 324
 325 /* EMAC DM646X control module registers */
 326 #define EMAC_DM646X_CMINTCTRL   0x0C
 327 #define EMAC_DM646X_CMRXINTEN   0x14
 328 #define EMAC_DM646X_CMTXINTEN   0x18
 329 #define EMAC_DM646X_CMRXINTMAX  0x70
 330 #define EMAC_DM646X_CMTXINTMAX  0x74
 331
 332 /* EMAC DM646X control module masks */
 333 #define EMAC_DM646X_INTPACEEN           (0x3 << 16)
 334 #define EMAC_DM646X_INTPRESCALE_MASK    (0x7FF << 0)
 335 #define EMAC_DM646X_CMINTMAX_CNT        63
 336 #define EMAC_DM646X_CMINTMIN_CNT        2
 337 #define EMAC_DM646X_CMINTMAX_INTVL      (1000 / EMAC_DM646X_CMINTMIN_CNT)
 338 #define EMAC_DM646X_CMINTMIN_INTVL      ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
 339
 340
 341 /* EMAC EOI codes for C0 */
 342 #define EMAC_DM646X_MAC_EOI_C0_RXEN     (0x01)
 343 #define EMAC_DM646X_MAC_EOI_C0_TXEN     (0x02)
 344
 345 /* EMAC Stats Clear Mask */
 346 #define EMAC_STATS_CLR_MASK    (0xFFFFFFFF)
 347
 348 /** net_buf_obj: EMAC network bufferdata structure
 349  *
 350  * EMAC network buffer data structure
 351  */
 352 struct emac_netbufobj {
 353         void *buf_token;
 354         char *data_ptr;
 355         int length;
 356 };
 357
 358 /** net_pkt_obj: EMAC network packet data structure
 359  *
 360  * EMAC network packet data structure - supports buffer list (for future)
 361  */
 362 struct emac_netpktobj {
 363         void *pkt_token; /* data token may hold tx/rx chan id */
 364         struct emac_netbufobj *buf_list; /* array of network buffer objects */
 365         int num_bufs;
 366         int pkt_length;
 367 };
 368
 369 /** emac_tx_bd: EMAC TX Buffer descriptor data structure
 370  *
 371  * EMAC TX Buffer descriptor data structure
 372  */
 373 struct emac_tx_bd {
 374         int h_next;
 375         int buff_ptr;
 376         int off_b_len;
 377         int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
 378         struct emac_tx_bd __iomem *next;
 379         void *buf_token;
 380 };
 381
 382 /** emac_txch: EMAC TX Channel data structure
 383  *
 384  * EMAC TX Channel data structure
 385  */
 386 struct emac_txch {
 387         /* Config related */
 388         u32 num_bd;
 389         u32 service_max;
 390
 391         /* CPPI specific */
 392         u32 alloc_size;
 393         void __iomem *bd_mem;
 394         struct emac_tx_bd __iomem *bd_pool_head;
 395         struct emac_tx_bd __iomem *active_queue_head;
 396         struct emac_tx_bd __iomem *active_queue_tail;
 397         struct emac_tx_bd __iomem *last_hw_bdprocessed;
 398         u32 queue_active;
 399         u32 teardown_pending;
 400         u32 *tx_complete;
 401
 402         /** statistics */
 403         u32 proc_count;     /* TX: # of times emac_tx_bdproc is called */
 404         u32 mis_queued_packets;
 405         u32 queue_reinit;
 406         u32 end_of_queue_add;
 407         u32 out_of_tx_bd;
 408         u32 no_active_pkts; /* IRQ when there were no packets to process */
 409         u32 active_queue_count;
 410 };
 411
 412 /** emac_rx_bd: EMAC RX Buffer descriptor data structure
 413  *
 414  * EMAC RX Buffer descriptor data structure
 415  */
 416 struct emac_rx_bd {
 417         int h_next;
 418         int buff_ptr;
 419         int off_b_len;
 420         int mode;
 421         struct emac_rx_bd __iomem *next;
 422         void *data_ptr;
 423         void *buf_token;
 424 };
 425
 426 /** emac_rxch: EMAC RX Channel data structure
 427  *
 428  * EMAC RX Channel data structure
 429  */
 430 struct emac_rxch {
 431         /* configuration info */
 432         u32 num_bd;
 433         u32 service_max;
 434         u32 buf_size;
 435         char mac_addr[6];
 436
 437         /** CPPI specific */
 438         u32 alloc_size;
 439         void __iomem *bd_mem;
 440         struct emac_rx_bd __iomem *bd_pool_head;
 441         struct emac_rx_bd __iomem *active_queue_head;
 442         struct emac_rx_bd __iomem *active_queue_tail;
 443         u32 queue_active;
 444         u32 teardown_pending;
 445
 446         /* packet and buffer objects */
 447         struct emac_netpktobj pkt_queue;
 448         struct emac_netbufobj buf_queue;
 449
 450         /** statistics */
 451         u32 proc_count; /* number of times emac_rx_bdproc is called */
 452         u32 processed_bd;
 453         u32 recycled_bd;
 454         u32 out_of_rx_bd;
 455         u32 out_of_rx_buffers;
 456         u32 queue_reinit;
 457         u32 end_of_queue_add;
 458         u32 end_of_queue;
 459         u32 mis_queued_packets;
 460 };
 461
 462 /* emac_priv: EMAC private data structure
 463  *
 464  * EMAC adapter private data structure
 465  */
 466 struct emac_priv {
 467         u32 msg_enable;
 468         struct net_device *ndev;
 469         struct platform_device *pdev;
 470         struct napi_struct napi;
 471         char mac_addr[6];
 472         spinlock_t tx_lock;
 473         spinlock_t rx_lock;
 474         void __iomem *remap_addr;
 475         u32 emac_base_phys;
 476         void __iomem *emac_base;
 477         void __iomem *ctrl_base;
 478         void __iomem *emac_ctrl_ram;
 479         u32 ctrl_ram_size;
 480         u32 hw_ram_addr;
 481         struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
 482         struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
 483         u32 link; /* 1=link on, 0=link off */
 484         u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
 485         u32 duplex; /* Link duplex: 0=Half, 1=Full */
 486         u32 rx_buf_size;
 487         u32 isr_count;
 488         u32 coal_intvl;
 489         u32 bus_freq_mhz;
 490         u8 rmii_en;
 491         u8 version;
 492         u32 mac_hash1;
 493         u32 mac_hash2;
 494         u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
 495         u32 rx_addr_type;
 496         /* periodic timer required for MDIO polling */
 497         struct timer_list periodic_timer;
 498         u32 periodic_ticks;
 499         u32 timer_active;
 500         u32 phy_mask;
 501         /* mii_bus,phy members */
 502         struct mii_bus *mii_bus;
 503         struct phy_device *phydev;
 504         spinlock_t lock;
 505         /*platform specific members*/
 506         void (*int_enable) (void);
 507         void (*int_disable) (void);
 508 };
 509
 510 /* clock frequency for EMAC */
 511 static struct clk *emac_clk;
 512 static unsigned long emac_bus_frequency;
 513 static unsigned long mdio_max_freq;
 514
 515 #define emac_virt_to_phys(addr, priv) \
 516         (((u32 __force)(addr) - (u32 __force)(priv->emac_ctrl_ram)) \
 517         + priv->hw_ram_addr)
 518
 519 /* Cache macros - Packet buffers would be from skb pool which is cached */
 520 #define EMAC_VIRT_NOCACHE(addr) (addr)
 521
 522 /* DM644x does not have BD's in cached memory - so no cache functions */
 523 #define BD_CACHE_INVALIDATE(addr, size)
 524 #define BD_CACHE_WRITEBACK(addr, size)
 525 #define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
 526
 527 /* EMAC TX Host Error description strings */
 528 static char *emac_txhost_errcodes[16] = {
 529         "No error", "SOP error", "Ownership bit not set in SOP buffer",
 530         "Zero Next Buffer Descriptor Pointer Without EOP",
 531         "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
 532         "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
 533         "Reserved", "Reserved", "Reserved", "Reserved"
 534 };
 535
 536 /* EMAC RX Host Error description strings */
 537 static char *emac_rxhost_errcodes[16] = {
 538         "No error", "Reserved", "Ownership bit not set in input buffer",
 539         "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
 540         "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
 541         "Reserved", "Reserved", "Reserved", "Reserved"
 542 };
 543
 544 /* Helper macros */
 545 #define emac_read(reg)            ioread32(priv->emac_base + (reg))
 546 #define emac_write(reg, val)      iowrite32(val, priv->emac_base + (reg))
 547
 548 #define emac_ctrl_read(reg)       ioread32((priv->ctrl_base + (reg)))
 549 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
 550
 551 #define emac_mdio_read(reg)       ioread32(bus->priv + (reg))
 552 #define emac_mdio_write(reg, val) iowrite32(val, (bus->priv + (reg)))
 553
 554 /**
 555  * emac_dump_regs: Dump important EMAC registers to debug terminal
 556  * @priv: The DaVinci EMAC private adapter structure
 557  *
 558  * Executes ethtool set cmd & sets phy mode
 559  *
 560  */
 561 static void emac_dump_regs(struct emac_priv *priv)
 562 {
 563         struct device *emac_dev = &priv->ndev->dev;
 564
 565         /* Print important registers in EMAC */
 566         dev_info(emac_dev, "EMAC Basic registers\n");
 567         if (priv->version == EMAC_VERSION_1) {
 568                 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
 569                         emac_ctrl_read(EMAC_CTRL_EWCTL),
 570                         emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
 571         }
 572         dev_info(emac_dev, "EMAC: TXID: %08X %s, RXID: %08X %s\n",
 573                 emac_read(EMAC_TXIDVER),
 574                 ((emac_read(EMAC_TXCONTROL)) ? "enabled" : "disabled"),
 575                 emac_read(EMAC_RXIDVER),
 576                 ((emac_read(EMAC_RXCONTROL)) ? "enabled" : "disabled"));
 577         dev_info(emac_dev, "EMAC: TXIntRaw:%08X, TxIntMasked: %08X, "\
 578                 "TxIntMasSet: %08X\n", emac_read(EMAC_TXINTSTATRAW),
 579                 emac_read(EMAC_TXINTSTATMASKED), emac_read(EMAC_TXINTMASKSET));
 580         dev_info(emac_dev, "EMAC: RXIntRaw:%08X, RxIntMasked: %08X, "\
 581                 "RxIntMasSet: %08X\n", emac_read(EMAC_RXINTSTATRAW),
 582                 emac_read(EMAC_RXINTSTATMASKED), emac_read(EMAC_RXINTMASKSET));
 583         dev_info(emac_dev, "EMAC: MacIntRaw:%08X, MacIntMasked: %08X, "\
 584                 "MacInVector=%08X\n", emac_read(EMAC_MACINTSTATRAW),
 585                 emac_read(EMAC_MACINTSTATMASKED), emac_read(EMAC_MACINVECTOR));
 586         dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
 587                 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
 588         dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
 589                 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
 590                 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
 591         dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
 592                 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
 593                 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
 594         dev_info(emac_dev, "EMAC: TXHDP[0]:%08X, RXHDP[0]: %08X\n",
 595                 emac_read(EMAC_TXHDP(0)), emac_read(EMAC_RXHDP(0)));
 596         dev_info(emac_dev, "EMAC Statistics\n");
 597         dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
 598                 emac_read(EMAC_RXGOODFRAMES));
 599         dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
 600                 emac_read(EMAC_RXBCASTFRAMES));
 601         dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
 602                 emac_read(EMAC_RXMCASTFRAMES));
 603         dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
 604                 emac_read(EMAC_RXPAUSEFRAMES));
 605         dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
 606                 emac_read(EMAC_RXCRCERRORS));
 607         dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
 608                 emac_read(EMAC_RXALIGNCODEERRORS));
 609         dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
 610                 emac_read(EMAC_RXOVERSIZED));
 611         dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
 612                 emac_read(EMAC_RXJABBER));
 613         dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
 614                 emac_read(EMAC_RXUNDERSIZED));
 615         dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
 616                 emac_read(EMAC_RXFRAGMENTS));
 617         dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
 618                 emac_read(EMAC_RXFILTERED));
 619         dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
 620                 emac_read(EMAC_RXQOSFILTERED));
 621         dev_info(emac_dev, "EMAC: rx_octets:%d\n",
 622                 emac_read(EMAC_RXOCTETS));
 623         dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
 624                 emac_read(EMAC_TXGOODFRAMES));
 625         dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
 626                 emac_read(EMAC_TXBCASTFRAMES));
 627         dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
 628                 emac_read(EMAC_TXMCASTFRAMES));
 629         dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
 630                 emac_read(EMAC_TXPAUSEFRAMES));
 631         dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
 632                 emac_read(EMAC_TXDEFERRED));
 633         dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
 634                 emac_read(EMAC_TXCOLLISION));
 635         dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
 636                 emac_read(EMAC_TXSINGLECOLL));
 637         dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
 638                 emac_read(EMAC_TXMULTICOLL));
 639         dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
 640                 emac_read(EMAC_TXEXCESSIVECOLL));
 641         dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
 642                 emac_read(EMAC_TXLATECOLL));
 643         dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
 644                 emac_read(EMAC_TXUNDERRUN));
 645         dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
 646                 emac_read(EMAC_TXCARRIERSENSE));
 647         dev_info(emac_dev, "EMAC: tx_octets:%d\n",
 648                 emac_read(EMAC_TXOCTETS));
 649         dev_info(emac_dev, "EMAC: net_octets:%d\n",
 650                 emac_read(EMAC_NETOCTETS));
 651         dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
 652                 emac_read(EMAC_RXSOFOVERRUNS));
 653         dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
 654                 emac_read(EMAC_RXMOFOVERRUNS));
 655         dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
 656                 emac_read(EMAC_RXDMAOVERRUNS));
 657 }
 658
 659 /*************************************************************************
 660  *  EMAC MDIO/Phy Functionality
 661  *************************************************************************/
 662 /**
 663  * emac_get_drvinfo: Get EMAC driver information
 664  * @ndev: The DaVinci EMAC network adapter
 665  * @info: ethtool info structure containing name and version
 666  *
 667  * Returns EMAC driver information (name and version)
 668  *
 669  */
 670 static void emac_get_drvinfo(struct net_device *ndev,
 671                              struct ethtool_drvinfo *info)
 672 {
 673         strcpy(info->driver, emac_version_string);
 674         strcpy(info->version, EMAC_MODULE_VERSION);
 675 }
 676
 677 /**
 678  * emac_get_settings: Get EMAC settings
 679  * @ndev: The DaVinci EMAC network adapter
 680  * @ecmd: ethtool command
 681  *
 682  * Executes ethool get command
 683  *
 684  */
 685 static int emac_get_settings(struct net_device *ndev,
 686                              struct ethtool_cmd *ecmd)
 687 {
 688         struct emac_priv *priv = netdev_priv(ndev);
 689         if (priv->phy_mask)
 690                 return phy_ethtool_gset(priv->phydev, ecmd);
 691         else
 692                 return -EOPNOTSUPP;
 693
 694 }
 695
 696 /**
 697  * emac_set_settings: Set EMAC settings
 698  * @ndev: The DaVinci EMAC network adapter
 699  * @ecmd: ethtool command
 700  *
 701  * Executes ethool set command
 702  *
 703  */
 704 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
 705 {
 706         struct emac_priv *priv = netdev_priv(ndev);
 707         if (priv->phy_mask)
 708                 return phy_ethtool_sset(priv->phydev, ecmd);
 709         else
 710                 return -EOPNOTSUPP;
 711
 712 }
 713
 714 /**
 715  * emac_get_coalesce : Get interrupt coalesce settings for this device
 716  * @ndev : The DaVinci EMAC network adapter
 717  * @coal : ethtool coalesce settings structure
 718  *
 719  * Fetch the current interrupt coalesce settings
 720  *
 721  */
 722 static int emac_get_coalesce(struct net_device *ndev,
 723                                 struct ethtool_coalesce *coal)
 724 {
 725         struct emac_priv *priv = netdev_priv(ndev);
 726
 727         coal->rx_coalesce_usecs = priv->coal_intvl;
 728         return 0;
 729
 730 }
 731
 732 /**
 733  * emac_set_coalesce : Set interrupt coalesce settings for this device
 734  * @ndev : The DaVinci EMAC network adapter
 735  * @coal : ethtool coalesce settings structure
 736  *
 737  * Set interrupt coalesce parameters
 738  *
 739  */
 740 static int emac_set_coalesce(struct net_device *ndev,
 741                                 struct ethtool_coalesce *coal)
 742 {
 743         struct emac_priv *priv = netdev_priv(ndev);
 744         u32 int_ctrl, num_interrupts = 0;
 745         u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
 746
 747         if (!coal->rx_coalesce_usecs)
 748                 return -EINVAL;
 749
 750         coal_intvl = coal->rx_coalesce_usecs;
 751
 752         switch (priv->version) {
 753         case EMAC_VERSION_2:
 754                 int_ctrl =  emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
 755                 prescale = priv->bus_freq_mhz * 4;
 756
 757                 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
 758                         coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
 759
 760                 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
 761                         /*
 762                          * Interrupt pacer works with 4us Pulse, we can
 763                          * throttle further by dilating the 4us pulse.
 764                          */
 765                         addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
 766
 767                         if (addnl_dvdr > 1) {
 768                                 prescale *= addnl_dvdr;
 769                                 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
 770                                                         * addnl_dvdr))
 771                                         coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
 772                                                         * addnl_dvdr);
 773                         } else {
 774                                 addnl_dvdr = 1;
 775                                 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
 776                         }
 777                 }
 778
 779                 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 780
 781                 int_ctrl |= EMAC_DM646X_INTPACEEN;
 782                 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
 783                 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
 784                 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
 785
 786                 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
 787                 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
 788
 789                 break;
 790         default:
 791                 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
 792                 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
 793                 prescale = coal_intvl * priv->bus_freq_mhz;
 794                 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
 795                         prescale = EMAC_DM644X_EWINTCNT_MASK;
 796                         coal_intvl = prescale / priv->bus_freq_mhz;
 797                 }
 798                 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
 799
 800                 break;
 801         }
 802
 803         printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
 804         priv->coal_intvl = coal_intvl;
 805
 806         return 0;
 807
 808 }
 809
 810
 811 /**
 812  * ethtool_ops: DaVinci EMAC Ethtool structure
 813  *
 814  * Ethtool support for EMAC adapter
 815  *
 816  */
 817 static const struct ethtool_ops ethtool_ops = {
 818         .get_drvinfo = emac_get_drvinfo,
 819         .get_settings = emac_get_settings,
 820         .set_settings = emac_set_settings,
 821         .get_link = ethtool_op_get_link,
 822         .get_coalesce = emac_get_coalesce,
 823         .set_coalesce =  emac_set_coalesce,
 824 };
 825
 826 /**
 827  * emac_update_phystatus: Update Phy status
 828  * @priv: The DaVinci EMAC private adapter structure
 829  *
 830  * Updates phy status and takes action for network queue if required
 831  * based upon link status
 832  *
 833  */
 834 static void emac_update_phystatus(struct emac_priv *priv)
 835 {
 836         u32 mac_control;
 837         u32 new_duplex;
 838         u32 cur_duplex;
 839         struct net_device *ndev = priv->ndev;
 840
 841         mac_control = emac_read(EMAC_MACCONTROL);
 842         cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
 843                         DUPLEX_FULL : DUPLEX_HALF;
 844         if (priv->phy_mask)
 845                 new_duplex = priv->phydev->duplex;
 846         else
 847                 new_duplex = DUPLEX_FULL;
 848
 849         /* We get called only if link has changed (speed/duplex/status) */
 850         if ((priv->link) && (new_duplex != cur_duplex)) {
 851                 priv->duplex = new_duplex;
 852                 if (DUPLEX_FULL == priv->duplex)
 853                         mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
 854                 else
 855                         mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
 856         }
 857
 858         if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
 859                 mac_control = emac_read(EMAC_MACCONTROL);
 860                 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
 861                                 EMAC_DM646X_MACCONTORL_GIGFORCE);
 862         } else {
 863                 /* Clear the GIG bit and GIGFORCE bit */
 864                 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
 865                                         EMAC_DM646X_MACCONTORL_GIG);
 866
 867                 if (priv->rmii_en && (priv->speed == SPEED_100))
 868                         mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
 869                 else
 870                         mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
 871         }
 872
 873         /* Update mac_control if changed */
 874         emac_write(EMAC_MACCONTROL, mac_control);
 875
 876         if (priv->link) {
 877                 /* link ON */
 878                 if (!netif_carrier_ok(ndev))
 879                         netif_carrier_on(ndev);
 880         /* reactivate the transmit queue if it is stopped */
 881                 if (netif_running(ndev) && netif_queue_stopped(ndev))
 882                         netif_wake_queue(ndev);
 883         } else {
 884                 /* link OFF */
 885                 if (netif_carrier_ok(ndev))
 886                         netif_carrier_off(ndev);
 887                 if (!netif_queue_stopped(ndev))
 888                         netif_stop_queue(ndev);
 889         }
 890 }
 891
 892 /**
 893  * hash_get: Calculate hash value from mac address
 894  * @addr: mac address to delete from hash table
 895  *
 896  * Calculates hash value from mac address
 897  *
 898  */
 899 static u32 hash_get(u8 *addr)
 900 {
 901         u32 hash;
 902         u8 tmpval;
 903         int cnt;
 904         hash = 0;
 905
 906         for (cnt = 0; cnt < 2; cnt++) {
 907                 tmpval = *addr++;
 908                 hash ^= (tmpval >> 2) ^ (tmpval << 4);
 909                 tmpval = *addr++;
 910                 hash ^= (tmpval >> 4) ^ (tmpval << 2);
 911                 tmpval = *addr++;
 912                 hash ^= (tmpval >> 6) ^ (tmpval);
 913         }
 914
 915         return hash & 0x3F;
 916 }
 917
 918 /**
 919  * hash_add: Hash function to add mac addr from hash table
 920  * @priv: The DaVinci EMAC private adapter structure
 921  * mac_addr: mac address to delete from hash table
 922  *
 923  * Adds mac address to the internal hash table
 924  *
 925  */
 926 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
 927 {
 928         struct device *emac_dev = &priv->ndev->dev;
 929         u32 rc = 0;
 930         u32 hash_bit;
 931         u32 hash_value = hash_get(mac_addr);
 932
 933         if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
 934                 if (netif_msg_drv(priv)) {
 935                         dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
 936                                 "Hash %08x, should not be greater than %08x",
 937                                 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
 938                 }
 939                 return -1;
 940         }
 941
 942         /* set the hash bit only if not previously set */
 943         if (priv->multicast_hash_cnt[hash_value] == 0) {
 944                 rc = 1; /* hash value changed */
 945                 if (hash_value < 32) {
 946                         hash_bit = BIT(hash_value);
 947                         priv->mac_hash1 |= hash_bit;
 948                 } else {
 949                         hash_bit = BIT((hash_value - 32));
 950                         priv->mac_hash2 |= hash_bit;
 951                 }
 952         }
 953
 954         /* incr counter for num of mcast addr's mapped to "this" hash bit */
 955         ++priv->multicast_hash_cnt[hash_value];
 956
 957         return rc;
 958 }
 959
 960 /**
 961  * hash_del: Hash function to delete mac addr from hash table
 962  * @priv: The DaVinci EMAC private adapter structure
 963  * mac_addr: mac address to delete from hash table
 964  *
 965  * Removes mac address from the internal hash table
 966  *
 967  */
 968 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
 969 {
 970         u32 hash_value;
 971         u32 hash_bit;
 972
 973         hash_value = hash_get(mac_addr);
 974         if (priv->multicast_hash_cnt[hash_value] > 0) {
 975                 /* dec cntr for num of mcast addr's mapped to this hash bit */
 976                 --priv->multicast_hash_cnt[hash_value];
 977         }
 978
 979         /* if counter still > 0, at least one multicast address refers
 980          * to this hash bit. so return 0 */
 981         if (priv->multicast_hash_cnt[hash_value] > 0)
 982                 return 0;
 983
 984         if (hash_value < 32) {
 985                 hash_bit = BIT(hash_value);
 986                 priv->mac_hash1 &= ~hash_bit;
 987         } else {
 988                 hash_bit = BIT((hash_value - 32));
 989                 priv->mac_hash2 &= ~hash_bit;
 990         }
 991
 992         /* return 1 to indicate change in mac_hash registers reqd */
 993         return 1;
 994 }
 995
 996 /* EMAC multicast operation */
 997 #define EMAC_MULTICAST_ADD      0
 998 #define EMAC_MULTICAST_DEL      1
 999 #define EMAC_ALL_MULTI_SET      2
1000 #define EMAC_ALL_MULTI_CLR      3
1001
1002 /**
1003  * emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
1004  * @priv: The DaVinci EMAC private adapter structure
1005  * @action: multicast operation to perform
1006  * mac_addr: mac address to set
1007  *
1008  * Set multicast addresses in EMAC adapter - internal function
1009  *
1010  */
1011 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
1012 {
1013         struct device *emac_dev = &priv->ndev->dev;
1014         int update = -1;
1015
1016         switch (action) {
1017         case EMAC_MULTICAST_ADD:
1018                 update = hash_add(priv, mac_addr);
1019                 break;
1020         case EMAC_MULTICAST_DEL:
1021                 update = hash_del(priv, mac_addr);
1022                 break;
1023         case EMAC_ALL_MULTI_SET:
1024                 update = 1;
1025                 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
1026                 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
1027                 break;
1028         case EMAC_ALL_MULTI_CLR:
1029                 update = 1;
1030                 priv->mac_hash1 = 0;
1031                 priv->mac_hash2 = 0;
1032                 memset(&(priv->multicast_hash_cnt[0]), 0,
1033                 sizeof(priv->multicast_hash_cnt[0]) *
1034                        EMAC_NUM_MULTICAST_BITS);
1035                 break;
1036         default:
1037                 if (netif_msg_drv(priv))
1038                         dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
1039                                 ": bad operation %d", action);
1040                 break;
1041         }
1042
1043         /* write to the hardware only if the register status chances */
1044         if (update > 0) {
1045                 emac_write(EMAC_MACHASH1, priv->mac_hash1);
1046                 emac_write(EMAC_MACHASH2, priv->mac_hash2);
1047         }
1048 }
1049
1050 /**
1051  * emac_dev_mcast_set: Set multicast address in the EMAC adapter
1052  * @ndev: The DaVinci EMAC network adapter
1053  *
1054  * Set multicast addresses in EMAC adapter
1055  *
1056  */
1057 static void emac_dev_mcast_set(struct net_device *ndev)
1058 {
1059         u32 mbp_enable;
1060         struct emac_priv *priv = netdev_priv(ndev);
1061
1062         mbp_enable = emac_read(EMAC_RXMBPENABLE);
1063         if (ndev->flags & IFF_PROMISC) {
1064                 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
1065                 mbp_enable |= (EMAC_MBP_RXPROMISC);
1066         } else {
1067                 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
1068                 if ((ndev->flags & IFF_ALLMULTI) ||
1069                     netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
1070                         mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
1071                         emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
1072                 }
1073                 if (!netdev_mc_empty(ndev)) {
1074                         struct netdev_hw_addr *ha;
1075
1076                         mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
1077                         emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
1078                         /* program multicast address list into EMAC hardware */
1079                         netdev_for_each_mc_addr(ha, ndev) {
1080                                 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
1081                                                (u8 *) ha->addr);
1082                         }
1083                 } else {
1084                         mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
1085                         emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
1086                 }
1087         }
1088         /* Set mbp config register */
1089         emac_write(EMAC_RXMBPENABLE, mbp_enable);
1090 }
1091
1092 /*************************************************************************
1093  *  EMAC Hardware manipulation
1094  *************************************************************************/
1095
1096 /**
1097  * emac_int_disable: Disable EMAC module interrupt (from adapter)
1098  * @priv: The DaVinci EMAC private adapter structure
1099  *
1100  * Disable EMAC interrupt on the adapter
1101  *
1102  */
1103 static void emac_int_disable(struct emac_priv *priv)
1104 {
1105         if (priv->version == EMAC_VERSION_2) {
1106                 unsigned long flags;
1107
1108                 local_irq_save(flags);
1109
1110                 /* Program C0_Int_En to zero to turn off
1111                 * interrupts to the CPU */
1112                 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
1113                 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
1114                 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
1115                 if (priv->int_disable)
1116                         priv->int_disable();
1117
1118                 local_irq_restore(flags);
1119
1120         } else {
1121                 /* Set DM644x control registers for interrupt control */
1122                 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
1123         }
1124 }
1125
1126 /**
1127  * emac_int_enable: Enable EMAC module interrupt (from adapter)
1128  * @priv: The DaVinci EMAC private adapter structure
1129  *
1130  * Enable EMAC interrupt on the adapter
1131  *
1132  */
1133 static void emac_int_enable(struct emac_priv *priv)
1134 {
1135         if (priv->version == EMAC_VERSION_2) {
1136                 if (priv->int_enable)
1137                         priv->int_enable();
1138
1139                 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
1140                 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
1141
1142                 /* In addition to turning on interrupt Enable, we need
1143                  * ack by writing appropriate values to the EOI
1144                  * register */
1145
1146                 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
1147
1148                 /* ack rxen only then a new pulse will be generated */
1149                 emac_write(EMAC_DM646X_MACEOIVECTOR,
1150                         EMAC_DM646X_MAC_EOI_C0_RXEN);
1151
1152                 /* ack txen- only then a new pulse will be generated */
1153                 emac_write(EMAC_DM646X_MACEOIVECTOR,
1154                         EMAC_DM646X_MAC_EOI_C0_TXEN);
1155
1156         } else {
1157                 /* Set DM644x control registers for interrupt control */
1158                 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
1159         }
1160 }
1161
1162 /**
1163  * emac_irq: EMAC interrupt handler
1164  * @irq: interrupt number
1165  * @dev_id: EMAC network adapter data structure ptr
1166  *
1167  * EMAC Interrupt handler - we only schedule NAPI and not process any packets
1168  * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
1169  *
1170  * Returns interrupt handled condition
1171  */
1172 static irqreturn_t emac_irq(int irq, void *dev_id)
1173 {
1174         struct net_device *ndev = (struct net_device *)dev_id;
1175         struct emac_priv *priv = netdev_priv(ndev);
1176
1177         ++priv->isr_count;
1178         if (likely(netif_running(priv->ndev))) {
1179                 emac_int_disable(priv);
1180                 napi_schedule(&priv->napi);
1181         } else {
1182                 /* we are closing down, so dont process anything */
1183         }
1184         return IRQ_HANDLED;
1185 }
1186
1187 /** EMAC on-chip buffer descriptor memory
1188  *
1189  * WARNING: Please note that the on chip memory is used for both TX and RX
1190  * buffer descriptor queues and is equally divided between TX and RX desc's
1191  * If the number of TX or RX descriptors change this memory pointers need
1192  * to be adjusted. If external memory is allocated then these pointers can
1193  * pointer to the memory
1194  *
1195  */
1196 #define EMAC_TX_BD_MEM(priv)    ((priv)->emac_ctrl_ram)
1197 #define EMAC_RX_BD_MEM(priv)    ((priv)->emac_ctrl_ram + \
1198                                 (((priv)->ctrl_ram_size) >> 1))
1199
1200 /**
1201  * emac_init_txch: TX channel initialization
1202  * @priv: The DaVinci EMAC private adapter structure
1203  * @ch: RX channel number
1204  *
1205  * Called during device init to setup a TX channel (allocate buffer desc
1206  * create free pool and keep ready for transmission
1207  *
1208  * Returns success(0) or mem alloc failures error code
1209  */
1210 static int emac_init_txch(struct emac_priv *priv, u32 ch)
1211 {
1212         struct device *emac_dev = &priv->ndev->dev;
1213         u32 cnt, bd_size;
1214         void __iomem *mem;
1215         struct emac_tx_bd __iomem *curr_bd;
1216         struct emac_txch *txch = NULL;
1217
1218         txch = kzalloc(sizeof(struct emac_txch), GFP_KERNEL);
1219         if (NULL == txch) {
1220                 dev_err(emac_dev, "DaVinci EMAC: TX Ch mem alloc failed");
1221                 return -ENOMEM;
1222         }
1223         priv->txch[ch] = txch;
1224         txch->service_max = EMAC_DEF_TX_MAX_SERVICE;
1225         txch->active_queue_head = NULL;
1226         txch->active_queue_tail = NULL;
1227         txch->queue_active = 0;
1228         txch->teardown_pending = 0;
1229
1230         /* allocate memory for TX CPPI channel on a 4 byte boundry */
1231         txch->tx_complete = kzalloc(txch->service_max * sizeof(u32),
1232                                     GFP_KERNEL);
1233         if (NULL == txch->tx_complete) {
1234                 dev_err(emac_dev, "DaVinci EMAC: Tx service mem alloc failed");
1235                 kfree(txch);
1236                 return -ENOMEM;
1237         }
1238
1239         /* allocate buffer descriptor pool align every BD on four word
1240          * boundry for future requirements */
1241         bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF;
1242         txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1243         txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF);
1244
1245         /* alloc TX BD memory */
1246         txch->bd_mem = EMAC_TX_BD_MEM(priv);
1247         __memzero((void __force *)txch->bd_mem, txch->alloc_size);
1248
1249         /* initialize the BD linked list */
1250         mem = (void __force __iomem *)
1251                         (((u32 __force) txch->bd_mem + 0xF) & ~0xF);
1252         txch->bd_pool_head = NULL;
1253         for (cnt = 0; cnt < txch->num_bd; cnt++) {
1254                 curr_bd = mem + (cnt * bd_size);
1255                 curr_bd->next = txch->bd_pool_head;
1256                 txch->bd_pool_head = curr_bd;
1257         }
1258
1259         /* reset statistics counters */
1260         txch->out_of_tx_bd = 0;
1261         txch->no_active_pkts = 0;
1262         txch->active_queue_count = 0;
1263
1264         return 0;
1265 }
1266
1267 /**
1268  * emac_cleanup_txch: Book-keep function to clean TX channel resources
1269  * @priv: The DaVinci EMAC private adapter structure
1270  * @ch: TX channel number
1271  *
1272  * Called to clean up TX channel resources
1273  *
1274  */
1275 static void emac_cleanup_txch(struct emac_priv *priv, u32 ch)
1276 {
1277         struct emac_txch *txch = priv->txch[ch];
1278
1279         if (txch) {
1280                 if (txch->bd_mem)
1281                         txch->bd_mem = NULL;
1282                 kfree(txch->tx_complete);
1283                 kfree(txch);
1284                 priv->txch[ch] = NULL;
1285         }
1286 }
1287
1288 /**
1289  * emac_net_tx_complete: TX packet completion function
1290  * @priv: The DaVinci EMAC private adapter structure
1291  * @net_data_tokens: packet token - skb pointer
1292  * @num_tokens: number of skb's to free
1293  * @ch: TX channel number
1294  *
1295  * Frees the skb once packet is transmitted
1296  *
1297  */
1298 static int emac_net_tx_complete(struct emac_priv *priv,
1299                                 void **net_data_tokens,
1300                                 int num_tokens, u32 ch)
1301 {
1302         struct net_device *ndev = priv->ndev;
1303         u32 cnt;
1304
1305         if (unlikely(num_tokens && netif_queue_stopped(ndev)))
1306                 netif_start_queue(ndev);
1307         for (cnt = 0; cnt < num_tokens; cnt++) {
1308                 struct sk_buff *skb = (struct sk_buff *)net_data_tokens[cnt];
1309                 if (skb == NULL)
1310                         continue;
1311                 ndev->stats.tx_packets++;
1312                 ndev->stats.tx_bytes += skb->len;
1313                 dev_kfree_skb_any(skb);
1314         }
1315         return 0;
1316 }
1317
1318 /**
1319  * emac_txch_teardown: TX channel teardown
1320  * @priv: The DaVinci EMAC private adapter structure
1321  * @ch: TX channel number
1322  *
1323  * Called to teardown TX channel
1324  *
1325  */
1326 static void emac_txch_teardown(struct emac_priv *priv, u32 ch)
1327 {
1328         struct device *emac_dev = &priv->ndev->dev;
1329         u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1330         struct emac_txch *txch = priv->txch[ch];
1331         struct emac_tx_bd __iomem *curr_bd;
1332
1333         while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1334                EMAC_TEARDOWN_VALUE) {
1335                 /* wait till tx teardown complete */
1336                 cpu_relax(); /* TODO: check if this helps ... */
1337                 --teardown_cnt;
1338                 if (0 == teardown_cnt) {
1339                         dev_err(emac_dev, "EMAC: TX teardown aborted\n");
1340                         break;
1341                 }
1342         }
1343         emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE);
1344
1345         /* process sent packets and return skb's to upper layer */
1346         if (1 == txch->queue_active) {
1347                 curr_bd = txch->active_queue_head;
1348                 while (curr_bd != NULL) {
1349                         dma_unmap_single(emac_dev, curr_bd->buff_ptr,
1350                                 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
1351                                 DMA_TO_DEVICE);
1352
1353                         emac_net_tx_complete(priv, (void __force *)
1354                                         &curr_bd->buf_token, 1, ch);
1355                         if (curr_bd != txch->active_queue_tail)
1356                                 curr_bd = curr_bd->next;
1357                         else
1358                                 break;
1359                 }
1360                 txch->bd_pool_head = txch->active_queue_head;
1361                 txch->active_queue_head =
1362                 txch->active_queue_tail = NULL;
1363         }
1364 }
1365
1366 /**
1367  * emac_stop_txch: Stop TX channel operation
1368  * @priv: The DaVinci EMAC private adapter structure
1369  * @ch: TX channel number
1370  *
1371  * Called to stop TX channel operation
1372  *
1373  */
1374 static void emac_stop_txch(struct emac_priv *priv, u32 ch)
1375 {
1376         struct emac_txch *txch = priv->txch[ch];
1377
1378         if (txch) {
1379                 txch->teardown_pending = 1;
1380                 emac_write(EMAC_TXTEARDOWN, 0);
1381                 emac_txch_teardown(priv, ch);
1382                 txch->teardown_pending = 0;
1383                 emac_write(EMAC_TXINTMASKCLEAR, BIT(ch));
1384         }
1385 }
1386
1387 /**
1388  * emac_tx_bdproc: TX buffer descriptor (packet) processing
1389  * @priv: The DaVinci EMAC private adapter structure
1390  * @ch: TX channel number to process buffer descriptors for
1391  * @budget: number of packets allowed to process
1392  * @pending: indication to caller that packets are pending to process
1393  *
1394  * Processes TX buffer descriptors after packets are transmitted - checks
1395  * ownership bit on the TX * descriptor and requeues it to free pool & frees
1396  * the SKB buffer. Only "budget" number of packets are processed and
1397  * indication of pending packets provided to the caller
1398  *
1399  * Returns number of packets processed
1400  */
1401 static int emac_tx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
1402 {
1403         struct device *emac_dev = &priv->ndev->dev;
1404         unsigned long flags;
1405         u32 frame_status;
1406         u32 pkts_processed = 0;
1407         u32 tx_complete_cnt = 0;
1408         struct emac_tx_bd __iomem *curr_bd;
1409         struct emac_txch *txch = priv->txch[ch];
1410         u32 *tx_complete_ptr = txch->tx_complete;
1411
1412         if (unlikely(1 == txch->teardown_pending)) {
1413                 if (netif_msg_tx_err(priv) && net_ratelimit()) {
1414                         dev_err(emac_dev, "DaVinci EMAC:emac_tx_bdproc: "\
1415                                 "teardown pending\n");
1416                 }
1417                 return 0;  /* dont handle any pkt completions */
1418         }
1419
1420         ++txch->proc_count;
1421         spin_lock_irqsave(&priv->tx_lock, flags);
1422         curr_bd = txch->active_queue_head;
1423         if (NULL == curr_bd) {
1424                 emac_write(EMAC_TXCP(ch),
1425                            emac_virt_to_phys(txch->last_hw_bdprocessed, priv));
1426                 txch->no_active_pkts++;
1427                 spin_unlock_irqrestore(&priv->tx_lock, flags);
1428                 return 0;
1429         }
1430         BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1431         frame_status = curr_bd->mode;
1432         while ((curr_bd) &&
1433               ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
1434               (pkts_processed < budget)) {
1435                 emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd, priv));
1436                 txch->active_queue_head = curr_bd->next;
1437                 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1438                         if (curr_bd->next) {    /* misqueued packet */
1439                                 emac_write(EMAC_TXHDP(ch), curr_bd->h_next);
1440                                 ++txch->mis_queued_packets;
1441                         } else {
1442                                 txch->queue_active = 0; /* end of queue */
1443                         }
1444                 }
1445
1446                 dma_unmap_single(emac_dev, curr_bd->buff_ptr,
1447                                 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
1448                                 DMA_TO_DEVICE);
1449
1450                 *tx_complete_ptr = (u32) curr_bd->buf_token;
1451                 ++tx_complete_ptr;
1452                 ++tx_complete_cnt;
1453                 curr_bd->next = txch->bd_pool_head;
1454                 txch->bd_pool_head = curr_bd;
1455                 --txch->active_queue_count;
1456                 pkts_processed++;
1457                 txch->last_hw_bdprocessed = curr_bd;
1458                 curr_bd = txch->active_queue_head;
1459                 if (curr_bd) {
1460                         BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1461                         frame_status = curr_bd->mode;
1462                 }
1463         } /* end of pkt processing loop */
1464
1465         emac_net_tx_complete(priv,
1466                              (void *)&txch->tx_complete[0],
1467                              tx_complete_cnt, ch);
1468         spin_unlock_irqrestore(&priv->tx_lock, flags);
1469         return pkts_processed;
1470 }
1471
1472 #define EMAC_ERR_TX_OUT_OF_BD -1
1473
1474 /**
1475  * emac_send: EMAC Transmit function (internal)
1476  * @priv: The DaVinci EMAC private adapter structure
1477  * @pkt: packet pointer (contains skb ptr)
1478  * @ch: TX channel number
1479  *
1480  * Called by the transmit function to queue the packet in EMAC hardware queue
1481  *
1482  * Returns success(0) or error code (typically out of desc's)
1483  */
1484 static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, u32 ch)
1485 {
1486         unsigned long flags;
1487         struct emac_tx_bd __iomem *curr_bd;
1488         struct emac_txch *txch;
1489         struct emac_netbufobj *buf_list;
1490
1491         txch = priv->txch[ch];
1492         buf_list = pkt->buf_list;   /* get handle to the buffer array */
1493
1494         /* check packet size and pad if short */
1495         if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) {
1496                 buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length);
1497                 pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE;
1498         }
1499
1500         spin_lock_irqsave(&priv->tx_lock, flags);
1501         curr_bd = txch->bd_pool_head;
1502         if (curr_bd == NULL) {
1503                 txch->out_of_tx_bd++;
1504                 spin_unlock_irqrestore(&priv->tx_lock, flags);
1505                 return EMAC_ERR_TX_OUT_OF_BD;
1506         }
1507
1508         txch->bd_pool_head = curr_bd->next;
1509         curr_bd->buf_token = buf_list->buf_token;
1510         curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buf_list->data_ptr,
1511                         buf_list->length, DMA_TO_DEVICE);
1512         curr_bd->off_b_len = buf_list->length;
1513         curr_bd->h_next = 0;
1514         curr_bd->next = NULL;
1515         curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT |
1516                          EMAC_CPPI_EOP_BIT | pkt->pkt_length);
1517
1518         /* flush the packet from cache if write back cache is present */
1519         BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
1520
1521         /* send the packet */
1522         if (txch->active_queue_head == NULL) {
1523                 txch->active_queue_head = curr_bd;
1524                 txch->active_queue_tail = curr_bd;
1525                 if (1 != txch->queue_active) {
1526                         emac_write(EMAC_TXHDP(ch),
1527                                         emac_virt_to_phys(curr_bd, priv));
1528                         txch->queue_active = 1;
1529                 }
1530                 ++txch->queue_reinit;
1531         } else {
1532                 register struct emac_tx_bd __iomem *tail_bd;
1533                 register u32 frame_status;
1534
1535                 tail_bd = txch->active_queue_tail;
1536                 tail_bd->next = curr_bd;
1537                 txch->active_queue_tail = curr_bd;
1538                 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
1539                 tail_bd->h_next = (int)emac_virt_to_phys(curr_bd, priv);
1540                 frame_status = tail_bd->mode;
1541                 if (frame_status & EMAC_CPPI_EOQ_BIT) {
1542                         emac_write(EMAC_TXHDP(ch),
1543                                 emac_virt_to_phys(curr_bd, priv));
1544                         frame_status &= ~(EMAC_CPPI_EOQ_BIT);
1545                         tail_bd->mode = frame_status;
1546                         ++txch->end_of_queue_add;
1547                 }
1548         }
1549         txch->active_queue_count++;
1550         spin_unlock_irqrestore(&priv->tx_lock, flags);
1551         return 0;
1552 }
1553
1554 /**
1555  * emac_dev_xmit: EMAC Transmit function
1556  * @skb: SKB pointer
1557  * @ndev: The DaVinci EMAC network adapter
1558  *
1559  * Called by the system to transmit a packet  - we queue the packet in
1560  * EMAC hardware transmit queue
1561  *
1562  * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1563  */
1564 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1565 {
1566         struct device *emac_dev = &ndev->dev;
1567         int ret_code;
1568         struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */
1569         struct emac_netpktobj tx_packet;  /* packet object */
1570         struct emac_priv *priv = netdev_priv(ndev);
1571
1572         /* If no link, return */
1573         if (unlikely(!priv->link)) {
1574                 if (netif_msg_tx_err(priv) && net_ratelimit())
1575                         dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1576                 return NETDEV_TX_BUSY;
1577         }
1578
1579         /* Build the buffer and packet objects - Since only single fragment is
1580          * supported, need not set length and token in both packet & object.
1581          * Doing so for completeness sake & to show that this needs to be done
1582          * in multifragment case
1583          */
1584         tx_packet.buf_list = &tx_buf;
1585         tx_packet.num_bufs = 1; /* only single fragment supported */
1586         tx_packet.pkt_length = skb->len;
1587         tx_packet.pkt_token = (void *)skb;
1588         tx_buf.length = skb->len;
1589         tx_buf.buf_token = (void *)skb;
1590         tx_buf.data_ptr = skb->data;
1591         ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
1592         if (unlikely(ret_code != 0)) {
1593                 if (ret_code == EMAC_ERR_TX_OUT_OF_BD) {
1594                         if (netif_msg_tx_err(priv) && net_ratelimit())
1595                                 dev_err(emac_dev, "DaVinci EMAC: xmit() fatal"\
1596                                         " err. Out of TX BD's");
1597                         netif_stop_queue(priv->ndev);
1598                 }
1599                 ndev->stats.tx_dropped++;
1600                 return NETDEV_TX_BUSY;
1601         }
1602
1603         return NETDEV_TX_OK;
1604 }
1605
1606 /**
1607  * emac_dev_tx_timeout: EMAC Transmit timeout function
1608  * @ndev: The DaVinci EMAC network adapter
1609  *
1610  * Called when system detects that a skb timeout period has expired
1611  * potentially due to a fault in the adapter in not being able to send
1612  * it out on the wire. We teardown the TX channel assuming a hardware
1613  * error and re-initialize the TX channel for hardware operation
1614  *
1615  */
1616 static void emac_dev_tx_timeout(struct net_device *ndev)
1617 {
1618         struct emac_priv *priv = netdev_priv(ndev);
1619         struct device *emac_dev = &ndev->dev;
1620
1621         if (netif_msg_tx_err(priv))
1622                 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1623
1624         ndev->stats.tx_errors++;
1625         emac_int_disable(priv);
1626         emac_stop_txch(priv, EMAC_DEF_TX_CH);
1627         emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
1628         emac_init_txch(priv, EMAC_DEF_TX_CH);
1629         emac_write(EMAC_TXHDP(0), 0);
1630         emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH));
1631         emac_int_enable(priv);
1632 }
1633
1634 /**
1635  * emac_net_alloc_rx_buf: Allocate a skb for RX
1636  * @priv: The DaVinci EMAC private adapter structure
1637  * @buf_size: size of SKB data buffer to allocate
1638  * @data_token: data token returned (skb handle for storing in buffer desc)
1639  * @ch: RX channel number
1640  *
1641  * Called during RX channel setup - allocates skb buffer of required size
1642  * and provides the skb handle and allocated buffer data pointer to caller
1643  *
1644  * Returns skb data pointer or 0 on failure to alloc skb
1645  */
1646 static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size,
1647                 void **data_token, u32 ch)
1648 {
1649         struct net_device *ndev = priv->ndev;
1650         struct device *emac_dev = &ndev->dev;
1651         struct sk_buff *p_skb;
1652
1653         p_skb = dev_alloc_skb(buf_size);
1654         if (unlikely(NULL == p_skb)) {
1655                 if (netif_msg_rx_err(priv) && net_ratelimit())
1656                         dev_err(emac_dev, "DaVinci EMAC: failed to alloc skb");
1657                 return NULL;
1658         }
1659
1660         /* set device pointer in skb and reserve space for extra bytes */
1661         p_skb->dev = ndev;
1662         skb_reserve(p_skb, NET_IP_ALIGN);
1663         *data_token = (void *) p_skb;
1664         return p_skb->data;
1665 }
1666
1667 /**
1668  * emac_init_rxch: RX channel initialization
1669  * @priv: The DaVinci EMAC private adapter structure
1670  * @ch: RX channel number
1671  * @param: mac address for RX channel
1672  *
1673  * Called during device init to setup a RX channel (allocate buffers and
1674  * buffer descriptors, create queue and keep ready for reception
1675  *
1676  * Returns success(0) or mem alloc failures error code
1677  */
1678 static int emac_init_rxch(struct emac_priv *priv, u32 ch, char *param)
1679 {
1680         struct device *emac_dev = &priv->ndev->dev;
1681         u32 cnt, bd_size;
1682         void __iomem *mem;
1683         struct emac_rx_bd __iomem *curr_bd;
1684         struct emac_rxch *rxch = NULL;
1685
1686         rxch = kzalloc(sizeof(struct emac_rxch), GFP_KERNEL);
1687         if (NULL == rxch) {
1688                 dev_err(emac_dev, "DaVinci EMAC: RX Ch mem alloc failed");
1689                 return -ENOMEM;
1690         }
1691         priv->rxch[ch] = rxch;
1692         rxch->buf_size = priv->rx_buf_size;
1693         rxch->service_max = EMAC_DEF_RX_MAX_SERVICE;
1694         rxch->queue_active = 0;
1695         rxch->teardown_pending = 0;
1696
1697         /* save mac address */
1698         for (cnt = 0; cnt < 6; cnt++)
1699                 rxch->mac_addr[cnt] = param[cnt];
1700
1701         /* allocate buffer descriptor pool align every BD on four word
1702          * boundry for future requirements */
1703         bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF;
1704         rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
1705         rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF);
1706         rxch->bd_mem = EMAC_RX_BD_MEM(priv);
1707         __memzero((void __force *)rxch->bd_mem, rxch->alloc_size);
1708         rxch->pkt_queue.buf_list = &rxch->buf_queue;
1709
1710         /* allocate RX buffer and initialize the BD linked list */
1711         mem = (void __force __iomem *)
1712                         (((u32 __force) rxch->bd_mem + 0xF) & ~0xF);
1713         rxch->active_queue_head = NULL;
1714         rxch->active_queue_tail = mem;
1715         for (cnt = 0; cnt < rxch->num_bd; cnt++) {
1716                 curr_bd = mem + (cnt * bd_size);
1717                 /* for future use the last parameter contains the BD ptr */
1718                 curr_bd->data_ptr = emac_net_alloc_rx_buf(priv,
1719                                     rxch->buf_size,
1720                                     (void __force **)&curr_bd->buf_token,
1721                                     EMAC_DEF_RX_CH);
1722                 if (curr_bd->data_ptr == NULL) {
1723                         dev_err(emac_dev, "DaVinci EMAC: RX buf mem alloc " \
1724                                 "failed for ch %d\n", ch);
1725                         kfree(rxch);
1726                         return -ENOMEM;
1727                 }
1728
1729                 /* populate the hardware descriptor */
1730                 curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head,
1731                                 priv);
1732                 curr_bd->buff_ptr = dma_map_single(emac_dev, curr_bd->data_ptr,
1733                                 rxch->buf_size, DMA_FROM_DEVICE);
1734                 curr_bd->off_b_len = rxch->buf_size;
1735                 curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
1736
1737                 /* write back to hardware memory */
1738                 BD_CACHE_WRITEBACK_INVALIDATE((u32) curr_bd,
1739                                               EMAC_BD_LENGTH_FOR_CACHE);
1740                 curr_bd->next = rxch->active_queue_head;
1741                 rxch->active_queue_head = curr_bd;
1742         }
1743
1744         /* At this point rxCppi->activeQueueHead points to the first
1745            RX BD ready to be given to RX HDP and rxch->active_queue_tail
1746            points to the last RX BD
1747          */
1748         return 0;
1749 }
1750
1751 /**
1752  * emac_rxch_teardown: RX channel teardown
1753  * @priv: The DaVinci EMAC private adapter structure
1754  * @ch: RX channel number
1755  *
1756  * Called during device stop to teardown RX channel
1757  *
1758  */
1759 static void emac_rxch_teardown(struct emac_priv *priv, u32 ch)
1760 {
1761         struct device *emac_dev = &priv->ndev->dev;
1762         u32 teardown_cnt = 0xFFFFFFF0; /* Some high value */
1763
1764         while ((emac_read(EMAC_RXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
1765                EMAC_TEARDOWN_VALUE) {
1766                 /* wait till tx teardown complete */
1767                 cpu_relax(); /* TODO: check if this helps ... */
1768                 --teardown_cnt;
1769                 if (0 == teardown_cnt) {
1770                         dev_err(emac_dev, "EMAC: RX teardown aborted\n");
1771                         break;
1772                 }
1773         }
1774         emac_write(EMAC_RXCP(ch), EMAC_TEARDOWN_VALUE);
1775 }
1776
1777 /**
1778  * emac_stop_rxch: Stop RX channel operation
1779  * @priv: The DaVinci EMAC private adapter structure
1780  * @ch: RX channel number
1781  *
1782  * Called during device stop to stop RX channel operation
1783  *
1784  */
1785 static void emac_stop_rxch(struct emac_priv *priv, u32 ch)
1786 {
1787         struct emac_rxch *rxch = priv->rxch[ch];
1788
1789         if (rxch) {
1790                 rxch->teardown_pending = 1;
1791                 emac_write(EMAC_RXTEARDOWN, ch);
1792                 /* wait for teardown complete */
1793                 emac_rxch_teardown(priv, ch);
1794                 rxch->teardown_pending = 0;
1795                 emac_write(EMAC_RXINTMASKCLEAR, BIT(ch));
1796         }
1797 }
1798
1799 /**
1800  * emac_cleanup_rxch: Book-keep function to clean RX channel resources
1801  * @priv: The DaVinci EMAC private adapter structure
1802  * @ch: RX channel number
1803  *
1804  * Called during device stop to clean up RX channel resources
1805  *
1806  */
1807 static void emac_cleanup_rxch(struct emac_priv *priv, u32 ch)
1808 {
1809         struct emac_rxch *rxch = priv->rxch[ch];
1810         struct emac_rx_bd __iomem *curr_bd;
1811
1812         if (rxch) {
1813                 /* free the receive buffers previously allocated */
1814                 curr_bd = rxch->active_queue_head;
1815                 while (curr_bd) {
1816                         if (curr_bd->buf_token) {
1817                                 dma_unmap_single(&priv->ndev->dev,
1818                                         curr_bd->buff_ptr,
1819                                         curr_bd->off_b_len
1820                                                 & EMAC_RX_BD_BUF_SIZE,
1821                                         DMA_FROM_DEVICE);
1822
1823                                 dev_kfree_skb_any((struct sk_buff *)\
1824                                                   curr_bd->buf_token);
1825                         }
1826                         curr_bd = curr_bd->next;
1827                 }
1828                 if (rxch->bd_mem)
1829                         rxch->bd_mem = NULL;
1830                 kfree(rxch);
1831                 priv->rxch[ch] = NULL;
1832         }
1833 }
1834
1835 /**
1836  * emac_set_type0addr: Set EMAC Type0 mac address
1837  * @priv: The DaVinci EMAC private adapter structure
1838  * @ch: RX channel number
1839  * @mac_addr: MAC address to set in device
1840  *
1841  * Called internally to set Type0 mac address of the adapter (Device)
1842  *
1843  * Returns success (0) or appropriate error code (none as of now)
1844  */
1845 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1846 {
1847         u32 val;
1848         val = ((mac_addr[5] << 8) | (mac_addr[4]));
1849         emac_write(EMAC_MACSRCADDRLO, val);
1850
1851         val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1852                (mac_addr[1] << 8) | (mac_addr[0]));
1853         emac_write(EMAC_MACSRCADDRHI, val);
1854         val = emac_read(EMAC_RXUNICASTSET);
1855         val |= BIT(ch);
1856         emac_write(EMAC_RXUNICASTSET, val);
1857         val = emac_read(EMAC_RXUNICASTCLEAR);
1858         val &= ~BIT(ch);
1859         emac_write(EMAC_RXUNICASTCLEAR, val);
1860 }
1861
1862 /**
1863  * emac_set_type1addr: Set EMAC Type1 mac address
1864  * @priv: The DaVinci EMAC private adapter structure
1865  * @ch: RX channel number
1866  * @mac_addr: MAC address to set in device
1867  *
1868  * Called internally to set Type1 mac address of the adapter (Device)
1869  *
1870  * Returns success (0) or appropriate error code (none as of now)
1871  */
1872 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1873 {
1874         u32 val;
1875         emac_write(EMAC_MACINDEX, ch);
1876         val = ((mac_addr[5] << 8) | mac_addr[4]);
1877         emac_write(EMAC_MACADDRLO, val);
1878         val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1879                (mac_addr[1] << 8) | (mac_addr[0]));
1880         emac_write(EMAC_MACADDRHI, val);
1881         emac_set_type0addr(priv, ch, mac_addr);
1882 }
1883
1884 /**
1885  * emac_set_type2addr: Set EMAC Type2 mac address
1886  * @priv: The DaVinci EMAC private adapter structure
1887  * @ch: RX channel number
1888  * @mac_addr: MAC address to set in device
1889  * @index: index into RX address entries
1890  * @match: match parameter for RX address matching logic
1891  *
1892  * Called internally to set Type2 mac address of the adapter (Device)
1893  *
1894  * Returns success (0) or appropriate error code (none as of now)
1895  */
1896 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1897                                char *mac_addr, int index, int match)
1898 {
1899         u32 val;
1900         emac_write(EMAC_MACINDEX, index);
1901         val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1902                (mac_addr[1] << 8) | (mac_addr[0]));
1903         emac_write(EMAC_MACADDRHI, val);
1904         val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1905                (match << 19) | BIT(20));
1906         emac_write(EMAC_MACADDRLO, val);
1907         emac_set_type0addr(priv, ch, mac_addr);
1908 }
1909
1910 /**
1911  * emac_setmac: Set mac address in the adapter (internal function)
1912  * @priv: The DaVinci EMAC private adapter structure
1913  * @ch: RX channel number
1914  * @mac_addr: MAC address to set in device
1915  *
1916  * Called internally to set the mac address of the adapter (Device)
1917  *
1918  * Returns success (0) or appropriate error code (none as of now)
1919  */
1920 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1921 {
1922         struct device *emac_dev = &priv->ndev->dev;
1923
1924         if (priv->rx_addr_type == 0) {
1925                 emac_set_type0addr(priv, ch, mac_addr);
1926         } else if (priv->rx_addr_type == 1) {
1927                 u32 cnt;
1928                 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1929                         emac_set_type1addr(priv, ch, mac_addr);
1930         } else if (priv->rx_addr_type == 2) {
1931                 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1932                 emac_set_type0addr(priv, ch, mac_addr);
1933         } else {
1934                 if (netif_msg_drv(priv))
1935                         dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1936         }
1937 }
1938
1939 /**
1940  * emac_dev_setmac_addr: Set mac address in the adapter
1941  * @ndev: The DaVinci EMAC network adapter
1942  * @addr: MAC address to set in device
1943  *
1944  * Called by the system to set the mac address of the adapter (Device)
1945  *
1946  * Returns success (0) or appropriate error code (none as of now)
1947  */
1948 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1949 {
1950         struct emac_priv *priv = netdev_priv(ndev);
1951         struct emac_rxch *rxch = priv->rxch[EMAC_DEF_RX_CH];
1952         struct device *emac_dev = &priv->ndev->dev;
1953         struct sockaddr *sa = addr;
1954
1955         if (!is_valid_ether_addr(sa->sa_data))
1956                 return -EINVAL;
1957
1958         /* Store mac addr in priv and rx channel and set it in EMAC hw */
1959         memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1960         memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1961
1962         /* If the interface is down - rxch is NULL. */
1963         /* MAC address is configured only after the interface is enabled. */
1964         if (netif_running(ndev)) {
1965                 memcpy(rxch->mac_addr, sa->sa_data, ndev->addr_len);
1966                 emac_setmac(priv, EMAC_DEF_RX_CH, rxch->mac_addr);
1967         }
1968
1969         if (netif_msg_drv(priv))
1970                 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1971                                         priv->mac_addr);
1972
1973         return 0;
1974 }
1975
1976 /**
1977  * emac_addbd_to_rx_queue: Recycle RX buffer descriptor
1978  * @priv: The DaVinci EMAC private adapter structure
1979  * @ch: RX channel number to process buffer descriptors for
1980  * @curr_bd: current buffer descriptor
1981  * @buffer: buffer pointer for descriptor
1982  * @buf_token: buffer token (stores skb information)
1983  *
1984  * Prepares the recycled buffer descriptor and addes it to hardware
1985  * receive queue - if queue empty this descriptor becomes the head
1986  * else addes the descriptor to end of queue
1987  *
1988  */
1989 static void emac_addbd_to_rx_queue(struct emac_priv *priv, u32 ch,
1990                 struct emac_rx_bd __iomem *curr_bd,
1991                 char *buffer, void *buf_token)
1992 {
1993         struct emac_rxch *rxch = priv->rxch[ch];
1994
1995         /* populate the hardware descriptor */
1996         curr_bd->h_next = 0;
1997         curr_bd->buff_ptr = dma_map_single(&priv->ndev->dev, buffer,
1998                                 rxch->buf_size, DMA_FROM_DEVICE);
1999         curr_bd->off_b_len = rxch->buf_size;
2000         curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
2001         curr_bd->next = NULL;
2002         curr_bd->data_ptr = buffer;
2003         curr_bd->buf_token = buf_token;
2004
2005         /* write back  */
2006         BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2007         if (rxch->active_queue_head == NULL) {
2008                 rxch->active_queue_head = curr_bd;
2009                 rxch->active_queue_tail = curr_bd;
2010                 if (0 != rxch->queue_active) {
2011                         emac_write(EMAC_RXHDP(ch),
2012                            emac_virt_to_phys(rxch->active_queue_head, priv));
2013                         rxch->queue_active = 1;
2014                 }
2015         } else {
2016                 struct emac_rx_bd __iomem *tail_bd;
2017                 u32 frame_status;
2018
2019                 tail_bd = rxch->active_queue_tail;
2020                 rxch->active_queue_tail = curr_bd;
2021                 tail_bd->next = curr_bd;
2022                 tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
2023                 tail_bd->h_next = emac_virt_to_phys(curr_bd, priv);
2024                 frame_status = tail_bd->mode;
2025                 if (frame_status & EMAC_CPPI_EOQ_BIT) {
2026                         emac_write(EMAC_RXHDP(ch),
2027                                         emac_virt_to_phys(curr_bd, priv));
2028                         frame_status &= ~(EMAC_CPPI_EOQ_BIT);
2029                         tail_bd->mode = frame_status;
2030                         ++rxch->end_of_queue_add;
2031                 }
2032         }
2033         ++rxch->recycled_bd;
2034 }
2035
2036 /**
2037  * emac_net_rx_cb: Prepares packet and sends to upper layer
2038  * @priv: The DaVinci EMAC private adapter structure
2039  * @net_pkt_list: Network packet list (received packets)
2040  *
2041  * Invalidates packet buffer memory and sends the received packet to upper
2042  * layer
2043  *
2044  * Returns success or appropriate error code (none as of now)
2045  */
2046 static int emac_net_rx_cb(struct emac_priv *priv,
2047                           struct emac_netpktobj *net_pkt_list)
2048 {
2049         struct net_device *ndev = priv->ndev;
2050         struct sk_buff *p_skb = net_pkt_list->pkt_token;
2051         /* set length of packet */
2052         skb_put(p_skb, net_pkt_list->pkt_length);
2053         p_skb->protocol = eth_type_trans(p_skb, priv->ndev);
2054         netif_receive_skb(p_skb);
2055         ndev->stats.rx_bytes += net_pkt_list->pkt_length;
2056         ndev->stats.rx_packets++;
2057         return 0;
2058 }
2059
2060 /**
2061  * emac_rx_bdproc: RX buffer descriptor (packet) processing
2062  * @priv: The DaVinci EMAC private adapter structure
2063  * @ch: RX channel number to process buffer descriptors for
2064  * @budget: number of packets allowed to process
2065  * @pending: indication to caller that packets are pending to process
2066  *
2067  * Processes RX buffer descriptors - checks ownership bit on the RX buffer
2068  * descriptor, sends the receive packet to upper layer, allocates a new SKB
2069  * and recycles the buffer descriptor (requeues it in hardware RX queue).
2070  * Only "budget" number of packets are processed and indication of pending
2071  * packets provided to the caller.
2072  *
2073  * Returns number of packets processed (and indication of pending packets)
2074  */
2075 static int emac_rx_bdproc(struct emac_priv *priv, u32 ch, u32 budget)
2076 {
2077         unsigned long flags;
2078         u32 frame_status;
2079         u32 pkts_processed = 0;
2080         char *new_buffer;
2081         struct emac_rx_bd __iomem *curr_bd;
2082         struct emac_rx_bd __iomem *last_bd;
2083         struct emac_netpktobj *curr_pkt, pkt_obj;
2084         struct emac_netbufobj buf_obj;
2085         struct emac_netbufobj *rx_buf_obj;
2086         void *new_buf_token;
2087         struct emac_rxch *rxch = priv->rxch[ch];
2088
2089         if (unlikely(1 == rxch->teardown_pending))
2090                 return 0;
2091         ++rxch->proc_count;
2092         spin_lock_irqsave(&priv->rx_lock, flags);
2093         pkt_obj.buf_list = &buf_obj;
2094         curr_pkt = &pkt_obj;
2095         curr_bd = rxch->active_queue_head;
2096         BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2097         frame_status = curr_bd->mode;
2098
2099         while ((curr_bd) &&
2100                ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
2101                (pkts_processed < budget)) {
2102
2103                 new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size,
2104                                         &new_buf_token, EMAC_DEF_RX_CH);
2105                 if (unlikely(NULL == new_buffer)) {
2106                         ++rxch->out_of_rx_buffers;
2107                         goto end_emac_rx_bdproc;
2108                 }
2109
2110                 /* populate received packet data structure */
2111                 rx_buf_obj = &curr_pkt->buf_list[0];
2112                 rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
2113                 rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
2114                 rx_buf_obj->buf_token = curr_bd->buf_token;
2115
2116                 dma_unmap_single(&priv->ndev->dev, curr_bd->buff_ptr,
2117                                 curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE,
2118                                 DMA_FROM_DEVICE);
2119
2120                 curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
2121                 curr_pkt->num_bufs = 1;
2122                 curr_pkt->pkt_length =
2123                         (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
2124                 emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd, priv));
2125                 ++rxch->processed_bd;
2126                 last_bd = curr_bd;
2127                 curr_bd = last_bd->next;
2128                 rxch->active_queue_head = curr_bd;
2129
2130                 /* check if end of RX queue ? */
2131                 if (frame_status & EMAC_CPPI_EOQ_BIT) {
2132                         if (curr_bd) {
2133                                 ++rxch->mis_queued_packets;
2134                                 emac_write(EMAC_RXHDP(ch),
2135                                            emac_virt_to_phys(curr_bd, priv));
2136                         } else {
2137                                 ++rxch->end_of_queue;
2138                                 rxch->queue_active = 0;
2139                         }
2140                 }
2141
2142                 /* recycle BD */
2143                 emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer,
2144                                        new_buf_token);
2145
2146                 /* return the packet to the user - BD ptr passed in
2147                  * last parameter for potential *future* use */
2148                 spin_unlock_irqrestore(&priv->rx_lock, flags);
2149                 emac_net_rx_cb(priv, curr_pkt);
2150                 spin_lock_irqsave(&priv->rx_lock, flags);
2151                 curr_bd = rxch->active_queue_head;
2152                 if (curr_bd) {
2153                         BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
2154                         frame_status = curr_bd->mode;
2155                 }
2156                 ++pkts_processed;
2157         }
2158
2159 end_emac_rx_bdproc:
2160         spin_unlock_irqrestore(&priv->rx_lock, flags);
2161         return pkts_processed;
2162 }
2163
2164 /**
2165  * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
2166  * @priv: The DaVinci EMAC private adapter structure
2167  *
2168  * Enables EMAC hardware for packet processing - enables PHY, enables RX
2169  * for packet reception and enables device interrupts and then NAPI
2170  *
2171  * Returns success (0) or appropriate error code (none right now)
2172  */
2173 static int emac_hw_enable(struct emac_priv *priv)
2174 {
2175         u32 ch, val, mbp_enable, mac_control;
2176
2177         /* Soft reset */
2178         emac_write(EMAC_SOFTRESET, 1);
2179         while (emac_read(EMAC_SOFTRESET))
2180                 cpu_relax();
2181
2182         /* Disable interrupt & Set pacing for more interrupts initially */
2183         emac_int_disable(priv);
2184
2185         /* Full duplex enable bit set when auto negotiation happens */
2186         mac_control =
2187                 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
2188                 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
2189                 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
2190                 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
2191         emac_write(EMAC_MACCONTROL, mac_control);
2192
2193         mbp_enable =
2194                 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
2195                 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
2196                  ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
2197                  ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
2198                  ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
2199                  ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
2200                  ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
2201                  ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
2202                         EMAC_RXMBP_PROMCH_SHIFT) |
2203                  ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
2204                  ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
2205                         EMAC_RXMBP_BROADCH_SHIFT) |
2206                  ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
2207                  ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
2208                         EMAC_RXMBP_MULTICH_SHIFT));
2209         emac_write(EMAC_RXMBPENABLE, mbp_enable);
2210         emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
2211                                    EMAC_RX_MAX_LEN_MASK));
2212         emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
2213                                          EMAC_RX_BUFFER_OFFSET_MASK));
2214         emac_write(EMAC_RXFILTERLOWTHRESH, 0);
2215         emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
2216         priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
2217
2218         val = emac_read(EMAC_TXCONTROL);
2219         val |= EMAC_TX_CONTROL_TX_ENABLE_VAL;
2220         emac_write(EMAC_TXCONTROL, val);
2221         val = emac_read(EMAC_RXCONTROL);
2222         val |= EMAC_RX_CONTROL_RX_ENABLE_VAL;
2223         emac_write(EMAC_RXCONTROL, val);
2224         emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
2225
2226         for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) {
2227                 emac_write(EMAC_TXHDP(ch), 0);
2228                 emac_write(EMAC_TXINTMASKSET, BIT(ch));
2229         }
2230         for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) {
2231                 struct emac_rxch *rxch = priv->rxch[ch];
2232                 emac_setmac(priv, ch, rxch->mac_addr);
2233                 emac_write(EMAC_RXINTMASKSET, BIT(ch));
2234                 rxch->queue_active = 1;
2235                 emac_write(EMAC_RXHDP(ch),
2236                            emac_virt_to_phys(rxch->active_queue_head, priv));
2237         }
2238
2239         /* Enable MII */
2240         val = emac_read(EMAC_MACCONTROL);
2241         val |= (EMAC_MACCONTROL_GMIIEN);
2242         emac_write(EMAC_MACCONTROL, val);
2243
2244         /* Enable NAPI and interrupts */
2245         napi_enable(&priv->napi);
2246         emac_int_enable(priv);
2247         return 0;
2248
2249 }
2250
2251 /**
2252  * emac_poll: EMAC NAPI Poll function
2253  * @ndev: The DaVinci EMAC network adapter
2254  * @budget: Number of receive packets to process (as told by NAPI layer)
2255  *
2256  * NAPI Poll function implemented to process packets as per budget. We check
2257  * the type of interrupt on the device and accordingly call the TX or RX
2258  * packet processing functions. We follow the budget for RX processing and
2259  * also put a cap on number of TX pkts processed through config param. The
2260  * NAPI schedule function is called if more packets pending.
2261  *
2262  * Returns number of packets received (in most cases; else TX pkts - rarely)
2263  */
2264 static int emac_poll(struct napi_struct *napi, int budget)
2265 {
2266         unsigned int mask;
2267         struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
2268         struct net_device *ndev = priv->ndev;
2269         struct device *emac_dev = &ndev->dev;
2270         u32 status = 0;
2271         u32 num_tx_pkts = 0, num_rx_pkts = 0;
2272
2273         /* Check interrupt vectors and call packet processing */
2274         status = emac_read(EMAC_MACINVECTOR);
2275
2276         mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
2277
2278         if (priv->version == EMAC_VERSION_2)
2279                 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
2280
2281         if (status & mask) {
2282                 num_tx_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
2283                                           EMAC_DEF_TX_MAX_SERVICE);
2284         } /* TX processing */
2285
2286         mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
2287
2288         if (priv->version == EMAC_VERSION_2)
2289                 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
2290
2291         if (status & mask) {
2292                 num_rx_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, budget);
2293         } /* RX processing */
2294
2295         mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
2296         if (priv->version == EMAC_VERSION_2)
2297                 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
2298
2299         if (unlikely(status & mask)) {
2300                 u32 ch, cause;
2301                 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
2302                 netif_stop_queue(ndev);
2303                 napi_disable(&priv->napi);
2304
2305                 status = emac_read(EMAC_MACSTATUS);
2306                 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
2307                          EMAC_MACSTATUS_TXERRCODE_SHIFT);
2308                 if (cause) {
2309                         ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
2310                               EMAC_MACSTATUS_TXERRCH_SHIFT);
2311                         if (net_ratelimit()) {
2312                                 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
2313                                         &emac_txhost_errcodes[cause][0], ch);
2314                         }
2315                 }
2316                 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
2317                          EMAC_MACSTATUS_RXERRCODE_SHIFT);
2318                 if (cause) {
2319                         ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
2320                               EMAC_MACSTATUS_RXERRCH_SHIFT);
2321                         if (netif_msg_hw(priv) && net_ratelimit())
2322                                 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
2323                                         &emac_rxhost_errcodes[cause][0], ch);
2324                 }
2325         } else if (num_rx_pkts < budget) {
2326                 napi_complete(napi);
2327                 emac_int_enable(priv);
2328         }
2329
2330         return num_rx_pkts;
2331 }
2332
2333 #ifdef CONFIG_NET_POLL_CONTROLLER
2334 /**
2335  * emac_poll_controller: EMAC Poll controller function
2336  * @ndev: The DaVinci EMAC network adapter
2337  *
2338  * Polled functionality used by netconsole and others in non interrupt mode
2339  *
2340  */
2341 void emac_poll_controller(struct net_device *ndev)
2342 {
2343         struct emac_priv *priv = netdev_priv(ndev);
2344
2345         emac_int_disable(priv);
2346         emac_irq(ndev->irq, ndev);
2347         emac_int_enable(priv);
2348 }
2349 #endif
2350
2351 /* PHY/MII bus related */
2352
2353 /* Wait until mdio is ready for next command */
2354 #define MDIO_WAIT_FOR_USER_ACCESS\
2355                 while ((emac_mdio_read((MDIO_USERACCESS(0))) &\
2356                         MDIO_USERACCESS_GO) != 0)
2357
2358 static int emac_mii_read(struct mii_bus *bus, int phy_id, int phy_reg)
2359 {
2360         unsigned int phy_data = 0;
2361         unsigned int phy_control;
2362
2363         /* Wait until mdio is ready for next command */
2364         MDIO_WAIT_FOR_USER_ACCESS;
2365
2366         phy_control = (MDIO_USERACCESS_GO |
2367                        MDIO_USERACCESS_READ |
2368                        ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2369                        ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2370                        (phy_data & MDIO_USERACCESS_DATA));
2371         emac_mdio_write(MDIO_USERACCESS(0), phy_control);
2372
2373         /* Wait until mdio is ready for next command */
2374         MDIO_WAIT_FOR_USER_ACCESS;
2375
2376         return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA;
2377
2378 }
2379
2380 static int emac_mii_write(struct mii_bus *bus, int phy_id,
2381                           int phy_reg, u16 phy_data)
2382 {
2383
2384         unsigned int control;
2385
2386         /*  until mdio is ready for next command */
2387         MDIO_WAIT_FOR_USER_ACCESS;
2388
2389         control = (MDIO_USERACCESS_GO |
2390                    MDIO_USERACCESS_WRITE |
2391                    ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
2392                    ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
2393                    (phy_data & MDIO_USERACCESS_DATA));
2394         emac_mdio_write(MDIO_USERACCESS(0), control);
2395
2396         return 0;
2397 }
2398
2399 static int emac_mii_reset(struct mii_bus *bus)
2400 {
2401         unsigned int clk_div;
2402         int mdio_bus_freq = emac_bus_frequency;
2403
2404         if (mdio_max_freq && mdio_bus_freq)
2405                 clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
2406         else
2407                 clk_div = 0xFF;
2408
2409         clk_div &= MDIO_CONTROL_CLKDIV;
2410
2411         /* Set enable and clock divider in MDIOControl */
2412         emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE));
2413
2414         return 0;
2415
2416 }
2417
2418 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, PHY_POLL };
2419
2420 /* emac_driver: EMAC MII bus structure */
2421
2422 static struct mii_bus *emac_mii;
2423
2424 static void emac_adjust_link(struct net_device *ndev)
2425 {
2426         struct emac_priv *priv = netdev_priv(ndev);
2427         struct phy_device *phydev = priv->phydev;
2428         unsigned long flags;
2429         int new_state = 0;
2430
2431         spin_lock_irqsave(&priv->lock, flags);
2432
2433         if (phydev->link) {
2434                 /* check the mode of operation - full/half duplex */
2435                 if (phydev->duplex != priv->duplex) {
2436                         new_state = 1;
2437                         priv->duplex = phydev->duplex;
2438                 }
2439                 if (phydev->speed != priv->speed) {
2440                         new_state = 1;
2441                         priv->speed = phydev->speed;
2442                 }
2443                 if (!priv->link) {
2444                         new_state = 1;
2445                         priv->link = 1;
2446                 }
2447
2448         } else if (priv->link) {
2449                 new_state = 1;
2450                 priv->link = 0;
2451                 priv->speed = 0;
2452                 priv->duplex = ~0;
2453         }
2454         if (new_state) {
2455                 emac_update_phystatus(priv);
2456                 phy_print_status(priv->phydev);
2457         }
2458
2459         spin_unlock_irqrestore(&priv->lock, flags);
2460 }
2461
2462 /*************************************************************************
2463  *  Linux Driver Model
2464  *************************************************************************/
2465
2466 /**
2467  * emac_devioctl: EMAC adapter ioctl
2468  * @ndev: The DaVinci EMAC network adapter
2469  * @ifrq: request parameter
2470  * @cmd: command parameter
2471  *
2472  * EMAC driver ioctl function
2473  *
2474  * Returns success(0) or appropriate error code
2475  */
2476 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
2477 {
2478         dev_warn(&ndev->dev, "DaVinci EMAC: ioctl not supported\n");
2479
2480         if (!(netif_running(ndev)))
2481                 return -EINVAL;
2482
2483         /* TODO: Add phy read and write and private statistics get feature */
2484
2485         return -EOPNOTSUPP;
2486 }
2487
2488 /**
2489  * emac_dev_open: EMAC device open
2490  * @ndev: The DaVinci EMAC network adapter
2491  *
2492  * Called when system wants to start the interface. We init TX/RX channels
2493  * and enable the hardware for packet reception/transmission and start the
2494  * network queue.
2495  *
2496  * Returns 0 for a successful open, or appropriate error code
2497  */
2498 static int emac_dev_open(struct net_device *ndev)
2499 {
2500         struct device *emac_dev = &ndev->dev;
2501         u32 rc, cnt, ch;
2502         int phy_addr;
2503         struct resource *res;
2504         int q, m;
2505         int i = 0;
2506         int k = 0;
2507         struct emac_priv *priv = netdev_priv(ndev);
2508
2509         netif_carrier_off(ndev);
2510         for (cnt = 0; cnt < ETH_ALEN; cnt++)
2511                 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
2512
2513         /* Configuration items */
2514         priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
2515
2516         /* Clear basic hardware */
2517         for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) {
2518                 emac_write(EMAC_TXHDP(ch), 0);
2519                 emac_write(EMAC_RXHDP(ch), 0);
2520                 emac_write(EMAC_RXHDP(ch), 0);
2521                 emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2522                 emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
2523         }
2524         priv->mac_hash1 = 0;
2525         priv->mac_hash2 = 0;
2526         emac_write(EMAC_MACHASH1, 0);
2527         emac_write(EMAC_MACHASH2, 0);
2528
2529         /* multi ch not supported - open 1 TX, 1RX ch by default */
2530         rc = emac_init_txch(priv, EMAC_DEF_TX_CH);
2531         if (0 != rc) {
2532                 dev_err(emac_dev, "DaVinci EMAC: emac_init_txch() failed");
2533                 return rc;
2534         }
2535         rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr);
2536         if (0 != rc) {
2537                 dev_err(emac_dev, "DaVinci EMAC: emac_init_rxch() failed");
2538                 return rc;
2539         }
2540
2541         /* Request IRQ */
2542
2543         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2544                 for (i = res->start; i <= res->end; i++) {
2545                         if (request_irq(i, emac_irq, IRQF_DISABLED,
2546                                         ndev->name, ndev))
2547                                 goto rollback;
2548                 }
2549                 k++;
2550         }
2551
2552         /* Start/Enable EMAC hardware */
2553         emac_hw_enable(priv);
2554
2555         /* Enable Interrupt pacing if configured */
2556         if (priv->coal_intvl != 0) {
2557                 struct ethtool_coalesce coal;
2558
2559                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
2560                 emac_set_coalesce(ndev, &coal);
2561         }
2562
2563         /* find the first phy */
2564         priv->phydev = NULL;
2565         if (priv->phy_mask) {
2566                 emac_mii_reset(priv->mii_bus);
2567                 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
2568                         if (priv->mii_bus->phy_map[phy_addr]) {
2569                                 priv->phydev = priv->mii_bus->phy_map[phy_addr];
2570                                 break;
2571                         }
2572                 }
2573
2574                 if (!priv->phydev) {
2575                         printk(KERN_ERR "%s: no PHY found\n", ndev->name);
2576                         return -1;
2577                 }
2578
2579                 priv->phydev = phy_connect(ndev, dev_name(&priv->phydev->dev),
2580                                 &emac_adjust_link, 0, PHY_INTERFACE_MODE_MII);
2581
2582                 if (IS_ERR(priv->phydev)) {
2583                         printk(KERN_ERR "%s: Could not attach to PHY\n",
2584                                                                 ndev->name);
2585                         return PTR_ERR(priv->phydev);
2586                 }
2587
2588                 priv->link = 0;
2589                 priv->speed = 0;
2590                 priv->duplex = ~0;
2591
2592                 printk(KERN_INFO "%s: attached PHY driver [%s] "
2593                         "(mii_bus:phy_addr=%s, id=%x)\n", ndev->name,
2594                         priv->phydev->drv->name, dev_name(&priv->phydev->dev),
2595                         priv->phydev->phy_id);
2596         } else{
2597                 /* No PHY , fix the link, speed and duplex settings */
2598                 priv->link = 1;
2599                 priv->speed = SPEED_100;
2600                 priv->duplex = DUPLEX_FULL;
2601                 emac_update_phystatus(priv);
2602         }
2603
2604         if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
2605                 emac_dump_regs(priv);
2606
2607         if (netif_msg_drv(priv))
2608                 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
2609
2610         if (priv->phy_mask)
2611                 phy_start(priv->phydev);
2612
2613         return 0;
2614
2615 rollback:
2616
2617         dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
2618
2619         for (q = k; k >= 0; k--) {
2620                 for (m = i; m >= res->start; m--)
2621                         free_irq(m, ndev);
2622                 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
2623                 m = res->end;
2624         }
2625         return -EBUSY;
2626 }
2627
2628 /**
2629  * emac_dev_stop: EMAC device stop
2630  * @ndev: The DaVinci EMAC network adapter
2631  *
2632  * Called when system wants to stop or down the interface. We stop the network
2633  * queue, disable interrupts and cleanup TX/RX channels.
2634  *
2635  * We return the statistics in net_device_stats structure pulled from emac
2636  */
2637 static int emac_dev_stop(struct net_device *ndev)
2638 {
2639         struct resource *res;
2640         int i = 0;
2641         int irq_num;
2642         struct emac_priv *priv = netdev_priv(ndev);
2643         struct device *emac_dev = &ndev->dev;
2644
2645         /* inform the upper layers. */
2646         netif_stop_queue(ndev);
2647         napi_disable(&priv->napi);
2648
2649         netif_carrier_off(ndev);
2650         emac_int_disable(priv);
2651         emac_stop_txch(priv, EMAC_DEF_TX_CH);
2652         emac_stop_rxch(priv, EMAC_DEF_RX_CH);
2653         emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
2654         emac_cleanup_rxch(priv, EMAC_DEF_RX_CH);
2655         emac_write(EMAC_SOFTRESET, 1);
2656
2657         if (priv->phydev)
2658                 phy_disconnect(priv->phydev);
2659
2660         /* Free IRQ */
2661         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
2662                 for (irq_num = res->start; irq_num <= res->end; irq_num++)
2663                         free_irq(irq_num, priv->ndev);
2664                 i++;
2665         }
2666
2667         if (netif_msg_drv(priv))
2668                 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
2669
2670         return 0;
2671 }
2672
2673 /**
2674  * emac_dev_getnetstats: EMAC get statistics function
2675  * @ndev: The DaVinci EMAC network adapter
2676  *
2677  * Called when system wants to get statistics from the device.
2678  *
2679  * We return the statistics in net_device_stats structure pulled from emac
2680  */
2681 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
2682 {
2683         struct emac_priv *priv = netdev_priv(ndev);
2684         u32 mac_control;
2685         u32 stats_clear_mask;
2686
2687         /* update emac hardware stats and reset the registers*/
2688
2689         mac_control = emac_read(EMAC_MACCONTROL);
2690
2691         if (mac_control & EMAC_MACCONTROL_GMIIEN)
2692                 stats_clear_mask = EMAC_STATS_CLR_MASK;
2693         else
2694                 stats_clear_mask = 0;
2695
2696         ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
2697         emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
2698
2699         ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
2700                                            emac_read(EMAC_TXSINGLECOLL) +
2701                                            emac_read(EMAC_TXMULTICOLL));
2702         emac_write(EMAC_TXCOLLISION, stats_clear_mask);
2703         emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
2704         emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
2705
2706         ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
2707                                                 emac_read(EMAC_RXJABBER) +
2708                                                 emac_read(EMAC_RXUNDERSIZED));
2709         emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
2710         emac_write(EMAC_RXJABBER, stats_clear_mask);
2711         emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
2712
2713         ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
2714                                                emac_read(EMAC_RXMOFOVERRUNS));
2715         emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
2716         emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
2717
2718         ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
2719         emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
2720
2721         ndev->stats.tx_carrier_errors +=
2722                 emac_read(EMAC_TXCARRIERSENSE);
2723         emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
2724
2725         ndev->stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
2726         emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
2727
2728         return &ndev->stats;
2729 }
2730
2731 static const struct net_device_ops emac_netdev_ops = {
2732         .ndo_open               = emac_dev_open,
2733         .ndo_stop               = emac_dev_stop,
2734         .ndo_start_xmit         = emac_dev_xmit,
2735         .ndo_set_multicast_list = emac_dev_mcast_set,
2736         .ndo_set_mac_address    = emac_dev_setmac_addr,
2737         .ndo_do_ioctl           = emac_devioctl,
2738         .ndo_tx_timeout         = emac_dev_tx_timeout,
2739         .ndo_get_stats          = emac_dev_getnetstats,
2740 #ifdef CONFIG_NET_POLL_CONTROLLER
2741         .ndo_poll_controller    = emac_poll_controller,
2742 #endif
2743 };
2744
2745 /**
2746  * davinci_emac_probe: EMAC device probe
2747  * @pdev: The DaVinci EMAC device that we are removing
2748  *
2749  * Called when probing for emac devicesr. We get details of instances and
2750  * resource information from platform init and register a network device
2751  * and allocate resources necessary for driver to perform
2752  */
2753 static int __devinit davinci_emac_probe(struct platform_device *pdev)
2754 {
2755         int rc = 0;
2756         struct resource *res;
2757         struct net_device *ndev;
2758         struct emac_priv *priv;
2759         unsigned long size;
2760         struct emac_platform_data *pdata;
2761         struct device *emac_dev;
2762
2763         /* obtain emac clock from kernel */
2764         emac_clk = clk_get(&pdev->dev, NULL);
2765         if (IS_ERR(emac_clk)) {
2766                 printk(KERN_ERR "DaVinci EMAC: Failed to get EMAC clock\n");
2767                 return -EBUSY;
2768         }
2769         emac_bus_frequency = clk_get_rate(emac_clk);
2770         /* TODO: Probe PHY here if possible */
2771
2772         ndev = alloc_etherdev(sizeof(struct emac_priv));
2773         if (!ndev) {
2774                 printk(KERN_ERR "DaVinci EMAC: Error allocating net_device\n");
2775                 clk_put(emac_clk);
2776                 return -ENOMEM;
2777         }
2778
2779         platform_set_drvdata(pdev, ndev);
2780         priv = netdev_priv(ndev);
2781         priv->pdev = pdev;
2782         priv->ndev = ndev;
2783         priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
2784
2785         spin_lock_init(&priv->tx_lock);
2786         spin_lock_init(&priv->rx_lock);
2787         spin_lock_init(&priv->lock);
2788
2789         pdata = pdev->dev.platform_data;
2790         if (!pdata) {
2791                 printk(KERN_ERR "DaVinci EMAC: No platform data\n");
2792                 return -ENODEV;
2793         }
2794
2795         /* MAC addr and PHY mask , RMII enable info from platform_data */
2796         memcpy(priv->mac_addr, pdata->mac_addr, 6);
2797         priv->phy_mask = pdata->phy_mask;
2798         priv->rmii_en = pdata->rmii_en;
2799         priv->version = pdata->version;
2800         priv->int_enable = pdata->interrupt_enable;
2801         priv->int_disable = pdata->interrupt_disable;
2802
2803         priv->coal_intvl = 0;
2804         priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
2805
2806         emac_dev = &ndev->dev;
2807         /* Get EMAC platform data */
2808         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2809         if (!res) {
2810                 dev_err(emac_dev, "DaVinci EMAC: Error getting res\n");
2811                 rc = -ENOENT;
2812                 goto probe_quit;
2813         }
2814
2815         priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
2816         size = res->end - res->start + 1;
2817         if (!request_mem_region(res->start, size, ndev->name)) {
2818                 dev_err(emac_dev, "DaVinci EMAC: failed request_mem_region() for regs\n");
2819                 rc = -ENXIO;
2820                 goto probe_quit;
2821         }
2822
2823         priv->remap_addr = ioremap(res->start, size);
2824         if (!priv->remap_addr) {
2825                 dev_err(emac_dev, "Unable to map IO\n");
2826                 rc = -ENOMEM;
2827                 release_mem_region(res->start, size);
2828                 goto probe_quit;
2829         }
2830         priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
2831         ndev->base_addr = (unsigned long)priv->remap_addr;
2832
2833         priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
2834         priv->ctrl_ram_size = pdata->ctrl_ram_size;
2835         priv->emac_ctrl_ram = priv->remap_addr + pdata->ctrl_ram_offset;
2836
2837         if (pdata->hw_ram_addr)
2838                 priv->hw_ram_addr = pdata->hw_ram_addr;
2839         else
2840                 priv->hw_ram_addr = (u32 __force)res->start +
2841                                         pdata->ctrl_ram_offset;
2842
2843         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2844         if (!res) {
2845                 dev_err(emac_dev, "DaVinci EMAC: Error getting irq res\n");
2846                 rc = -ENOENT;
2847                 goto no_irq_res;
2848         }
2849         ndev->irq = res->start;
2850
2851         if (!is_valid_ether_addr(priv->mac_addr)) {
2852                 /* Use random MAC if none passed */
2853                 random_ether_addr(priv->mac_addr);
2854                 printk(KERN_WARNING "%s: using random MAC addr: %pM\n",
2855                                 __func__, priv->mac_addr);
2856         }
2857
2858         ndev->netdev_ops = &emac_netdev_ops;
2859         SET_ETHTOOL_OPS(ndev, &ethtool_ops);
2860         netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
2861
2862         clk_enable(emac_clk);
2863
2864         /* register the network device */
2865         SET_NETDEV_DEV(ndev, &pdev->dev);
2866         rc = register_netdev(ndev);
2867         if (rc) {
2868                 dev_err(emac_dev, "DaVinci EMAC: Error in register_netdev\n");
2869                 rc = -ENODEV;
2870                 goto netdev_reg_err;
2871         }
2872
2873
2874         /* MII/Phy intialisation, mdio bus registration */
2875         emac_mii = mdiobus_alloc();
2876         if (emac_mii == NULL) {
2877                 dev_err(emac_dev, "DaVinci EMAC: Error allocating mii_bus\n");
2878                 rc = -ENOMEM;
2879                 goto mdio_alloc_err;
2880         }
2881
2882         priv->mii_bus = emac_mii;
2883         emac_mii->name  = "emac-mii",
2884         emac_mii->read  = emac_mii_read,
2885         emac_mii->write = emac_mii_write,
2886         emac_mii->reset = emac_mii_reset,
2887         emac_mii->irq   = mii_irqs,
2888         emac_mii->phy_mask = ~(priv->phy_mask);
2889         emac_mii->parent = &pdev->dev;
2890         emac_mii->priv = priv->remap_addr + pdata->mdio_reg_offset;
2891         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", priv->pdev->id);
2892         mdio_max_freq = pdata->mdio_max_freq;
2893         emac_mii->reset(emac_mii);
2894
2895         /* Register the MII bus */
2896         rc = mdiobus_register(emac_mii);
2897         if (rc)
2898                 goto mdiobus_quit;
2899
2900         if (netif_msg_probe(priv)) {
2901                 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
2902                            "(regs: %p, irq: %d)\n",
2903                            (void *)priv->emac_base_phys, ndev->irq);
2904         }
2905         return 0;
2906
2907 mdiobus_quit:
2908         mdiobus_free(emac_mii);
2909
2910 netdev_reg_err:
2911 mdio_alloc_err:
2912         clk_disable(emac_clk);
2913 no_irq_res:
2914         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2915         release_mem_region(res->start, res->end - res->start + 1);
2916         iounmap(priv->remap_addr);
2917
2918 probe_quit:
2919         clk_put(emac_clk);
2920         free_netdev(ndev);
2921         return rc;
2922 }
2923
2924 /**
2925  * davinci_emac_remove: EMAC device remove
2926  * @pdev: The DaVinci EMAC device that we are removing
2927  *
2928  * Called when removing the device driver. We disable clock usage and release
2929  * the resources taken up by the driver and unregister network device
2930  */
2931 static int __devexit davinci_emac_remove(struct platform_device *pdev)
2932 {
2933         struct resource *res;
2934         struct net_device *ndev = platform_get_drvdata(pdev);
2935         struct emac_priv *priv = netdev_priv(ndev);
2936
2937         dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2938
2939         platform_set_drvdata(pdev, NULL);
2940         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2941         mdiobus_unregister(priv->mii_bus);
2942         mdiobus_free(priv->mii_bus);
2943
2944         release_mem_region(res->start, res->end - res->start + 1);
2945
2946         unregister_netdev(ndev);
2947         iounmap(priv->remap_addr);
2948         free_netdev(ndev);
2949
2950         clk_disable(emac_clk);
2951         clk_put(emac_clk);
2952
2953         return 0;
2954 }
2955
2956 static int davinci_emac_suspend(struct device *dev)
2957 {
2958         struct platform_device *pdev = to_platform_device(dev);
2959         struct net_device *ndev = platform_get_drvdata(pdev);
2960
2961         if (netif_running(ndev))
2962                 emac_dev_stop(ndev);
2963
2964         clk_disable(emac_clk);
2965
2966         return 0;
2967 }
2968
2969 static int davinci_emac_resume(struct device *dev)
2970 {
2971         struct platform_device *pdev = to_platform_device(dev);
2972         struct net_device *ndev = platform_get_drvdata(pdev);
2973
2974         clk_enable(emac_clk);
2975
2976         if (netif_running(ndev))
2977                 emac_dev_open(ndev);
2978
2979         return 0;
2980 }
2981
2982 static const struct dev_pm_ops davinci_emac_pm_ops = {
2983         .suspend        = davinci_emac_suspend,
2984         .resume         = davinci_emac_resume,
2985 };
2986
2987 /**
2988  * davinci_emac_driver: EMAC platform driver structure
2989  */
2990 static struct platform_driver davinci_emac_driver = {
2991         .driver = {
2992                 .name    = "davinci_emac",
2993                 .owner   = THIS_MODULE,
2994                 .pm      = &davinci_emac_pm_ops,
2995         },
2996         .probe = davinci_emac_probe,
2997         .remove = __devexit_p(davinci_emac_remove),
2998 };
2999
3000 /**
3001  * davinci_emac_init: EMAC driver module init
3002  *
3003  * Called when initializing the driver. We register the driver with
3004  * the platform.
3005  */
3006 static int __init davinci_emac_init(void)
3007 {
3008         return platform_driver_register(&davinci_emac_driver);
3009 }
3010 late_initcall(davinci_emac_init);
3011
3012 /**
3013  * davinci_emac_exit: EMAC driver module exit
3014  *
3015  * Called when exiting the driver completely. We unregister the driver with
3016  * the platform and exit
3017  */
3018 static void __exit davinci_emac_exit(void)
3019 {
3020         platform_driver_unregister(&davinci_emac_driver);
3021 }
3022 module_exit(davinci_emac_exit);
3023
3024 MODULE_LICENSE("GPL");
3025 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
3026 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
3027 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");