1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 /* General customization:
36 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
38 #define DRIVER_NAME "i915"
39 #define DRIVER_DESC "Intel Graphics"
40 #define DRIVER_DATE "20060119"
45 * 1.2: Add Power Management
46 * 1.3: Add vblank support
47 * 1.4: Fix cmdbuffer path, add heap destroy
48 * 1.5: Add vblank pipe configuration
49 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
50 * - Support vertical blank on secondary display pipe
52 #define DRIVER_MAJOR 1
53 #define DRIVER_MINOR 6
54 #define DRIVER_PATCHLEVEL 0
56 typedef struct _drm_i915_ring_buffer
{
66 } drm_i915_ring_buffer_t
;
69 struct mem_block
*next
;
70 struct mem_block
*prev
;
73 DRMFILE filp
; /* 0: free, -1: heap, other: real files */
76 typedef struct _drm_i915_vbl_swap
{
77 struct list_head head
;
78 drm_drawable_t drw_id
;
80 unsigned int sequence
;
81 } drm_i915_vbl_swap_t
;
83 typedef struct drm_i915_private
{
84 drm_local_map_t
*sarea
;
85 drm_local_map_t
*mmio_map
;
87 drm_i915_sarea_t
*sarea_priv
;
88 drm_i915_ring_buffer_t ring
;
90 drm_dma_handle_t
*status_page_dmah
;
92 dma_addr_t dma_status_page
;
93 unsigned long counter
;
100 int use_mi_batchbuffer_start
;
102 wait_queue_head_t irq_queue
;
103 atomic_t irq_received
;
104 atomic_t irq_emitted
;
106 int tex_lru_log_granularity
;
107 int allow_batchbuffer
;
108 struct mem_block
*agp_heap
;
109 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
112 spinlock_t swaps_lock
;
113 drm_i915_vbl_swap_t vbl_swaps
;
114 unsigned int swaps_pending
;
115 } drm_i915_private_t
;
117 extern drm_ioctl_desc_t i915_ioctls
[];
118 extern int i915_max_ioctl
;
121 extern void i915_kernel_lost_context(drm_device_t
* dev
);
122 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
123 extern void i915_driver_lastclose(drm_device_t
* dev
);
124 extern void i915_driver_preclose(drm_device_t
* dev
, DRMFILE filp
);
125 extern int i915_driver_device_is_agp(drm_device_t
* dev
);
126 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
130 extern int i915_irq_emit(DRM_IOCTL_ARGS
);
131 extern int i915_irq_wait(DRM_IOCTL_ARGS
);
133 extern int i915_driver_vblank_wait(drm_device_t
*dev
, unsigned int *sequence
);
134 extern int i915_driver_vblank_wait2(drm_device_t
*dev
, unsigned int *sequence
);
135 extern irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
);
136 extern void i915_driver_irq_preinstall(drm_device_t
* dev
);
137 extern void i915_driver_irq_postinstall(drm_device_t
* dev
);
138 extern void i915_driver_irq_uninstall(drm_device_t
* dev
);
139 extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS
);
140 extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS
);
141 extern int i915_vblank_swap(DRM_IOCTL_ARGS
);
144 extern int i915_mem_alloc(DRM_IOCTL_ARGS
);
145 extern int i915_mem_free(DRM_IOCTL_ARGS
);
146 extern int i915_mem_init_heap(DRM_IOCTL_ARGS
);
147 extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS
);
148 extern void i915_mem_takedown(struct mem_block
**heap
);
149 extern void i915_mem_release(drm_device_t
* dev
,
150 DRMFILE filp
, struct mem_block
*heap
);
152 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
153 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
154 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
155 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
157 #define I915_VERBOSE 0
159 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
162 #define BEGIN_LP_RING(n) do { \
164 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \
165 (n), __FUNCTION__); \
166 if (dev_priv->ring.space < (n)*4) \
167 i915_wait_ring(dev, (n)*4, __FUNCTION__); \
169 outring = dev_priv->ring.tail; \
170 ringmask = dev_priv->ring.tail_mask; \
171 virt = dev_priv->ring.virtual_start; \
174 #define OUT_RING(n) do { \
175 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
176 *(volatile unsigned int *)(virt + outring) = (n); \
179 outring &= ringmask; \
182 #define ADVANCE_LP_RING() do { \
183 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
184 dev_priv->ring.tail = outring; \
185 dev_priv->ring.space -= outcount * 4; \
186 I915_WRITE(LP_RING + RING_TAIL, outring); \
189 extern int i915_wait_ring(drm_device_t
* dev
, int n
, const char *caller
);
191 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
192 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
193 #define CMD_REPORT_HEAD (7<<23)
194 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
195 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
197 #define INST_PARSER_CLIENT 0x00000000
198 #define INST_OP_FLUSH 0x02000000
199 #define INST_FLUSH_MAP_CACHE 0x00000001
201 #define BB1_START_ADDR_MASK (~0x7)
202 #define BB1_PROTECTED (1<<0)
203 #define BB1_UNPROTECTED (0<<0)
204 #define BB2_END_ADDR_MASK (~0x7)
206 #define I915REG_HWSTAM 0x02098
207 #define I915REG_INT_IDENTITY_R 0x020a4
208 #define I915REG_INT_MASK_R 0x020a8
209 #define I915REG_INT_ENABLE_R 0x020a0
211 #define SRX_INDEX 0x3c4
212 #define SRX_DATA 0x3c5
214 #define SR01_SCREEN_OFF (1<<5)
217 #define PPCR_ON (1<<0)
220 #define DVOB_ON (1<<31)
222 #define DVOC_ON (1<<31)
224 #define LVDS_ON (1<<31)
227 #define ADPA_DPMS_MASK (~(3<<10))
228 #define ADPA_DPMS_ON (0<<10)
229 #define ADPA_DPMS_SUSPEND (1<<10)
230 #define ADPA_DPMS_STANDBY (2<<10)
231 #define ADPA_DPMS_OFF (3<<10)
234 #define LP_RING 0x2030
235 #define HP_RING 0x2040
236 #define RING_TAIL 0x00
237 #define TAIL_ADDR 0x001FFFF8
238 #define RING_HEAD 0x04
239 #define HEAD_WRAP_COUNT 0xFFE00000
240 #define HEAD_WRAP_ONE 0x00200000
241 #define HEAD_ADDR 0x001FFFFC
242 #define RING_START 0x08
243 #define START_ADDR 0x0xFFFFF000
244 #define RING_LEN 0x0C
245 #define RING_NR_PAGES 0x001FF000
246 #define RING_REPORT_MASK 0x00000006
247 #define RING_REPORT_64K 0x00000002
248 #define RING_REPORT_128K 0x00000004
249 #define RING_NO_REPORT 0x00000000
250 #define RING_VALID_MASK 0x00000001
251 #define RING_VALID 0x00000001
252 #define RING_INVALID 0x00000000
254 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
255 #define SC_UPDATE_SCISSOR (0x1<<1)
256 #define SC_ENABLE_MASK (0x1<<0)
257 #define SC_ENABLE (0x1<<0)
259 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
260 #define SCI_YMIN_MASK (0xffff<<16)
261 #define SCI_XMIN_MASK (0xffff<<0)
262 #define SCI_YMAX_MASK (0xffff<<16)
263 #define SCI_XMAX_MASK (0xffff<<0)
265 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
266 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
267 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
268 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
269 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
270 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
271 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
273 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
275 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
276 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
277 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
279 #define MI_BATCH_BUFFER ((0x30<<23)|1)
280 #define MI_BATCH_BUFFER_START (0x31<<23)
281 #define MI_BATCH_BUFFER_END (0xA<<23)
282 #define MI_BATCH_NON_SECURE (1)
284 #define MI_WAIT_FOR_EVENT ((0x3<<23))
285 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
286 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
288 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
290 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
291 #define ASYNC_FLIP (1<<22)
293 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
295 #define READ_BREADCRUMB(dev_priv) (((u32 *)(dev_priv->hw_status_page))[5])