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Linux 2.6.20.7
[linux/fpc-iii.git] / drivers / char / synclink_gt.c
blob792c79c315e00292abc21e7febea957c171506c0
1 /*
2 * $Id: synclink_gt.c,v 4.36 2006/08/28 20:47:14 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink GT serial adapters.
5 *
6 * written by Paul Fulghum for Microgate Corporation
7 * paulkf@microgate.com
8 *
9 * Microgate and SyncLink are trademarks of Microgate Corporation
10 *
11 * This code is released under the GNU General Public License (GPL)
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
17 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
23 * OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26 /*
27 * DEBUG OUTPUT DEFINITIONS
28 *
29 * uncomment lines below to enable specific types of debug output
30 *
31 * DBGINFO information - most verbose output
32 * DBGERR serious errors
33 * DBGBH bottom half service routine debugging
34 * DBGISR interrupt service routine debugging
35 * DBGDATA output receive and transmit data
36 * DBGTBUF output transmit DMA buffers and registers
37 * DBGRBUF output receive DMA buffers and registers
38 */
39
40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
45 //#define DBGTBUF(info) dump_tbufs(info)
46 //#define DBGRBUF(info) dump_rbufs(info)
47
48
49 #include <linux/module.h>
50 #include <linux/version.h>
51 #include <linux/errno.h>
52 #include <linux/signal.h>
53 #include <linux/sched.h>
54 #include <linux/timer.h>
55 #include <linux/interrupt.h>
56 #include <linux/pci.h>
57 #include <linux/tty.h>
58 #include <linux/tty_flip.h>
59 #include <linux/serial.h>
60 #include <linux/major.h>
61 #include <linux/string.h>
62 #include <linux/fcntl.h>
63 #include <linux/ptrace.h>
64 #include <linux/ioport.h>
65 #include <linux/mm.h>
66 #include <linux/slab.h>
67 #include <linux/netdevice.h>
68 #include <linux/vmalloc.h>
69 #include <linux/init.h>
70 #include <linux/delay.h>
71 #include <linux/ioctl.h>
72 #include <linux/termios.h>
73 #include <linux/bitops.h>
74 #include <linux/workqueue.h>
75 #include <linux/hdlc.h>
76
77 #include <asm/system.h>
78 #include <asm/io.h>
79 #include <asm/irq.h>
80 #include <asm/dma.h>
81 #include <asm/types.h>
82 #include <asm/uaccess.h>
83
84 #include "linux/synclink.h"
85
86 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
87 #define SYNCLINK_GENERIC_HDLC 1
88 #else
89 #define SYNCLINK_GENERIC_HDLC 0
90 #endif
91
92 /*
93 * module identification
94 */
95 static char *driver_name = "SyncLink GT";
96 static char *driver_version = "$Revision: 4.36 $";
97 static char *tty_driver_name = "synclink_gt";
98 static char *tty_dev_prefix = "ttySLG";
99 MODULE_LICENSE("GPL");
100 #define MGSL_MAGIC 0x5401
101 #define MAX_DEVICES 32
102
103 static struct pci_device_id pci_table[] = {
104 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
105 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
106 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
107 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
108 {0,}, /* terminate list */
109 };
110 MODULE_DEVICE_TABLE(pci, pci_table);
111
112 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
113 static void remove_one(struct pci_dev *dev);
114 static struct pci_driver pci_driver = {
115 .name = "synclink_gt",
116 .id_table = pci_table,
117 .probe = init_one,
118 .remove = __devexit_p(remove_one),
119 };
120
121 static int pci_registered;
122
123 /*
124 * module configuration and status
125 */
126 static struct slgt_info *slgt_device_list;
127 static int slgt_device_count;
128
129 static int ttymajor;
130 static int debug_level;
131 static int maxframe[MAX_DEVICES];
132 static int dosyncppp[MAX_DEVICES];
133
134 module_param(ttymajor, int, 0);
135 module_param(debug_level, int, 0);
136 module_param_array(maxframe, int, NULL, 0);
137 module_param_array(dosyncppp, int, NULL, 0);
138
139 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
140 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
141 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
142 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
143
144 /*
145 * tty support and callbacks
146 */
147 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
148
149 static struct tty_driver *serial_driver;
150
151 static int open(struct tty_struct *tty, struct file * filp);
152 static void close(struct tty_struct *tty, struct file * filp);
153 static void hangup(struct tty_struct *tty);
154 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
155
156 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
157 static void put_char(struct tty_struct *tty, unsigned char ch);
158 static void send_xchar(struct tty_struct *tty, char ch);
159 static void wait_until_sent(struct tty_struct *tty, int timeout);
160 static int write_room(struct tty_struct *tty);
161 static void flush_chars(struct tty_struct *tty);
162 static void flush_buffer(struct tty_struct *tty);
163 static void tx_hold(struct tty_struct *tty);
164 static void tx_release(struct tty_struct *tty);
165
166 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
167 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
168 static int chars_in_buffer(struct tty_struct *tty);
169 static void throttle(struct tty_struct * tty);
170 static void unthrottle(struct tty_struct * tty);
171 static void set_break(struct tty_struct *tty, int break_state);
172
173 /*
174 * generic HDLC support and callbacks
175 */
176 #if SYNCLINK_GENERIC_HDLC
177 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
178 static void hdlcdev_tx_done(struct slgt_info *info);
179 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
180 static int hdlcdev_init(struct slgt_info *info);
181 static void hdlcdev_exit(struct slgt_info *info);
182 #endif
183
184
185 /*
186 * device specific structures, macros and functions
187 */
188
189 #define SLGT_MAX_PORTS 4
190 #define SLGT_REG_SIZE 256
191
192 /*
193 * conditional wait facility
194 */
195 struct cond_wait {
196 struct cond_wait *next;
197 wait_queue_head_t q;
198 wait_queue_t wait;
199 unsigned int data;
200 };
201 static void init_cond_wait(struct cond_wait *w, unsigned int data);
202 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
203 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
204 static void flush_cond_wait(struct cond_wait **head);
205
206 /*
207 * DMA buffer descriptor and access macros
208 */
209 struct slgt_desc
210 {
211 unsigned short count;
212 unsigned short status;
213 unsigned int pbuf; /* physical address of data buffer */
214 unsigned int next; /* physical address of next descriptor */
215
216 /* driver book keeping */
217 char *buf; /* virtual address of data buffer */
218 unsigned int pdesc; /* physical address of this descriptor */
219 dma_addr_t buf_dma_addr;
220 };
221
222 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
223 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
224 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
225 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
226 #define desc_count(a) (le16_to_cpu((a).count))
227 #define desc_status(a) (le16_to_cpu((a).status))
228 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
229 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
230 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
231 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
232 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
233
234 struct _input_signal_events {
235 int ri_up;
236 int ri_down;
237 int dsr_up;
238 int dsr_down;
239 int dcd_up;
240 int dcd_down;
241 int cts_up;
242 int cts_down;
243 };
244
245 /*
246 * device instance data structure
247 */
248 struct slgt_info {
249 void *if_ptr; /* General purpose pointer (used by SPPP) */
250
251 struct slgt_info *next_device; /* device list link */
252
253 int magic;
254 int flags;
255
256 char device_name[25];
257 struct pci_dev *pdev;
258
259 int port_count; /* count of ports on adapter */
260 int adapter_num; /* adapter instance number */
261 int port_num; /* port instance number */
262
263 /* array of pointers to port contexts on this adapter */
264 struct slgt_info *port_array[SLGT_MAX_PORTS];
265
266 int count; /* count of opens */
267 int line; /* tty line instance number */
268 unsigned short close_delay;
269 unsigned short closing_wait; /* time to wait before closing */
270
271 struct mgsl_icount icount;
272
273 struct tty_struct *tty;
274 int timeout;
275 int x_char; /* xon/xoff character */
276 int blocked_open; /* # of blocked opens */
277 unsigned int read_status_mask;
278 unsigned int ignore_status_mask;
279
280 wait_queue_head_t open_wait;
281 wait_queue_head_t close_wait;
282
283 wait_queue_head_t status_event_wait_q;
284 wait_queue_head_t event_wait_q;
285 struct timer_list tx_timer;
286 struct timer_list rx_timer;
287
288 unsigned int gpio_present;
289 struct cond_wait *gpio_wait_q;
290
291 spinlock_t lock; /* spinlock for synchronizing with ISR */
292
293 struct work_struct task;
294 u32 pending_bh;
295 int bh_requested;
296 int bh_running;
297
298 int isr_overflow;
299 int irq_requested; /* nonzero if IRQ requested */
300 int irq_occurred; /* for diagnostics use */
301
302 /* device configuration */
303
304 unsigned int bus_type;
305 unsigned int irq_level;
306 unsigned long irq_flags;
307
308 unsigned char __iomem * reg_addr; /* memory mapped registers address */
309 u32 phys_reg_addr;
310 int reg_addr_requested;
311
312 MGSL_PARAMS params; /* communications parameters */
313 u32 idle_mode;
314 u32 max_frame_size; /* as set by device config */
315
316 unsigned int raw_rx_size;
317 unsigned int if_mode;
318
319 /* device status */
320
321 int rx_enabled;
322 int rx_restart;
323
324 int tx_enabled;
325 int tx_active;
326
327 unsigned char signals; /* serial signal states */
328 int init_error; /* initialization error */
329
330 unsigned char *tx_buf;
331 int tx_count;
332
333 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
334 char char_buf[MAX_ASYNC_BUFFER_SIZE];
335 BOOLEAN drop_rts_on_tx_done;
336 struct _input_signal_events input_signal_events;
337
338 int dcd_chkcount; /* check counts to prevent */
339 int cts_chkcount; /* too many IRQs if a signal */
340 int dsr_chkcount; /* is floating */
341 int ri_chkcount;
342
343 char *bufs; /* virtual address of DMA buffer lists */
344 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
345
346 unsigned int rbuf_count;
347 struct slgt_desc *rbufs;
348 unsigned int rbuf_current;
349 unsigned int rbuf_index;
350
351 unsigned int tbuf_count;
352 struct slgt_desc *tbufs;
353 unsigned int tbuf_current;
354 unsigned int tbuf_start;
355
356 unsigned char *tmp_rbuf;
357 unsigned int tmp_rbuf_count;
358
359 /* SPPP/Cisco HDLC device parts */
360
361 int netcount;
362 int dosyncppp;
363 spinlock_t netlock;
364 #if SYNCLINK_GENERIC_HDLC
365 struct net_device *netdev;
366 #endif
367
368 };
369
370 static MGSL_PARAMS default_params = {
371 .mode = MGSL_MODE_HDLC,
372 .loopback = 0,
373 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
374 .encoding = HDLC_ENCODING_NRZI_SPACE,
375 .clock_speed = 0,
376 .addr_filter = 0xff,
377 .crc_type = HDLC_CRC_16_CCITT,
378 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
379 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
380 .data_rate = 9600,
381 .data_bits = 8,
382 .stop_bits = 1,
383 .parity = ASYNC_PARITY_NONE
384 };
385
386
387 #define BH_RECEIVE 1
388 #define BH_TRANSMIT 2
389 #define BH_STATUS 4
390 #define IO_PIN_SHUTDOWN_LIMIT 100
391
392 #define DMABUFSIZE 256
393 #define DESC_LIST_SIZE 4096
394
395 #define MASK_PARITY BIT1
396 #define MASK_FRAMING BIT0
397 #define MASK_BREAK BIT14
398 #define MASK_OVERRUN BIT4
399
400 #define GSR 0x00 /* global status */
401 #define JCR 0x04 /* JTAG control */
402 #define IODR 0x08 /* GPIO direction */
403 #define IOER 0x0c /* GPIO interrupt enable */
404 #define IOVR 0x10 /* GPIO value */
405 #define IOSR 0x14 /* GPIO interrupt status */
406 #define TDR 0x80 /* tx data */
407 #define RDR 0x80 /* rx data */
408 #define TCR 0x82 /* tx control */
409 #define TIR 0x84 /* tx idle */
410 #define TPR 0x85 /* tx preamble */
411 #define RCR 0x86 /* rx control */
412 #define VCR 0x88 /* V.24 control */
413 #define CCR 0x89 /* clock control */
414 #define BDR 0x8a /* baud divisor */
415 #define SCR 0x8c /* serial control */
416 #define SSR 0x8e /* serial status */
417 #define RDCSR 0x90 /* rx DMA control/status */
418 #define TDCSR 0x94 /* tx DMA control/status */
419 #define RDDAR 0x98 /* rx DMA descriptor address */
420 #define TDDAR 0x9c /* tx DMA descriptor address */
421
422 #define RXIDLE BIT14
423 #define RXBREAK BIT14
424 #define IRQ_TXDATA BIT13
425 #define IRQ_TXIDLE BIT12
426 #define IRQ_TXUNDER BIT11 /* HDLC */
427 #define IRQ_RXDATA BIT10
428 #define IRQ_RXIDLE BIT9 /* HDLC */
429 #define IRQ_RXBREAK BIT9 /* async */
430 #define IRQ_RXOVER BIT8
431 #define IRQ_DSR BIT7
432 #define IRQ_CTS BIT6
433 #define IRQ_DCD BIT5
434 #define IRQ_RI BIT4
435 #define IRQ_ALL 0x3ff0
436 #define IRQ_MASTER BIT0
437
438 #define slgt_irq_on(info, mask) \
439 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
440 #define slgt_irq_off(info, mask) \
441 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
442
443 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
444 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
445 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
446 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
447 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
448 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
449
450 static void msc_set_vcr(struct slgt_info *info);
451
452 static int startup(struct slgt_info *info);
453 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
454 static void shutdown(struct slgt_info *info);
455 static void program_hw(struct slgt_info *info);
456 static void change_params(struct slgt_info *info);
457
458 static int register_test(struct slgt_info *info);
459 static int irq_test(struct slgt_info *info);
460 static int loopback_test(struct slgt_info *info);
461 static int adapter_test(struct slgt_info *info);
462
463 static void reset_adapter(struct slgt_info *info);
464 static void reset_port(struct slgt_info *info);
465 static void async_mode(struct slgt_info *info);
466 static void sync_mode(struct slgt_info *info);
467
468 static void rx_stop(struct slgt_info *info);
469 static void rx_start(struct slgt_info *info);
470 static void reset_rbufs(struct slgt_info *info);
471 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
472 static void rdma_reset(struct slgt_info *info);
473 static int rx_get_frame(struct slgt_info *info);
474 static int rx_get_buf(struct slgt_info *info);
475
476 static void tx_start(struct slgt_info *info);
477 static void tx_stop(struct slgt_info *info);
478 static void tx_set_idle(struct slgt_info *info);
479 static unsigned int free_tbuf_count(struct slgt_info *info);
480 static void reset_tbufs(struct slgt_info *info);
481 static void tdma_reset(struct slgt_info *info);
482 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
483
484 static void get_signals(struct slgt_info *info);
485 static void set_signals(struct slgt_info *info);
486 static void enable_loopback(struct slgt_info *info);
487 static void set_rate(struct slgt_info *info, u32 data_rate);
488
489 static int bh_action(struct slgt_info *info);
490 static void bh_handler(struct work_struct *work);
491 static void bh_transmit(struct slgt_info *info);
492 static void isr_serial(struct slgt_info *info);
493 static void isr_rdma(struct slgt_info *info);
494 static void isr_txeom(struct slgt_info *info, unsigned short status);
495 static void isr_tdma(struct slgt_info *info);
496 static irqreturn_t slgt_interrupt(int irq, void *dev_id);
497
498 static int alloc_dma_bufs(struct slgt_info *info);
499 static void free_dma_bufs(struct slgt_info *info);
500 static int alloc_desc(struct slgt_info *info);
501 static void free_desc(struct slgt_info *info);
502 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
503 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
504
505 static int alloc_tmp_rbuf(struct slgt_info *info);
506 static void free_tmp_rbuf(struct slgt_info *info);
507
508 static void tx_timeout(unsigned long context);
509 static void rx_timeout(unsigned long context);
510
511 /*
512 * ioctl handlers
513 */
514 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
515 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
516 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
517 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
518 static int set_txidle(struct slgt_info *info, int idle_mode);
519 static int tx_enable(struct slgt_info *info, int enable);
520 static int tx_abort(struct slgt_info *info);
521 static int rx_enable(struct slgt_info *info, int enable);
522 static int modem_input_wait(struct slgt_info *info,int arg);
523 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
524 static int tiocmget(struct tty_struct *tty, struct file *file);
525 static int tiocmset(struct tty_struct *tty, struct file *file,
526 unsigned int set, unsigned int clear);
527 static void set_break(struct tty_struct *tty, int break_state);
528 static int get_interface(struct slgt_info *info, int __user *if_mode);
529 static int set_interface(struct slgt_info *info, int if_mode);
530 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
531 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
532 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
533
534 /*
535 * driver functions
536 */
537 static void add_device(struct slgt_info *info);
538 static void device_init(int adapter_num, struct pci_dev *pdev);
539 static int claim_resources(struct slgt_info *info);
540 static void release_resources(struct slgt_info *info);
541
542 /*
543 * DEBUG OUTPUT CODE
544 */
545 #ifndef DBGINFO
546 #define DBGINFO(fmt)
547 #endif
548 #ifndef DBGERR
549 #define DBGERR(fmt)
550 #endif
551 #ifndef DBGBH
552 #define DBGBH(fmt)
553 #endif
554 #ifndef DBGISR
555 #define DBGISR(fmt)
556 #endif
557
558 #ifdef DBGDATA
559 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
560 {
561 int i;
562 int linecount;
563 printk("%s %s data:\n",info->device_name, label);
564 while(count) {
565 linecount = (count > 16) ? 16 : count;
566 for(i=0; i < linecount; i++)
567 printk("%02X ",(unsigned char)data[i]);
568 for(;i<17;i++)
569 printk(" ");
570 for(i=0;i<linecount;i++) {
571 if (data[i]>=040 && data[i]<=0176)
572 printk("%c",data[i]);
573 else
574 printk(".");
575 }
576 printk("\n");
577 data += linecount;
578 count -= linecount;
579 }
580 }
581 #else
582 #define DBGDATA(info, buf, size, label)
583 #endif
584
585 #ifdef DBGTBUF
586 static void dump_tbufs(struct slgt_info *info)
587 {
588 int i;
589 printk("tbuf_current=%d\n", info->tbuf_current);
590 for (i=0 ; i < info->tbuf_count ; i++) {
591 printk("%d: count=%04X status=%04X\n",
592 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
593 }
594 }
595 #else
596 #define DBGTBUF(info)
597 #endif
598
599 #ifdef DBGRBUF
600 static void dump_rbufs(struct slgt_info *info)
601 {
602 int i;
603 printk("rbuf_current=%d\n", info->rbuf_current);
604 for (i=0 ; i < info->rbuf_count ; i++) {
605 printk("%d: count=%04X status=%04X\n",
606 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
607 }
608 }
609 #else
610 #define DBGRBUF(info)
611 #endif
612
613 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
614 {
615 #ifdef SANITY_CHECK
616 if (!info) {
617 printk("null struct slgt_info for (%s) in %s\n", devname, name);
618 return 1;
619 }
620 if (info->magic != MGSL_MAGIC) {
621 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
622 return 1;
623 }
624 #else
625 if (!info)
626 return 1;
627 #endif
628 return 0;
629 }
630
631 /**
632 * line discipline callback wrappers
633 *
634 * The wrappers maintain line discipline references
635 * while calling into the line discipline.
636 *
637 * ldisc_receive_buf - pass receive data to line discipline
638 */
639 static void ldisc_receive_buf(struct tty_struct *tty,
640 const __u8 *data, char *flags, int count)
641 {
642 struct tty_ldisc *ld;
643 if (!tty)
644 return;
645 ld = tty_ldisc_ref(tty);
646 if (ld) {
647 if (ld->receive_buf)
648 ld->receive_buf(tty, data, flags, count);
649 tty_ldisc_deref(ld);
650 }
651 }
652
653 /* tty callbacks */
654
655 static int open(struct tty_struct *tty, struct file *filp)
656 {
657 struct slgt_info *info;
658 int retval, line;
659 unsigned long flags;
660
661 line = tty->index;
662 if ((line < 0) || (line >= slgt_device_count)) {
663 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
664 return -ENODEV;
665 }
666
667 info = slgt_device_list;
668 while(info && info->line != line)
669 info = info->next_device;
670 if (sanity_check(info, tty->name, "open"))
671 return -ENODEV;
672 if (info->init_error) {
673 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
674 return -ENODEV;
675 }
676
677 tty->driver_data = info;
678 info->tty = tty;
679
680 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
681
682 /* If port is closing, signal caller to try again */
683 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
684 if (info->flags & ASYNC_CLOSING)
685 interruptible_sleep_on(&info->close_wait);
686 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
687 -EAGAIN : -ERESTARTSYS);
688 goto cleanup;
689 }
690
691 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
692
693 spin_lock_irqsave(&info->netlock, flags);
694 if (info->netcount) {
695 retval = -EBUSY;
696 spin_unlock_irqrestore(&info->netlock, flags);
697 goto cleanup;
698 }
699 info->count++;
700 spin_unlock_irqrestore(&info->netlock, flags);
701
702 if (info->count == 1) {
703 /* 1st open on this device, init hardware */
704 retval = startup(info);
705 if (retval < 0)
706 goto cleanup;
707 }
708
709 retval = block_til_ready(tty, filp, info);
710 if (retval) {
711 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
712 goto cleanup;
713 }
714
715 retval = 0;
716
717 cleanup:
718 if (retval) {
719 if (tty->count == 1)
720 info->tty = NULL; /* tty layer will release tty struct */
721 if(info->count)
722 info->count--;
723 }
724
725 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
726 return retval;
727 }
728
729 static void close(struct tty_struct *tty, struct file *filp)
730 {
731 struct slgt_info *info = tty->driver_data;
732
733 if (sanity_check(info, tty->name, "close"))
734 return;
735 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
736
737 if (!info->count)
738 return;
739
740 if (tty_hung_up_p(filp))
741 goto cleanup;
742
743 if ((tty->count == 1) && (info->count != 1)) {
744 /*
745 * tty->count is 1 and the tty structure will be freed.
746 * info->count should be one in this case.
747 * if it's not, correct it so that the port is shutdown.
748 */
749 DBGERR(("%s close: bad refcount; tty->count=1, "
750 "info->count=%d\n", info->device_name, info->count));
751 info->count = 1;
752 }
753
754 info->count--;
755
756 /* if at least one open remaining, leave hardware active */
757 if (info->count)
758 goto cleanup;
759
760 info->flags |= ASYNC_CLOSING;
761
762 /* set tty->closing to notify line discipline to
763 * only process XON/XOFF characters. Only the N_TTY
764 * discipline appears to use this (ppp does not).
765 */
766 tty->closing = 1;
767
768 /* wait for transmit data to clear all layers */
769
770 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
771 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
772 tty_wait_until_sent(tty, info->closing_wait);
773 }
774
775 if (info->flags & ASYNC_INITIALIZED)
776 wait_until_sent(tty, info->timeout);
777 if (tty->driver->flush_buffer)
778 tty->driver->flush_buffer(tty);
779 tty_ldisc_flush(tty);
780
781 shutdown(info);
782
783 tty->closing = 0;
784 info->tty = NULL;
785
786 if (info->blocked_open) {
787 if (info->close_delay) {
788 msleep_interruptible(jiffies_to_msecs(info->close_delay));
789 }
790 wake_up_interruptible(&info->open_wait);
791 }
792
793 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
794
795 wake_up_interruptible(&info->close_wait);
796
797 cleanup:
798 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
799 }
800
801 static void hangup(struct tty_struct *tty)
802 {
803 struct slgt_info *info = tty->driver_data;
804
805 if (sanity_check(info, tty->name, "hangup"))
806 return;
807 DBGINFO(("%s hangup\n", info->device_name));
808
809 flush_buffer(tty);
810 shutdown(info);
811
812 info->count = 0;
813 info->flags &= ~ASYNC_NORMAL_ACTIVE;
814 info->tty = NULL;
815
816 wake_up_interruptible(&info->open_wait);
817 }
818
819 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
820 {
821 struct slgt_info *info = tty->driver_data;
822 unsigned long flags;
823
824 DBGINFO(("%s set_termios\n", tty->driver->name));
825
826 /* just return if nothing has changed */
827 if ((tty->termios->c_cflag == old_termios->c_cflag)
828 && (RELEVANT_IFLAG(tty->termios->c_iflag)
829 == RELEVANT_IFLAG(old_termios->c_iflag)))
830 return;
831
832 change_params(info);
833
834 /* Handle transition to B0 status */
835 if (old_termios->c_cflag & CBAUD &&
836 !(tty->termios->c_cflag & CBAUD)) {
837 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
838 spin_lock_irqsave(&info->lock,flags);
839 set_signals(info);
840 spin_unlock_irqrestore(&info->lock,flags);
841 }
842
843 /* Handle transition away from B0 status */
844 if (!(old_termios->c_cflag & CBAUD) &&
845 tty->termios->c_cflag & CBAUD) {
846 info->signals |= SerialSignal_DTR;
847 if (!(tty->termios->c_cflag & CRTSCTS) ||
848 !test_bit(TTY_THROTTLED, &tty->flags)) {
849 info->signals |= SerialSignal_RTS;
850 }
851 spin_lock_irqsave(&info->lock,flags);
852 set_signals(info);
853 spin_unlock_irqrestore(&info->lock,flags);
854 }
855
856 /* Handle turning off CRTSCTS */
857 if (old_termios->c_cflag & CRTSCTS &&
858 !(tty->termios->c_cflag & CRTSCTS)) {
859 tty->hw_stopped = 0;
860 tx_release(tty);
861 }
862 }
863
864 static int write(struct tty_struct *tty,
865 const unsigned char *buf, int count)
866 {
867 int ret = 0;
868 struct slgt_info *info = tty->driver_data;
869 unsigned long flags;
870
871 if (sanity_check(info, tty->name, "write"))
872 goto cleanup;
873 DBGINFO(("%s write count=%d\n", info->device_name, count));
874
875 if (!info->tx_buf)
876 goto cleanup;
877
878 if (count > info->max_frame_size) {
879 ret = -EIO;
880 goto cleanup;
881 }
882
883 if (!count)
884 goto cleanup;
885
886 if (info->params.mode == MGSL_MODE_RAW ||
887 info->params.mode == MGSL_MODE_MONOSYNC ||
888 info->params.mode == MGSL_MODE_BISYNC) {
889 unsigned int bufs_needed = (count/DMABUFSIZE);
890 unsigned int bufs_free = free_tbuf_count(info);
891 if (count % DMABUFSIZE)
892 ++bufs_needed;
893 if (bufs_needed > bufs_free)
894 goto cleanup;
895 } else {
896 if (info->tx_active)
897 goto cleanup;
898 if (info->tx_count) {
899 /* send accumulated data from send_char() calls */
900 /* as frame and wait before accepting more data. */
901 tx_load(info, info->tx_buf, info->tx_count);
902 goto start;
903 }
904 }
905
906 ret = info->tx_count = count;
907 tx_load(info, buf, count);
908 goto start;
909
910 start:
911 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
912 spin_lock_irqsave(&info->lock,flags);
913 if (!info->tx_active)
914 tx_start(info);
915 spin_unlock_irqrestore(&info->lock,flags);
916 }
917
918 cleanup:
919 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
920 return ret;
921 }
922
923 static void put_char(struct tty_struct *tty, unsigned char ch)
924 {
925 struct slgt_info *info = tty->driver_data;
926 unsigned long flags;
927
928 if (sanity_check(info, tty->name, "put_char"))
929 return;
930 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
931 if (!info->tx_buf)
932 return;
933 spin_lock_irqsave(&info->lock,flags);
934 if (!info->tx_active && (info->tx_count < info->max_frame_size))
935 info->tx_buf[info->tx_count++] = ch;
936 spin_unlock_irqrestore(&info->lock,flags);
937 }
938
939 static void send_xchar(struct tty_struct *tty, char ch)
940 {
941 struct slgt_info *info = tty->driver_data;
942 unsigned long flags;
943
944 if (sanity_check(info, tty->name, "send_xchar"))
945 return;
946 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
947 info->x_char = ch;
948 if (ch) {
949 spin_lock_irqsave(&info->lock,flags);
950 if (!info->tx_enabled)
951 tx_start(info);
952 spin_unlock_irqrestore(&info->lock,flags);
953 }
954 }
955
956 static void wait_until_sent(struct tty_struct *tty, int timeout)
957 {
958 struct slgt_info *info = tty->driver_data;
959 unsigned long orig_jiffies, char_time;
960
961 if (!info )
962 return;
963 if (sanity_check(info, tty->name, "wait_until_sent"))
964 return;
965 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
966 if (!(info->flags & ASYNC_INITIALIZED))
967 goto exit;
968
969 orig_jiffies = jiffies;
970
971 /* Set check interval to 1/5 of estimated time to
972 * send a character, and make it at least 1. The check
973 * interval should also be less than the timeout.
974 * Note: use tight timings here to satisfy the NIST-PCTS.
975 */
976
977 if (info->params.data_rate) {
978 char_time = info->timeout/(32 * 5);
979 if (!char_time)
980 char_time++;
981 } else
982 char_time = 1;
983
984 if (timeout)
985 char_time = min_t(unsigned long, char_time, timeout);
986
987 while (info->tx_active) {
988 msleep_interruptible(jiffies_to_msecs(char_time));
989 if (signal_pending(current))
990 break;
991 if (timeout && time_after(jiffies, orig_jiffies + timeout))
992 break;
993 }
994
995 exit:
996 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
997 }
998
999 static int write_room(struct tty_struct *tty)
1000 {
1001 struct slgt_info *info = tty->driver_data;
1002 int ret;
1003
1004 if (sanity_check(info, tty->name, "write_room"))
1005 return 0;
1006 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1007 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1008 return ret;
1009 }
1010
1011 static void flush_chars(struct tty_struct *tty)
1012 {
1013 struct slgt_info *info = tty->driver_data;
1014 unsigned long flags;
1015
1016 if (sanity_check(info, tty->name, "flush_chars"))
1017 return;
1018 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1019
1020 if (info->tx_count <= 0 || tty->stopped ||
1021 tty->hw_stopped || !info->tx_buf)
1022 return;
1023
1024 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1025
1026 spin_lock_irqsave(&info->lock,flags);
1027 if (!info->tx_active && info->tx_count) {
1028 tx_load(info, info->tx_buf,info->tx_count);
1029 tx_start(info);
1030 }
1031 spin_unlock_irqrestore(&info->lock,flags);
1032 }
1033
1034 static void flush_buffer(struct tty_struct *tty)
1035 {
1036 struct slgt_info *info = tty->driver_data;
1037 unsigned long flags;
1038
1039 if (sanity_check(info, tty->name, "flush_buffer"))
1040 return;
1041 DBGINFO(("%s flush_buffer\n", info->device_name));
1042
1043 spin_lock_irqsave(&info->lock,flags);
1044 if (!info->tx_active)
1045 info->tx_count = 0;
1046 spin_unlock_irqrestore(&info->lock,flags);
1047
1048 wake_up_interruptible(&tty->write_wait);
1049 tty_wakeup(tty);
1050 }
1051
1052 /*
1053 * throttle (stop) transmitter
1054 */
1055 static void tx_hold(struct tty_struct *tty)
1056 {
1057 struct slgt_info *info = tty->driver_data;
1058 unsigned long flags;
1059
1060 if (sanity_check(info, tty->name, "tx_hold"))
1061 return;
1062 DBGINFO(("%s tx_hold\n", info->device_name));
1063 spin_lock_irqsave(&info->lock,flags);
1064 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1065 tx_stop(info);
1066 spin_unlock_irqrestore(&info->lock,flags);
1067 }
1068
1069 /*
1070 * release (start) transmitter
1071 */
1072 static void tx_release(struct tty_struct *tty)
1073 {
1074 struct slgt_info *info = tty->driver_data;
1075 unsigned long flags;
1076
1077 if (sanity_check(info, tty->name, "tx_release"))
1078 return;
1079 DBGINFO(("%s tx_release\n", info->device_name));
1080 spin_lock_irqsave(&info->lock,flags);
1081 if (!info->tx_active && info->tx_count) {
1082 tx_load(info, info->tx_buf, info->tx_count);
1083 tx_start(info);
1084 }
1085 spin_unlock_irqrestore(&info->lock,flags);
1086 }
1087
1088 /*
1089 * Service an IOCTL request
1090 *
1091 * Arguments
1092 *
1093 * tty pointer to tty instance data
1094 * file pointer to associated file object for device
1095 * cmd IOCTL command code
1096 * arg command argument/context
1097 *
1098 * Return 0 if success, otherwise error code
1099 */
1100 static int ioctl(struct tty_struct *tty, struct file *file,
1101 unsigned int cmd, unsigned long arg)
1102 {
1103 struct slgt_info *info = tty->driver_data;
1104 struct mgsl_icount cnow; /* kernel counter temps */
1105 struct serial_icounter_struct __user *p_cuser; /* user space */
1106 unsigned long flags;
1107 void __user *argp = (void __user *)arg;
1108
1109 if (sanity_check(info, tty->name, "ioctl"))
1110 return -ENODEV;
1111 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1112
1113 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1114 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1115 if (tty->flags & (1 << TTY_IO_ERROR))
1116 return -EIO;
1117 }
1118
1119 switch (cmd) {
1120 case MGSL_IOCGPARAMS:
1121 return get_params(info, argp);
1122 case MGSL_IOCSPARAMS:
1123 return set_params(info, argp);
1124 case MGSL_IOCGTXIDLE:
1125 return get_txidle(info, argp);
1126 case MGSL_IOCSTXIDLE:
1127 return set_txidle(info, (int)arg);
1128 case MGSL_IOCTXENABLE:
1129 return tx_enable(info, (int)arg);
1130 case MGSL_IOCRXENABLE:
1131 return rx_enable(info, (int)arg);
1132 case MGSL_IOCTXABORT:
1133 return tx_abort(info);
1134 case MGSL_IOCGSTATS:
1135 return get_stats(info, argp);
1136 case MGSL_IOCWAITEVENT:
1137 return wait_mgsl_event(info, argp);
1138 case TIOCMIWAIT:
1139 return modem_input_wait(info,(int)arg);
1140 case MGSL_IOCGIF:
1141 return get_interface(info, argp);
1142 case MGSL_IOCSIF:
1143 return set_interface(info,(int)arg);
1144 case MGSL_IOCSGPIO:
1145 return set_gpio(info, argp);
1146 case MGSL_IOCGGPIO:
1147 return get_gpio(info, argp);
1148 case MGSL_IOCWAITGPIO:
1149 return wait_gpio(info, argp);
1150 case TIOCGICOUNT:
1151 spin_lock_irqsave(&info->lock,flags);
1152 cnow = info->icount;
1153 spin_unlock_irqrestore(&info->lock,flags);
1154 p_cuser = argp;
1155 if (put_user(cnow.cts, &p_cuser->cts) ||
1156 put_user(cnow.dsr, &p_cuser->dsr) ||
1157 put_user(cnow.rng, &p_cuser->rng) ||
1158 put_user(cnow.dcd, &p_cuser->dcd) ||
1159 put_user(cnow.rx, &p_cuser->rx) ||
1160 put_user(cnow.tx, &p_cuser->tx) ||
1161 put_user(cnow.frame, &p_cuser->frame) ||
1162 put_user(cnow.overrun, &p_cuser->overrun) ||
1163 put_user(cnow.parity, &p_cuser->parity) ||
1164 put_user(cnow.brk, &p_cuser->brk) ||
1165 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1166 return -EFAULT;
1167 return 0;
1168 default:
1169 return -ENOIOCTLCMD;
1170 }
1171 return 0;
1172 }
1173
1174 /*
1175 * proc fs support
1176 */
1177 static inline int line_info(char *buf, struct slgt_info *info)
1178 {
1179 char stat_buf[30];
1180 int ret;
1181 unsigned long flags;
1182
1183 ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1184 info->device_name, info->phys_reg_addr,
1185 info->irq_level, info->max_frame_size);
1186
1187 /* output current serial signal states */
1188 spin_lock_irqsave(&info->lock,flags);
1189 get_signals(info);
1190 spin_unlock_irqrestore(&info->lock,flags);
1191
1192 stat_buf[0] = 0;
1193 stat_buf[1] = 0;
1194 if (info->signals & SerialSignal_RTS)
1195 strcat(stat_buf, "|RTS");
1196 if (info->signals & SerialSignal_CTS)
1197 strcat(stat_buf, "|CTS");
1198 if (info->signals & SerialSignal_DTR)
1199 strcat(stat_buf, "|DTR");
1200 if (info->signals & SerialSignal_DSR)
1201 strcat(stat_buf, "|DSR");
1202 if (info->signals & SerialSignal_DCD)
1203 strcat(stat_buf, "|CD");
1204 if (info->signals & SerialSignal_RI)
1205 strcat(stat_buf, "|RI");
1206
1207 if (info->params.mode != MGSL_MODE_ASYNC) {
1208 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1209 info->icount.txok, info->icount.rxok);
1210 if (info->icount.txunder)
1211 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1212 if (info->icount.txabort)
1213 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1214 if (info->icount.rxshort)
1215 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1216 if (info->icount.rxlong)
1217 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1218 if (info->icount.rxover)
1219 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1220 if (info->icount.rxcrc)
1221 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1222 } else {
1223 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1224 info->icount.tx, info->icount.rx);
1225 if (info->icount.frame)
1226 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1227 if (info->icount.parity)
1228 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1229 if (info->icount.brk)
1230 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1231 if (info->icount.overrun)
1232 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1233 }
1234
1235 /* Append serial signal status to end */
1236 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1237
1238 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1239 info->tx_active,info->bh_requested,info->bh_running,
1240 info->pending_bh);
1241
1242 return ret;
1243 }
1244
1245 /* Called to print information about devices
1246 */
1247 static int read_proc(char *page, char **start, off_t off, int count,
1248 int *eof, void *data)
1249 {
1250 int len = 0, l;
1251 off_t begin = 0;
1252 struct slgt_info *info;
1253
1254 len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1255
1256 info = slgt_device_list;
1257 while( info ) {
1258 l = line_info(page + len, info);
1259 len += l;
1260 if (len+begin > off+count)
1261 goto done;
1262 if (len+begin < off) {
1263 begin += len;
1264 len = 0;
1265 }
1266 info = info->next_device;
1267 }
1268
1269 *eof = 1;
1270 done:
1271 if (off >= len+begin)
1272 return 0;
1273 *start = page + (off-begin);
1274 return ((count < begin+len-off) ? count : begin+len-off);
1275 }
1276
1277 /*
1278 * return count of bytes in transmit buffer
1279 */
1280 static int chars_in_buffer(struct tty_struct *tty)
1281 {
1282 struct slgt_info *info = tty->driver_data;
1283 if (sanity_check(info, tty->name, "chars_in_buffer"))
1284 return 0;
1285 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1286 return info->tx_count;
1287 }
1288
1289 /*
1290 * signal remote device to throttle send data (our receive data)
1291 */
1292 static void throttle(struct tty_struct * tty)
1293 {
1294 struct slgt_info *info = tty->driver_data;
1295 unsigned long flags;
1296
1297 if (sanity_check(info, tty->name, "throttle"))
1298 return;
1299 DBGINFO(("%s throttle\n", info->device_name));
1300 if (I_IXOFF(tty))
1301 send_xchar(tty, STOP_CHAR(tty));
1302 if (tty->termios->c_cflag & CRTSCTS) {
1303 spin_lock_irqsave(&info->lock,flags);
1304 info->signals &= ~SerialSignal_RTS;
1305 set_signals(info);
1306 spin_unlock_irqrestore(&info->lock,flags);
1307 }
1308 }
1309
1310 /*
1311 * signal remote device to stop throttling send data (our receive data)
1312 */
1313 static void unthrottle(struct tty_struct * tty)
1314 {
1315 struct slgt_info *info = tty->driver_data;
1316 unsigned long flags;
1317
1318 if (sanity_check(info, tty->name, "unthrottle"))
1319 return;
1320 DBGINFO(("%s unthrottle\n", info->device_name));
1321 if (I_IXOFF(tty)) {
1322 if (info->x_char)
1323 info->x_char = 0;
1324 else
1325 send_xchar(tty, START_CHAR(tty));
1326 }
1327 if (tty->termios->c_cflag & CRTSCTS) {
1328 spin_lock_irqsave(&info->lock,flags);
1329 info->signals |= SerialSignal_RTS;
1330 set_signals(info);
1331 spin_unlock_irqrestore(&info->lock,flags);
1332 }
1333 }
1334
1335 /*
1336 * set or clear transmit break condition
1337 * break_state -1=set break condition, 0=clear
1338 */
1339 static void set_break(struct tty_struct *tty, int break_state)
1340 {
1341 struct slgt_info *info = tty->driver_data;
1342 unsigned short value;
1343 unsigned long flags;
1344
1345 if (sanity_check(info, tty->name, "set_break"))
1346 return;
1347 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1348
1349 spin_lock_irqsave(&info->lock,flags);
1350 value = rd_reg16(info, TCR);
1351 if (break_state == -1)
1352 value |= BIT6;
1353 else
1354 value &= ~BIT6;
1355 wr_reg16(info, TCR, value);
1356 spin_unlock_irqrestore(&info->lock,flags);
1357 }
1358
1359 #if SYNCLINK_GENERIC_HDLC
1360
1361 /**
1362 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1363 * set encoding and frame check sequence (FCS) options
1364 *
1365 * dev pointer to network device structure
1366 * encoding serial encoding setting
1367 * parity FCS setting
1368 *
1369 * returns 0 if success, otherwise error code
1370 */
1371 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1372 unsigned short parity)
1373 {
1374 struct slgt_info *info = dev_to_port(dev);
1375 unsigned char new_encoding;
1376 unsigned short new_crctype;
1377
1378 /* return error if TTY interface open */
1379 if (info->count)
1380 return -EBUSY;
1381
1382 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1383
1384 switch (encoding)
1385 {
1386 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1387 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1388 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1389 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1390 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1391 default: return -EINVAL;
1392 }
1393
1394 switch (parity)
1395 {
1396 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1397 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1398 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1399 default: return -EINVAL;
1400 }
1401
1402 info->params.encoding = new_encoding;
1403 info->params.crc_type = new_crctype;
1404
1405 /* if network interface up, reprogram hardware */
1406 if (info->netcount)
1407 program_hw(info);
1408
1409 return 0;
1410 }
1411
1412 /**
1413 * called by generic HDLC layer to send frame
1414 *
1415 * skb socket buffer containing HDLC frame
1416 * dev pointer to network device structure
1417 *
1418 * returns 0 if success, otherwise error code
1419 */
1420 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1421 {
1422 struct slgt_info *info = dev_to_port(dev);
1423 struct net_device_stats *stats = hdlc_stats(dev);
1424 unsigned long flags;
1425
1426 DBGINFO(("%s hdlc_xmit\n", dev->name));
1427
1428 /* stop sending until this frame completes */
1429 netif_stop_queue(dev);
1430
1431 /* copy data to device buffers */
1432 info->tx_count = skb->len;
1433 tx_load(info, skb->data, skb->len);
1434
1435 /* update network statistics */
1436 stats->tx_packets++;
1437 stats->tx_bytes += skb->len;
1438
1439 /* done with socket buffer, so free it */
1440 dev_kfree_skb(skb);
1441
1442 /* save start time for transmit timeout detection */
1443 dev->trans_start = jiffies;
1444
1445 /* start hardware transmitter if necessary */
1446 spin_lock_irqsave(&info->lock,flags);
1447 if (!info->tx_active)
1448 tx_start(info);
1449 spin_unlock_irqrestore(&info->lock,flags);
1450
1451 return 0;
1452 }
1453
1454 /**
1455 * called by network layer when interface enabled
1456 * claim resources and initialize hardware
1457 *
1458 * dev pointer to network device structure
1459 *
1460 * returns 0 if success, otherwise error code
1461 */
1462 static int hdlcdev_open(struct net_device *dev)
1463 {
1464 struct slgt_info *info = dev_to_port(dev);
1465 int rc;
1466 unsigned long flags;
1467
1468 DBGINFO(("%s hdlcdev_open\n", dev->name));
1469
1470 /* generic HDLC layer open processing */
1471 if ((rc = hdlc_open(dev)))
1472 return rc;
1473
1474 /* arbitrate between network and tty opens */
1475 spin_lock_irqsave(&info->netlock, flags);
1476 if (info->count != 0 || info->netcount != 0) {
1477 DBGINFO(("%s hdlc_open busy\n", dev->name));
1478 spin_unlock_irqrestore(&info->netlock, flags);
1479 return -EBUSY;
1480 }
1481 info->netcount=1;
1482 spin_unlock_irqrestore(&info->netlock, flags);
1483
1484 /* claim resources and init adapter */
1485 if ((rc = startup(info)) != 0) {
1486 spin_lock_irqsave(&info->netlock, flags);
1487 info->netcount=0;
1488 spin_unlock_irqrestore(&info->netlock, flags);
1489 return rc;
1490 }
1491
1492 /* assert DTR and RTS, apply hardware settings */
1493 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1494 program_hw(info);
1495
1496 /* enable network layer transmit */
1497 dev->trans_start = jiffies;
1498 netif_start_queue(dev);
1499
1500 /* inform generic HDLC layer of current DCD status */
1501 spin_lock_irqsave(&info->lock, flags);
1502 get_signals(info);
1503 spin_unlock_irqrestore(&info->lock, flags);
1504 if (info->signals & SerialSignal_DCD)
1505 netif_carrier_on(dev);
1506 else
1507 netif_carrier_off(dev);
1508 return 0;
1509 }
1510
1511 /**
1512 * called by network layer when interface is disabled
1513 * shutdown hardware and release resources
1514 *
1515 * dev pointer to network device structure
1516 *
1517 * returns 0 if success, otherwise error code
1518 */
1519 static int hdlcdev_close(struct net_device *dev)
1520 {
1521 struct slgt_info *info = dev_to_port(dev);
1522 unsigned long flags;
1523
1524 DBGINFO(("%s hdlcdev_close\n", dev->name));
1525
1526 netif_stop_queue(dev);
1527
1528 /* shutdown adapter and release resources */
1529 shutdown(info);
1530
1531 hdlc_close(dev);
1532
1533 spin_lock_irqsave(&info->netlock, flags);
1534 info->netcount=0;
1535 spin_unlock_irqrestore(&info->netlock, flags);
1536
1537 return 0;
1538 }
1539
1540 /**
1541 * called by network layer to process IOCTL call to network device
1542 *
1543 * dev pointer to network device structure
1544 * ifr pointer to network interface request structure
1545 * cmd IOCTL command code
1546 *
1547 * returns 0 if success, otherwise error code
1548 */
1549 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1550 {
1551 const size_t size = sizeof(sync_serial_settings);
1552 sync_serial_settings new_line;
1553 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1554 struct slgt_info *info = dev_to_port(dev);
1555 unsigned int flags;
1556
1557 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1558
1559 /* return error if TTY interface open */
1560 if (info->count)
1561 return -EBUSY;
1562
1563 if (cmd != SIOCWANDEV)
1564 return hdlc_ioctl(dev, ifr, cmd);
1565
1566 switch(ifr->ifr_settings.type) {
1567 case IF_GET_IFACE: /* return current sync_serial_settings */
1568
1569 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1570 if (ifr->ifr_settings.size < size) {
1571 ifr->ifr_settings.size = size; /* data size wanted */
1572 return -ENOBUFS;
1573 }
1574
1575 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1576 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1577 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1578 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1579
1580 switch (flags){
1581 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1582 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1583 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1584 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1585 default: new_line.clock_type = CLOCK_DEFAULT;
1586 }
1587
1588 new_line.clock_rate = info->params.clock_speed;
1589 new_line.loopback = info->params.loopback ? 1:0;
1590
1591 if (copy_to_user(line, &new_line, size))
1592 return -EFAULT;
1593 return 0;
1594
1595 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1596
1597 if(!capable(CAP_NET_ADMIN))
1598 return -EPERM;
1599 if (copy_from_user(&new_line, line, size))
1600 return -EFAULT;
1601
1602 switch (new_line.clock_type)
1603 {
1604 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1605 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1606 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1607 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1608 case CLOCK_DEFAULT: flags = info->params.flags &
1609 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1610 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1611 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1612 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1613 default: return -EINVAL;
1614 }
1615
1616 if (new_line.loopback != 0 && new_line.loopback != 1)
1617 return -EINVAL;
1618
1619 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1620 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1621 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1622 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1623 info->params.flags |= flags;
1624
1625 info->params.loopback = new_line.loopback;
1626
1627 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1628 info->params.clock_speed = new_line.clock_rate;
1629 else
1630 info->params.clock_speed = 0;
1631
1632 /* if network interface up, reprogram hardware */
1633 if (info->netcount)
1634 program_hw(info);
1635 return 0;
1636
1637 default:
1638 return hdlc_ioctl(dev, ifr, cmd);
1639 }
1640 }
1641
1642 /**
1643 * called by network layer when transmit timeout is detected
1644 *
1645 * dev pointer to network device structure
1646 */
1647 static void hdlcdev_tx_timeout(struct net_device *dev)
1648 {
1649 struct slgt_info *info = dev_to_port(dev);
1650 struct net_device_stats *stats = hdlc_stats(dev);
1651 unsigned long flags;
1652
1653 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1654
1655 stats->tx_errors++;
1656 stats->tx_aborted_errors++;
1657
1658 spin_lock_irqsave(&info->lock,flags);
1659 tx_stop(info);
1660 spin_unlock_irqrestore(&info->lock,flags);
1661
1662 netif_wake_queue(dev);
1663 }
1664
1665 /**
1666 * called by device driver when transmit completes
1667 * reenable network layer transmit if stopped
1668 *
1669 * info pointer to device instance information
1670 */
1671 static void hdlcdev_tx_done(struct slgt_info *info)
1672 {
1673 if (netif_queue_stopped(info->netdev))
1674 netif_wake_queue(info->netdev);
1675 }
1676
1677 /**
1678 * called by device driver when frame received
1679 * pass frame to network layer
1680 *
1681 * info pointer to device instance information
1682 * buf pointer to buffer contianing frame data
1683 * size count of data bytes in buf
1684 */
1685 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1686 {
1687 struct sk_buff *skb = dev_alloc_skb(size);
1688 struct net_device *dev = info->netdev;
1689 struct net_device_stats *stats = hdlc_stats(dev);
1690
1691 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1692
1693 if (skb == NULL) {
1694 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1695 stats->rx_dropped++;
1696 return;
1697 }
1698
1699 memcpy(skb_put(skb, size),buf,size);
1700
1701 skb->protocol = hdlc_type_trans(skb, info->netdev);
1702
1703 stats->rx_packets++;
1704 stats->rx_bytes += size;
1705
1706 netif_rx(skb);
1707
1708 info->netdev->last_rx = jiffies;
1709 }
1710
1711 /**
1712 * called by device driver when adding device instance
1713 * do generic HDLC initialization
1714 *
1715 * info pointer to device instance information
1716 *
1717 * returns 0 if success, otherwise error code
1718 */
1719 static int hdlcdev_init(struct slgt_info *info)
1720 {
1721 int rc;
1722 struct net_device *dev;
1723 hdlc_device *hdlc;
1724
1725 /* allocate and initialize network and HDLC layer objects */
1726
1727 if (!(dev = alloc_hdlcdev(info))) {
1728 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1729 return -ENOMEM;
1730 }
1731
1732 /* for network layer reporting purposes only */
1733 dev->mem_start = info->phys_reg_addr;
1734 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1735 dev->irq = info->irq_level;
1736
1737 /* network layer callbacks and settings */
1738 dev->do_ioctl = hdlcdev_ioctl;
1739 dev->open = hdlcdev_open;
1740 dev->stop = hdlcdev_close;
1741 dev->tx_timeout = hdlcdev_tx_timeout;
1742 dev->watchdog_timeo = 10*HZ;
1743 dev->tx_queue_len = 50;
1744
1745 /* generic HDLC layer callbacks and settings */
1746 hdlc = dev_to_hdlc(dev);
1747 hdlc->attach = hdlcdev_attach;
1748 hdlc->xmit = hdlcdev_xmit;
1749
1750 /* register objects with HDLC layer */
1751 if ((rc = register_hdlc_device(dev))) {
1752 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1753 free_netdev(dev);
1754 return rc;
1755 }
1756
1757 info->netdev = dev;
1758 return 0;
1759 }
1760
1761 /**
1762 * called by device driver when removing device instance
1763 * do generic HDLC cleanup
1764 *
1765 * info pointer to device instance information
1766 */
1767 static void hdlcdev_exit(struct slgt_info *info)
1768 {
1769 unregister_hdlc_device(info->netdev);
1770 free_netdev(info->netdev);
1771 info->netdev = NULL;
1772 }
1773
1774 #endif /* ifdef CONFIG_HDLC */
1775
1776 /*
1777 * get async data from rx DMA buffers
1778 */
1779 static void rx_async(struct slgt_info *info)
1780 {
1781 struct tty_struct *tty = info->tty;
1782 struct mgsl_icount *icount = &info->icount;
1783 unsigned int start, end;
1784 unsigned char *p;
1785 unsigned char status;
1786 struct slgt_desc *bufs = info->rbufs;
1787 int i, count;
1788 int chars = 0;
1789 int stat;
1790 unsigned char ch;
1791
1792 start = end = info->rbuf_current;
1793
1794 while(desc_complete(bufs[end])) {
1795 count = desc_count(bufs[end]) - info->rbuf_index;
1796 p = bufs[end].buf + info->rbuf_index;
1797
1798 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1799 DBGDATA(info, p, count, "rx");
1800
1801 for(i=0 ; i < count; i+=2, p+=2) {
1802 ch = *p;
1803 icount->rx++;
1804
1805 stat = 0;
1806
1807 if ((status = *(p+1) & (BIT1 + BIT0))) {
1808 if (status & BIT1)
1809 icount->parity++;
1810 else if (status & BIT0)
1811 icount->frame++;
1812 /* discard char if tty control flags say so */
1813 if (status & info->ignore_status_mask)
1814 continue;
1815 if (status & BIT1)
1816 stat = TTY_PARITY;
1817 else if (status & BIT0)
1818 stat = TTY_FRAME;
1819 }
1820 if (tty) {
1821 tty_insert_flip_char(tty, ch, stat);
1822 chars++;
1823 }
1824 }
1825
1826 if (i < count) {
1827 /* receive buffer not completed */
1828 info->rbuf_index += i;
1829 info->rx_timer.expires = jiffies + 1;
1830 add_timer(&info->rx_timer);
1831 break;
1832 }
1833
1834 info->rbuf_index = 0;
1835 free_rbufs(info, end, end);
1836
1837 if (++end == info->rbuf_count)
1838 end = 0;
1839
1840 /* if entire list searched then no frame available */
1841 if (end == start)
1842 break;
1843 }
1844
1845 if (tty && chars)
1846 tty_flip_buffer_push(tty);
1847 }
1848
1849 /*
1850 * return next bottom half action to perform
1851 */
1852 static int bh_action(struct slgt_info *info)
1853 {
1854 unsigned long flags;
1855 int rc;
1856
1857 spin_lock_irqsave(&info->lock,flags);
1858
1859 if (info->pending_bh & BH_RECEIVE) {
1860 info->pending_bh &= ~BH_RECEIVE;
1861 rc = BH_RECEIVE;
1862 } else if (info->pending_bh & BH_TRANSMIT) {
1863 info->pending_bh &= ~BH_TRANSMIT;
1864 rc = BH_TRANSMIT;
1865 } else if (info->pending_bh & BH_STATUS) {
1866 info->pending_bh &= ~BH_STATUS;
1867 rc = BH_STATUS;
1868 } else {
1869 /* Mark BH routine as complete */
1870 info->bh_running = 0;
1871 info->bh_requested = 0;
1872 rc = 0;
1873 }
1874
1875 spin_unlock_irqrestore(&info->lock,flags);
1876
1877 return rc;
1878 }
1879
1880 /*
1881 * perform bottom half processing
1882 */
1883 static void bh_handler(struct work_struct *work)
1884 {
1885 struct slgt_info *info = container_of(work, struct slgt_info, task);
1886 int action;
1887
1888 if (!info)
1889 return;
1890 info->bh_running = 1;
1891
1892 while((action = bh_action(info))) {
1893 switch (action) {
1894 case BH_RECEIVE:
1895 DBGBH(("%s bh receive\n", info->device_name));
1896 switch(info->params.mode) {
1897 case MGSL_MODE_ASYNC:
1898 rx_async(info);
1899 break;
1900 case MGSL_MODE_HDLC:
1901 while(rx_get_frame(info));
1902 break;
1903 case MGSL_MODE_RAW:
1904 case MGSL_MODE_MONOSYNC:
1905 case MGSL_MODE_BISYNC:
1906 while(rx_get_buf(info));
1907 break;
1908 }
1909 /* restart receiver if rx DMA buffers exhausted */
1910 if (info->rx_restart)
1911 rx_start(info);
1912 break;
1913 case BH_TRANSMIT:
1914 bh_transmit(info);
1915 break;
1916 case BH_STATUS:
1917 DBGBH(("%s bh status\n", info->device_name));
1918 info->ri_chkcount = 0;
1919 info->dsr_chkcount = 0;
1920 info->dcd_chkcount = 0;
1921 info->cts_chkcount = 0;
1922 break;
1923 default:
1924 DBGBH(("%s unknown action\n", info->device_name));
1925 break;
1926 }
1927 }
1928 DBGBH(("%s bh_handler exit\n", info->device_name));
1929 }
1930
1931 static void bh_transmit(struct slgt_info *info)
1932 {
1933 struct tty_struct *tty = info->tty;
1934
1935 DBGBH(("%s bh_transmit\n", info->device_name));
1936 if (tty) {
1937 tty_wakeup(tty);
1938 wake_up_interruptible(&tty->write_wait);
1939 }
1940 }
1941
1942 static void dsr_change(struct slgt_info *info)
1943 {
1944 get_signals(info);
1945 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1946 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1947 slgt_irq_off(info, IRQ_DSR);
1948 return;
1949 }
1950 info->icount.dsr++;
1951 if (info->signals & SerialSignal_DSR)
1952 info->input_signal_events.dsr_up++;
1953 else
1954 info->input_signal_events.dsr_down++;
1955 wake_up_interruptible(&info->status_event_wait_q);
1956 wake_up_interruptible(&info->event_wait_q);
1957 info->pending_bh |= BH_STATUS;
1958 }
1959
1960 static void cts_change(struct slgt_info *info)
1961 {
1962 get_signals(info);
1963 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1964 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1965 slgt_irq_off(info, IRQ_CTS);
1966 return;
1967 }
1968 info->icount.cts++;
1969 if (info->signals & SerialSignal_CTS)
1970 info->input_signal_events.cts_up++;
1971 else
1972 info->input_signal_events.cts_down++;
1973 wake_up_interruptible(&info->status_event_wait_q);
1974 wake_up_interruptible(&info->event_wait_q);
1975 info->pending_bh |= BH_STATUS;
1976
1977 if (info->flags & ASYNC_CTS_FLOW) {
1978 if (info->tty) {
1979 if (info->tty->hw_stopped) {
1980 if (info->signals & SerialSignal_CTS) {
1981 info->tty->hw_stopped = 0;
1982 info->pending_bh |= BH_TRANSMIT;
1983 return;
1984 }
1985 } else {
1986 if (!(info->signals & SerialSignal_CTS))
1987 info->tty->hw_stopped = 1;
1988 }
1989 }
1990 }
1991 }
1992
1993 static void dcd_change(struct slgt_info *info)
1994 {
1995 get_signals(info);
1996 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1997 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1998 slgt_irq_off(info, IRQ_DCD);
1999 return;
2000 }
2001 info->icount.dcd++;
2002 if (info->signals & SerialSignal_DCD) {
2003 info->input_signal_events.dcd_up++;
2004 } else {
2005 info->input_signal_events.dcd_down++;
2006 }
2007 #if SYNCLINK_GENERIC_HDLC
2008 if (info->netcount) {
2009 if (info->signals & SerialSignal_DCD)
2010 netif_carrier_on(info->netdev);
2011 else
2012 netif_carrier_off(info->netdev);
2013 }
2014 #endif
2015 wake_up_interruptible(&info->status_event_wait_q);
2016 wake_up_interruptible(&info->event_wait_q);
2017 info->pending_bh |= BH_STATUS;
2018
2019 if (info->flags & ASYNC_CHECK_CD) {
2020 if (info->signals & SerialSignal_DCD)
2021 wake_up_interruptible(&info->open_wait);
2022 else {
2023 if (info->tty)
2024 tty_hangup(info->tty);
2025 }
2026 }
2027 }
2028
2029 static void ri_change(struct slgt_info *info)
2030 {
2031 get_signals(info);
2032 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2033 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2034 slgt_irq_off(info, IRQ_RI);
2035 return;
2036 }
2037 info->icount.dcd++;
2038 if (info->signals & SerialSignal_RI) {
2039 info->input_signal_events.ri_up++;
2040 } else {
2041 info->input_signal_events.ri_down++;
2042 }
2043 wake_up_interruptible(&info->status_event_wait_q);
2044 wake_up_interruptible(&info->event_wait_q);
2045 info->pending_bh |= BH_STATUS;
2046 }
2047
2048 static void isr_serial(struct slgt_info *info)
2049 {
2050 unsigned short status = rd_reg16(info, SSR);
2051
2052 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2053
2054 wr_reg16(info, SSR, status); /* clear pending */
2055
2056 info->irq_occurred = 1;
2057
2058 if (info->params.mode == MGSL_MODE_ASYNC) {
2059 if (status & IRQ_TXIDLE) {
2060 if (info->tx_count)
2061 isr_txeom(info, status);
2062 }
2063 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2064 info->icount.brk++;
2065 /* process break detection if tty control allows */
2066 if (info->tty) {
2067 if (!(status & info->ignore_status_mask)) {
2068 if (info->read_status_mask & MASK_BREAK) {
2069 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
2070 if (info->flags & ASYNC_SAK)
2071 do_SAK(info->tty);
2072 }
2073 }
2074 }
2075 }
2076 } else {
2077 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2078 isr_txeom(info, status);
2079
2080 if (status & IRQ_RXIDLE) {
2081 if (status & RXIDLE)
2082 info->icount.rxidle++;
2083 else
2084 info->icount.exithunt++;
2085 wake_up_interruptible(&info->event_wait_q);
2086 }
2087
2088 if (status & IRQ_RXOVER)
2089 rx_start(info);
2090 }
2091
2092 if (status & IRQ_DSR)
2093 dsr_change(info);
2094 if (status & IRQ_CTS)
2095 cts_change(info);
2096 if (status & IRQ_DCD)
2097 dcd_change(info);
2098 if (status & IRQ_RI)
2099 ri_change(info);
2100 }
2101
2102 static void isr_rdma(struct slgt_info *info)
2103 {
2104 unsigned int status = rd_reg32(info, RDCSR);
2105
2106 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2107
2108 /* RDCSR (rx DMA control/status)
2109 *
2110 * 31..07 reserved
2111 * 06 save status byte to DMA buffer
2112 * 05 error
2113 * 04 eol (end of list)
2114 * 03 eob (end of buffer)
2115 * 02 IRQ enable
2116 * 01 reset
2117 * 00 enable
2118 */
2119 wr_reg32(info, RDCSR, status); /* clear pending */
2120
2121 if (status & (BIT5 + BIT4)) {
2122 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2123 info->rx_restart = 1;
2124 }
2125 info->pending_bh |= BH_RECEIVE;
2126 }
2127
2128 static void isr_tdma(struct slgt_info *info)
2129 {
2130 unsigned int status = rd_reg32(info, TDCSR);
2131
2132 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2133
2134 /* TDCSR (tx DMA control/status)
2135 *
2136 * 31..06 reserved
2137 * 05 error
2138 * 04 eol (end of list)
2139 * 03 eob (end of buffer)
2140 * 02 IRQ enable
2141 * 01 reset
2142 * 00 enable
2143 */
2144 wr_reg32(info, TDCSR, status); /* clear pending */
2145
2146 if (status & (BIT5 + BIT4 + BIT3)) {
2147 // another transmit buffer has completed
2148 // run bottom half to get more send data from user
2149 info->pending_bh |= BH_TRANSMIT;
2150 }
2151 }
2152
2153 static void isr_txeom(struct slgt_info *info, unsigned short status)
2154 {
2155 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2156
2157 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2158 tdma_reset(info);
2159 reset_tbufs(info);
2160 if (status & IRQ_TXUNDER) {
2161 unsigned short val = rd_reg16(info, TCR);
2162 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2163 wr_reg16(info, TCR, val); /* clear reset bit */
2164 }
2165
2166 if (info->tx_active) {
2167 if (info->params.mode != MGSL_MODE_ASYNC) {
2168 if (status & IRQ_TXUNDER)
2169 info->icount.txunder++;
2170 else if (status & IRQ_TXIDLE)
2171 info->icount.txok++;
2172 }
2173
2174 info->tx_active = 0;
2175 info->tx_count = 0;
2176
2177 del_timer(&info->tx_timer);
2178
2179 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2180 info->signals &= ~SerialSignal_RTS;
2181 info->drop_rts_on_tx_done = 0;
2182 set_signals(info);
2183 }
2184
2185 #if SYNCLINK_GENERIC_HDLC
2186 if (info->netcount)
2187 hdlcdev_tx_done(info);
2188 else
2189 #endif
2190 {
2191 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2192 tx_stop(info);
2193 return;
2194 }
2195 info->pending_bh |= BH_TRANSMIT;
2196 }
2197 }
2198 }
2199
2200 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2201 {
2202 struct cond_wait *w, *prev;
2203
2204 /* wake processes waiting for specific transitions */
2205 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2206 if (w->data & changed) {
2207 w->data = state;
2208 wake_up_interruptible(&w->q);
2209 if (prev != NULL)
2210 prev->next = w->next;
2211 else
2212 info->gpio_wait_q = w->next;
2213 } else
2214 prev = w;
2215 }
2216 }
2217
2218 /* interrupt service routine
2219 *
2220 * irq interrupt number
2221 * dev_id device ID supplied during interrupt registration
2222 */
2223 static irqreturn_t slgt_interrupt(int irq, void *dev_id)
2224 {
2225 struct slgt_info *info;
2226 unsigned int gsr;
2227 unsigned int i;
2228
2229 DBGISR(("slgt_interrupt irq=%d entry\n", irq));
2230
2231 info = dev_id;
2232 if (!info)
2233 return IRQ_NONE;
2234
2235 spin_lock(&info->lock);
2236
2237 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2238 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2239 info->irq_occurred = 1;
2240 for(i=0; i < info->port_count ; i++) {
2241 if (info->port_array[i] == NULL)
2242 continue;
2243 if (gsr & (BIT8 << i))
2244 isr_serial(info->port_array[i]);
2245 if (gsr & (BIT16 << (i*2)))
2246 isr_rdma(info->port_array[i]);
2247 if (gsr & (BIT17 << (i*2)))
2248 isr_tdma(info->port_array[i]);
2249 }
2250 }
2251
2252 if (info->gpio_present) {
2253 unsigned int state;
2254 unsigned int changed;
2255 while ((changed = rd_reg32(info, IOSR)) != 0) {
2256 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2257 /* read latched state of GPIO signals */
2258 state = rd_reg32(info, IOVR);
2259 /* clear pending GPIO interrupt bits */
2260 wr_reg32(info, IOSR, changed);
2261 for (i=0 ; i < info->port_count ; i++) {
2262 if (info->port_array[i] != NULL)
2263 isr_gpio(info->port_array[i], changed, state);
2264 }
2265 }
2266 }
2267
2268 for(i=0; i < info->port_count ; i++) {
2269 struct slgt_info *port = info->port_array[i];
2270
2271 if (port && (port->count || port->netcount) &&
2272 port->pending_bh && !port->bh_running &&
2273 !port->bh_requested) {
2274 DBGISR(("%s bh queued\n", port->device_name));
2275 schedule_work(&port->task);
2276 port->bh_requested = 1;
2277 }
2278 }
2279
2280 spin_unlock(&info->lock);
2281
2282 DBGISR(("slgt_interrupt irq=%d exit\n", irq));
2283 return IRQ_HANDLED;
2284 }
2285
2286 static int startup(struct slgt_info *info)
2287 {
2288 DBGINFO(("%s startup\n", info->device_name));
2289
2290 if (info->flags & ASYNC_INITIALIZED)
2291 return 0;
2292
2293 if (!info->tx_buf) {
2294 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2295 if (!info->tx_buf) {
2296 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2297 return -ENOMEM;
2298 }
2299 }
2300
2301 info->pending_bh = 0;
2302
2303 memset(&info->icount, 0, sizeof(info->icount));
2304
2305 /* program hardware for current parameters */
2306 change_params(info);
2307
2308 if (info->tty)
2309 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2310
2311 info->flags |= ASYNC_INITIALIZED;
2312
2313 return 0;
2314 }
2315
2316 /*
2317 * called by close() and hangup() to shutdown hardware
2318 */
2319 static void shutdown(struct slgt_info *info)
2320 {
2321 unsigned long flags;
2322
2323 if (!(info->flags & ASYNC_INITIALIZED))
2324 return;
2325
2326 DBGINFO(("%s shutdown\n", info->device_name));
2327
2328 /* clear status wait queue because status changes */
2329 /* can't happen after shutting down the hardware */
2330 wake_up_interruptible(&info->status_event_wait_q);
2331 wake_up_interruptible(&info->event_wait_q);
2332
2333 del_timer_sync(&info->tx_timer);
2334 del_timer_sync(&info->rx_timer);
2335
2336 kfree(info->tx_buf);
2337 info->tx_buf = NULL;
2338
2339 spin_lock_irqsave(&info->lock,flags);
2340
2341 tx_stop(info);
2342 rx_stop(info);
2343
2344 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2345
2346 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2347 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2348 set_signals(info);
2349 }
2350
2351 flush_cond_wait(&info->gpio_wait_q);
2352
2353 spin_unlock_irqrestore(&info->lock,flags);
2354
2355 if (info->tty)
2356 set_bit(TTY_IO_ERROR, &info->tty->flags);
2357
2358 info->flags &= ~ASYNC_INITIALIZED;
2359 }
2360
2361 static void program_hw(struct slgt_info *info)
2362 {
2363 unsigned long flags;
2364
2365 spin_lock_irqsave(&info->lock,flags);
2366
2367 rx_stop(info);
2368 tx_stop(info);
2369
2370 if (info->params.mode != MGSL_MODE_ASYNC ||
2371 info->netcount)
2372 sync_mode(info);
2373 else
2374 async_mode(info);
2375
2376 set_signals(info);
2377
2378 info->dcd_chkcount = 0;
2379 info->cts_chkcount = 0;
2380 info->ri_chkcount = 0;
2381 info->dsr_chkcount = 0;
2382
2383 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2384 get_signals(info);
2385
2386 if (info->netcount ||
2387 (info->tty && info->tty->termios->c_cflag & CREAD))
2388 rx_start(info);
2389
2390 spin_unlock_irqrestore(&info->lock,flags);
2391 }
2392
2393 /*
2394 * reconfigure adapter based on new parameters
2395 */
2396 static void change_params(struct slgt_info *info)
2397 {
2398 unsigned cflag;
2399 int bits_per_char;
2400
2401 if (!info->tty || !info->tty->termios)
2402 return;
2403 DBGINFO(("%s change_params\n", info->device_name));
2404
2405 cflag = info->tty->termios->c_cflag;
2406
2407 /* if B0 rate (hangup) specified then negate DTR and RTS */
2408 /* otherwise assert DTR and RTS */
2409 if (cflag & CBAUD)
2410 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2411 else
2412 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2413
2414 /* byte size and parity */
2415
2416 switch (cflag & CSIZE) {
2417 case CS5: info->params.data_bits = 5; break;
2418 case CS6: info->params.data_bits = 6; break;
2419 case CS7: info->params.data_bits = 7; break;
2420 case CS8: info->params.data_bits = 8; break;
2421 default: info->params.data_bits = 7; break;
2422 }
2423
2424 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2425
2426 if (cflag & PARENB)
2427 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2428 else
2429 info->params.parity = ASYNC_PARITY_NONE;
2430
2431 /* calculate number of jiffies to transmit a full
2432 * FIFO (32 bytes) at specified data rate
2433 */
2434 bits_per_char = info->params.data_bits +
2435 info->params.stop_bits + 1;
2436
2437 info->params.data_rate = tty_get_baud_rate(info->tty);
2438
2439 if (info->params.data_rate) {
2440 info->timeout = (32*HZ*bits_per_char) /
2441 info->params.data_rate;
2442 }
2443 info->timeout += HZ/50; /* Add .02 seconds of slop */
2444
2445 if (cflag & CRTSCTS)
2446 info->flags |= ASYNC_CTS_FLOW;
2447 else
2448 info->flags &= ~ASYNC_CTS_FLOW;
2449
2450 if (cflag & CLOCAL)
2451 info->flags &= ~ASYNC_CHECK_CD;
2452 else
2453 info->flags |= ASYNC_CHECK_CD;
2454
2455 /* process tty input control flags */
2456
2457 info->read_status_mask = IRQ_RXOVER;
2458 if (I_INPCK(info->tty))
2459 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2460 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2461 info->read_status_mask |= MASK_BREAK;
2462 if (I_IGNPAR(info->tty))
2463 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2464 if (I_IGNBRK(info->tty)) {
2465 info->ignore_status_mask |= MASK_BREAK;
2466 /* If ignoring parity and break indicators, ignore
2467 * overruns too. (For real raw support).
2468 */
2469 if (I_IGNPAR(info->tty))
2470 info->ignore_status_mask |= MASK_OVERRUN;
2471 }
2472
2473 program_hw(info);
2474 }
2475
2476 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2477 {
2478 DBGINFO(("%s get_stats\n", info->device_name));
2479 if (!user_icount) {
2480 memset(&info->icount, 0, sizeof(info->icount));
2481 } else {
2482 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2483 return -EFAULT;
2484 }
2485 return 0;
2486 }
2487
2488 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2489 {
2490 DBGINFO(("%s get_params\n", info->device_name));
2491 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2492 return -EFAULT;
2493 return 0;
2494 }
2495
2496 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2497 {
2498 unsigned long flags;
2499 MGSL_PARAMS tmp_params;
2500
2501 DBGINFO(("%s set_params\n", info->device_name));
2502 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2503 return -EFAULT;
2504
2505 spin_lock_irqsave(&info->lock, flags);
2506 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2507 spin_unlock_irqrestore(&info->lock, flags);
2508
2509 change_params(info);
2510
2511 return 0;
2512 }
2513
2514 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2515 {
2516 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2517 if (put_user(info->idle_mode, idle_mode))
2518 return -EFAULT;
2519 return 0;
2520 }
2521
2522 static int set_txidle(struct slgt_info *info, int idle_mode)
2523 {
2524 unsigned long flags;
2525 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2526 spin_lock_irqsave(&info->lock,flags);
2527 info->idle_mode = idle_mode;
2528 if (info->params.mode != MGSL_MODE_ASYNC)
2529 tx_set_idle(info);
2530 spin_unlock_irqrestore(&info->lock,flags);
2531 return 0;
2532 }
2533
2534 static int tx_enable(struct slgt_info *info, int enable)
2535 {
2536 unsigned long flags;
2537 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2538 spin_lock_irqsave(&info->lock,flags);
2539 if (enable) {
2540 if (!info->tx_enabled)
2541 tx_start(info);
2542 } else {
2543 if (info->tx_enabled)
2544 tx_stop(info);
2545 }
2546 spin_unlock_irqrestore(&info->lock,flags);
2547 return 0;
2548 }
2549
2550 /*
2551 * abort transmit HDLC frame
2552 */
2553 static int tx_abort(struct slgt_info *info)
2554 {
2555 unsigned long flags;
2556 DBGINFO(("%s tx_abort\n", info->device_name));
2557 spin_lock_irqsave(&info->lock,flags);
2558 tdma_reset(info);
2559 spin_unlock_irqrestore(&info->lock,flags);
2560 return 0;
2561 }
2562
2563 static int rx_enable(struct slgt_info *info, int enable)
2564 {
2565 unsigned long flags;
2566 DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2567 spin_lock_irqsave(&info->lock,flags);
2568 if (enable) {
2569 if (!info->rx_enabled)
2570 rx_start(info);
2571 else if (enable == 2) {
2572 /* force hunt mode (write 1 to RCR[3]) */
2573 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2574 }
2575 } else {
2576 if (info->rx_enabled)
2577 rx_stop(info);
2578 }
2579 spin_unlock_irqrestore(&info->lock,flags);
2580 return 0;
2581 }
2582
2583 /*
2584 * wait for specified event to occur
2585 */
2586 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2587 {
2588 unsigned long flags;
2589 int s;
2590 int rc=0;
2591 struct mgsl_icount cprev, cnow;
2592 int events;
2593 int mask;
2594 struct _input_signal_events oldsigs, newsigs;
2595 DECLARE_WAITQUEUE(wait, current);
2596
2597 if (get_user(mask, mask_ptr))
2598 return -EFAULT;
2599
2600 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2601
2602 spin_lock_irqsave(&info->lock,flags);
2603
2604 /* return immediately if state matches requested events */
2605 get_signals(info);
2606 s = info->signals;
2607
2608 events = mask &
2609 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2610 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2611 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2612 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2613 if (events) {
2614 spin_unlock_irqrestore(&info->lock,flags);
2615 goto exit;
2616 }
2617
2618 /* save current irq counts */
2619 cprev = info->icount;
2620 oldsigs = info->input_signal_events;
2621
2622 /* enable hunt and idle irqs if needed */
2623 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2624 unsigned short val = rd_reg16(info, SCR);
2625 if (!(val & IRQ_RXIDLE))
2626 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2627 }
2628
2629 set_current_state(TASK_INTERRUPTIBLE);
2630 add_wait_queue(&info->event_wait_q, &wait);
2631
2632 spin_unlock_irqrestore(&info->lock,flags);
2633
2634 for(;;) {
2635 schedule();
2636 if (signal_pending(current)) {
2637 rc = -ERESTARTSYS;
2638 break;
2639 }
2640
2641 /* get current irq counts */
2642 spin_lock_irqsave(&info->lock,flags);
2643 cnow = info->icount;
2644 newsigs = info->input_signal_events;
2645 set_current_state(TASK_INTERRUPTIBLE);
2646 spin_unlock_irqrestore(&info->lock,flags);
2647
2648 /* if no change, wait aborted for some reason */
2649 if (newsigs.dsr_up == oldsigs.dsr_up &&
2650 newsigs.dsr_down == oldsigs.dsr_down &&
2651 newsigs.dcd_up == oldsigs.dcd_up &&
2652 newsigs.dcd_down == oldsigs.dcd_down &&
2653 newsigs.cts_up == oldsigs.cts_up &&
2654 newsigs.cts_down == oldsigs.cts_down &&
2655 newsigs.ri_up == oldsigs.ri_up &&
2656 newsigs.ri_down == oldsigs.ri_down &&
2657 cnow.exithunt == cprev.exithunt &&
2658 cnow.rxidle == cprev.rxidle) {
2659 rc = -EIO;
2660 break;
2661 }
2662
2663 events = mask &
2664 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2665 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2666 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2667 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2668 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2669 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2670 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2671 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2672 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2673 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2674 if (events)
2675 break;
2676
2677 cprev = cnow;
2678 oldsigs = newsigs;
2679 }
2680
2681 remove_wait_queue(&info->event_wait_q, &wait);
2682 set_current_state(TASK_RUNNING);
2683
2684
2685 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2686 spin_lock_irqsave(&info->lock,flags);
2687 if (!waitqueue_active(&info->event_wait_q)) {
2688 /* disable enable exit hunt mode/idle rcvd IRQs */
2689 wr_reg16(info, SCR,
2690 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2691 }
2692 spin_unlock_irqrestore(&info->lock,flags);
2693 }
2694 exit:
2695 if (rc == 0)
2696 rc = put_user(events, mask_ptr);
2697 return rc;
2698 }
2699
2700 static int get_interface(struct slgt_info *info, int __user *if_mode)
2701 {
2702 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2703 if (put_user(info->if_mode, if_mode))
2704 return -EFAULT;
2705 return 0;
2706 }
2707
2708 static int set_interface(struct slgt_info *info, int if_mode)
2709 {
2710 unsigned long flags;
2711 unsigned short val;
2712
2713 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2714 spin_lock_irqsave(&info->lock,flags);
2715 info->if_mode = if_mode;
2716
2717 msc_set_vcr(info);
2718
2719 /* TCR (tx control) 07 1=RTS driver control */
2720 val = rd_reg16(info, TCR);
2721 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2722 val |= BIT7;
2723 else
2724 val &= ~BIT7;
2725 wr_reg16(info, TCR, val);
2726
2727 spin_unlock_irqrestore(&info->lock,flags);
2728 return 0;
2729 }
2730
2731 /*
2732 * set general purpose IO pin state and direction
2733 *
2734 * user_gpio fields:
2735 * state each bit indicates a pin state
2736 * smask set bit indicates pin state to set
2737 * dir each bit indicates a pin direction (0=input, 1=output)
2738 * dmask set bit indicates pin direction to set
2739 */
2740 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2741 {
2742 unsigned long flags;
2743 struct gpio_desc gpio;
2744 __u32 data;
2745
2746 if (!info->gpio_present)
2747 return -EINVAL;
2748 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2749 return -EFAULT;
2750 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2751 info->device_name, gpio.state, gpio.smask,
2752 gpio.dir, gpio.dmask));
2753
2754 spin_lock_irqsave(&info->lock,flags);
2755 if (gpio.dmask) {
2756 data = rd_reg32(info, IODR);
2757 data |= gpio.dmask & gpio.dir;
2758 data &= ~(gpio.dmask & ~gpio.dir);
2759 wr_reg32(info, IODR, data);
2760 }
2761 if (gpio.smask) {
2762 data = rd_reg32(info, IOVR);
2763 data |= gpio.smask & gpio.state;
2764 data &= ~(gpio.smask & ~gpio.state);
2765 wr_reg32(info, IOVR, data);
2766 }
2767 spin_unlock_irqrestore(&info->lock,flags);
2768
2769 return 0;
2770 }
2771
2772 /*
2773 * get general purpose IO pin state and direction
2774 */
2775 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2776 {
2777 struct gpio_desc gpio;
2778 if (!info->gpio_present)
2779 return -EINVAL;
2780 gpio.state = rd_reg32(info, IOVR);
2781 gpio.smask = 0xffffffff;
2782 gpio.dir = rd_reg32(info, IODR);
2783 gpio.dmask = 0xffffffff;
2784 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2785 return -EFAULT;
2786 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2787 info->device_name, gpio.state, gpio.dir));
2788 return 0;
2789 }
2790
2791 /*
2792 * conditional wait facility
2793 */
2794 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2795 {
2796 init_waitqueue_head(&w->q);
2797 init_waitqueue_entry(&w->wait, current);
2798 w->data = data;
2799 }
2800
2801 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2802 {
2803 set_current_state(TASK_INTERRUPTIBLE);
2804 add_wait_queue(&w->q, &w->wait);
2805 w->next = *head;
2806 *head = w;
2807 }
2808
2809 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2810 {
2811 struct cond_wait *w, *prev;
2812 remove_wait_queue(&cw->q, &cw->wait);
2813 set_current_state(TASK_RUNNING);
2814 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2815 if (w == cw) {
2816 if (prev != NULL)
2817 prev->next = w->next;
2818 else
2819 *head = w->next;
2820 break;
2821 }
2822 }
2823 }
2824
2825 static void flush_cond_wait(struct cond_wait **head)
2826 {
2827 while (*head != NULL) {
2828 wake_up_interruptible(&(*head)->q);
2829 *head = (*head)->next;
2830 }
2831 }
2832
2833 /*
2834 * wait for general purpose I/O pin(s) to enter specified state
2835 *
2836 * user_gpio fields:
2837 * state - bit indicates target pin state
2838 * smask - set bit indicates watched pin
2839 *
2840 * The wait ends when at least one watched pin enters the specified
2841 * state. When 0 (no error) is returned, user_gpio->state is set to the
2842 * state of all GPIO pins when the wait ends.
2843 *
2844 * Note: Each pin may be a dedicated input, dedicated output, or
2845 * configurable input/output. The number and configuration of pins
2846 * varies with the specific adapter model. Only input pins (dedicated
2847 * or configured) can be monitored with this function.
2848 */
2849 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2850 {
2851 unsigned long flags;
2852 int rc = 0;
2853 struct gpio_desc gpio;
2854 struct cond_wait wait;
2855 u32 state;
2856
2857 if (!info->gpio_present)
2858 return -EINVAL;
2859 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2860 return -EFAULT;
2861 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2862 info->device_name, gpio.state, gpio.smask));
2863 /* ignore output pins identified by set IODR bit */
2864 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2865 return -EINVAL;
2866 init_cond_wait(&wait, gpio.smask);
2867
2868 spin_lock_irqsave(&info->lock, flags);
2869 /* enable interrupts for watched pins */
2870 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2871 /* get current pin states */
2872 state = rd_reg32(info, IOVR);
2873
2874 if (gpio.smask & ~(state ^ gpio.state)) {
2875 /* already in target state */
2876 gpio.state = state;
2877 } else {
2878 /* wait for target state */
2879 add_cond_wait(&info->gpio_wait_q, &wait);
2880 spin_unlock_irqrestore(&info->lock, flags);
2881 schedule();
2882 if (signal_pending(current))
2883 rc = -ERESTARTSYS;
2884 else
2885 gpio.state = wait.data;
2886 spin_lock_irqsave(&info->lock, flags);
2887 remove_cond_wait(&info->gpio_wait_q, &wait);
2888 }
2889
2890 /* disable all GPIO interrupts if no waiting processes */
2891 if (info->gpio_wait_q == NULL)
2892 wr_reg32(info, IOER, 0);
2893 spin_unlock_irqrestore(&info->lock,flags);
2894
2895 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2896 rc = -EFAULT;
2897 return rc;
2898 }
2899
2900 static int modem_input_wait(struct slgt_info *info,int arg)
2901 {
2902 unsigned long flags;
2903 int rc;
2904 struct mgsl_icount cprev, cnow;
2905 DECLARE_WAITQUEUE(wait, current);
2906
2907 /* save current irq counts */
2908 spin_lock_irqsave(&info->lock,flags);
2909 cprev = info->icount;
2910 add_wait_queue(&info->status_event_wait_q, &wait);
2911 set_current_state(TASK_INTERRUPTIBLE);
2912 spin_unlock_irqrestore(&info->lock,flags);
2913
2914 for(;;) {
2915 schedule();
2916 if (signal_pending(current)) {
2917 rc = -ERESTARTSYS;
2918 break;
2919 }
2920
2921 /* get new irq counts */
2922 spin_lock_irqsave(&info->lock,flags);
2923 cnow = info->icount;
2924 set_current_state(TASK_INTERRUPTIBLE);
2925 spin_unlock_irqrestore(&info->lock,flags);
2926
2927 /* if no change, wait aborted for some reason */
2928 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2929 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2930 rc = -EIO;
2931 break;
2932 }
2933
2934 /* check for change in caller specified modem input */
2935 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2936 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2937 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2938 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2939 rc = 0;
2940 break;
2941 }
2942
2943 cprev = cnow;
2944 }
2945 remove_wait_queue(&info->status_event_wait_q, &wait);
2946 set_current_state(TASK_RUNNING);
2947 return rc;
2948 }
2949
2950 /*
2951 * return state of serial control and status signals
2952 */
2953 static int tiocmget(struct tty_struct *tty, struct file *file)
2954 {
2955 struct slgt_info *info = tty->driver_data;
2956 unsigned int result;
2957 unsigned long flags;
2958
2959 spin_lock_irqsave(&info->lock,flags);
2960 get_signals(info);
2961 spin_unlock_irqrestore(&info->lock,flags);
2962
2963 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2964 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2965 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2966 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2967 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2968 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2969
2970 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
2971 return result;
2972 }
2973
2974 /*
2975 * set modem control signals (DTR/RTS)
2976 *
2977 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
2978 * TIOCMSET = set/clear signal values
2979 * value bit mask for command
2980 */
2981 static int tiocmset(struct tty_struct *tty, struct file *file,
2982 unsigned int set, unsigned int clear)
2983 {
2984 struct slgt_info *info = tty->driver_data;
2985 unsigned long flags;
2986
2987 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
2988
2989 if (set & TIOCM_RTS)
2990 info->signals |= SerialSignal_RTS;
2991 if (set & TIOCM_DTR)
2992 info->signals |= SerialSignal_DTR;
2993 if (clear & TIOCM_RTS)
2994 info->signals &= ~SerialSignal_RTS;
2995 if (clear & TIOCM_DTR)
2996 info->signals &= ~SerialSignal_DTR;
2997
2998 spin_lock_irqsave(&info->lock,flags);
2999 set_signals(info);
3000 spin_unlock_irqrestore(&info->lock,flags);
3001 return 0;
3002 }
3003
3004 /*
3005 * block current process until the device is ready to open
3006 */
3007 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3008 struct slgt_info *info)
3009 {
3010 DECLARE_WAITQUEUE(wait, current);
3011 int retval;
3012 int do_clocal = 0, extra_count = 0;
3013 unsigned long flags;
3014
3015 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3016
3017 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3018 /* nonblock mode is set or port is not enabled */
3019 info->flags |= ASYNC_NORMAL_ACTIVE;
3020 return 0;
3021 }
3022
3023 if (tty->termios->c_cflag & CLOCAL)
3024 do_clocal = 1;
3025
3026 /* Wait for carrier detect and the line to become
3027 * free (i.e., not in use by the callout). While we are in
3028 * this loop, info->count is dropped by one, so that
3029 * close() knows when to free things. We restore it upon
3030 * exit, either normal or abnormal.
3031 */
3032
3033 retval = 0;
3034 add_wait_queue(&info->open_wait, &wait);
3035
3036 spin_lock_irqsave(&info->lock, flags);
3037 if (!tty_hung_up_p(filp)) {
3038 extra_count = 1;
3039 info->count--;
3040 }
3041 spin_unlock_irqrestore(&info->lock, flags);
3042 info->blocked_open++;
3043
3044 while (1) {
3045 if ((tty->termios->c_cflag & CBAUD)) {
3046 spin_lock_irqsave(&info->lock,flags);
3047 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3048 set_signals(info);
3049 spin_unlock_irqrestore(&info->lock,flags);
3050 }
3051
3052 set_current_state(TASK_INTERRUPTIBLE);
3053
3054 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3055 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3056 -EAGAIN : -ERESTARTSYS;
3057 break;
3058 }
3059
3060 spin_lock_irqsave(&info->lock,flags);
3061 get_signals(info);
3062 spin_unlock_irqrestore(&info->lock,flags);
3063
3064 if (!(info->flags & ASYNC_CLOSING) &&
3065 (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3066 break;
3067 }
3068
3069 if (signal_pending(current)) {
3070 retval = -ERESTARTSYS;
3071 break;
3072 }
3073
3074 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3075 schedule();
3076 }
3077
3078 set_current_state(TASK_RUNNING);
3079 remove_wait_queue(&info->open_wait, &wait);
3080
3081 if (extra_count)
3082 info->count++;
3083 info->blocked_open--;
3084
3085 if (!retval)
3086 info->flags |= ASYNC_NORMAL_ACTIVE;
3087
3088 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3089 return retval;
3090 }
3091
3092 static int alloc_tmp_rbuf(struct slgt_info *info)
3093 {
3094 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3095 if (info->tmp_rbuf == NULL)
3096 return -ENOMEM;
3097 return 0;
3098 }
3099
3100 static void free_tmp_rbuf(struct slgt_info *info)
3101 {
3102 kfree(info->tmp_rbuf);
3103 info->tmp_rbuf = NULL;
3104 }
3105
3106 /*
3107 * allocate DMA descriptor lists.
3108 */
3109 static int alloc_desc(struct slgt_info *info)
3110 {
3111 unsigned int i;
3112 unsigned int pbufs;
3113
3114 /* allocate memory to hold descriptor lists */
3115 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3116 if (info->bufs == NULL)
3117 return -ENOMEM;
3118
3119 memset(info->bufs, 0, DESC_LIST_SIZE);
3120
3121 info->rbufs = (struct slgt_desc*)info->bufs;
3122 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3123
3124 pbufs = (unsigned int)info->bufs_dma_addr;
3125
3126 /*
3127 * Build circular lists of descriptors
3128 */
3129
3130 for (i=0; i < info->rbuf_count; i++) {
3131 /* physical address of this descriptor */
3132 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3133
3134 /* physical address of next descriptor */
3135 if (i == info->rbuf_count - 1)
3136 info->rbufs[i].next = cpu_to_le32(pbufs);
3137 else
3138 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3139 set_desc_count(info->rbufs[i], DMABUFSIZE);
3140 }
3141
3142 for (i=0; i < info->tbuf_count; i++) {
3143 /* physical address of this descriptor */
3144 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3145
3146 /* physical address of next descriptor */
3147 if (i == info->tbuf_count - 1)
3148 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3149 else
3150 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3151 }
3152
3153 return 0;
3154 }
3155
3156 static void free_desc(struct slgt_info *info)
3157 {
3158 if (info->bufs != NULL) {
3159 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3160 info->bufs = NULL;
3161 info->rbufs = NULL;
3162 info->tbufs = NULL;
3163 }
3164 }
3165
3166 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3167 {
3168 int i;
3169 for (i=0; i < count; i++) {
3170 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3171 return -ENOMEM;
3172 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3173 }
3174 return 0;
3175 }
3176
3177 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3178 {
3179 int i;
3180 for (i=0; i < count; i++) {
3181 if (bufs[i].buf == NULL)
3182 continue;
3183 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3184 bufs[i].buf = NULL;
3185 }
3186 }
3187
3188 static int alloc_dma_bufs(struct slgt_info *info)
3189 {
3190 info->rbuf_count = 32;
3191 info->tbuf_count = 32;
3192
3193 if (alloc_desc(info) < 0 ||
3194 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3195 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3196 alloc_tmp_rbuf(info) < 0) {
3197 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3198 return -ENOMEM;
3199 }
3200 reset_rbufs(info);
3201 return 0;
3202 }
3203
3204 static void free_dma_bufs(struct slgt_info *info)
3205 {
3206 if (info->bufs) {
3207 free_bufs(info, info->rbufs, info->rbuf_count);
3208 free_bufs(info, info->tbufs, info->tbuf_count);
3209 free_desc(info);
3210 }
3211 free_tmp_rbuf(info);
3212 }
3213
3214 static int claim_resources(struct slgt_info *info)
3215 {
3216 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3217 DBGERR(("%s reg addr conflict, addr=%08X\n",
3218 info->device_name, info->phys_reg_addr));
3219 info->init_error = DiagStatus_AddressConflict;
3220 goto errout;
3221 }
3222 else
3223 info->reg_addr_requested = 1;
3224
3225 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3226 if (!info->reg_addr) {
3227 DBGERR(("%s cant map device registers, addr=%08X\n",
3228 info->device_name, info->phys_reg_addr));
3229 info->init_error = DiagStatus_CantAssignPciResources;
3230 goto errout;
3231 }
3232 return 0;
3233
3234 errout:
3235 release_resources(info);
3236 return -ENODEV;
3237 }
3238
3239 static void release_resources(struct slgt_info *info)
3240 {
3241 if (info->irq_requested) {
3242 free_irq(info->irq_level, info);
3243 info->irq_requested = 0;
3244 }
3245
3246 if (info->reg_addr_requested) {
3247 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3248 info->reg_addr_requested = 0;
3249 }
3250
3251 if (info->reg_addr) {
3252 iounmap(info->reg_addr);
3253 info->reg_addr = NULL;
3254 }
3255 }
3256
3257 /* Add the specified device instance data structure to the
3258 * global linked list of devices and increment the device count.
3259 */
3260 static void add_device(struct slgt_info *info)
3261 {
3262 char *devstr;
3263
3264 info->next_device = NULL;
3265 info->line = slgt_device_count;
3266 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3267
3268 if (info->line < MAX_DEVICES) {
3269 if (maxframe[info->line])
3270 info->max_frame_size = maxframe[info->line];
3271 info->dosyncppp = dosyncppp[info->line];
3272 }
3273
3274 slgt_device_count++;
3275
3276 if (!slgt_device_list)
3277 slgt_device_list = info;
3278 else {
3279 struct slgt_info *current_dev = slgt_device_list;
3280 while(current_dev->next_device)
3281 current_dev = current_dev->next_device;
3282 current_dev->next_device = info;
3283 }
3284
3285 if (info->max_frame_size < 4096)
3286 info->max_frame_size = 4096;
3287 else if (info->max_frame_size > 65535)
3288 info->max_frame_size = 65535;
3289
3290 switch(info->pdev->device) {
3291 case SYNCLINK_GT_DEVICE_ID:
3292 devstr = "GT";
3293 break;
3294 case SYNCLINK_GT2_DEVICE_ID:
3295 devstr = "GT2";
3296 break;
3297 case SYNCLINK_GT4_DEVICE_ID:
3298 devstr = "GT4";
3299 break;
3300 case SYNCLINK_AC_DEVICE_ID:
3301 devstr = "AC";
3302 info->params.mode = MGSL_MODE_ASYNC;
3303 break;
3304 default:
3305 devstr = "(unknown model)";
3306 }
3307 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3308 devstr, info->device_name, info->phys_reg_addr,
3309 info->irq_level, info->max_frame_size);
3310
3311 #if SYNCLINK_GENERIC_HDLC
3312 hdlcdev_init(info);
3313 #endif
3314 }
3315
3316 /*
3317 * allocate device instance structure, return NULL on failure
3318 */
3319 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3320 {
3321 struct slgt_info *info;
3322
3323 info = kmalloc(sizeof(struct slgt_info), GFP_KERNEL);
3324
3325 if (!info) {
3326 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3327 driver_name, adapter_num, port_num));
3328 } else {
3329 memset(info, 0, sizeof(struct slgt_info));
3330 info->magic = MGSL_MAGIC;
3331 INIT_WORK(&info->task, bh_handler);
3332 info->max_frame_size = 4096;
3333 info->raw_rx_size = DMABUFSIZE;
3334 info->close_delay = 5*HZ/10;
3335 info->closing_wait = 30*HZ;
3336 init_waitqueue_head(&info->open_wait);
3337 init_waitqueue_head(&info->close_wait);
3338 init_waitqueue_head(&info->status_event_wait_q);
3339 init_waitqueue_head(&info->event_wait_q);
3340 spin_lock_init(&info->netlock);
3341 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3342 info->idle_mode = HDLC_TXIDLE_FLAGS;
3343 info->adapter_num = adapter_num;
3344 info->port_num = port_num;
3345
3346 init_timer(&info->tx_timer);
3347 info->tx_timer.data = (unsigned long)info;
3348 info->tx_timer.function = tx_timeout;
3349
3350 init_timer(&info->rx_timer);
3351 info->rx_timer.data = (unsigned long)info;
3352 info->rx_timer.function = rx_timeout;
3353
3354 /* Copy configuration info to device instance data */
3355 info->pdev = pdev;
3356 info->irq_level = pdev->irq;
3357 info->phys_reg_addr = pci_resource_start(pdev,0);
3358
3359 info->bus_type = MGSL_BUS_TYPE_PCI;
3360 info->irq_flags = IRQF_SHARED;
3361
3362 info->init_error = -1; /* assume error, set to 0 on successful init */
3363 }
3364
3365 return info;
3366 }
3367
3368 static void device_init(int adapter_num, struct pci_dev *pdev)
3369 {
3370 struct slgt_info *port_array[SLGT_MAX_PORTS];
3371 int i;
3372 int port_count = 1;
3373
3374 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3375 port_count = 2;
3376 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3377 port_count = 4;
3378
3379 /* allocate device instances for all ports */
3380 for (i=0; i < port_count; ++i) {
3381 port_array[i] = alloc_dev(adapter_num, i, pdev);
3382 if (port_array[i] == NULL) {
3383 for (--i; i >= 0; --i)
3384 kfree(port_array[i]);
3385 return;
3386 }
3387 }
3388
3389 /* give copy of port_array to all ports and add to device list */
3390 for (i=0; i < port_count; ++i) {
3391 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3392 add_device(port_array[i]);
3393 port_array[i]->port_count = port_count;
3394 spin_lock_init(&port_array[i]->lock);
3395 }
3396
3397 /* Allocate and claim adapter resources */
3398 if (!claim_resources(port_array[0])) {
3399
3400 alloc_dma_bufs(port_array[0]);
3401
3402 /* copy resource information from first port to others */
3403 for (i = 1; i < port_count; ++i) {
3404 port_array[i]->lock = port_array[0]->lock;
3405 port_array[i]->irq_level = port_array[0]->irq_level;
3406 port_array[i]->reg_addr = port_array[0]->reg_addr;
3407 alloc_dma_bufs(port_array[i]);
3408 }
3409
3410 if (request_irq(port_array[0]->irq_level,
3411 slgt_interrupt,
3412 port_array[0]->irq_flags,
3413 port_array[0]->device_name,
3414 port_array[0]) < 0) {
3415 DBGERR(("%s request_irq failed IRQ=%d\n",
3416 port_array[0]->device_name,
3417 port_array[0]->irq_level));
3418 } else {
3419 port_array[0]->irq_requested = 1;
3420 adapter_test(port_array[0]);
3421 for (i=1 ; i < port_count ; i++) {
3422 port_array[i]->init_error = port_array[0]->init_error;
3423 port_array[i]->gpio_present = port_array[0]->gpio_present;
3424 }
3425 }
3426 }
3427 }
3428
3429 static int __devinit init_one(struct pci_dev *dev,
3430 const struct pci_device_id *ent)
3431 {
3432 if (pci_enable_device(dev)) {
3433 printk("error enabling pci device %p\n", dev);
3434 return -EIO;
3435 }
3436 pci_set_master(dev);
3437 device_init(slgt_device_count, dev);
3438 return 0;
3439 }
3440
3441 static void __devexit remove_one(struct pci_dev *dev)
3442 {
3443 }
3444
3445 static const struct tty_operations ops = {
3446 .open = open,
3447 .close = close,
3448 .write = write,
3449 .put_char = put_char,
3450 .flush_chars = flush_chars,
3451 .write_room = write_room,
3452 .chars_in_buffer = chars_in_buffer,
3453 .flush_buffer = flush_buffer,
3454 .ioctl = ioctl,
3455 .throttle = throttle,
3456 .unthrottle = unthrottle,
3457 .send_xchar = send_xchar,
3458 .break_ctl = set_break,
3459 .wait_until_sent = wait_until_sent,
3460 .read_proc = read_proc,
3461 .set_termios = set_termios,
3462 .stop = tx_hold,
3463 .start = tx_release,
3464 .hangup = hangup,
3465 .tiocmget = tiocmget,
3466 .tiocmset = tiocmset,
3467 };
3468
3469 static void slgt_cleanup(void)
3470 {
3471 int rc;
3472 struct slgt_info *info;
3473 struct slgt_info *tmp;
3474
3475 printk("unload %s %s\n", driver_name, driver_version);
3476
3477 if (serial_driver) {
3478 if ((rc = tty_unregister_driver(serial_driver)))
3479 DBGERR(("tty_unregister_driver error=%d\n", rc));
3480 put_tty_driver(serial_driver);
3481 }
3482
3483 /* reset devices */
3484 info = slgt_device_list;
3485 while(info) {
3486 reset_port(info);
3487 info = info->next_device;
3488 }
3489
3490 /* release devices */
3491 info = slgt_device_list;
3492 while(info) {
3493 #if SYNCLINK_GENERIC_HDLC
3494 hdlcdev_exit(info);
3495 #endif
3496 free_dma_bufs(info);
3497 free_tmp_rbuf(info);
3498 if (info->port_num == 0)
3499 release_resources(info);
3500 tmp = info;
3501 info = info->next_device;
3502 kfree(tmp);
3503 }
3504
3505 if (pci_registered)
3506 pci_unregister_driver(&pci_driver);
3507 }
3508
3509 /*
3510 * Driver initialization entry point.
3511 */
3512 static int __init slgt_init(void)
3513 {
3514 int rc;
3515
3516 printk("%s %s\n", driver_name, driver_version);
3517
3518 slgt_device_count = 0;
3519 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3520 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3521 return rc;
3522 }
3523 pci_registered = 1;
3524
3525 if (!slgt_device_list) {
3526 printk("%s no devices found\n",driver_name);
3527 pci_unregister_driver(&pci_driver);
3528 return -ENODEV;
3529 }
3530
3531 serial_driver = alloc_tty_driver(MAX_DEVICES);
3532 if (!serial_driver) {
3533 rc = -ENOMEM;
3534 goto error;
3535 }
3536
3537 /* Initialize the tty_driver structure */
3538
3539 serial_driver->owner = THIS_MODULE;
3540 serial_driver->driver_name = tty_driver_name;
3541 serial_driver->name = tty_dev_prefix;
3542 serial_driver->major = ttymajor;
3543 serial_driver->minor_start = 64;
3544 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3545 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3546 serial_driver->init_termios = tty_std_termios;
3547 serial_driver->init_termios.c_cflag =
3548 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3549 serial_driver->init_termios.c_ispeed = 9600;
3550 serial_driver->init_termios.c_ospeed = 9600;
3551 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3552 tty_set_operations(serial_driver, &ops);
3553 if ((rc = tty_register_driver(serial_driver)) < 0) {
3554 DBGERR(("%s can't register serial driver\n", driver_name));
3555 put_tty_driver(serial_driver);
3556 serial_driver = NULL;
3557 goto error;
3558 }
3559
3560 printk("%s %s, tty major#%d\n",
3561 driver_name, driver_version,
3562 serial_driver->major);
3563
3564 return 0;
3565
3566 error:
3567 slgt_cleanup();
3568 return rc;
3569 }
3570
3571 static void __exit slgt_exit(void)
3572 {
3573 slgt_cleanup();
3574 }
3575
3576 module_init(slgt_init);
3577 module_exit(slgt_exit);
3578
3579 /*
3580 * register access routines
3581 */
3582
3583 #define CALC_REGADDR() \
3584 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3585 if (addr >= 0x80) \
3586 reg_addr += (info->port_num) * 32;
3587
3588 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3589 {
3590 CALC_REGADDR();
3591 return readb((void __iomem *)reg_addr);
3592 }
3593
3594 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3595 {
3596 CALC_REGADDR();
3597 writeb(value, (void __iomem *)reg_addr);
3598 }
3599
3600 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3601 {
3602 CALC_REGADDR();
3603 return readw((void __iomem *)reg_addr);
3604 }
3605
3606 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3607 {
3608 CALC_REGADDR();
3609 writew(value, (void __iomem *)reg_addr);
3610 }
3611
3612 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3613 {
3614 CALC_REGADDR();
3615 return readl((void __iomem *)reg_addr);
3616 }
3617
3618 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3619 {
3620 CALC_REGADDR();
3621 writel(value, (void __iomem *)reg_addr);
3622 }
3623
3624 static void rdma_reset(struct slgt_info *info)
3625 {
3626 unsigned int i;
3627
3628 /* set reset bit */
3629 wr_reg32(info, RDCSR, BIT1);
3630
3631 /* wait for enable bit cleared */
3632 for(i=0 ; i < 1000 ; i++)
3633 if (!(rd_reg32(info, RDCSR) & BIT0))
3634 break;
3635 }
3636
3637 static void tdma_reset(struct slgt_info *info)
3638 {
3639 unsigned int i;
3640
3641 /* set reset bit */
3642 wr_reg32(info, TDCSR, BIT1);
3643
3644 /* wait for enable bit cleared */
3645 for(i=0 ; i < 1000 ; i++)
3646 if (!(rd_reg32(info, TDCSR) & BIT0))
3647 break;
3648 }
3649
3650 /*
3651 * enable internal loopback
3652 * TxCLK and RxCLK are generated from BRG
3653 * and TxD is looped back to RxD internally.
3654 */
3655 static void enable_loopback(struct slgt_info *info)
3656 {
3657 /* SCR (serial control) BIT2=looopback enable */
3658 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3659
3660 if (info->params.mode != MGSL_MODE_ASYNC) {
3661 /* CCR (clock control)
3662 * 07..05 tx clock source (010 = BRG)
3663 * 04..02 rx clock source (010 = BRG)
3664 * 01 auxclk enable (0 = disable)
3665 * 00 BRG enable (1 = enable)
3666 *
3667 * 0100 1001
3668 */
3669 wr_reg8(info, CCR, 0x49);
3670
3671 /* set speed if available, otherwise use default */
3672 if (info->params.clock_speed)
3673 set_rate(info, info->params.clock_speed);
3674 else
3675 set_rate(info, 3686400);
3676 }
3677 }
3678
3679 /*
3680 * set baud rate generator to specified rate
3681 */
3682 static void set_rate(struct slgt_info *info, u32 rate)
3683 {
3684 unsigned int div;
3685 static unsigned int osc = 14745600;
3686
3687 /* div = osc/rate - 1
3688 *
3689 * Round div up if osc/rate is not integer to
3690 * force to next slowest rate.
3691 */
3692
3693 if (rate) {
3694 div = osc/rate;
3695 if (!(osc % rate) && div)
3696 div--;
3697 wr_reg16(info, BDR, (unsigned short)div);
3698 }
3699 }
3700
3701 static void rx_stop(struct slgt_info *info)
3702 {
3703 unsigned short val;
3704
3705 /* disable and reset receiver */
3706 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3707 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3708 wr_reg16(info, RCR, val); /* clear reset bit */
3709
3710 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3711
3712 /* clear pending rx interrupts */
3713 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3714
3715 rdma_reset(info);
3716
3717 info->rx_enabled = 0;
3718 info->rx_restart = 0;
3719 }
3720
3721 static void rx_start(struct slgt_info *info)
3722 {
3723 unsigned short val;
3724
3725 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3726
3727 /* clear pending rx overrun IRQ */
3728 wr_reg16(info, SSR, IRQ_RXOVER);
3729
3730 /* reset and disable receiver */
3731 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3732 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3733 wr_reg16(info, RCR, val); /* clear reset bit */
3734
3735 rdma_reset(info);
3736 reset_rbufs(info);
3737
3738 /* set 1st descriptor address */
3739 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3740
3741 if (info->params.mode != MGSL_MODE_ASYNC) {
3742 /* enable rx DMA and DMA interrupt */
3743 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3744 } else {
3745 /* enable saving of rx status, rx DMA and DMA interrupt */
3746 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3747 }
3748
3749 slgt_irq_on(info, IRQ_RXOVER);
3750
3751 /* enable receiver */
3752 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3753
3754 info->rx_restart = 0;
3755 info->rx_enabled = 1;
3756 }
3757
3758 static void tx_start(struct slgt_info *info)
3759 {
3760 if (!info->tx_enabled) {
3761 wr_reg16(info, TCR,
3762 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3763 info->tx_enabled = TRUE;
3764 }
3765
3766 if (info->tx_count) {
3767 info->drop_rts_on_tx_done = 0;
3768
3769 if (info->params.mode != MGSL_MODE_ASYNC) {
3770 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3771 get_signals(info);
3772 if (!(info->signals & SerialSignal_RTS)) {
3773 info->signals |= SerialSignal_RTS;
3774 set_signals(info);
3775 info->drop_rts_on_tx_done = 1;
3776 }
3777 }
3778
3779 slgt_irq_off(info, IRQ_TXDATA);
3780 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3781 /* clear tx idle and underrun status bits */
3782 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3783
3784 if (!(rd_reg32(info, TDCSR) & BIT0)) {
3785 /* tx DMA stopped, restart tx DMA */
3786 tdma_reset(info);
3787 /* set 1st descriptor address */
3788 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3789 switch(info->params.mode) {
3790 case MGSL_MODE_RAW:
3791 case MGSL_MODE_MONOSYNC:
3792 case MGSL_MODE_BISYNC:
3793 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3794 break;
3795 default:
3796 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3797 }
3798 }
3799
3800 if (info->params.mode == MGSL_MODE_HDLC) {
3801 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
3802 add_timer(&info->tx_timer);
3803 }
3804 } else {
3805 tdma_reset(info);
3806 /* set 1st descriptor address */
3807 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3808
3809 slgt_irq_off(info, IRQ_TXDATA);
3810 slgt_irq_on(info, IRQ_TXIDLE);
3811 /* clear tx idle status bit */
3812 wr_reg16(info, SSR, IRQ_TXIDLE);
3813
3814 /* enable tx DMA */
3815 wr_reg32(info, TDCSR, BIT0);
3816 }
3817
3818 info->tx_active = 1;
3819 }
3820 }
3821
3822 static void tx_stop(struct slgt_info *info)
3823 {
3824 unsigned short val;
3825
3826 del_timer(&info->tx_timer);
3827
3828 tdma_reset(info);
3829
3830 /* reset and disable transmitter */
3831 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3832 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3833
3834 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3835
3836 /* clear tx idle and underrun status bit */
3837 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3838
3839 reset_tbufs(info);
3840
3841 info->tx_enabled = 0;
3842 info->tx_active = 0;
3843 }
3844
3845 static void reset_port(struct slgt_info *info)
3846 {
3847 if (!info->reg_addr)
3848 return;
3849
3850 tx_stop(info);
3851 rx_stop(info);
3852
3853 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3854 set_signals(info);
3855
3856 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3857 }
3858
3859 static void reset_adapter(struct slgt_info *info)
3860 {
3861 int i;
3862 for (i=0; i < info->port_count; ++i) {
3863 if (info->port_array[i])
3864 reset_port(info->port_array[i]);
3865 }
3866 }
3867
3868 static void async_mode(struct slgt_info *info)
3869 {
3870 unsigned short val;
3871
3872 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3873 tx_stop(info);
3874 rx_stop(info);
3875
3876 /* TCR (tx control)
3877 *
3878 * 15..13 mode, 010=async
3879 * 12..10 encoding, 000=NRZ
3880 * 09 parity enable
3881 * 08 1=odd parity, 0=even parity
3882 * 07 1=RTS driver control
3883 * 06 1=break enable
3884 * 05..04 character length
3885 * 00=5 bits
3886 * 01=6 bits
3887 * 10=7 bits
3888 * 11=8 bits
3889 * 03 0=1 stop bit, 1=2 stop bits
3890 * 02 reset
3891 * 01 enable
3892 * 00 auto-CTS enable
3893 */
3894 val = 0x4000;
3895
3896 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3897 val |= BIT7;
3898
3899 if (info->params.parity != ASYNC_PARITY_NONE) {
3900 val |= BIT9;
3901 if (info->params.parity == ASYNC_PARITY_ODD)
3902 val |= BIT8;
3903 }
3904
3905 switch (info->params.data_bits)
3906 {
3907 case 6: val |= BIT4; break;
3908 case 7: val |= BIT5; break;
3909 case 8: val |= BIT5 + BIT4; break;
3910 }
3911
3912 if (info->params.stop_bits != 1)
3913 val |= BIT3;
3914
3915 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3916 val |= BIT0;
3917
3918 wr_reg16(info, TCR, val);
3919
3920 /* RCR (rx control)
3921 *
3922 * 15..13 mode, 010=async
3923 * 12..10 encoding, 000=NRZ
3924 * 09 parity enable
3925 * 08 1=odd parity, 0=even parity
3926 * 07..06 reserved, must be 0
3927 * 05..04 character length
3928 * 00=5 bits
3929 * 01=6 bits
3930 * 10=7 bits
3931 * 11=8 bits
3932 * 03 reserved, must be zero
3933 * 02 reset
3934 * 01 enable
3935 * 00 auto-DCD enable
3936 */
3937 val = 0x4000;
3938
3939 if (info->params.parity != ASYNC_PARITY_NONE) {
3940 val |= BIT9;
3941 if (info->params.parity == ASYNC_PARITY_ODD)
3942 val |= BIT8;
3943 }
3944
3945 switch (info->params.data_bits)
3946 {
3947 case 6: val |= BIT4; break;
3948 case 7: val |= BIT5; break;
3949 case 8: val |= BIT5 + BIT4; break;
3950 }
3951
3952 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3953 val |= BIT0;
3954
3955 wr_reg16(info, RCR, val);
3956
3957 /* CCR (clock control)
3958 *
3959 * 07..05 011 = tx clock source is BRG/16
3960 * 04..02 010 = rx clock source is BRG
3961 * 01 0 = auxclk disabled
3962 * 00 1 = BRG enabled
3963 *
3964 * 0110 1001
3965 */
3966 wr_reg8(info, CCR, 0x69);
3967
3968 msc_set_vcr(info);
3969
3970 /* SCR (serial control)
3971 *
3972 * 15 1=tx req on FIFO half empty
3973 * 14 1=rx req on FIFO half full
3974 * 13 tx data IRQ enable
3975 * 12 tx idle IRQ enable
3976 * 11 rx break on IRQ enable
3977 * 10 rx data IRQ enable
3978 * 09 rx break off IRQ enable
3979 * 08 overrun IRQ enable
3980 * 07 DSR IRQ enable
3981 * 06 CTS IRQ enable
3982 * 05 DCD IRQ enable
3983 * 04 RI IRQ enable
3984 * 03 reserved, must be zero
3985 * 02 1=txd->rxd internal loopback enable
3986 * 01 reserved, must be zero
3987 * 00 1=master IRQ enable
3988 */
3989 val = BIT15 + BIT14 + BIT0;
3990 wr_reg16(info, SCR, val);
3991
3992 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
3993
3994 set_rate(info, info->params.data_rate * 16);
3995
3996 if (info->params.loopback)
3997 enable_loopback(info);
3998 }
3999
4000 static void sync_mode(struct slgt_info *info)
4001 {
4002 unsigned short val;
4003
4004 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4005 tx_stop(info);
4006 rx_stop(info);
4007
4008 /* TCR (tx control)
4009 *
4010 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4011 * 12..10 encoding
4012 * 09 CRC enable
4013 * 08 CRC32
4014 * 07 1=RTS driver control
4015 * 06 preamble enable
4016 * 05..04 preamble length
4017 * 03 share open/close flag
4018 * 02 reset
4019 * 01 enable
4020 * 00 auto-CTS enable
4021 */
4022 val = 0;
4023
4024 switch(info->params.mode) {
4025 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4026 case MGSL_MODE_BISYNC: val |= BIT15; break;
4027 case MGSL_MODE_RAW: val |= BIT13; break;
4028 }
4029 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4030 val |= BIT7;
4031
4032 switch(info->params.encoding)
4033 {
4034 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4035 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4036 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4037 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4038 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4039 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4040 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4041 }
4042
4043 switch (info->params.crc_type & HDLC_CRC_MASK)
4044 {
4045 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4046 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4047 }
4048
4049 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4050 val |= BIT6;
4051
4052 switch (info->params.preamble_length)
4053 {
4054 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4055 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4056 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4057 }
4058
4059 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4060 val |= BIT0;
4061
4062 wr_reg16(info, TCR, val);
4063
4064 /* TPR (transmit preamble) */
4065
4066 switch (info->params.preamble)
4067 {
4068 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4069 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4070 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4071 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4072 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4073 default: val = 0x7e; break;
4074 }
4075 wr_reg8(info, TPR, (unsigned char)val);
4076
4077 /* RCR (rx control)
4078 *
4079 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4080 * 12..10 encoding
4081 * 09 CRC enable
4082 * 08 CRC32
4083 * 07..03 reserved, must be 0
4084 * 02 reset
4085 * 01 enable
4086 * 00 auto-DCD enable
4087 */
4088 val = 0;
4089
4090 switch(info->params.mode) {
4091 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4092 case MGSL_MODE_BISYNC: val |= BIT15; break;
4093 case MGSL_MODE_RAW: val |= BIT13; break;
4094 }
4095
4096 switch(info->params.encoding)
4097 {
4098 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4099 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4100 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4101 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4102 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4103 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4104 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4105 }
4106
4107 switch (info->params.crc_type & HDLC_CRC_MASK)
4108 {
4109 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4110 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4111 }
4112
4113 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4114 val |= BIT0;
4115
4116 wr_reg16(info, RCR, val);
4117
4118 /* CCR (clock control)
4119 *
4120 * 07..05 tx clock source
4121 * 04..02 rx clock source
4122 * 01 auxclk enable
4123 * 00 BRG enable
4124 */
4125 val = 0;
4126
4127 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4128 {
4129 // when RxC source is DPLL, BRG generates 16X DPLL
4130 // reference clock, so take TxC from BRG/16 to get
4131 // transmit clock at actual data rate
4132 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4133 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4134 else
4135 val |= BIT6; /* 010, txclk = BRG */
4136 }
4137 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4138 val |= BIT7; /* 100, txclk = DPLL Input */
4139 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4140 val |= BIT5; /* 001, txclk = RXC Input */
4141
4142 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4143 val |= BIT3; /* 010, rxclk = BRG */
4144 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4145 val |= BIT4; /* 100, rxclk = DPLL */
4146 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4147 val |= BIT2; /* 001, rxclk = TXC Input */
4148
4149 if (info->params.clock_speed)
4150 val |= BIT1 + BIT0;
4151
4152 wr_reg8(info, CCR, (unsigned char)val);
4153
4154 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4155 {
4156 // program DPLL mode
4157 switch(info->params.encoding)
4158 {
4159 case HDLC_ENCODING_BIPHASE_MARK:
4160 case HDLC_ENCODING_BIPHASE_SPACE:
4161 val = BIT7; break;
4162 case HDLC_ENCODING_BIPHASE_LEVEL:
4163 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4164 val = BIT7 + BIT6; break;
4165 default: val = BIT6; // NRZ encodings
4166 }
4167 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4168
4169 // DPLL requires a 16X reference clock from BRG
4170 set_rate(info, info->params.clock_speed * 16);
4171 }
4172 else
4173 set_rate(info, info->params.clock_speed);
4174
4175 tx_set_idle(info);
4176
4177 msc_set_vcr(info);
4178
4179 /* SCR (serial control)
4180 *
4181 * 15 1=tx req on FIFO half empty
4182 * 14 1=rx req on FIFO half full
4183 * 13 tx data IRQ enable
4184 * 12 tx idle IRQ enable
4185 * 11 underrun IRQ enable
4186 * 10 rx data IRQ enable
4187 * 09 rx idle IRQ enable
4188 * 08 overrun IRQ enable
4189 * 07 DSR IRQ enable
4190 * 06 CTS IRQ enable
4191 * 05 DCD IRQ enable
4192 * 04 RI IRQ enable
4193 * 03 reserved, must be zero
4194 * 02 1=txd->rxd internal loopback enable
4195 * 01 reserved, must be zero
4196 * 00 1=master IRQ enable
4197 */
4198 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4199
4200 if (info->params.loopback)
4201 enable_loopback(info);
4202 }
4203
4204 /*
4205 * set transmit idle mode
4206 */
4207 static void tx_set_idle(struct slgt_info *info)
4208 {
4209 unsigned char val;
4210 unsigned short tcr;
4211
4212 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4213 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4214 */
4215 tcr = rd_reg16(info, TCR);
4216 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4217 /* disable preamble, set idle size to 16 bits */
4218 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4219 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4220 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4221 } else if (!(tcr & BIT6)) {
4222 /* preamble is disabled, set idle size to 8 bits */
4223 tcr &= ~(BIT5 + BIT4);
4224 }
4225 wr_reg16(info, TCR, tcr);
4226
4227 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4228 /* LSB of custom tx idle specified in tx idle register */
4229 val = (unsigned char)(info->idle_mode & 0xff);
4230 } else {
4231 /* standard 8 bit idle patterns */
4232 switch(info->idle_mode)
4233 {
4234 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4235 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4236 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4237 case HDLC_TXIDLE_ZEROS:
4238 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4239 default: val = 0xff;
4240 }
4241 }
4242
4243 wr_reg8(info, TIR, val);
4244 }
4245
4246 /*
4247 * get state of V24 status (input) signals
4248 */
4249 static void get_signals(struct slgt_info *info)
4250 {
4251 unsigned short status = rd_reg16(info, SSR);
4252
4253 /* clear all serial signals except DTR and RTS */
4254 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4255
4256 if (status & BIT3)
4257 info->signals |= SerialSignal_DSR;
4258 if (status & BIT2)
4259 info->signals |= SerialSignal_CTS;
4260 if (status & BIT1)
4261 info->signals |= SerialSignal_DCD;
4262 if (status & BIT0)
4263 info->signals |= SerialSignal_RI;
4264 }
4265
4266 /*
4267 * set V.24 Control Register based on current configuration
4268 */
4269 static void msc_set_vcr(struct slgt_info *info)
4270 {
4271 unsigned char val = 0;
4272
4273 /* VCR (V.24 control)
4274 *
4275 * 07..04 serial IF select
4276 * 03 DTR
4277 * 02 RTS
4278 * 01 LL
4279 * 00 RL
4280 */
4281
4282 switch(info->if_mode & MGSL_INTERFACE_MASK)
4283 {
4284 case MGSL_INTERFACE_RS232:
4285 val |= BIT5; /* 0010 */
4286 break;
4287 case MGSL_INTERFACE_V35:
4288 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4289 break;
4290 case MGSL_INTERFACE_RS422:
4291 val |= BIT6; /* 0100 */
4292 break;
4293 }
4294
4295 if (info->signals & SerialSignal_DTR)
4296 val |= BIT3;
4297 if (info->signals & SerialSignal_RTS)
4298 val |= BIT2;
4299 if (info->if_mode & MGSL_INTERFACE_LL)
4300 val |= BIT1;
4301 if (info->if_mode & MGSL_INTERFACE_RL)
4302 val |= BIT0;
4303 wr_reg8(info, VCR, val);
4304 }
4305
4306 /*
4307 * set state of V24 control (output) signals
4308 */
4309 static void set_signals(struct slgt_info *info)
4310 {
4311 unsigned char val = rd_reg8(info, VCR);
4312 if (info->signals & SerialSignal_DTR)
4313 val |= BIT3;
4314 else
4315 val &= ~BIT3;
4316 if (info->signals & SerialSignal_RTS)
4317 val |= BIT2;
4318 else
4319 val &= ~BIT2;
4320 wr_reg8(info, VCR, val);
4321 }
4322
4323 /*
4324 * free range of receive DMA buffers (i to last)
4325 */
4326 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4327 {
4328 int done = 0;
4329
4330 while(!done) {
4331 /* reset current buffer for reuse */
4332 info->rbufs[i].status = 0;
4333 switch(info->params.mode) {
4334 case MGSL_MODE_RAW:
4335 case MGSL_MODE_MONOSYNC:
4336 case MGSL_MODE_BISYNC:
4337 set_desc_count(info->rbufs[i], info->raw_rx_size);
4338 break;
4339 default:
4340 set_desc_count(info->rbufs[i], DMABUFSIZE);
4341 }
4342
4343 if (i == last)
4344 done = 1;
4345 if (++i == info->rbuf_count)
4346 i = 0;
4347 }
4348 info->rbuf_current = i;
4349 }
4350
4351 /*
4352 * mark all receive DMA buffers as free
4353 */
4354 static void reset_rbufs(struct slgt_info *info)
4355 {
4356 free_rbufs(info, 0, info->rbuf_count - 1);
4357 }
4358
4359 /*
4360 * pass receive HDLC frame to upper layer
4361 *
4362 * return 1 if frame available, otherwise 0
4363 */
4364 static int rx_get_frame(struct slgt_info *info)
4365 {
4366 unsigned int start, end;
4367 unsigned short status;
4368 unsigned int framesize = 0;
4369 int rc = 0;
4370 unsigned long flags;
4371 struct tty_struct *tty = info->tty;
4372 unsigned char addr_field = 0xff;
4373 unsigned int crc_size = 0;
4374
4375 switch (info->params.crc_type & HDLC_CRC_MASK) {
4376 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4377 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4378 }
4379
4380 check_again:
4381
4382 framesize = 0;
4383 addr_field = 0xff;
4384 start = end = info->rbuf_current;
4385
4386 for (;;) {
4387 if (!desc_complete(info->rbufs[end]))
4388 goto cleanup;
4389
4390 if (framesize == 0 && info->params.addr_filter != 0xff)
4391 addr_field = info->rbufs[end].buf[0];
4392
4393 framesize += desc_count(info->rbufs[end]);
4394
4395 if (desc_eof(info->rbufs[end]))
4396 break;
4397
4398 if (++end == info->rbuf_count)
4399 end = 0;
4400
4401 if (end == info->rbuf_current) {
4402 if (info->rx_enabled){
4403 spin_lock_irqsave(&info->lock,flags);
4404 rx_start(info);
4405 spin_unlock_irqrestore(&info->lock,flags);
4406 }
4407 goto cleanup;
4408 }
4409 }
4410
4411 /* status
4412 *
4413 * 15 buffer complete
4414 * 14..06 reserved
4415 * 05..04 residue
4416 * 02 eof (end of frame)
4417 * 01 CRC error
4418 * 00 abort
4419 */
4420 status = desc_status(info->rbufs[end]);
4421
4422 /* ignore CRC bit if not using CRC (bit is undefined) */
4423 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4424 status &= ~BIT1;
4425
4426 if (framesize == 0 ||
4427 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4428 free_rbufs(info, start, end);
4429 goto check_again;
4430 }
4431
4432 if (framesize < (2 + crc_size) || status & BIT0) {
4433 info->icount.rxshort++;
4434 framesize = 0;
4435 } else if (status & BIT1) {
4436 info->icount.rxcrc++;
4437 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4438 framesize = 0;
4439 }
4440
4441 #if SYNCLINK_GENERIC_HDLC
4442 if (framesize == 0) {
4443 struct net_device_stats *stats = hdlc_stats(info->netdev);
4444 stats->rx_errors++;
4445 stats->rx_frame_errors++;
4446 }
4447 #endif
4448
4449 DBGBH(("%s rx frame status=%04X size=%d\n",
4450 info->device_name, status, framesize));
4451 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4452
4453 if (framesize) {
4454 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4455 framesize -= crc_size;
4456 crc_size = 0;
4457 }
4458
4459 if (framesize > info->max_frame_size + crc_size)
4460 info->icount.rxlong++;
4461 else {
4462 /* copy dma buffer(s) to contiguous temp buffer */
4463 int copy_count = framesize;
4464 int i = start;
4465 unsigned char *p = info->tmp_rbuf;
4466 info->tmp_rbuf_count = framesize;
4467
4468 info->icount.rxok++;
4469
4470 while(copy_count) {
4471 int partial_count = min(copy_count, DMABUFSIZE);
4472 memcpy(p, info->rbufs[i].buf, partial_count);
4473 p += partial_count;
4474 copy_count -= partial_count;
4475 if (++i == info->rbuf_count)
4476 i = 0;
4477 }
4478
4479 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4480 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4481 framesize++;
4482 }
4483
4484 #if SYNCLINK_GENERIC_HDLC
4485 if (info->netcount)
4486 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4487 else
4488 #endif
4489 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4490 }
4491 }
4492 free_rbufs(info, start, end);
4493 rc = 1;
4494
4495 cleanup:
4496 return rc;
4497 }
4498
4499 /*
4500 * pass receive buffer (RAW synchronous mode) to tty layer
4501 * return 1 if buffer available, otherwise 0
4502 */
4503 static int rx_get_buf(struct slgt_info *info)
4504 {
4505 unsigned int i = info->rbuf_current;
4506 unsigned int count;
4507
4508 if (!desc_complete(info->rbufs[i]))
4509 return 0;
4510 count = desc_count(info->rbufs[i]);
4511 switch(info->params.mode) {
4512 case MGSL_MODE_MONOSYNC:
4513 case MGSL_MODE_BISYNC:
4514 /* ignore residue in byte synchronous modes */
4515 if (desc_residue(info->rbufs[i]))
4516 count--;
4517 break;
4518 }
4519 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4520 DBGINFO(("rx_get_buf size=%d\n", count));
4521 if (count)
4522 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4523 info->flag_buf, count);
4524 free_rbufs(info, i, i);
4525 return 1;
4526 }
4527
4528 static void reset_tbufs(struct slgt_info *info)
4529 {
4530 unsigned int i;
4531 info->tbuf_current = 0;
4532 for (i=0 ; i < info->tbuf_count ; i++) {
4533 info->tbufs[i].status = 0;
4534 info->tbufs[i].count = 0;
4535 }
4536 }
4537
4538 /*
4539 * return number of free transmit DMA buffers
4540 */
4541 static unsigned int free_tbuf_count(struct slgt_info *info)
4542 {
4543 unsigned int count = 0;
4544 unsigned int i = info->tbuf_current;
4545
4546 do
4547 {
4548 if (desc_count(info->tbufs[i]))
4549 break; /* buffer in use */
4550 ++count;
4551 if (++i == info->tbuf_count)
4552 i=0;
4553 } while (i != info->tbuf_current);
4554
4555 /* last buffer with zero count may be in use, assume it is */
4556 if (count)
4557 --count;
4558
4559 return count;
4560 }
4561
4562 /*
4563 * load transmit DMA buffer(s) with data
4564 */
4565 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4566 {
4567 unsigned short count;
4568 unsigned int i;
4569 struct slgt_desc *d;
4570
4571 if (size == 0)
4572 return;
4573
4574 DBGDATA(info, buf, size, "tx");
4575
4576 info->tbuf_start = i = info->tbuf_current;
4577
4578 while (size) {
4579 d = &info->tbufs[i];
4580 if (++i == info->tbuf_count)
4581 i = 0;
4582
4583 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4584 memcpy(d->buf, buf, count);
4585
4586 size -= count;
4587 buf += count;
4588
4589 /*
4590 * set EOF bit for last buffer of HDLC frame or
4591 * for every buffer in raw mode
4592 */
4593 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4594 info->params.mode == MGSL_MODE_RAW)
4595 set_desc_eof(*d, 1);
4596 else
4597 set_desc_eof(*d, 0);
4598
4599 set_desc_count(*d, count);
4600 }
4601
4602 info->tbuf_current = i;
4603 }
4604
4605 static int register_test(struct slgt_info *info)
4606 {
4607 static unsigned short patterns[] =
4608 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4609 static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4610 unsigned int i;
4611 int rc = 0;
4612
4613 for (i=0 ; i < count ; i++) {
4614 wr_reg16(info, TIR, patterns[i]);
4615 wr_reg16(info, BDR, patterns[(i+1)%count]);
4616 if ((rd_reg16(info, TIR) != patterns[i]) ||
4617 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4618 rc = -ENODEV;
4619 break;
4620 }
4621 }
4622 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4623 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4624 return rc;
4625 }
4626
4627 static int irq_test(struct slgt_info *info)
4628 {
4629 unsigned long timeout;
4630 unsigned long flags;
4631 struct tty_struct *oldtty = info->tty;
4632 u32 speed = info->params.data_rate;
4633
4634 info->params.data_rate = 921600;
4635 info->tty = NULL;
4636
4637 spin_lock_irqsave(&info->lock, flags);
4638 async_mode(info);
4639 slgt_irq_on(info, IRQ_TXIDLE);
4640
4641 /* enable transmitter */
4642 wr_reg16(info, TCR,
4643 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4644
4645 /* write one byte and wait for tx idle */
4646 wr_reg16(info, TDR, 0);
4647
4648 /* assume failure */
4649 info->init_error = DiagStatus_IrqFailure;
4650 info->irq_occurred = FALSE;
4651
4652 spin_unlock_irqrestore(&info->lock, flags);
4653
4654 timeout=100;
4655 while(timeout-- && !info->irq_occurred)
4656 msleep_interruptible(10);
4657
4658 spin_lock_irqsave(&info->lock,flags);
4659 reset_port(info);
4660 spin_unlock_irqrestore(&info->lock,flags);
4661
4662 info->params.data_rate = speed;
4663 info->tty = oldtty;
4664
4665 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4666 return info->irq_occurred ? 0 : -ENODEV;
4667 }
4668
4669 static int loopback_test_rx(struct slgt_info *info)
4670 {
4671 unsigned char *src, *dest;
4672 int count;
4673
4674 if (desc_complete(info->rbufs[0])) {
4675 count = desc_count(info->rbufs[0]);
4676 src = info->rbufs[0].buf;
4677 dest = info->tmp_rbuf;
4678
4679 for( ; count ; count-=2, src+=2) {
4680 /* src=data byte (src+1)=status byte */
4681 if (!(*(src+1) & (BIT9 + BIT8))) {
4682 *dest = *src;
4683 dest++;
4684 info->tmp_rbuf_count++;
4685 }
4686 }
4687 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4688 return 1;
4689 }
4690 return 0;
4691 }
4692
4693 static int loopback_test(struct slgt_info *info)
4694 {
4695 #define TESTFRAMESIZE 20
4696
4697 unsigned long timeout;
4698 u16 count = TESTFRAMESIZE;
4699 unsigned char buf[TESTFRAMESIZE];
4700 int rc = -ENODEV;
4701 unsigned long flags;
4702
4703 struct tty_struct *oldtty = info->tty;
4704 MGSL_PARAMS params;
4705
4706 memcpy(&params, &info->params, sizeof(params));
4707
4708 info->params.mode = MGSL_MODE_ASYNC;
4709 info->params.data_rate = 921600;
4710 info->params.loopback = 1;
4711 info->tty = NULL;
4712
4713 /* build and send transmit frame */
4714 for (count = 0; count < TESTFRAMESIZE; ++count)
4715 buf[count] = (unsigned char)count;
4716
4717 info->tmp_rbuf_count = 0;
4718 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4719
4720 /* program hardware for HDLC and enabled receiver */
4721 spin_lock_irqsave(&info->lock,flags);
4722 async_mode(info);
4723 rx_start(info);
4724 info->tx_count = count;
4725 tx_load(info, buf, count);
4726 tx_start(info);
4727 spin_unlock_irqrestore(&info->lock, flags);
4728
4729 /* wait for receive complete */
4730 for (timeout = 100; timeout; --timeout) {
4731 msleep_interruptible(10);
4732 if (loopback_test_rx(info)) {
4733 rc = 0;
4734 break;
4735 }
4736 }
4737
4738 /* verify received frame length and contents */
4739 if (!rc && (info->tmp_rbuf_count != count ||
4740 memcmp(buf, info->tmp_rbuf, count))) {
4741 rc = -ENODEV;
4742 }
4743
4744 spin_lock_irqsave(&info->lock,flags);
4745 reset_adapter(info);
4746 spin_unlock_irqrestore(&info->lock,flags);
4747
4748 memcpy(&info->params, &params, sizeof(info->params));
4749 info->tty = oldtty;
4750
4751 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4752 return rc;
4753 }
4754
4755 static int adapter_test(struct slgt_info *info)
4756 {
4757 DBGINFO(("testing %s\n", info->device_name));
4758 if (register_test(info) < 0) {
4759 printk("register test failure %s addr=%08X\n",
4760 info->device_name, info->phys_reg_addr);
4761 } else if (irq_test(info) < 0) {
4762 printk("IRQ test failure %s IRQ=%d\n",
4763 info->device_name, info->irq_level);
4764 } else if (loopback_test(info) < 0) {
4765 printk("loopback test failure %s\n", info->device_name);
4766 }
4767 return info->init_error;
4768 }
4769
4770 /*
4771 * transmit timeout handler
4772 */
4773 static void tx_timeout(unsigned long context)
4774 {
4775 struct slgt_info *info = (struct slgt_info*)context;
4776 unsigned long flags;
4777
4778 DBGINFO(("%s tx_timeout\n", info->device_name));
4779 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4780 info->icount.txtimeout++;
4781 }
4782 spin_lock_irqsave(&info->lock,flags);
4783 info->tx_active = 0;
4784 info->tx_count = 0;
4785 spin_unlock_irqrestore(&info->lock,flags);
4786
4787 #if SYNCLINK_GENERIC_HDLC
4788 if (info->netcount)
4789 hdlcdev_tx_done(info);
4790 else
4791 #endif
4792 bh_transmit(info);
4793 }
4794
4795 /*
4796 * receive buffer polling timer
4797 */
4798 static void rx_timeout(unsigned long context)
4799 {
4800 struct slgt_info *info = (struct slgt_info*)context;
4801 unsigned long flags;
4802
4803 DBGINFO(("%s rx_timeout\n", info->device_name));
4804 spin_lock_irqsave(&info->lock, flags);
4805 info->pending_bh |= BH_RECEIVE;
4806 spin_unlock_irqrestore(&info->lock, flags);
4807 bh_handler(&info->task);
4808 }
4809
Linux with added FPC-III support