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Linux 2.6.20.7
[linux/fpc-iii.git] / drivers / char / synclinkmp.c
blob8f4d67afe5bf99fe1daea30940640b2c1cbbbe72
1 /*
2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 # define BREAKPOINT() asm(" int $3");
31 #else
32 # define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/slab.h>
54 #include <linux/netdevice.h>
55 #include <linux/vmalloc.h>
56 #include <linux/init.h>
57 #include <linux/delay.h>
58 #include <linux/ioctl.h>
59
60 #include <asm/system.h>
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/dma.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69
70 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
71 #define SYNCLINK_GENERIC_HDLC 1
72 #else
73 #define SYNCLINK_GENERIC_HDLC 0
74 #endif
75
76 #define GET_USER(error,value,addr) error = get_user(value,addr)
77 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
78 #define PUT_USER(error,value,addr) error = put_user(value,addr)
79 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
80
81 #include <asm/uaccess.h>
82
83 #include "linux/synclink.h"
84
85 static MGSL_PARAMS default_params = {
86 MGSL_MODE_HDLC, /* unsigned long mode */
87 0, /* unsigned char loopback; */
88 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
89 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
90 0, /* unsigned long clock_speed; */
91 0xff, /* unsigned char addr_filter; */
92 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
93 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
94 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
95 9600, /* unsigned long data_rate; */
96 8, /* unsigned char data_bits; */
97 1, /* unsigned char stop_bits; */
98 ASYNC_PARITY_NONE /* unsigned char parity; */
99 };
100
101 /* size in bytes of DMA data buffers */
102 #define SCABUFSIZE 1024
103 #define SCA_MEM_SIZE 0x40000
104 #define SCA_BASE_SIZE 512
105 #define SCA_REG_SIZE 16
106 #define SCA_MAX_PORTS 4
107 #define SCAMAXDESC 128
108
109 #define BUFFERLISTSIZE 4096
110
111 /* SCA-I style DMA buffer descriptor */
112 typedef struct _SCADESC
113 {
114 u16 next; /* lower l6 bits of next descriptor addr */
115 u16 buf_ptr; /* lower 16 bits of buffer addr */
116 u8 buf_base; /* upper 8 bits of buffer addr */
117 u8 pad1;
118 u16 length; /* length of buffer */
119 u8 status; /* status of buffer */
120 u8 pad2;
121 } SCADESC, *PSCADESC;
122
123 typedef struct _SCADESC_EX
124 {
125 /* device driver bookkeeping section */
126 char *virt_addr; /* virtual address of data buffer */
127 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
128 } SCADESC_EX, *PSCADESC_EX;
129
130 /* The queue of BH actions to be performed */
131
132 #define BH_RECEIVE 1
133 #define BH_TRANSMIT 2
134 #define BH_STATUS 4
135
136 #define IO_PIN_SHUTDOWN_LIMIT 100
137
138 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
139
140 struct _input_signal_events {
141 int ri_up;
142 int ri_down;
143 int dsr_up;
144 int dsr_down;
145 int dcd_up;
146 int dcd_down;
147 int cts_up;
148 int cts_down;
149 };
150
151 /*
152 * Device instance data structure
153 */
154 typedef struct _synclinkmp_info {
155 void *if_ptr; /* General purpose pointer (used by SPPP) */
156 int magic;
157 int flags;
158 int count; /* count of opens */
159 int line;
160 unsigned short close_delay;
161 unsigned short closing_wait; /* time to wait before closing */
162
163 struct mgsl_icount icount;
164
165 struct tty_struct *tty;
166 int timeout;
167 int x_char; /* xon/xoff character */
168 int blocked_open; /* # of blocked opens */
169 u16 read_status_mask1; /* break detection (SR1 indications) */
170 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
171 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
172 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
173 unsigned char *tx_buf;
174 int tx_put;
175 int tx_get;
176 int tx_count;
177
178 wait_queue_head_t open_wait;
179 wait_queue_head_t close_wait;
180
181 wait_queue_head_t status_event_wait_q;
182 wait_queue_head_t event_wait_q;
183 struct timer_list tx_timer; /* HDLC transmit timeout timer */
184 struct _synclinkmp_info *next_device; /* device list link */
185 struct timer_list status_timer; /* input signal status check timer */
186
187 spinlock_t lock; /* spinlock for synchronizing with ISR */
188 struct work_struct task; /* task structure for scheduling bh */
189
190 u32 max_frame_size; /* as set by device config */
191
192 u32 pending_bh;
193
194 int bh_running; /* Protection from multiple */
195 int isr_overflow;
196 int bh_requested;
197
198 int dcd_chkcount; /* check counts to prevent */
199 int cts_chkcount; /* too many IRQs if a signal */
200 int dsr_chkcount; /* is floating */
201 int ri_chkcount;
202
203 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
204 unsigned long buffer_list_phys;
205
206 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
207 SCADESC *rx_buf_list; /* list of receive buffer entries */
208 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
209 unsigned int current_rx_buf;
210
211 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
212 SCADESC *tx_buf_list; /* list of transmit buffer entries */
213 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
214 unsigned int last_tx_buf;
215
216 unsigned char *tmp_rx_buf;
217 unsigned int tmp_rx_buf_count;
218
219 int rx_enabled;
220 int rx_overflow;
221
222 int tx_enabled;
223 int tx_active;
224 u32 idle_mode;
225
226 unsigned char ie0_value;
227 unsigned char ie1_value;
228 unsigned char ie2_value;
229 unsigned char ctrlreg_value;
230 unsigned char old_signals;
231
232 char device_name[25]; /* device instance name */
233
234 int port_count;
235 int adapter_num;
236 int port_num;
237
238 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
239
240 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
241
242 unsigned int irq_level; /* interrupt level */
243 unsigned long irq_flags;
244 int irq_requested; /* nonzero if IRQ requested */
245
246 MGSL_PARAMS params; /* communications parameters */
247
248 unsigned char serial_signals; /* current serial signal states */
249
250 int irq_occurred; /* for diagnostics use */
251 unsigned int init_error; /* Initialization startup error */
252
253 u32 last_mem_alloc;
254 unsigned char* memory_base; /* shared memory address (PCI only) */
255 u32 phys_memory_base;
256 int shared_mem_requested;
257
258 unsigned char* sca_base; /* HD64570 SCA Memory address */
259 u32 phys_sca_base;
260 u32 sca_offset;
261 int sca_base_requested;
262
263 unsigned char* lcr_base; /* local config registers (PCI only) */
264 u32 phys_lcr_base;
265 u32 lcr_offset;
266 int lcr_mem_requested;
267
268 unsigned char* statctrl_base; /* status/control register memory */
269 u32 phys_statctrl_base;
270 u32 statctrl_offset;
271 int sca_statctrl_requested;
272
273 u32 misc_ctrl_value;
274 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
275 char char_buf[MAX_ASYNC_BUFFER_SIZE];
276 BOOLEAN drop_rts_on_tx_done;
277
278 struct _input_signal_events input_signal_events;
279
280 /* SPPP/Cisco HDLC device parts */
281 int netcount;
282 int dosyncppp;
283 spinlock_t netlock;
284
285 #if SYNCLINK_GENERIC_HDLC
286 struct net_device *netdev;
287 #endif
288
289 } SLMP_INFO;
290
291 #define MGSL_MAGIC 0x5401
292
293 /*
294 * define serial signal status change macros
295 */
296 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
297 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
298 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
299 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
300
301 /* Common Register macros */
302 #define LPR 0x00
303 #define PABR0 0x02
304 #define PABR1 0x03
305 #define WCRL 0x04
306 #define WCRM 0x05
307 #define WCRH 0x06
308 #define DPCR 0x08
309 #define DMER 0x09
310 #define ISR0 0x10
311 #define ISR1 0x11
312 #define ISR2 0x12
313 #define IER0 0x14
314 #define IER1 0x15
315 #define IER2 0x16
316 #define ITCR 0x18
317 #define INTVR 0x1a
318 #define IMVR 0x1c
319
320 /* MSCI Register macros */
321 #define TRB 0x20
322 #define TRBL 0x20
323 #define TRBH 0x21
324 #define SR0 0x22
325 #define SR1 0x23
326 #define SR2 0x24
327 #define SR3 0x25
328 #define FST 0x26
329 #define IE0 0x28
330 #define IE1 0x29
331 #define IE2 0x2a
332 #define FIE 0x2b
333 #define CMD 0x2c
334 #define MD0 0x2e
335 #define MD1 0x2f
336 #define MD2 0x30
337 #define CTL 0x31
338 #define SA0 0x32
339 #define SA1 0x33
340 #define IDL 0x34
341 #define TMC 0x35
342 #define RXS 0x36
343 #define TXS 0x37
344 #define TRC0 0x38
345 #define TRC1 0x39
346 #define RRC 0x3a
347 #define CST0 0x3c
348 #define CST1 0x3d
349
350 /* Timer Register Macros */
351 #define TCNT 0x60
352 #define TCNTL 0x60
353 #define TCNTH 0x61
354 #define TCONR 0x62
355 #define TCONRL 0x62
356 #define TCONRH 0x63
357 #define TMCS 0x64
358 #define TEPR 0x65
359
360 /* DMA Controller Register macros */
361 #define DARL 0x80
362 #define DARH 0x81
363 #define DARB 0x82
364 #define BAR 0x80
365 #define BARL 0x80
366 #define BARH 0x81
367 #define BARB 0x82
368 #define SAR 0x84
369 #define SARL 0x84
370 #define SARH 0x85
371 #define SARB 0x86
372 #define CPB 0x86
373 #define CDA 0x88
374 #define CDAL 0x88
375 #define CDAH 0x89
376 #define EDA 0x8a
377 #define EDAL 0x8a
378 #define EDAH 0x8b
379 #define BFL 0x8c
380 #define BFLL 0x8c
381 #define BFLH 0x8d
382 #define BCR 0x8e
383 #define BCRL 0x8e
384 #define BCRH 0x8f
385 #define DSR 0x90
386 #define DMR 0x91
387 #define FCT 0x93
388 #define DIR 0x94
389 #define DCMD 0x95
390
391 /* combine with timer or DMA register address */
392 #define TIMER0 0x00
393 #define TIMER1 0x08
394 #define TIMER2 0x10
395 #define TIMER3 0x18
396 #define RXDMA 0x00
397 #define TXDMA 0x20
398
399 /* SCA Command Codes */
400 #define NOOP 0x00
401 #define TXRESET 0x01
402 #define TXENABLE 0x02
403 #define TXDISABLE 0x03
404 #define TXCRCINIT 0x04
405 #define TXCRCEXCL 0x05
406 #define TXEOM 0x06
407 #define TXABORT 0x07
408 #define MPON 0x08
409 #define TXBUFCLR 0x09
410 #define RXRESET 0x11
411 #define RXENABLE 0x12
412 #define RXDISABLE 0x13
413 #define RXCRCINIT 0x14
414 #define RXREJECT 0x15
415 #define SEARCHMP 0x16
416 #define RXCRCEXCL 0x17
417 #define RXCRCCALC 0x18
418 #define CHRESET 0x21
419 #define HUNT 0x31
420
421 /* DMA command codes */
422 #define SWABORT 0x01
423 #define FEICLEAR 0x02
424
425 /* IE0 */
426 #define TXINTE BIT7
427 #define RXINTE BIT6
428 #define TXRDYE BIT1
429 #define RXRDYE BIT0
430
431 /* IE1 & SR1 */
432 #define UDRN BIT7
433 #define IDLE BIT6
434 #define SYNCD BIT4
435 #define FLGD BIT4
436 #define CCTS BIT3
437 #define CDCD BIT2
438 #define BRKD BIT1
439 #define ABTD BIT1
440 #define GAPD BIT1
441 #define BRKE BIT0
442 #define IDLD BIT0
443
444 /* IE2 & SR2 */
445 #define EOM BIT7
446 #define PMP BIT6
447 #define SHRT BIT6
448 #define PE BIT5
449 #define ABT BIT5
450 #define FRME BIT4
451 #define RBIT BIT4
452 #define OVRN BIT3
453 #define CRCE BIT2
454
455
456 /*
457 * Global linked list of SyncLink devices
458 */
459 static SLMP_INFO *synclinkmp_device_list = NULL;
460 static int synclinkmp_adapter_count = -1;
461 static int synclinkmp_device_count = 0;
462
463 /*
464 * Set this param to non-zero to load eax with the
465 * .text section address and breakpoint on module load.
466 * This is useful for use with gdb and add-symbol-file command.
467 */
468 static int break_on_load=0;
469
470 /*
471 * Driver major number, defaults to zero to get auto
472 * assigned major number. May be forced as module parameter.
473 */
474 static int ttymajor=0;
475
476 /*
477 * Array of user specified options for ISA adapters.
478 */
479 static int debug_level = 0;
480 static int maxframe[MAX_DEVICES] = {0,};
481 static int dosyncppp[MAX_DEVICES] = {0,};
482
483 module_param(break_on_load, bool, 0);
484 module_param(ttymajor, int, 0);
485 module_param(debug_level, int, 0);
486 module_param_array(maxframe, int, NULL, 0);
487 module_param_array(dosyncppp, int, NULL, 0);
488
489 static char *driver_name = "SyncLink MultiPort driver";
490 static char *driver_version = "$Revision: 4.38 $";
491
492 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
493 static void synclinkmp_remove_one(struct pci_dev *dev);
494
495 static struct pci_device_id synclinkmp_pci_tbl[] = {
496 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
497 { 0, }, /* terminate list */
498 };
499 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
500
501 MODULE_LICENSE("GPL");
502
503 static struct pci_driver synclinkmp_pci_driver = {
504 .name = "synclinkmp",
505 .id_table = synclinkmp_pci_tbl,
506 .probe = synclinkmp_init_one,
507 .remove = __devexit_p(synclinkmp_remove_one),
508 };
509
510
511 static struct tty_driver *serial_driver;
512
513 /* number of characters left in xmit buffer before we ask for more */
514 #define WAKEUP_CHARS 256
515
516
517 /* tty callbacks */
518
519 static int open(struct tty_struct *tty, struct file * filp);
520 static void close(struct tty_struct *tty, struct file * filp);
521 static void hangup(struct tty_struct *tty);
522 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
523
524 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
525 static void put_char(struct tty_struct *tty, unsigned char ch);
526 static void send_xchar(struct tty_struct *tty, char ch);
527 static void wait_until_sent(struct tty_struct *tty, int timeout);
528 static int write_room(struct tty_struct *tty);
529 static void flush_chars(struct tty_struct *tty);
530 static void flush_buffer(struct tty_struct *tty);
531 static void tx_hold(struct tty_struct *tty);
532 static void tx_release(struct tty_struct *tty);
533
534 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
535 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
536 static int chars_in_buffer(struct tty_struct *tty);
537 static void throttle(struct tty_struct * tty);
538 static void unthrottle(struct tty_struct * tty);
539 static void set_break(struct tty_struct *tty, int break_state);
540
541 #if SYNCLINK_GENERIC_HDLC
542 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
543 static void hdlcdev_tx_done(SLMP_INFO *info);
544 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
545 static int hdlcdev_init(SLMP_INFO *info);
546 static void hdlcdev_exit(SLMP_INFO *info);
547 #endif
548
549 /* ioctl handlers */
550
551 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
552 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
553 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
554 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
555 static int set_txidle(SLMP_INFO *info, int idle_mode);
556 static int tx_enable(SLMP_INFO *info, int enable);
557 static int tx_abort(SLMP_INFO *info);
558 static int rx_enable(SLMP_INFO *info, int enable);
559 static int modem_input_wait(SLMP_INFO *info,int arg);
560 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
561 static int tiocmget(struct tty_struct *tty, struct file *file);
562 static int tiocmset(struct tty_struct *tty, struct file *file,
563 unsigned int set, unsigned int clear);
564 static void set_break(struct tty_struct *tty, int break_state);
565
566 static void add_device(SLMP_INFO *info);
567 static void device_init(int adapter_num, struct pci_dev *pdev);
568 static int claim_resources(SLMP_INFO *info);
569 static void release_resources(SLMP_INFO *info);
570
571 static int startup(SLMP_INFO *info);
572 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
573 static void shutdown(SLMP_INFO *info);
574 static void program_hw(SLMP_INFO *info);
575 static void change_params(SLMP_INFO *info);
576
577 static int init_adapter(SLMP_INFO *info);
578 static int register_test(SLMP_INFO *info);
579 static int irq_test(SLMP_INFO *info);
580 static int loopback_test(SLMP_INFO *info);
581 static int adapter_test(SLMP_INFO *info);
582 static int memory_test(SLMP_INFO *info);
583
584 static void reset_adapter(SLMP_INFO *info);
585 static void reset_port(SLMP_INFO *info);
586 static void async_mode(SLMP_INFO *info);
587 static void hdlc_mode(SLMP_INFO *info);
588
589 static void rx_stop(SLMP_INFO *info);
590 static void rx_start(SLMP_INFO *info);
591 static void rx_reset_buffers(SLMP_INFO *info);
592 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
593 static int rx_get_frame(SLMP_INFO *info);
594
595 static void tx_start(SLMP_INFO *info);
596 static void tx_stop(SLMP_INFO *info);
597 static void tx_load_fifo(SLMP_INFO *info);
598 static void tx_set_idle(SLMP_INFO *info);
599 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
600
601 static void get_signals(SLMP_INFO *info);
602 static void set_signals(SLMP_INFO *info);
603 static void enable_loopback(SLMP_INFO *info, int enable);
604 static void set_rate(SLMP_INFO *info, u32 data_rate);
605
606 static int bh_action(SLMP_INFO *info);
607 static void bh_handler(struct work_struct *work);
608 static void bh_receive(SLMP_INFO *info);
609 static void bh_transmit(SLMP_INFO *info);
610 static void bh_status(SLMP_INFO *info);
611 static void isr_timer(SLMP_INFO *info);
612 static void isr_rxint(SLMP_INFO *info);
613 static void isr_rxrdy(SLMP_INFO *info);
614 static void isr_txint(SLMP_INFO *info);
615 static void isr_txrdy(SLMP_INFO *info);
616 static void isr_rxdmaok(SLMP_INFO *info);
617 static void isr_rxdmaerror(SLMP_INFO *info);
618 static void isr_txdmaok(SLMP_INFO *info);
619 static void isr_txdmaerror(SLMP_INFO *info);
620 static void isr_io_pin(SLMP_INFO *info, u16 status);
621
622 static int alloc_dma_bufs(SLMP_INFO *info);
623 static void free_dma_bufs(SLMP_INFO *info);
624 static int alloc_buf_list(SLMP_INFO *info);
625 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
626 static int alloc_tmp_rx_buf(SLMP_INFO *info);
627 static void free_tmp_rx_buf(SLMP_INFO *info);
628
629 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
630 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
631 static void tx_timeout(unsigned long context);
632 static void status_timeout(unsigned long context);
633
634 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
635 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
636 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
637 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
638 static unsigned char read_status_reg(SLMP_INFO * info);
639 static void write_control_reg(SLMP_INFO * info);
640
641
642 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
643 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
644 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
645
646 static u32 misc_ctrl_value = 0x007e4040;
647 static u32 lcr1_brdr_value = 0x00800028;
648
649 static u32 read_ahead_count = 8;
650
651 /* DPCR, DMA Priority Control
652 *
653 * 07..05 Not used, must be 0
654 * 04 BRC, bus release condition: 0=all transfers complete
655 * 1=release after 1 xfer on all channels
656 * 03 CCC, channel change condition: 0=every cycle
657 * 1=after each channel completes all xfers
658 * 02..00 PR<2..0>, priority 100=round robin
659 *
660 * 00000100 = 0x00
661 */
662 static unsigned char dma_priority = 0x04;
663
664 // Number of bytes that can be written to shared RAM
665 // in a single write operation
666 static u32 sca_pci_load_interval = 64;
667
668 /*
669 * 1st function defined in .text section. Calling this function in
670 * init_module() followed by a breakpoint allows a remote debugger
671 * (gdb) to get the .text address for the add-symbol-file command.
672 * This allows remote debugging of dynamically loadable modules.
673 */
674 static void* synclinkmp_get_text_ptr(void);
675 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
676
677 static inline int sanity_check(SLMP_INFO *info,
678 char *name, const char *routine)
679 {
680 #ifdef SANITY_CHECK
681 static const char *badmagic =
682 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
683 static const char *badinfo =
684 "Warning: null synclinkmp_struct for (%s) in %s\n";
685
686 if (!info) {
687 printk(badinfo, name, routine);
688 return 1;
689 }
690 if (info->magic != MGSL_MAGIC) {
691 printk(badmagic, name, routine);
692 return 1;
693 }
694 #else
695 if (!info)
696 return 1;
697 #endif
698 return 0;
699 }
700
701 /**
702 * line discipline callback wrappers
703 *
704 * The wrappers maintain line discipline references
705 * while calling into the line discipline.
706 *
707 * ldisc_receive_buf - pass receive data to line discipline
708 */
709
710 static void ldisc_receive_buf(struct tty_struct *tty,
711 const __u8 *data, char *flags, int count)
712 {
713 struct tty_ldisc *ld;
714 if (!tty)
715 return;
716 ld = tty_ldisc_ref(tty);
717 if (ld) {
718 if (ld->receive_buf)
719 ld->receive_buf(tty, data, flags, count);
720 tty_ldisc_deref(ld);
721 }
722 }
723
724 /* tty callbacks */
725
726 /* Called when a port is opened. Init and enable port.
727 */
728 static int open(struct tty_struct *tty, struct file *filp)
729 {
730 SLMP_INFO *info;
731 int retval, line;
732 unsigned long flags;
733
734 line = tty->index;
735 if ((line < 0) || (line >= synclinkmp_device_count)) {
736 printk("%s(%d): open with invalid line #%d.\n",
737 __FILE__,__LINE__,line);
738 return -ENODEV;
739 }
740
741 info = synclinkmp_device_list;
742 while(info && info->line != line)
743 info = info->next_device;
744 if (sanity_check(info, tty->name, "open"))
745 return -ENODEV;
746 if ( info->init_error ) {
747 printk("%s(%d):%s device is not allocated, init error=%d\n",
748 __FILE__,__LINE__,info->device_name,info->init_error);
749 return -ENODEV;
750 }
751
752 tty->driver_data = info;
753 info->tty = tty;
754
755 if (debug_level >= DEBUG_LEVEL_INFO)
756 printk("%s(%d):%s open(), old ref count = %d\n",
757 __FILE__,__LINE__,tty->driver->name, info->count);
758
759 /* If port is closing, signal caller to try again */
760 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
761 if (info->flags & ASYNC_CLOSING)
762 interruptible_sleep_on(&info->close_wait);
763 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
764 -EAGAIN : -ERESTARTSYS);
765 goto cleanup;
766 }
767
768 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
769
770 spin_lock_irqsave(&info->netlock, flags);
771 if (info->netcount) {
772 retval = -EBUSY;
773 spin_unlock_irqrestore(&info->netlock, flags);
774 goto cleanup;
775 }
776 info->count++;
777 spin_unlock_irqrestore(&info->netlock, flags);
778
779 if (info->count == 1) {
780 /* 1st open on this device, init hardware */
781 retval = startup(info);
782 if (retval < 0)
783 goto cleanup;
784 }
785
786 retval = block_til_ready(tty, filp, info);
787 if (retval) {
788 if (debug_level >= DEBUG_LEVEL_INFO)
789 printk("%s(%d):%s block_til_ready() returned %d\n",
790 __FILE__,__LINE__, info->device_name, retval);
791 goto cleanup;
792 }
793
794 if (debug_level >= DEBUG_LEVEL_INFO)
795 printk("%s(%d):%s open() success\n",
796 __FILE__,__LINE__, info->device_name);
797 retval = 0;
798
799 cleanup:
800 if (retval) {
801 if (tty->count == 1)
802 info->tty = NULL; /* tty layer will release tty struct */
803 if(info->count)
804 info->count--;
805 }
806
807 return retval;
808 }
809
810 /* Called when port is closed. Wait for remaining data to be
811 * sent. Disable port and free resources.
812 */
813 static void close(struct tty_struct *tty, struct file *filp)
814 {
815 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
816
817 if (sanity_check(info, tty->name, "close"))
818 return;
819
820 if (debug_level >= DEBUG_LEVEL_INFO)
821 printk("%s(%d):%s close() entry, count=%d\n",
822 __FILE__,__LINE__, info->device_name, info->count);
823
824 if (!info->count)
825 return;
826
827 if (tty_hung_up_p(filp))
828 goto cleanup;
829
830 if ((tty->count == 1) && (info->count != 1)) {
831 /*
832 * tty->count is 1 and the tty structure will be freed.
833 * info->count should be one in this case.
834 * if it's not, correct it so that the port is shutdown.
835 */
836 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
837 "info->count is %d\n",
838 __FILE__,__LINE__, info->device_name, info->count);
839 info->count = 1;
840 }
841
842 info->count--;
843
844 /* if at least one open remaining, leave hardware active */
845 if (info->count)
846 goto cleanup;
847
848 info->flags |= ASYNC_CLOSING;
849
850 /* set tty->closing to notify line discipline to
851 * only process XON/XOFF characters. Only the N_TTY
852 * discipline appears to use this (ppp does not).
853 */
854 tty->closing = 1;
855
856 /* wait for transmit data to clear all layers */
857
858 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
859 if (debug_level >= DEBUG_LEVEL_INFO)
860 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
861 __FILE__,__LINE__, info->device_name );
862 tty_wait_until_sent(tty, info->closing_wait);
863 }
864
865 if (info->flags & ASYNC_INITIALIZED)
866 wait_until_sent(tty, info->timeout);
867
868 if (tty->driver->flush_buffer)
869 tty->driver->flush_buffer(tty);
870
871 tty_ldisc_flush(tty);
872
873 shutdown(info);
874
875 tty->closing = 0;
876 info->tty = NULL;
877
878 if (info->blocked_open) {
879 if (info->close_delay) {
880 msleep_interruptible(jiffies_to_msecs(info->close_delay));
881 }
882 wake_up_interruptible(&info->open_wait);
883 }
884
885 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
886
887 wake_up_interruptible(&info->close_wait);
888
889 cleanup:
890 if (debug_level >= DEBUG_LEVEL_INFO)
891 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
892 tty->driver->name, info->count);
893 }
894
895 /* Called by tty_hangup() when a hangup is signaled.
896 * This is the same as closing all open descriptors for the port.
897 */
898 static void hangup(struct tty_struct *tty)
899 {
900 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
901
902 if (debug_level >= DEBUG_LEVEL_INFO)
903 printk("%s(%d):%s hangup()\n",
904 __FILE__,__LINE__, info->device_name );
905
906 if (sanity_check(info, tty->name, "hangup"))
907 return;
908
909 flush_buffer(tty);
910 shutdown(info);
911
912 info->count = 0;
913 info->flags &= ~ASYNC_NORMAL_ACTIVE;
914 info->tty = NULL;
915
916 wake_up_interruptible(&info->open_wait);
917 }
918
919 /* Set new termios settings
920 */
921 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
922 {
923 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
924 unsigned long flags;
925
926 if (debug_level >= DEBUG_LEVEL_INFO)
927 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
928 tty->driver->name );
929
930 /* just return if nothing has changed */
931 if ((tty->termios->c_cflag == old_termios->c_cflag)
932 && (RELEVANT_IFLAG(tty->termios->c_iflag)
933 == RELEVANT_IFLAG(old_termios->c_iflag)))
934 return;
935
936 change_params(info);
937
938 /* Handle transition to B0 status */
939 if (old_termios->c_cflag & CBAUD &&
940 !(tty->termios->c_cflag & CBAUD)) {
941 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
942 spin_lock_irqsave(&info->lock,flags);
943 set_signals(info);
944 spin_unlock_irqrestore(&info->lock,flags);
945 }
946
947 /* Handle transition away from B0 status */
948 if (!(old_termios->c_cflag & CBAUD) &&
949 tty->termios->c_cflag & CBAUD) {
950 info->serial_signals |= SerialSignal_DTR;
951 if (!(tty->termios->c_cflag & CRTSCTS) ||
952 !test_bit(TTY_THROTTLED, &tty->flags)) {
953 info->serial_signals |= SerialSignal_RTS;
954 }
955 spin_lock_irqsave(&info->lock,flags);
956 set_signals(info);
957 spin_unlock_irqrestore(&info->lock,flags);
958 }
959
960 /* Handle turning off CRTSCTS */
961 if (old_termios->c_cflag & CRTSCTS &&
962 !(tty->termios->c_cflag & CRTSCTS)) {
963 tty->hw_stopped = 0;
964 tx_release(tty);
965 }
966 }
967
968 /* Send a block of data
969 *
970 * Arguments:
971 *
972 * tty pointer to tty information structure
973 * buf pointer to buffer containing send data
974 * count size of send data in bytes
975 *
976 * Return Value: number of characters written
977 */
978 static int write(struct tty_struct *tty,
979 const unsigned char *buf, int count)
980 {
981 int c, ret = 0;
982 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
983 unsigned long flags;
984
985 if (debug_level >= DEBUG_LEVEL_INFO)
986 printk("%s(%d):%s write() count=%d\n",
987 __FILE__,__LINE__,info->device_name,count);
988
989 if (sanity_check(info, tty->name, "write"))
990 goto cleanup;
991
992 if (!info->tx_buf)
993 goto cleanup;
994
995 if (info->params.mode == MGSL_MODE_HDLC) {
996 if (count > info->max_frame_size) {
997 ret = -EIO;
998 goto cleanup;
999 }
1000 if (info->tx_active)
1001 goto cleanup;
1002 if (info->tx_count) {
1003 /* send accumulated data from send_char() calls */
1004 /* as frame and wait before accepting more data. */
1005 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1006 goto start;
1007 }
1008 ret = info->tx_count = count;
1009 tx_load_dma_buffer(info, buf, count);
1010 goto start;
1011 }
1012
1013 for (;;) {
1014 c = min_t(int, count,
1015 min(info->max_frame_size - info->tx_count - 1,
1016 info->max_frame_size - info->tx_put));
1017 if (c <= 0)
1018 break;
1019
1020 memcpy(info->tx_buf + info->tx_put, buf, c);
1021
1022 spin_lock_irqsave(&info->lock,flags);
1023 info->tx_put += c;
1024 if (info->tx_put >= info->max_frame_size)
1025 info->tx_put -= info->max_frame_size;
1026 info->tx_count += c;
1027 spin_unlock_irqrestore(&info->lock,flags);
1028
1029 buf += c;
1030 count -= c;
1031 ret += c;
1032 }
1033
1034 if (info->params.mode == MGSL_MODE_HDLC) {
1035 if (count) {
1036 ret = info->tx_count = 0;
1037 goto cleanup;
1038 }
1039 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1040 }
1041 start:
1042 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1043 spin_lock_irqsave(&info->lock,flags);
1044 if (!info->tx_active)
1045 tx_start(info);
1046 spin_unlock_irqrestore(&info->lock,flags);
1047 }
1048
1049 cleanup:
1050 if (debug_level >= DEBUG_LEVEL_INFO)
1051 printk( "%s(%d):%s write() returning=%d\n",
1052 __FILE__,__LINE__,info->device_name,ret);
1053 return ret;
1054 }
1055
1056 /* Add a character to the transmit buffer.
1057 */
1058 static void put_char(struct tty_struct *tty, unsigned char ch)
1059 {
1060 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1061 unsigned long flags;
1062
1063 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1064 printk( "%s(%d):%s put_char(%d)\n",
1065 __FILE__,__LINE__,info->device_name,ch);
1066 }
1067
1068 if (sanity_check(info, tty->name, "put_char"))
1069 return;
1070
1071 if (!info->tx_buf)
1072 return;
1073
1074 spin_lock_irqsave(&info->lock,flags);
1075
1076 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1077 !info->tx_active ) {
1078
1079 if (info->tx_count < info->max_frame_size - 1) {
1080 info->tx_buf[info->tx_put++] = ch;
1081 if (info->tx_put >= info->max_frame_size)
1082 info->tx_put -= info->max_frame_size;
1083 info->tx_count++;
1084 }
1085 }
1086
1087 spin_unlock_irqrestore(&info->lock,flags);
1088 }
1089
1090 /* Send a high-priority XON/XOFF character
1091 */
1092 static void send_xchar(struct tty_struct *tty, char ch)
1093 {
1094 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1095 unsigned long flags;
1096
1097 if (debug_level >= DEBUG_LEVEL_INFO)
1098 printk("%s(%d):%s send_xchar(%d)\n",
1099 __FILE__,__LINE__, info->device_name, ch );
1100
1101 if (sanity_check(info, tty->name, "send_xchar"))
1102 return;
1103
1104 info->x_char = ch;
1105 if (ch) {
1106 /* Make sure transmit interrupts are on */
1107 spin_lock_irqsave(&info->lock,flags);
1108 if (!info->tx_enabled)
1109 tx_start(info);
1110 spin_unlock_irqrestore(&info->lock,flags);
1111 }
1112 }
1113
1114 /* Wait until the transmitter is empty.
1115 */
1116 static void wait_until_sent(struct tty_struct *tty, int timeout)
1117 {
1118 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1119 unsigned long orig_jiffies, char_time;
1120
1121 if (!info )
1122 return;
1123
1124 if (debug_level >= DEBUG_LEVEL_INFO)
1125 printk("%s(%d):%s wait_until_sent() entry\n",
1126 __FILE__,__LINE__, info->device_name );
1127
1128 if (sanity_check(info, tty->name, "wait_until_sent"))
1129 return;
1130
1131 if (!(info->flags & ASYNC_INITIALIZED))
1132 goto exit;
1133
1134 orig_jiffies = jiffies;
1135
1136 /* Set check interval to 1/5 of estimated time to
1137 * send a character, and make it at least 1. The check
1138 * interval should also be less than the timeout.
1139 * Note: use tight timings here to satisfy the NIST-PCTS.
1140 */
1141
1142 if ( info->params.data_rate ) {
1143 char_time = info->timeout/(32 * 5);
1144 if (!char_time)
1145 char_time++;
1146 } else
1147 char_time = 1;
1148
1149 if (timeout)
1150 char_time = min_t(unsigned long, char_time, timeout);
1151
1152 if ( info->params.mode == MGSL_MODE_HDLC ) {
1153 while (info->tx_active) {
1154 msleep_interruptible(jiffies_to_msecs(char_time));
1155 if (signal_pending(current))
1156 break;
1157 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1158 break;
1159 }
1160 } else {
1161 //TODO: determine if there is something similar to USC16C32
1162 // TXSTATUS_ALL_SENT status
1163 while ( info->tx_active && info->tx_enabled) {
1164 msleep_interruptible(jiffies_to_msecs(char_time));
1165 if (signal_pending(current))
1166 break;
1167 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1168 break;
1169 }
1170 }
1171
1172 exit:
1173 if (debug_level >= DEBUG_LEVEL_INFO)
1174 printk("%s(%d):%s wait_until_sent() exit\n",
1175 __FILE__,__LINE__, info->device_name );
1176 }
1177
1178 /* Return the count of free bytes in transmit buffer
1179 */
1180 static int write_room(struct tty_struct *tty)
1181 {
1182 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1183 int ret;
1184
1185 if (sanity_check(info, tty->name, "write_room"))
1186 return 0;
1187
1188 if (info->params.mode == MGSL_MODE_HDLC) {
1189 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1190 } else {
1191 ret = info->max_frame_size - info->tx_count - 1;
1192 if (ret < 0)
1193 ret = 0;
1194 }
1195
1196 if (debug_level >= DEBUG_LEVEL_INFO)
1197 printk("%s(%d):%s write_room()=%d\n",
1198 __FILE__, __LINE__, info->device_name, ret);
1199
1200 return ret;
1201 }
1202
1203 /* enable transmitter and send remaining buffered characters
1204 */
1205 static void flush_chars(struct tty_struct *tty)
1206 {
1207 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1208 unsigned long flags;
1209
1210 if ( debug_level >= DEBUG_LEVEL_INFO )
1211 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1212 __FILE__,__LINE__,info->device_name,info->tx_count);
1213
1214 if (sanity_check(info, tty->name, "flush_chars"))
1215 return;
1216
1217 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1218 !info->tx_buf)
1219 return;
1220
1221 if ( debug_level >= DEBUG_LEVEL_INFO )
1222 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1223 __FILE__,__LINE__,info->device_name );
1224
1225 spin_lock_irqsave(&info->lock,flags);
1226
1227 if (!info->tx_active) {
1228 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1229 info->tx_count ) {
1230 /* operating in synchronous (frame oriented) mode */
1231 /* copy data from circular tx_buf to */
1232 /* transmit DMA buffer. */
1233 tx_load_dma_buffer(info,
1234 info->tx_buf,info->tx_count);
1235 }
1236 tx_start(info);
1237 }
1238
1239 spin_unlock_irqrestore(&info->lock,flags);
1240 }
1241
1242 /* Discard all data in the send buffer
1243 */
1244 static void flush_buffer(struct tty_struct *tty)
1245 {
1246 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1247 unsigned long flags;
1248
1249 if (debug_level >= DEBUG_LEVEL_INFO)
1250 printk("%s(%d):%s flush_buffer() entry\n",
1251 __FILE__,__LINE__, info->device_name );
1252
1253 if (sanity_check(info, tty->name, "flush_buffer"))
1254 return;
1255
1256 spin_lock_irqsave(&info->lock,flags);
1257 info->tx_count = info->tx_put = info->tx_get = 0;
1258 del_timer(&info->tx_timer);
1259 spin_unlock_irqrestore(&info->lock,flags);
1260
1261 wake_up_interruptible(&tty->write_wait);
1262 tty_wakeup(tty);
1263 }
1264
1265 /* throttle (stop) transmitter
1266 */
1267 static void tx_hold(struct tty_struct *tty)
1268 {
1269 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1270 unsigned long flags;
1271
1272 if (sanity_check(info, tty->name, "tx_hold"))
1273 return;
1274
1275 if ( debug_level >= DEBUG_LEVEL_INFO )
1276 printk("%s(%d):%s tx_hold()\n",
1277 __FILE__,__LINE__,info->device_name);
1278
1279 spin_lock_irqsave(&info->lock,flags);
1280 if (info->tx_enabled)
1281 tx_stop(info);
1282 spin_unlock_irqrestore(&info->lock,flags);
1283 }
1284
1285 /* release (start) transmitter
1286 */
1287 static void tx_release(struct tty_struct *tty)
1288 {
1289 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1290 unsigned long flags;
1291
1292 if (sanity_check(info, tty->name, "tx_release"))
1293 return;
1294
1295 if ( debug_level >= DEBUG_LEVEL_INFO )
1296 printk("%s(%d):%s tx_release()\n",
1297 __FILE__,__LINE__,info->device_name);
1298
1299 spin_lock_irqsave(&info->lock,flags);
1300 if (!info->tx_enabled)
1301 tx_start(info);
1302 spin_unlock_irqrestore(&info->lock,flags);
1303 }
1304
1305 /* Service an IOCTL request
1306 *
1307 * Arguments:
1308 *
1309 * tty pointer to tty instance data
1310 * file pointer to associated file object for device
1311 * cmd IOCTL command code
1312 * arg command argument/context
1313 *
1314 * Return Value: 0 if success, otherwise error code
1315 */
1316 static int ioctl(struct tty_struct *tty, struct file *file,
1317 unsigned int cmd, unsigned long arg)
1318 {
1319 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1320 int error;
1321 struct mgsl_icount cnow; /* kernel counter temps */
1322 struct serial_icounter_struct __user *p_cuser; /* user space */
1323 unsigned long flags;
1324 void __user *argp = (void __user *)arg;
1325
1326 if (debug_level >= DEBUG_LEVEL_INFO)
1327 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1328 info->device_name, cmd );
1329
1330 if (sanity_check(info, tty->name, "ioctl"))
1331 return -ENODEV;
1332
1333 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1334 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1335 if (tty->flags & (1 << TTY_IO_ERROR))
1336 return -EIO;
1337 }
1338
1339 switch (cmd) {
1340 case MGSL_IOCGPARAMS:
1341 return get_params(info, argp);
1342 case MGSL_IOCSPARAMS:
1343 return set_params(info, argp);
1344 case MGSL_IOCGTXIDLE:
1345 return get_txidle(info, argp);
1346 case MGSL_IOCSTXIDLE:
1347 return set_txidle(info, (int)arg);
1348 case MGSL_IOCTXENABLE:
1349 return tx_enable(info, (int)arg);
1350 case MGSL_IOCRXENABLE:
1351 return rx_enable(info, (int)arg);
1352 case MGSL_IOCTXABORT:
1353 return tx_abort(info);
1354 case MGSL_IOCGSTATS:
1355 return get_stats(info, argp);
1356 case MGSL_IOCWAITEVENT:
1357 return wait_mgsl_event(info, argp);
1358 case MGSL_IOCLOOPTXDONE:
1359 return 0; // TODO: Not supported, need to document
1360 /* Wait for modem input (DCD,RI,DSR,CTS) change
1361 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1362 */
1363 case TIOCMIWAIT:
1364 return modem_input_wait(info,(int)arg);
1365
1366 /*
1367 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1368 * Return: write counters to the user passed counter struct
1369 * NB: both 1->0 and 0->1 transitions are counted except for
1370 * RI where only 0->1 is counted.
1371 */
1372 case TIOCGICOUNT:
1373 spin_lock_irqsave(&info->lock,flags);
1374 cnow = info->icount;
1375 spin_unlock_irqrestore(&info->lock,flags);
1376 p_cuser = argp;
1377 PUT_USER(error,cnow.cts, &p_cuser->cts);
1378 if (error) return error;
1379 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1380 if (error) return error;
1381 PUT_USER(error,cnow.rng, &p_cuser->rng);
1382 if (error) return error;
1383 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1384 if (error) return error;
1385 PUT_USER(error,cnow.rx, &p_cuser->rx);
1386 if (error) return error;
1387 PUT_USER(error,cnow.tx, &p_cuser->tx);
1388 if (error) return error;
1389 PUT_USER(error,cnow.frame, &p_cuser->frame);
1390 if (error) return error;
1391 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1392 if (error) return error;
1393 PUT_USER(error,cnow.parity, &p_cuser->parity);
1394 if (error) return error;
1395 PUT_USER(error,cnow.brk, &p_cuser->brk);
1396 if (error) return error;
1397 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1398 if (error) return error;
1399 return 0;
1400 default:
1401 return -ENOIOCTLCMD;
1402 }
1403 return 0;
1404 }
1405
1406 /*
1407 * /proc fs routines....
1408 */
1409
1410 static inline int line_info(char *buf, SLMP_INFO *info)
1411 {
1412 char stat_buf[30];
1413 int ret;
1414 unsigned long flags;
1415
1416 ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1417 "\tIRQ=%d MaxFrameSize=%u\n",
1418 info->device_name,
1419 info->phys_sca_base,
1420 info->phys_memory_base,
1421 info->phys_statctrl_base,
1422 info->phys_lcr_base,
1423 info->irq_level,
1424 info->max_frame_size );
1425
1426 /* output current serial signal states */
1427 spin_lock_irqsave(&info->lock,flags);
1428 get_signals(info);
1429 spin_unlock_irqrestore(&info->lock,flags);
1430
1431 stat_buf[0] = 0;
1432 stat_buf[1] = 0;
1433 if (info->serial_signals & SerialSignal_RTS)
1434 strcat(stat_buf, "|RTS");
1435 if (info->serial_signals & SerialSignal_CTS)
1436 strcat(stat_buf, "|CTS");
1437 if (info->serial_signals & SerialSignal_DTR)
1438 strcat(stat_buf, "|DTR");
1439 if (info->serial_signals & SerialSignal_DSR)
1440 strcat(stat_buf, "|DSR");
1441 if (info->serial_signals & SerialSignal_DCD)
1442 strcat(stat_buf, "|CD");
1443 if (info->serial_signals & SerialSignal_RI)
1444 strcat(stat_buf, "|RI");
1445
1446 if (info->params.mode == MGSL_MODE_HDLC) {
1447 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1448 info->icount.txok, info->icount.rxok);
1449 if (info->icount.txunder)
1450 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1451 if (info->icount.txabort)
1452 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1453 if (info->icount.rxshort)
1454 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1455 if (info->icount.rxlong)
1456 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1457 if (info->icount.rxover)
1458 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1459 if (info->icount.rxcrc)
1460 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1461 } else {
1462 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1463 info->icount.tx, info->icount.rx);
1464 if (info->icount.frame)
1465 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1466 if (info->icount.parity)
1467 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1468 if (info->icount.brk)
1469 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1470 if (info->icount.overrun)
1471 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1472 }
1473
1474 /* Append serial signal status to end */
1475 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1476
1477 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1478 info->tx_active,info->bh_requested,info->bh_running,
1479 info->pending_bh);
1480
1481 return ret;
1482 }
1483
1484 /* Called to print information about devices
1485 */
1486 int read_proc(char *page, char **start, off_t off, int count,
1487 int *eof, void *data)
1488 {
1489 int len = 0, l;
1490 off_t begin = 0;
1491 SLMP_INFO *info;
1492
1493 len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1494
1495 info = synclinkmp_device_list;
1496 while( info ) {
1497 l = line_info(page + len, info);
1498 len += l;
1499 if (len+begin > off+count)
1500 goto done;
1501 if (len+begin < off) {
1502 begin += len;
1503 len = 0;
1504 }
1505 info = info->next_device;
1506 }
1507
1508 *eof = 1;
1509 done:
1510 if (off >= len+begin)
1511 return 0;
1512 *start = page + (off-begin);
1513 return ((count < begin+len-off) ? count : begin+len-off);
1514 }
1515
1516 /* Return the count of bytes in transmit buffer
1517 */
1518 static int chars_in_buffer(struct tty_struct *tty)
1519 {
1520 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1521
1522 if (sanity_check(info, tty->name, "chars_in_buffer"))
1523 return 0;
1524
1525 if (debug_level >= DEBUG_LEVEL_INFO)
1526 printk("%s(%d):%s chars_in_buffer()=%d\n",
1527 __FILE__, __LINE__, info->device_name, info->tx_count);
1528
1529 return info->tx_count;
1530 }
1531
1532 /* Signal remote device to throttle send data (our receive data)
1533 */
1534 static void throttle(struct tty_struct * tty)
1535 {
1536 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1537 unsigned long flags;
1538
1539 if (debug_level >= DEBUG_LEVEL_INFO)
1540 printk("%s(%d):%s throttle() entry\n",
1541 __FILE__,__LINE__, info->device_name );
1542
1543 if (sanity_check(info, tty->name, "throttle"))
1544 return;
1545
1546 if (I_IXOFF(tty))
1547 send_xchar(tty, STOP_CHAR(tty));
1548
1549 if (tty->termios->c_cflag & CRTSCTS) {
1550 spin_lock_irqsave(&info->lock,flags);
1551 info->serial_signals &= ~SerialSignal_RTS;
1552 set_signals(info);
1553 spin_unlock_irqrestore(&info->lock,flags);
1554 }
1555 }
1556
1557 /* Signal remote device to stop throttling send data (our receive data)
1558 */
1559 static void unthrottle(struct tty_struct * tty)
1560 {
1561 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1562 unsigned long flags;
1563
1564 if (debug_level >= DEBUG_LEVEL_INFO)
1565 printk("%s(%d):%s unthrottle() entry\n",
1566 __FILE__,__LINE__, info->device_name );
1567
1568 if (sanity_check(info, tty->name, "unthrottle"))
1569 return;
1570
1571 if (I_IXOFF(tty)) {
1572 if (info->x_char)
1573 info->x_char = 0;
1574 else
1575 send_xchar(tty, START_CHAR(tty));
1576 }
1577
1578 if (tty->termios->c_cflag & CRTSCTS) {
1579 spin_lock_irqsave(&info->lock,flags);
1580 info->serial_signals |= SerialSignal_RTS;
1581 set_signals(info);
1582 spin_unlock_irqrestore(&info->lock,flags);
1583 }
1584 }
1585
1586 /* set or clear transmit break condition
1587 * break_state -1=set break condition, 0=clear
1588 */
1589 static void set_break(struct tty_struct *tty, int break_state)
1590 {
1591 unsigned char RegValue;
1592 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1593 unsigned long flags;
1594
1595 if (debug_level >= DEBUG_LEVEL_INFO)
1596 printk("%s(%d):%s set_break(%d)\n",
1597 __FILE__,__LINE__, info->device_name, break_state);
1598
1599 if (sanity_check(info, tty->name, "set_break"))
1600 return;
1601
1602 spin_lock_irqsave(&info->lock,flags);
1603 RegValue = read_reg(info, CTL);
1604 if (break_state == -1)
1605 RegValue |= BIT3;
1606 else
1607 RegValue &= ~BIT3;
1608 write_reg(info, CTL, RegValue);
1609 spin_unlock_irqrestore(&info->lock,flags);
1610 }
1611
1612 #if SYNCLINK_GENERIC_HDLC
1613
1614 /**
1615 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1616 * set encoding and frame check sequence (FCS) options
1617 *
1618 * dev pointer to network device structure
1619 * encoding serial encoding setting
1620 * parity FCS setting
1621 *
1622 * returns 0 if success, otherwise error code
1623 */
1624 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1625 unsigned short parity)
1626 {
1627 SLMP_INFO *info = dev_to_port(dev);
1628 unsigned char new_encoding;
1629 unsigned short new_crctype;
1630
1631 /* return error if TTY interface open */
1632 if (info->count)
1633 return -EBUSY;
1634
1635 switch (encoding)
1636 {
1637 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1638 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1639 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1640 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1641 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1642 default: return -EINVAL;
1643 }
1644
1645 switch (parity)
1646 {
1647 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1648 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1649 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1650 default: return -EINVAL;
1651 }
1652
1653 info->params.encoding = new_encoding;
1654 info->params.crc_type = new_crctype;
1655
1656 /* if network interface up, reprogram hardware */
1657 if (info->netcount)
1658 program_hw(info);
1659
1660 return 0;
1661 }
1662
1663 /**
1664 * called by generic HDLC layer to send frame
1665 *
1666 * skb socket buffer containing HDLC frame
1667 * dev pointer to network device structure
1668 *
1669 * returns 0 if success, otherwise error code
1670 */
1671 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1672 {
1673 SLMP_INFO *info = dev_to_port(dev);
1674 struct net_device_stats *stats = hdlc_stats(dev);
1675 unsigned long flags;
1676
1677 if (debug_level >= DEBUG_LEVEL_INFO)
1678 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1679
1680 /* stop sending until this frame completes */
1681 netif_stop_queue(dev);
1682
1683 /* copy data to device buffers */
1684 info->tx_count = skb->len;
1685 tx_load_dma_buffer(info, skb->data, skb->len);
1686
1687 /* update network statistics */
1688 stats->tx_packets++;
1689 stats->tx_bytes += skb->len;
1690
1691 /* done with socket buffer, so free it */
1692 dev_kfree_skb(skb);
1693
1694 /* save start time for transmit timeout detection */
1695 dev->trans_start = jiffies;
1696
1697 /* start hardware transmitter if necessary */
1698 spin_lock_irqsave(&info->lock,flags);
1699 if (!info->tx_active)
1700 tx_start(info);
1701 spin_unlock_irqrestore(&info->lock,flags);
1702
1703 return 0;
1704 }
1705
1706 /**
1707 * called by network layer when interface enabled
1708 * claim resources and initialize hardware
1709 *
1710 * dev pointer to network device structure
1711 *
1712 * returns 0 if success, otherwise error code
1713 */
1714 static int hdlcdev_open(struct net_device *dev)
1715 {
1716 SLMP_INFO *info = dev_to_port(dev);
1717 int rc;
1718 unsigned long flags;
1719
1720 if (debug_level >= DEBUG_LEVEL_INFO)
1721 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1722
1723 /* generic HDLC layer open processing */
1724 if ((rc = hdlc_open(dev)))
1725 return rc;
1726
1727 /* arbitrate between network and tty opens */
1728 spin_lock_irqsave(&info->netlock, flags);
1729 if (info->count != 0 || info->netcount != 0) {
1730 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1731 spin_unlock_irqrestore(&info->netlock, flags);
1732 return -EBUSY;
1733 }
1734 info->netcount=1;
1735 spin_unlock_irqrestore(&info->netlock, flags);
1736
1737 /* claim resources and init adapter */
1738 if ((rc = startup(info)) != 0) {
1739 spin_lock_irqsave(&info->netlock, flags);
1740 info->netcount=0;
1741 spin_unlock_irqrestore(&info->netlock, flags);
1742 return rc;
1743 }
1744
1745 /* assert DTR and RTS, apply hardware settings */
1746 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1747 program_hw(info);
1748
1749 /* enable network layer transmit */
1750 dev->trans_start = jiffies;
1751 netif_start_queue(dev);
1752
1753 /* inform generic HDLC layer of current DCD status */
1754 spin_lock_irqsave(&info->lock, flags);
1755 get_signals(info);
1756 spin_unlock_irqrestore(&info->lock, flags);
1757 if (info->serial_signals & SerialSignal_DCD)
1758 netif_carrier_on(dev);
1759 else
1760 netif_carrier_off(dev);
1761 return 0;
1762 }
1763
1764 /**
1765 * called by network layer when interface is disabled
1766 * shutdown hardware and release resources
1767 *
1768 * dev pointer to network device structure
1769 *
1770 * returns 0 if success, otherwise error code
1771 */
1772 static int hdlcdev_close(struct net_device *dev)
1773 {
1774 SLMP_INFO *info = dev_to_port(dev);
1775 unsigned long flags;
1776
1777 if (debug_level >= DEBUG_LEVEL_INFO)
1778 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1779
1780 netif_stop_queue(dev);
1781
1782 /* shutdown adapter and release resources */
1783 shutdown(info);
1784
1785 hdlc_close(dev);
1786
1787 spin_lock_irqsave(&info->netlock, flags);
1788 info->netcount=0;
1789 spin_unlock_irqrestore(&info->netlock, flags);
1790
1791 return 0;
1792 }
1793
1794 /**
1795 * called by network layer to process IOCTL call to network device
1796 *
1797 * dev pointer to network device structure
1798 * ifr pointer to network interface request structure
1799 * cmd IOCTL command code
1800 *
1801 * returns 0 if success, otherwise error code
1802 */
1803 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1804 {
1805 const size_t size = sizeof(sync_serial_settings);
1806 sync_serial_settings new_line;
1807 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1808 SLMP_INFO *info = dev_to_port(dev);
1809 unsigned int flags;
1810
1811 if (debug_level >= DEBUG_LEVEL_INFO)
1812 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1813
1814 /* return error if TTY interface open */
1815 if (info->count)
1816 return -EBUSY;
1817
1818 if (cmd != SIOCWANDEV)
1819 return hdlc_ioctl(dev, ifr, cmd);
1820
1821 switch(ifr->ifr_settings.type) {
1822 case IF_GET_IFACE: /* return current sync_serial_settings */
1823
1824 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1825 if (ifr->ifr_settings.size < size) {
1826 ifr->ifr_settings.size = size; /* data size wanted */
1827 return -ENOBUFS;
1828 }
1829
1830 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1831 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1832 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1833 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1834
1835 switch (flags){
1836 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1837 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1838 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1839 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1840 default: new_line.clock_type = CLOCK_DEFAULT;
1841 }
1842
1843 new_line.clock_rate = info->params.clock_speed;
1844 new_line.loopback = info->params.loopback ? 1:0;
1845
1846 if (copy_to_user(line, &new_line, size))
1847 return -EFAULT;
1848 return 0;
1849
1850 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1851
1852 if(!capable(CAP_NET_ADMIN))
1853 return -EPERM;
1854 if (copy_from_user(&new_line, line, size))
1855 return -EFAULT;
1856
1857 switch (new_line.clock_type)
1858 {
1859 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1860 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1861 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1862 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1863 case CLOCK_DEFAULT: flags = info->params.flags &
1864 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1865 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1866 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1867 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1868 default: return -EINVAL;
1869 }
1870
1871 if (new_line.loopback != 0 && new_line.loopback != 1)
1872 return -EINVAL;
1873
1874 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1875 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1876 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1877 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1878 info->params.flags |= flags;
1879
1880 info->params.loopback = new_line.loopback;
1881
1882 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1883 info->params.clock_speed = new_line.clock_rate;
1884 else
1885 info->params.clock_speed = 0;
1886
1887 /* if network interface up, reprogram hardware */
1888 if (info->netcount)
1889 program_hw(info);
1890 return 0;
1891
1892 default:
1893 return hdlc_ioctl(dev, ifr, cmd);
1894 }
1895 }
1896
1897 /**
1898 * called by network layer when transmit timeout is detected
1899 *
1900 * dev pointer to network device structure
1901 */
1902 static void hdlcdev_tx_timeout(struct net_device *dev)
1903 {
1904 SLMP_INFO *info = dev_to_port(dev);
1905 struct net_device_stats *stats = hdlc_stats(dev);
1906 unsigned long flags;
1907
1908 if (debug_level >= DEBUG_LEVEL_INFO)
1909 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1910
1911 stats->tx_errors++;
1912 stats->tx_aborted_errors++;
1913
1914 spin_lock_irqsave(&info->lock,flags);
1915 tx_stop(info);
1916 spin_unlock_irqrestore(&info->lock,flags);
1917
1918 netif_wake_queue(dev);
1919 }
1920
1921 /**
1922 * called by device driver when transmit completes
1923 * reenable network layer transmit if stopped
1924 *
1925 * info pointer to device instance information
1926 */
1927 static void hdlcdev_tx_done(SLMP_INFO *info)
1928 {
1929 if (netif_queue_stopped(info->netdev))
1930 netif_wake_queue(info->netdev);
1931 }
1932
1933 /**
1934 * called by device driver when frame received
1935 * pass frame to network layer
1936 *
1937 * info pointer to device instance information
1938 * buf pointer to buffer contianing frame data
1939 * size count of data bytes in buf
1940 */
1941 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1942 {
1943 struct sk_buff *skb = dev_alloc_skb(size);
1944 struct net_device *dev = info->netdev;
1945 struct net_device_stats *stats = hdlc_stats(dev);
1946
1947 if (debug_level >= DEBUG_LEVEL_INFO)
1948 printk("hdlcdev_rx(%s)\n",dev->name);
1949
1950 if (skb == NULL) {
1951 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1952 stats->rx_dropped++;
1953 return;
1954 }
1955
1956 memcpy(skb_put(skb, size),buf,size);
1957
1958 skb->protocol = hdlc_type_trans(skb, info->netdev);
1959
1960 stats->rx_packets++;
1961 stats->rx_bytes += size;
1962
1963 netif_rx(skb);
1964
1965 info->netdev->last_rx = jiffies;
1966 }
1967
1968 /**
1969 * called by device driver when adding device instance
1970 * do generic HDLC initialization
1971 *
1972 * info pointer to device instance information
1973 *
1974 * returns 0 if success, otherwise error code
1975 */
1976 static int hdlcdev_init(SLMP_INFO *info)
1977 {
1978 int rc;
1979 struct net_device *dev;
1980 hdlc_device *hdlc;
1981
1982 /* allocate and initialize network and HDLC layer objects */
1983
1984 if (!(dev = alloc_hdlcdev(info))) {
1985 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1986 return -ENOMEM;
1987 }
1988
1989 /* for network layer reporting purposes only */
1990 dev->mem_start = info->phys_sca_base;
1991 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1992 dev->irq = info->irq_level;
1993
1994 /* network layer callbacks and settings */
1995 dev->do_ioctl = hdlcdev_ioctl;
1996 dev->open = hdlcdev_open;
1997 dev->stop = hdlcdev_close;
1998 dev->tx_timeout = hdlcdev_tx_timeout;
1999 dev->watchdog_timeo = 10*HZ;
2000 dev->tx_queue_len = 50;
2001
2002 /* generic HDLC layer callbacks and settings */
2003 hdlc = dev_to_hdlc(dev);
2004 hdlc->attach = hdlcdev_attach;
2005 hdlc->xmit = hdlcdev_xmit;
2006
2007 /* register objects with HDLC layer */
2008 if ((rc = register_hdlc_device(dev))) {
2009 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2010 free_netdev(dev);
2011 return rc;
2012 }
2013
2014 info->netdev = dev;
2015 return 0;
2016 }
2017
2018 /**
2019 * called by device driver when removing device instance
2020 * do generic HDLC cleanup
2021 *
2022 * info pointer to device instance information
2023 */
2024 static void hdlcdev_exit(SLMP_INFO *info)
2025 {
2026 unregister_hdlc_device(info->netdev);
2027 free_netdev(info->netdev);
2028 info->netdev = NULL;
2029 }
2030
2031 #endif /* CONFIG_HDLC */
2032
2033
2034 /* Return next bottom half action to perform.
2035 * Return Value: BH action code or 0 if nothing to do.
2036 */
2037 int bh_action(SLMP_INFO *info)
2038 {
2039 unsigned long flags;
2040 int rc = 0;
2041
2042 spin_lock_irqsave(&info->lock,flags);
2043
2044 if (info->pending_bh & BH_RECEIVE) {
2045 info->pending_bh &= ~BH_RECEIVE;
2046 rc = BH_RECEIVE;
2047 } else if (info->pending_bh & BH_TRANSMIT) {
2048 info->pending_bh &= ~BH_TRANSMIT;
2049 rc = BH_TRANSMIT;
2050 } else if (info->pending_bh & BH_STATUS) {
2051 info->pending_bh &= ~BH_STATUS;
2052 rc = BH_STATUS;
2053 }
2054
2055 if (!rc) {
2056 /* Mark BH routine as complete */
2057 info->bh_running = 0;
2058 info->bh_requested = 0;
2059 }
2060
2061 spin_unlock_irqrestore(&info->lock,flags);
2062
2063 return rc;
2064 }
2065
2066 /* Perform bottom half processing of work items queued by ISR.
2067 */
2068 void bh_handler(struct work_struct *work)
2069 {
2070 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2071 int action;
2072
2073 if (!info)
2074 return;
2075
2076 if ( debug_level >= DEBUG_LEVEL_BH )
2077 printk( "%s(%d):%s bh_handler() entry\n",
2078 __FILE__,__LINE__,info->device_name);
2079
2080 info->bh_running = 1;
2081
2082 while((action = bh_action(info)) != 0) {
2083
2084 /* Process work item */
2085 if ( debug_level >= DEBUG_LEVEL_BH )
2086 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2087 __FILE__,__LINE__,info->device_name, action);
2088
2089 switch (action) {
2090
2091 case BH_RECEIVE:
2092 bh_receive(info);
2093 break;
2094 case BH_TRANSMIT:
2095 bh_transmit(info);
2096 break;
2097 case BH_STATUS:
2098 bh_status(info);
2099 break;
2100 default:
2101 /* unknown work item ID */
2102 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2103 __FILE__,__LINE__,info->device_name,action);
2104 break;
2105 }
2106 }
2107
2108 if ( debug_level >= DEBUG_LEVEL_BH )
2109 printk( "%s(%d):%s bh_handler() exit\n",
2110 __FILE__,__LINE__,info->device_name);
2111 }
2112
2113 void bh_receive(SLMP_INFO *info)
2114 {
2115 if ( debug_level >= DEBUG_LEVEL_BH )
2116 printk( "%s(%d):%s bh_receive()\n",
2117 __FILE__,__LINE__,info->device_name);
2118
2119 while( rx_get_frame(info) );
2120 }
2121
2122 void bh_transmit(SLMP_INFO *info)
2123 {
2124 struct tty_struct *tty = info->tty;
2125
2126 if ( debug_level >= DEBUG_LEVEL_BH )
2127 printk( "%s(%d):%s bh_transmit() entry\n",
2128 __FILE__,__LINE__,info->device_name);
2129
2130 if (tty) {
2131 tty_wakeup(tty);
2132 wake_up_interruptible(&tty->write_wait);
2133 }
2134 }
2135
2136 void bh_status(SLMP_INFO *info)
2137 {
2138 if ( debug_level >= DEBUG_LEVEL_BH )
2139 printk( "%s(%d):%s bh_status() entry\n",
2140 __FILE__,__LINE__,info->device_name);
2141
2142 info->ri_chkcount = 0;
2143 info->dsr_chkcount = 0;
2144 info->dcd_chkcount = 0;
2145 info->cts_chkcount = 0;
2146 }
2147
2148 void isr_timer(SLMP_INFO * info)
2149 {
2150 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2151
2152 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2153 write_reg(info, IER2, 0);
2154
2155 /* TMCS, Timer Control/Status Register
2156 *
2157 * 07 CMF, Compare match flag (read only) 1=match
2158 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2159 * 05 Reserved, must be 0
2160 * 04 TME, Timer Enable
2161 * 03..00 Reserved, must be 0
2162 *
2163 * 0000 0000
2164 */
2165 write_reg(info, (unsigned char)(timer + TMCS), 0);
2166
2167 info->irq_occurred = TRUE;
2168
2169 if ( debug_level >= DEBUG_LEVEL_ISR )
2170 printk("%s(%d):%s isr_timer()\n",
2171 __FILE__,__LINE__,info->device_name);
2172 }
2173
2174 void isr_rxint(SLMP_INFO * info)
2175 {
2176 struct tty_struct *tty = info->tty;
2177 struct mgsl_icount *icount = &info->icount;
2178 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2179 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2180
2181 /* clear status bits */
2182 if (status)
2183 write_reg(info, SR1, status);
2184
2185 if (status2)
2186 write_reg(info, SR2, status2);
2187
2188 if ( debug_level >= DEBUG_LEVEL_ISR )
2189 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2190 __FILE__,__LINE__,info->device_name,status,status2);
2191
2192 if (info->params.mode == MGSL_MODE_ASYNC) {
2193 if (status & BRKD) {
2194 icount->brk++;
2195
2196 /* process break detection if tty control
2197 * is not set to ignore it
2198 */
2199 if ( tty ) {
2200 if (!(status & info->ignore_status_mask1)) {
2201 if (info->read_status_mask1 & BRKD) {
2202 tty_insert_flip_char(tty, 0, TTY_BREAK);
2203 if (info->flags & ASYNC_SAK)
2204 do_SAK(tty);
2205 }
2206 }
2207 }
2208 }
2209 }
2210 else {
2211 if (status & (FLGD|IDLD)) {
2212 if (status & FLGD)
2213 info->icount.exithunt++;
2214 else if (status & IDLD)
2215 info->icount.rxidle++;
2216 wake_up_interruptible(&info->event_wait_q);
2217 }
2218 }
2219
2220 if (status & CDCD) {
2221 /* simulate a common modem status change interrupt
2222 * for our handler
2223 */
2224 get_signals( info );
2225 isr_io_pin(info,
2226 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2227 }
2228 }
2229
2230 /*
2231 * handle async rx data interrupts
2232 */
2233 void isr_rxrdy(SLMP_INFO * info)
2234 {
2235 u16 status;
2236 unsigned char DataByte;
2237 struct tty_struct *tty = info->tty;
2238 struct mgsl_icount *icount = &info->icount;
2239
2240 if ( debug_level >= DEBUG_LEVEL_ISR )
2241 printk("%s(%d):%s isr_rxrdy\n",
2242 __FILE__,__LINE__,info->device_name);
2243
2244 while((status = read_reg(info,CST0)) & BIT0)
2245 {
2246 int flag = 0;
2247 int over = 0;
2248 DataByte = read_reg(info,TRB);
2249
2250 icount->rx++;
2251
2252 if ( status & (PE + FRME + OVRN) ) {
2253 printk("%s(%d):%s rxerr=%04X\n",
2254 __FILE__,__LINE__,info->device_name,status);
2255
2256 /* update error statistics */
2257 if (status & PE)
2258 icount->parity++;
2259 else if (status & FRME)
2260 icount->frame++;
2261 else if (status & OVRN)
2262 icount->overrun++;
2263
2264 /* discard char if tty control flags say so */
2265 if (status & info->ignore_status_mask2)
2266 continue;
2267
2268 status &= info->read_status_mask2;
2269
2270 if ( tty ) {
2271 if (status & PE)
2272 flag = TTY_PARITY;
2273 else if (status & FRME)
2274 flag = TTY_FRAME;
2275 if (status & OVRN) {
2276 /* Overrun is special, since it's
2277 * reported immediately, and doesn't
2278 * affect the current character
2279 */
2280 over = 1;
2281 }
2282 }
2283 } /* end of if (error) */
2284
2285 if ( tty ) {
2286 tty_insert_flip_char(tty, DataByte, flag);
2287 if (over)
2288 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2289 }
2290 }
2291
2292 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2293 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2294 __FILE__,__LINE__,info->device_name,
2295 icount->rx,icount->brk,icount->parity,
2296 icount->frame,icount->overrun);
2297 }
2298
2299 if ( tty )
2300 tty_flip_buffer_push(tty);
2301 }
2302
2303 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2304 {
2305 if ( debug_level >= DEBUG_LEVEL_ISR )
2306 printk("%s(%d):%s isr_txeom status=%02x\n",
2307 __FILE__,__LINE__,info->device_name,status);
2308
2309 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2310 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2311 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2312
2313 if (status & UDRN) {
2314 write_reg(info, CMD, TXRESET);
2315 write_reg(info, CMD, TXENABLE);
2316 } else
2317 write_reg(info, CMD, TXBUFCLR);
2318
2319 /* disable and clear tx interrupts */
2320 info->ie0_value &= ~TXRDYE;
2321 info->ie1_value &= ~(IDLE + UDRN);
2322 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2323 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2324
2325 if ( info->tx_active ) {
2326 if (info->params.mode != MGSL_MODE_ASYNC) {
2327 if (status & UDRN)
2328 info->icount.txunder++;
2329 else if (status & IDLE)
2330 info->icount.txok++;
2331 }
2332
2333 info->tx_active = 0;
2334 info->tx_count = info->tx_put = info->tx_get = 0;
2335
2336 del_timer(&info->tx_timer);
2337
2338 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2339 info->serial_signals &= ~SerialSignal_RTS;
2340 info->drop_rts_on_tx_done = 0;
2341 set_signals(info);
2342 }
2343
2344 #if SYNCLINK_GENERIC_HDLC
2345 if (info->netcount)
2346 hdlcdev_tx_done(info);
2347 else
2348 #endif
2349 {
2350 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2351 tx_stop(info);
2352 return;
2353 }
2354 info->pending_bh |= BH_TRANSMIT;
2355 }
2356 }
2357 }
2358
2359
2360 /*
2361 * handle tx status interrupts
2362 */
2363 void isr_txint(SLMP_INFO * info)
2364 {
2365 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2366
2367 /* clear status bits */
2368 write_reg(info, SR1, status);
2369
2370 if ( debug_level >= DEBUG_LEVEL_ISR )
2371 printk("%s(%d):%s isr_txint status=%02x\n",
2372 __FILE__,__LINE__,info->device_name,status);
2373
2374 if (status & (UDRN + IDLE))
2375 isr_txeom(info, status);
2376
2377 if (status & CCTS) {
2378 /* simulate a common modem status change interrupt
2379 * for our handler
2380 */
2381 get_signals( info );
2382 isr_io_pin(info,
2383 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2384
2385 }
2386 }
2387
2388 /*
2389 * handle async tx data interrupts
2390 */
2391 void isr_txrdy(SLMP_INFO * info)
2392 {
2393 if ( debug_level >= DEBUG_LEVEL_ISR )
2394 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2395 __FILE__,__LINE__,info->device_name,info->tx_count);
2396
2397 if (info->params.mode != MGSL_MODE_ASYNC) {
2398 /* disable TXRDY IRQ, enable IDLE IRQ */
2399 info->ie0_value &= ~TXRDYE;
2400 info->ie1_value |= IDLE;
2401 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2402 return;
2403 }
2404
2405 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2406 tx_stop(info);
2407 return;
2408 }
2409
2410 if ( info->tx_count )
2411 tx_load_fifo( info );
2412 else {
2413 info->tx_active = 0;
2414 info->ie0_value &= ~TXRDYE;
2415 write_reg(info, IE0, info->ie0_value);
2416 }
2417
2418 if (info->tx_count < WAKEUP_CHARS)
2419 info->pending_bh |= BH_TRANSMIT;
2420 }
2421
2422 void isr_rxdmaok(SLMP_INFO * info)
2423 {
2424 /* BIT7 = EOT (end of transfer)
2425 * BIT6 = EOM (end of message/frame)
2426 */
2427 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2428
2429 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2430 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2431
2432 if ( debug_level >= DEBUG_LEVEL_ISR )
2433 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2434 __FILE__,__LINE__,info->device_name,status);
2435
2436 info->pending_bh |= BH_RECEIVE;
2437 }
2438
2439 void isr_rxdmaerror(SLMP_INFO * info)
2440 {
2441 /* BIT5 = BOF (buffer overflow)
2442 * BIT4 = COF (counter overflow)
2443 */
2444 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2445
2446 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2447 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2448
2449 if ( debug_level >= DEBUG_LEVEL_ISR )
2450 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2451 __FILE__,__LINE__,info->device_name,status);
2452
2453 info->rx_overflow = TRUE;
2454 info->pending_bh |= BH_RECEIVE;
2455 }
2456
2457 void isr_txdmaok(SLMP_INFO * info)
2458 {
2459 unsigned char status_reg1 = read_reg(info, SR1);
2460
2461 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2462 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2463 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2464
2465 if ( debug_level >= DEBUG_LEVEL_ISR )
2466 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2467 __FILE__,__LINE__,info->device_name,status_reg1);
2468
2469 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2470 write_reg16(info, TRC0, 0);
2471 info->ie0_value |= TXRDYE;
2472 write_reg(info, IE0, info->ie0_value);
2473 }
2474
2475 void isr_txdmaerror(SLMP_INFO * info)
2476 {
2477 /* BIT5 = BOF (buffer overflow)
2478 * BIT4 = COF (counter overflow)
2479 */
2480 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2481
2482 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2483 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2484
2485 if ( debug_level >= DEBUG_LEVEL_ISR )
2486 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2487 __FILE__,__LINE__,info->device_name,status);
2488 }
2489
2490 /* handle input serial signal changes
2491 */
2492 void isr_io_pin( SLMP_INFO *info, u16 status )
2493 {
2494 struct mgsl_icount *icount;
2495
2496 if ( debug_level >= DEBUG_LEVEL_ISR )
2497 printk("%s(%d):isr_io_pin status=%04X\n",
2498 __FILE__,__LINE__,status);
2499
2500 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2501 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2502 icount = &info->icount;
2503 /* update input line counters */
2504 if (status & MISCSTATUS_RI_LATCHED) {
2505 icount->rng++;
2506 if ( status & SerialSignal_RI )
2507 info->input_signal_events.ri_up++;
2508 else
2509 info->input_signal_events.ri_down++;
2510 }
2511 if (status & MISCSTATUS_DSR_LATCHED) {
2512 icount->dsr++;
2513 if ( status & SerialSignal_DSR )
2514 info->input_signal_events.dsr_up++;
2515 else
2516 info->input_signal_events.dsr_down++;
2517 }
2518 if (status & MISCSTATUS_DCD_LATCHED) {
2519 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2520 info->ie1_value &= ~CDCD;
2521 write_reg(info, IE1, info->ie1_value);
2522 }
2523 icount->dcd++;
2524 if (status & SerialSignal_DCD) {
2525 info->input_signal_events.dcd_up++;
2526 } else
2527 info->input_signal_events.dcd_down++;
2528 #if SYNCLINK_GENERIC_HDLC
2529 if (info->netcount) {
2530 if (status & SerialSignal_DCD)
2531 netif_carrier_on(info->netdev);
2532 else
2533 netif_carrier_off(info->netdev);
2534 }
2535 #endif
2536 }
2537 if (status & MISCSTATUS_CTS_LATCHED)
2538 {
2539 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2540 info->ie1_value &= ~CCTS;
2541 write_reg(info, IE1, info->ie1_value);
2542 }
2543 icount->cts++;
2544 if ( status & SerialSignal_CTS )
2545 info->input_signal_events.cts_up++;
2546 else
2547 info->input_signal_events.cts_down++;
2548 }
2549 wake_up_interruptible(&info->status_event_wait_q);
2550 wake_up_interruptible(&info->event_wait_q);
2551
2552 if ( (info->flags & ASYNC_CHECK_CD) &&
2553 (status & MISCSTATUS_DCD_LATCHED) ) {
2554 if ( debug_level >= DEBUG_LEVEL_ISR )
2555 printk("%s CD now %s...", info->device_name,
2556 (status & SerialSignal_DCD) ? "on" : "off");
2557 if (status & SerialSignal_DCD)
2558 wake_up_interruptible(&info->open_wait);
2559 else {
2560 if ( debug_level >= DEBUG_LEVEL_ISR )
2561 printk("doing serial hangup...");
2562 if (info->tty)
2563 tty_hangup(info->tty);
2564 }
2565 }
2566
2567 if ( (info->flags & ASYNC_CTS_FLOW) &&
2568 (status & MISCSTATUS_CTS_LATCHED) ) {
2569 if ( info->tty ) {
2570 if (info->tty->hw_stopped) {
2571 if (status & SerialSignal_CTS) {
2572 if ( debug_level >= DEBUG_LEVEL_ISR )
2573 printk("CTS tx start...");
2574 info->tty->hw_stopped = 0;
2575 tx_start(info);
2576 info->pending_bh |= BH_TRANSMIT;
2577 return;
2578 }
2579 } else {
2580 if (!(status & SerialSignal_CTS)) {
2581 if ( debug_level >= DEBUG_LEVEL_ISR )
2582 printk("CTS tx stop...");
2583 info->tty->hw_stopped = 1;
2584 tx_stop(info);
2585 }
2586 }
2587 }
2588 }
2589 }
2590
2591 info->pending_bh |= BH_STATUS;
2592 }
2593
2594 /* Interrupt service routine entry point.
2595 *
2596 * Arguments:
2597 * irq interrupt number that caused interrupt
2598 * dev_id device ID supplied during interrupt registration
2599 * regs interrupted processor context
2600 */
2601 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id)
2602 {
2603 SLMP_INFO * info;
2604 unsigned char status, status0, status1=0;
2605 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2606 unsigned char timerstatus0, timerstatus1=0;
2607 unsigned char shift;
2608 unsigned int i;
2609 unsigned short tmp;
2610
2611 if ( debug_level >= DEBUG_LEVEL_ISR )
2612 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2613 __FILE__,__LINE__,irq);
2614
2615 info = (SLMP_INFO *)dev_id;
2616 if (!info)
2617 return IRQ_NONE;
2618
2619 spin_lock(&info->lock);
2620
2621 for(;;) {
2622
2623 /* get status for SCA0 (ports 0-1) */
2624 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2625 status0 = (unsigned char)tmp;
2626 dmastatus0 = (unsigned char)(tmp>>8);
2627 timerstatus0 = read_reg(info, ISR2);
2628
2629 if ( debug_level >= DEBUG_LEVEL_ISR )
2630 printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2631 __FILE__,__LINE__,info->device_name,
2632 status0,dmastatus0,timerstatus0);
2633
2634 if (info->port_count == 4) {
2635 /* get status for SCA1 (ports 2-3) */
2636 tmp = read_reg16(info->port_array[2], ISR0);
2637 status1 = (unsigned char)tmp;
2638 dmastatus1 = (unsigned char)(tmp>>8);
2639 timerstatus1 = read_reg(info->port_array[2], ISR2);
2640
2641 if ( debug_level >= DEBUG_LEVEL_ISR )
2642 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2643 __FILE__,__LINE__,info->device_name,
2644 status1,dmastatus1,timerstatus1);
2645 }
2646
2647 if (!status0 && !dmastatus0 && !timerstatus0 &&
2648 !status1 && !dmastatus1 && !timerstatus1)
2649 break;
2650
2651 for(i=0; i < info->port_count ; i++) {
2652 if (info->port_array[i] == NULL)
2653 continue;
2654 if (i < 2) {
2655 status = status0;
2656 dmastatus = dmastatus0;
2657 } else {
2658 status = status1;
2659 dmastatus = dmastatus1;
2660 }
2661
2662 shift = i & 1 ? 4 :0;
2663
2664 if (status & BIT0 << shift)
2665 isr_rxrdy(info->port_array[i]);
2666 if (status & BIT1 << shift)
2667 isr_txrdy(info->port_array[i]);
2668 if (status & BIT2 << shift)
2669 isr_rxint(info->port_array[i]);
2670 if (status & BIT3 << shift)
2671 isr_txint(info->port_array[i]);
2672
2673 if (dmastatus & BIT0 << shift)
2674 isr_rxdmaerror(info->port_array[i]);
2675 if (dmastatus & BIT1 << shift)
2676 isr_rxdmaok(info->port_array[i]);
2677 if (dmastatus & BIT2 << shift)
2678 isr_txdmaerror(info->port_array[i]);
2679 if (dmastatus & BIT3 << shift)
2680 isr_txdmaok(info->port_array[i]);
2681 }
2682
2683 if (timerstatus0 & (BIT5 | BIT4))
2684 isr_timer(info->port_array[0]);
2685 if (timerstatus0 & (BIT7 | BIT6))
2686 isr_timer(info->port_array[1]);
2687 if (timerstatus1 & (BIT5 | BIT4))
2688 isr_timer(info->port_array[2]);
2689 if (timerstatus1 & (BIT7 | BIT6))
2690 isr_timer(info->port_array[3]);
2691 }
2692
2693 for(i=0; i < info->port_count ; i++) {
2694 SLMP_INFO * port = info->port_array[i];
2695
2696 /* Request bottom half processing if there's something
2697 * for it to do and the bh is not already running.
2698 *
2699 * Note: startup adapter diags require interrupts.
2700 * do not request bottom half processing if the
2701 * device is not open in a normal mode.
2702 */
2703 if ( port && (port->count || port->netcount) &&
2704 port->pending_bh && !port->bh_running &&
2705 !port->bh_requested ) {
2706 if ( debug_level >= DEBUG_LEVEL_ISR )
2707 printk("%s(%d):%s queueing bh task.\n",
2708 __FILE__,__LINE__,port->device_name);
2709 schedule_work(&port->task);
2710 port->bh_requested = 1;
2711 }
2712 }
2713
2714 spin_unlock(&info->lock);
2715
2716 if ( debug_level >= DEBUG_LEVEL_ISR )
2717 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2718 __FILE__,__LINE__,irq);
2719 return IRQ_HANDLED;
2720 }
2721
2722 /* Initialize and start device.
2723 */
2724 static int startup(SLMP_INFO * info)
2725 {
2726 if ( debug_level >= DEBUG_LEVEL_INFO )
2727 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2728
2729 if (info->flags & ASYNC_INITIALIZED)
2730 return 0;
2731
2732 if (!info->tx_buf) {
2733 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2734 if (!info->tx_buf) {
2735 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2736 __FILE__,__LINE__,info->device_name);
2737 return -ENOMEM;
2738 }
2739 }
2740
2741 info->pending_bh = 0;
2742
2743 memset(&info->icount, 0, sizeof(info->icount));
2744
2745 /* program hardware for current parameters */
2746 reset_port(info);
2747
2748 change_params(info);
2749
2750 info->status_timer.expires = jiffies + msecs_to_jiffies(10);
2751 add_timer(&info->status_timer);
2752
2753 if (info->tty)
2754 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2755
2756 info->flags |= ASYNC_INITIALIZED;
2757
2758 return 0;
2759 }
2760
2761 /* Called by close() and hangup() to shutdown hardware
2762 */
2763 static void shutdown(SLMP_INFO * info)
2764 {
2765 unsigned long flags;
2766
2767 if (!(info->flags & ASYNC_INITIALIZED))
2768 return;
2769
2770 if (debug_level >= DEBUG_LEVEL_INFO)
2771 printk("%s(%d):%s synclinkmp_shutdown()\n",
2772 __FILE__,__LINE__, info->device_name );
2773
2774 /* clear status wait queue because status changes */
2775 /* can't happen after shutting down the hardware */
2776 wake_up_interruptible(&info->status_event_wait_q);
2777 wake_up_interruptible(&info->event_wait_q);
2778
2779 del_timer(&info->tx_timer);
2780 del_timer(&info->status_timer);
2781
2782 kfree(info->tx_buf);
2783 info->tx_buf = NULL;
2784
2785 spin_lock_irqsave(&info->lock,flags);
2786
2787 reset_port(info);
2788
2789 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2790 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2791 set_signals(info);
2792 }
2793
2794 spin_unlock_irqrestore(&info->lock,flags);
2795
2796 if (info->tty)
2797 set_bit(TTY_IO_ERROR, &info->tty->flags);
2798
2799 info->flags &= ~ASYNC_INITIALIZED;
2800 }
2801
2802 static void program_hw(SLMP_INFO *info)
2803 {
2804 unsigned long flags;
2805
2806 spin_lock_irqsave(&info->lock,flags);
2807
2808 rx_stop(info);
2809 tx_stop(info);
2810
2811 info->tx_count = info->tx_put = info->tx_get = 0;
2812
2813 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2814 hdlc_mode(info);
2815 else
2816 async_mode(info);
2817
2818 set_signals(info);
2819
2820 info->dcd_chkcount = 0;
2821 info->cts_chkcount = 0;
2822 info->ri_chkcount = 0;
2823 info->dsr_chkcount = 0;
2824
2825 info->ie1_value |= (CDCD|CCTS);
2826 write_reg(info, IE1, info->ie1_value);
2827
2828 get_signals(info);
2829
2830 if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2831 rx_start(info);
2832
2833 spin_unlock_irqrestore(&info->lock,flags);
2834 }
2835
2836 /* Reconfigure adapter based on new parameters
2837 */
2838 static void change_params(SLMP_INFO *info)
2839 {
2840 unsigned cflag;
2841 int bits_per_char;
2842
2843 if (!info->tty || !info->tty->termios)
2844 return;
2845
2846 if (debug_level >= DEBUG_LEVEL_INFO)
2847 printk("%s(%d):%s change_params()\n",
2848 __FILE__,__LINE__, info->device_name );
2849
2850 cflag = info->tty->termios->c_cflag;
2851
2852 /* if B0 rate (hangup) specified then negate DTR and RTS */
2853 /* otherwise assert DTR and RTS */
2854 if (cflag & CBAUD)
2855 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2856 else
2857 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2858
2859 /* byte size and parity */
2860
2861 switch (cflag & CSIZE) {
2862 case CS5: info->params.data_bits = 5; break;
2863 case CS6: info->params.data_bits = 6; break;
2864 case CS7: info->params.data_bits = 7; break;
2865 case CS8: info->params.data_bits = 8; break;
2866 /* Never happens, but GCC is too dumb to figure it out */
2867 default: info->params.data_bits = 7; break;
2868 }
2869
2870 if (cflag & CSTOPB)
2871 info->params.stop_bits = 2;
2872 else
2873 info->params.stop_bits = 1;
2874
2875 info->params.parity = ASYNC_PARITY_NONE;
2876 if (cflag & PARENB) {
2877 if (cflag & PARODD)
2878 info->params.parity = ASYNC_PARITY_ODD;
2879 else
2880 info->params.parity = ASYNC_PARITY_EVEN;
2881 #ifdef CMSPAR
2882 if (cflag & CMSPAR)
2883 info->params.parity = ASYNC_PARITY_SPACE;
2884 #endif
2885 }
2886
2887 /* calculate number of jiffies to transmit a full
2888 * FIFO (32 bytes) at specified data rate
2889 */
2890 bits_per_char = info->params.data_bits +
2891 info->params.stop_bits + 1;
2892
2893 /* if port data rate is set to 460800 or less then
2894 * allow tty settings to override, otherwise keep the
2895 * current data rate.
2896 */
2897 if (info->params.data_rate <= 460800) {
2898 info->params.data_rate = tty_get_baud_rate(info->tty);
2899 }
2900
2901 if ( info->params.data_rate ) {
2902 info->timeout = (32*HZ*bits_per_char) /
2903 info->params.data_rate;
2904 }
2905 info->timeout += HZ/50; /* Add .02 seconds of slop */
2906
2907 if (cflag & CRTSCTS)
2908 info->flags |= ASYNC_CTS_FLOW;
2909 else
2910 info->flags &= ~ASYNC_CTS_FLOW;
2911
2912 if (cflag & CLOCAL)
2913 info->flags &= ~ASYNC_CHECK_CD;
2914 else
2915 info->flags |= ASYNC_CHECK_CD;
2916
2917 /* process tty input control flags */
2918
2919 info->read_status_mask2 = OVRN;
2920 if (I_INPCK(info->tty))
2921 info->read_status_mask2 |= PE | FRME;
2922 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2923 info->read_status_mask1 |= BRKD;
2924 if (I_IGNPAR(info->tty))
2925 info->ignore_status_mask2 |= PE | FRME;
2926 if (I_IGNBRK(info->tty)) {
2927 info->ignore_status_mask1 |= BRKD;
2928 /* If ignoring parity and break indicators, ignore
2929 * overruns too. (For real raw support).
2930 */
2931 if (I_IGNPAR(info->tty))
2932 info->ignore_status_mask2 |= OVRN;
2933 }
2934
2935 program_hw(info);
2936 }
2937
2938 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2939 {
2940 int err;
2941
2942 if (debug_level >= DEBUG_LEVEL_INFO)
2943 printk("%s(%d):%s get_params()\n",
2944 __FILE__,__LINE__, info->device_name);
2945
2946 if (!user_icount) {
2947 memset(&info->icount, 0, sizeof(info->icount));
2948 } else {
2949 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2950 if (err)
2951 return -EFAULT;
2952 }
2953
2954 return 0;
2955 }
2956
2957 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2958 {
2959 int err;
2960 if (debug_level >= DEBUG_LEVEL_INFO)
2961 printk("%s(%d):%s get_params()\n",
2962 __FILE__,__LINE__, info->device_name);
2963
2964 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2965 if (err) {
2966 if ( debug_level >= DEBUG_LEVEL_INFO )
2967 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2968 __FILE__,__LINE__,info->device_name);
2969 return -EFAULT;
2970 }
2971
2972 return 0;
2973 }
2974
2975 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2976 {
2977 unsigned long flags;
2978 MGSL_PARAMS tmp_params;
2979 int err;
2980
2981 if (debug_level >= DEBUG_LEVEL_INFO)
2982 printk("%s(%d):%s set_params\n",
2983 __FILE__,__LINE__,info->device_name );
2984 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2985 if (err) {
2986 if ( debug_level >= DEBUG_LEVEL_INFO )
2987 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2988 __FILE__,__LINE__,info->device_name);
2989 return -EFAULT;
2990 }
2991
2992 spin_lock_irqsave(&info->lock,flags);
2993 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2994 spin_unlock_irqrestore(&info->lock,flags);
2995
2996 change_params(info);
2997
2998 return 0;
2999 }
3000
3001 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
3002 {
3003 int err;
3004
3005 if (debug_level >= DEBUG_LEVEL_INFO)
3006 printk("%s(%d):%s get_txidle()=%d\n",
3007 __FILE__,__LINE__, info->device_name, info->idle_mode);
3008
3009 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3010 if (err) {
3011 if ( debug_level >= DEBUG_LEVEL_INFO )
3012 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3013 __FILE__,__LINE__,info->device_name);
3014 return -EFAULT;
3015 }
3016
3017 return 0;
3018 }
3019
3020 static int set_txidle(SLMP_INFO * info, int idle_mode)
3021 {
3022 unsigned long flags;
3023
3024 if (debug_level >= DEBUG_LEVEL_INFO)
3025 printk("%s(%d):%s set_txidle(%d)\n",
3026 __FILE__,__LINE__,info->device_name, idle_mode );
3027
3028 spin_lock_irqsave(&info->lock,flags);
3029 info->idle_mode = idle_mode;
3030 tx_set_idle( info );
3031 spin_unlock_irqrestore(&info->lock,flags);
3032 return 0;
3033 }
3034
3035 static int tx_enable(SLMP_INFO * info, int enable)
3036 {
3037 unsigned long flags;
3038
3039 if (debug_level >= DEBUG_LEVEL_INFO)
3040 printk("%s(%d):%s tx_enable(%d)\n",
3041 __FILE__,__LINE__,info->device_name, enable);
3042
3043 spin_lock_irqsave(&info->lock,flags);
3044 if ( enable ) {
3045 if ( !info->tx_enabled ) {
3046 tx_start(info);
3047 }
3048 } else {
3049 if ( info->tx_enabled )
3050 tx_stop(info);
3051 }
3052 spin_unlock_irqrestore(&info->lock,flags);
3053 return 0;
3054 }
3055
3056 /* abort send HDLC frame
3057 */
3058 static int tx_abort(SLMP_INFO * info)
3059 {
3060 unsigned long flags;
3061
3062 if (debug_level >= DEBUG_LEVEL_INFO)
3063 printk("%s(%d):%s tx_abort()\n",
3064 __FILE__,__LINE__,info->device_name);
3065
3066 spin_lock_irqsave(&info->lock,flags);
3067 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3068 info->ie1_value &= ~UDRN;
3069 info->ie1_value |= IDLE;
3070 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
3071 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3072
3073 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3074 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3075
3076 write_reg(info, CMD, TXABORT);
3077 }
3078 spin_unlock_irqrestore(&info->lock,flags);
3079 return 0;
3080 }
3081
3082 static int rx_enable(SLMP_INFO * info, int enable)
3083 {
3084 unsigned long flags;
3085
3086 if (debug_level >= DEBUG_LEVEL_INFO)
3087 printk("%s(%d):%s rx_enable(%d)\n",
3088 __FILE__,__LINE__,info->device_name,enable);
3089
3090 spin_lock_irqsave(&info->lock,flags);
3091 if ( enable ) {
3092 if ( !info->rx_enabled )
3093 rx_start(info);
3094 } else {
3095 if ( info->rx_enabled )
3096 rx_stop(info);
3097 }
3098 spin_unlock_irqrestore(&info->lock,flags);
3099 return 0;
3100 }
3101
3102 /* wait for specified event to occur
3103 */
3104 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3105 {
3106 unsigned long flags;
3107 int s;
3108 int rc=0;
3109 struct mgsl_icount cprev, cnow;
3110 int events;
3111 int mask;
3112 struct _input_signal_events oldsigs, newsigs;
3113 DECLARE_WAITQUEUE(wait, current);
3114
3115 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3116 if (rc) {
3117 return -EFAULT;
3118 }
3119
3120 if (debug_level >= DEBUG_LEVEL_INFO)
3121 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3122 __FILE__,__LINE__,info->device_name,mask);
3123
3124 spin_lock_irqsave(&info->lock,flags);
3125
3126 /* return immediately if state matches requested events */
3127 get_signals(info);
3128 s = info->serial_signals;
3129
3130 events = mask &
3131 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3132 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3133 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3134 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3135 if (events) {
3136 spin_unlock_irqrestore(&info->lock,flags);
3137 goto exit;
3138 }
3139
3140 /* save current irq counts */
3141 cprev = info->icount;
3142 oldsigs = info->input_signal_events;
3143
3144 /* enable hunt and idle irqs if needed */
3145 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3146 unsigned char oldval = info->ie1_value;
3147 unsigned char newval = oldval +
3148 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3149 (mask & MgslEvent_IdleReceived ? IDLD:0);
3150 if ( oldval != newval ) {
3151 info->ie1_value = newval;
3152 write_reg(info, IE1, info->ie1_value);
3153 }
3154 }
3155
3156 set_current_state(TASK_INTERRUPTIBLE);
3157 add_wait_queue(&info->event_wait_q, &wait);
3158
3159 spin_unlock_irqrestore(&info->lock,flags);
3160
3161 for(;;) {
3162 schedule();
3163 if (signal_pending(current)) {
3164 rc = -ERESTARTSYS;
3165 break;
3166 }
3167
3168 /* get current irq counts */
3169 spin_lock_irqsave(&info->lock,flags);
3170 cnow = info->icount;
3171 newsigs = info->input_signal_events;
3172 set_current_state(TASK_INTERRUPTIBLE);
3173 spin_unlock_irqrestore(&info->lock,flags);
3174
3175 /* if no change, wait aborted for some reason */
3176 if (newsigs.dsr_up == oldsigs.dsr_up &&
3177 newsigs.dsr_down == oldsigs.dsr_down &&
3178 newsigs.dcd_up == oldsigs.dcd_up &&
3179 newsigs.dcd_down == oldsigs.dcd_down &&
3180 newsigs.cts_up == oldsigs.cts_up &&
3181 newsigs.cts_down == oldsigs.cts_down &&
3182 newsigs.ri_up == oldsigs.ri_up &&
3183 newsigs.ri_down == oldsigs.ri_down &&
3184 cnow.exithunt == cprev.exithunt &&
3185 cnow.rxidle == cprev.rxidle) {
3186 rc = -EIO;
3187 break;
3188 }
3189
3190 events = mask &
3191 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3192 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3193 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3194 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3195 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3196 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3197 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3198 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3199 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3200 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3201 if (events)
3202 break;
3203
3204 cprev = cnow;
3205 oldsigs = newsigs;
3206 }
3207
3208 remove_wait_queue(&info->event_wait_q, &wait);
3209 set_current_state(TASK_RUNNING);
3210
3211
3212 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3213 spin_lock_irqsave(&info->lock,flags);
3214 if (!waitqueue_active(&info->event_wait_q)) {
3215 /* disable enable exit hunt mode/idle rcvd IRQs */
3216 info->ie1_value &= ~(FLGD|IDLD);
3217 write_reg(info, IE1, info->ie1_value);
3218 }
3219 spin_unlock_irqrestore(&info->lock,flags);
3220 }
3221 exit:
3222 if ( rc == 0 )
3223 PUT_USER(rc, events, mask_ptr);
3224
3225 return rc;
3226 }
3227
3228 static int modem_input_wait(SLMP_INFO *info,int arg)
3229 {
3230 unsigned long flags;
3231 int rc;
3232 struct mgsl_icount cprev, cnow;
3233 DECLARE_WAITQUEUE(wait, current);
3234
3235 /* save current irq counts */
3236 spin_lock_irqsave(&info->lock,flags);
3237 cprev = info->icount;
3238 add_wait_queue(&info->status_event_wait_q, &wait);
3239 set_current_state(TASK_INTERRUPTIBLE);
3240 spin_unlock_irqrestore(&info->lock,flags);
3241
3242 for(;;) {
3243 schedule();
3244 if (signal_pending(current)) {
3245 rc = -ERESTARTSYS;
3246 break;
3247 }
3248
3249 /* get new irq counts */
3250 spin_lock_irqsave(&info->lock,flags);
3251 cnow = info->icount;
3252 set_current_state(TASK_INTERRUPTIBLE);
3253 spin_unlock_irqrestore(&info->lock,flags);
3254
3255 /* if no change, wait aborted for some reason */
3256 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3257 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3258 rc = -EIO;
3259 break;
3260 }
3261
3262 /* check for change in caller specified modem input */
3263 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3264 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3265 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3266 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3267 rc = 0;
3268 break;
3269 }
3270
3271 cprev = cnow;
3272 }
3273 remove_wait_queue(&info->status_event_wait_q, &wait);
3274 set_current_state(TASK_RUNNING);
3275 return rc;
3276 }
3277
3278 /* return the state of the serial control and status signals
3279 */
3280 static int tiocmget(struct tty_struct *tty, struct file *file)
3281 {
3282 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3283 unsigned int result;
3284 unsigned long flags;
3285
3286 spin_lock_irqsave(&info->lock,flags);
3287 get_signals(info);
3288 spin_unlock_irqrestore(&info->lock,flags);
3289
3290 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3291 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3292 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3293 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3294 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3295 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3296
3297 if (debug_level >= DEBUG_LEVEL_INFO)
3298 printk("%s(%d):%s tiocmget() value=%08X\n",
3299 __FILE__,__LINE__, info->device_name, result );
3300 return result;
3301 }
3302
3303 /* set modem control signals (DTR/RTS)
3304 */
3305 static int tiocmset(struct tty_struct *tty, struct file *file,
3306 unsigned int set, unsigned int clear)
3307 {
3308 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3309 unsigned long flags;
3310
3311 if (debug_level >= DEBUG_LEVEL_INFO)
3312 printk("%s(%d):%s tiocmset(%x,%x)\n",
3313 __FILE__,__LINE__,info->device_name, set, clear);
3314
3315 if (set & TIOCM_RTS)
3316 info->serial_signals |= SerialSignal_RTS;
3317 if (set & TIOCM_DTR)
3318 info->serial_signals |= SerialSignal_DTR;
3319 if (clear & TIOCM_RTS)
3320 info->serial_signals &= ~SerialSignal_RTS;
3321 if (clear & TIOCM_DTR)
3322 info->serial_signals &= ~SerialSignal_DTR;
3323
3324 spin_lock_irqsave(&info->lock,flags);
3325 set_signals(info);
3326 spin_unlock_irqrestore(&info->lock,flags);
3327
3328 return 0;
3329 }
3330
3331
3332
3333 /* Block the current process until the specified port is ready to open.
3334 */
3335 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3336 SLMP_INFO *info)
3337 {
3338 DECLARE_WAITQUEUE(wait, current);
3339 int retval;
3340 int do_clocal = 0, extra_count = 0;
3341 unsigned long flags;
3342
3343 if (debug_level >= DEBUG_LEVEL_INFO)
3344 printk("%s(%d):%s block_til_ready()\n",
3345 __FILE__,__LINE__, tty->driver->name );
3346
3347 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3348 /* nonblock mode is set or port is not enabled */
3349 /* just verify that callout device is not active */
3350 info->flags |= ASYNC_NORMAL_ACTIVE;
3351 return 0;
3352 }
3353
3354 if (tty->termios->c_cflag & CLOCAL)
3355 do_clocal = 1;
3356
3357 /* Wait for carrier detect and the line to become
3358 * free (i.e., not in use by the callout). While we are in
3359 * this loop, info->count is dropped by one, so that
3360 * close() knows when to free things. We restore it upon
3361 * exit, either normal or abnormal.
3362 */
3363
3364 retval = 0;
3365 add_wait_queue(&info->open_wait, &wait);
3366
3367 if (debug_level >= DEBUG_LEVEL_INFO)
3368 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3369 __FILE__,__LINE__, tty->driver->name, info->count );
3370
3371 spin_lock_irqsave(&info->lock, flags);
3372 if (!tty_hung_up_p(filp)) {
3373 extra_count = 1;
3374 info->count--;
3375 }
3376 spin_unlock_irqrestore(&info->lock, flags);
3377 info->blocked_open++;
3378
3379 while (1) {
3380 if ((tty->termios->c_cflag & CBAUD)) {
3381 spin_lock_irqsave(&info->lock,flags);
3382 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3383 set_signals(info);
3384 spin_unlock_irqrestore(&info->lock,flags);
3385 }
3386
3387 set_current_state(TASK_INTERRUPTIBLE);
3388
3389 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3390 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3391 -EAGAIN : -ERESTARTSYS;
3392 break;
3393 }
3394
3395 spin_lock_irqsave(&info->lock,flags);
3396 get_signals(info);
3397 spin_unlock_irqrestore(&info->lock,flags);
3398
3399 if (!(info->flags & ASYNC_CLOSING) &&
3400 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3401 break;
3402 }
3403
3404 if (signal_pending(current)) {
3405 retval = -ERESTARTSYS;
3406 break;
3407 }
3408
3409 if (debug_level >= DEBUG_LEVEL_INFO)
3410 printk("%s(%d):%s block_til_ready() count=%d\n",
3411 __FILE__,__LINE__, tty->driver->name, info->count );
3412
3413 schedule();
3414 }
3415
3416 set_current_state(TASK_RUNNING);
3417 remove_wait_queue(&info->open_wait, &wait);
3418
3419 if (extra_count)
3420 info->count++;
3421 info->blocked_open--;
3422
3423 if (debug_level >= DEBUG_LEVEL_INFO)
3424 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3425 __FILE__,__LINE__, tty->driver->name, info->count );
3426
3427 if (!retval)
3428 info->flags |= ASYNC_NORMAL_ACTIVE;
3429
3430 return retval;
3431 }
3432
3433 int alloc_dma_bufs(SLMP_INFO *info)
3434 {
3435 unsigned short BuffersPerFrame;
3436 unsigned short BufferCount;
3437
3438 // Force allocation to start at 64K boundary for each port.
3439 // This is necessary because *all* buffer descriptors for a port
3440 // *must* be in the same 64K block. All descriptors on a port
3441 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3442 // into the CBP register.
3443 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3444
3445 /* Calculate the number of DMA buffers necessary to hold the */
3446 /* largest allowable frame size. Note: If the max frame size is */
3447 /* not an even multiple of the DMA buffer size then we need to */
3448 /* round the buffer count per frame up one. */
3449
3450 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3451 if ( info->max_frame_size % SCABUFSIZE )
3452 BuffersPerFrame++;
3453
3454 /* calculate total number of data buffers (SCABUFSIZE) possible
3455 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3456 * for the descriptor list (BUFFERLISTSIZE).
3457 */
3458 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3459
3460 /* limit number of buffers to maximum amount of descriptors */
3461 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3462 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3463
3464 /* use enough buffers to transmit one max size frame */
3465 info->tx_buf_count = BuffersPerFrame + 1;
3466
3467 /* never use more than half the available buffers for transmit */
3468 if (info->tx_buf_count > (BufferCount/2))
3469 info->tx_buf_count = BufferCount/2;
3470
3471 if (info->tx_buf_count > SCAMAXDESC)
3472 info->tx_buf_count = SCAMAXDESC;
3473
3474 /* use remaining buffers for receive */
3475 info->rx_buf_count = BufferCount - info->tx_buf_count;
3476
3477 if (info->rx_buf_count > SCAMAXDESC)
3478 info->rx_buf_count = SCAMAXDESC;
3479
3480 if ( debug_level >= DEBUG_LEVEL_INFO )
3481 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3482 __FILE__,__LINE__, info->device_name,
3483 info->tx_buf_count,info->rx_buf_count);
3484
3485 if ( alloc_buf_list( info ) < 0 ||
3486 alloc_frame_bufs(info,
3487 info->rx_buf_list,
3488 info->rx_buf_list_ex,
3489 info->rx_buf_count) < 0 ||
3490 alloc_frame_bufs(info,
3491 info->tx_buf_list,
3492 info->tx_buf_list_ex,
3493 info->tx_buf_count) < 0 ||
3494 alloc_tmp_rx_buf(info) < 0 ) {
3495 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3496 __FILE__,__LINE__, info->device_name);
3497 return -ENOMEM;
3498 }
3499
3500 rx_reset_buffers( info );
3501
3502 return 0;
3503 }
3504
3505 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3506 */
3507 int alloc_buf_list(SLMP_INFO *info)
3508 {
3509 unsigned int i;
3510
3511 /* build list in adapter shared memory */
3512 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3513 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3514 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3515
3516 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3517
3518 /* Save virtual address pointers to the receive and */
3519 /* transmit buffer lists. (Receive 1st). These pointers will */
3520 /* be used by the processor to access the lists. */
3521 info->rx_buf_list = (SCADESC *)info->buffer_list;
3522
3523 info->tx_buf_list = (SCADESC *)info->buffer_list;
3524 info->tx_buf_list += info->rx_buf_count;
3525
3526 /* Build links for circular buffer entry lists (tx and rx)
3527 *
3528 * Note: links are physical addresses read by the SCA device
3529 * to determine the next buffer entry to use.
3530 */
3531
3532 for ( i = 0; i < info->rx_buf_count; i++ ) {
3533 /* calculate and store physical address of this buffer entry */
3534 info->rx_buf_list_ex[i].phys_entry =
3535 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3536
3537 /* calculate and store physical address of */
3538 /* next entry in cirular list of entries */
3539 info->rx_buf_list[i].next = info->buffer_list_phys;
3540 if ( i < info->rx_buf_count - 1 )
3541 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3542
3543 info->rx_buf_list[i].length = SCABUFSIZE;
3544 }
3545
3546 for ( i = 0; i < info->tx_buf_count; i++ ) {
3547 /* calculate and store physical address of this buffer entry */
3548 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3549 ((info->rx_buf_count + i) * sizeof(SCADESC));
3550
3551 /* calculate and store physical address of */
3552 /* next entry in cirular list of entries */
3553
3554 info->tx_buf_list[i].next = info->buffer_list_phys +
3555 info->rx_buf_count * sizeof(SCADESC);
3556
3557 if ( i < info->tx_buf_count - 1 )
3558 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3559 }
3560
3561 return 0;
3562 }
3563
3564 /* Allocate the frame DMA buffers used by the specified buffer list.
3565 */
3566 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3567 {
3568 int i;
3569 unsigned long phys_addr;
3570
3571 for ( i = 0; i < count; i++ ) {
3572 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3573 phys_addr = info->port_array[0]->last_mem_alloc;
3574 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3575
3576 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3577 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3578 }
3579
3580 return 0;
3581 }
3582
3583 void free_dma_bufs(SLMP_INFO *info)
3584 {
3585 info->buffer_list = NULL;
3586 info->rx_buf_list = NULL;
3587 info->tx_buf_list = NULL;
3588 }
3589
3590 /* allocate buffer large enough to hold max_frame_size.
3591 * This buffer is used to pass an assembled frame to the line discipline.
3592 */
3593 int alloc_tmp_rx_buf(SLMP_INFO *info)
3594 {
3595 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3596 if (info->tmp_rx_buf == NULL)
3597 return -ENOMEM;
3598 return 0;
3599 }
3600
3601 void free_tmp_rx_buf(SLMP_INFO *info)
3602 {
3603 kfree(info->tmp_rx_buf);
3604 info->tmp_rx_buf = NULL;
3605 }
3606
3607 int claim_resources(SLMP_INFO *info)
3608 {
3609 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3610 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3611 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3612 info->init_error = DiagStatus_AddressConflict;
3613 goto errout;
3614 }
3615 else
3616 info->shared_mem_requested = 1;
3617
3618 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3619 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3620 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3621 info->init_error = DiagStatus_AddressConflict;
3622 goto errout;
3623 }
3624 else
3625 info->lcr_mem_requested = 1;
3626
3627 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3628 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3629 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3630 info->init_error = DiagStatus_AddressConflict;
3631 goto errout;
3632 }
3633 else
3634 info->sca_base_requested = 1;
3635
3636 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3637 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3638 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3639 info->init_error = DiagStatus_AddressConflict;
3640 goto errout;
3641 }
3642 else
3643 info->sca_statctrl_requested = 1;
3644
3645 info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3646 if (!info->memory_base) {
3647 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3648 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3649 info->init_error = DiagStatus_CantAssignPciResources;
3650 goto errout;
3651 }
3652
3653 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3654 if (!info->lcr_base) {
3655 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3656 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3657 info->init_error = DiagStatus_CantAssignPciResources;
3658 goto errout;
3659 }
3660 info->lcr_base += info->lcr_offset;
3661
3662 info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3663 if (!info->sca_base) {
3664 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3665 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3666 info->init_error = DiagStatus_CantAssignPciResources;
3667 goto errout;
3668 }
3669 info->sca_base += info->sca_offset;
3670
3671 info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3672 if (!info->statctrl_base) {
3673 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3674 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3675 info->init_error = DiagStatus_CantAssignPciResources;
3676 goto errout;
3677 }
3678 info->statctrl_base += info->statctrl_offset;
3679
3680 if ( !memory_test(info) ) {
3681 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3682 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3683 info->init_error = DiagStatus_MemoryError;
3684 goto errout;
3685 }
3686
3687 return 0;
3688
3689 errout:
3690 release_resources( info );
3691 return -ENODEV;
3692 }
3693
3694 void release_resources(SLMP_INFO *info)
3695 {
3696 if ( debug_level >= DEBUG_LEVEL_INFO )
3697 printk( "%s(%d):%s release_resources() entry\n",
3698 __FILE__,__LINE__,info->device_name );
3699
3700 if ( info->irq_requested ) {
3701 free_irq(info->irq_level, info);
3702 info->irq_requested = 0;
3703 }
3704
3705 if ( info->shared_mem_requested ) {
3706 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3707 info->shared_mem_requested = 0;
3708 }
3709 if ( info->lcr_mem_requested ) {
3710 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3711 info->lcr_mem_requested = 0;
3712 }
3713 if ( info->sca_base_requested ) {
3714 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3715 info->sca_base_requested = 0;
3716 }
3717 if ( info->sca_statctrl_requested ) {
3718 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3719 info->sca_statctrl_requested = 0;
3720 }
3721
3722 if (info->memory_base){
3723 iounmap(info->memory_base);
3724 info->memory_base = NULL;
3725 }
3726
3727 if (info->sca_base) {
3728 iounmap(info->sca_base - info->sca_offset);
3729 info->sca_base=NULL;
3730 }
3731
3732 if (info->statctrl_base) {
3733 iounmap(info->statctrl_base - info->statctrl_offset);
3734 info->statctrl_base=NULL;
3735 }
3736
3737 if (info->lcr_base){
3738 iounmap(info->lcr_base - info->lcr_offset);
3739 info->lcr_base = NULL;
3740 }
3741
3742 if ( debug_level >= DEBUG_LEVEL_INFO )
3743 printk( "%s(%d):%s release_resources() exit\n",
3744 __FILE__,__LINE__,info->device_name );
3745 }
3746
3747 /* Add the specified device instance data structure to the
3748 * global linked list of devices and increment the device count.
3749 */
3750 void add_device(SLMP_INFO *info)
3751 {
3752 info->next_device = NULL;
3753 info->line = synclinkmp_device_count;
3754 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3755
3756 if (info->line < MAX_DEVICES) {
3757 if (maxframe[info->line])
3758 info->max_frame_size = maxframe[info->line];
3759 info->dosyncppp = dosyncppp[info->line];
3760 }
3761
3762 synclinkmp_device_count++;
3763
3764 if ( !synclinkmp_device_list )
3765 synclinkmp_device_list = info;
3766 else {
3767 SLMP_INFO *current_dev = synclinkmp_device_list;
3768 while( current_dev->next_device )
3769 current_dev = current_dev->next_device;
3770 current_dev->next_device = info;
3771 }
3772
3773 if ( info->max_frame_size < 4096 )
3774 info->max_frame_size = 4096;
3775 else if ( info->max_frame_size > 65535 )
3776 info->max_frame_size = 65535;
3777
3778 printk( "SyncLink MultiPort %s: "
3779 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3780 info->device_name,
3781 info->phys_sca_base,
3782 info->phys_memory_base,
3783 info->phys_statctrl_base,
3784 info->phys_lcr_base,
3785 info->irq_level,
3786 info->max_frame_size );
3787
3788 #if SYNCLINK_GENERIC_HDLC
3789 hdlcdev_init(info);
3790 #endif
3791 }
3792
3793 /* Allocate and initialize a device instance structure
3794 *
3795 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3796 */
3797 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3798 {
3799 SLMP_INFO *info;
3800
3801 info = kmalloc(sizeof(SLMP_INFO),
3802 GFP_KERNEL);
3803
3804 if (!info) {
3805 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3806 __FILE__,__LINE__, adapter_num, port_num);
3807 } else {
3808 memset(info, 0, sizeof(SLMP_INFO));
3809 info->magic = MGSL_MAGIC;
3810 INIT_WORK(&info->task, bh_handler);
3811 info->max_frame_size = 4096;
3812 info->close_delay = 5*HZ/10;
3813 info->closing_wait = 30*HZ;
3814 init_waitqueue_head(&info->open_wait);
3815 init_waitqueue_head(&info->close_wait);
3816 init_waitqueue_head(&info->status_event_wait_q);
3817 init_waitqueue_head(&info->event_wait_q);
3818 spin_lock_init(&info->netlock);
3819 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3820 info->idle_mode = HDLC_TXIDLE_FLAGS;
3821 info->adapter_num = adapter_num;
3822 info->port_num = port_num;
3823
3824 /* Copy configuration info to device instance data */
3825 info->irq_level = pdev->irq;
3826 info->phys_lcr_base = pci_resource_start(pdev,0);
3827 info->phys_sca_base = pci_resource_start(pdev,2);
3828 info->phys_memory_base = pci_resource_start(pdev,3);
3829 info->phys_statctrl_base = pci_resource_start(pdev,4);
3830
3831 /* Because veremap only works on page boundaries we must map
3832 * a larger area than is actually implemented for the LCR
3833 * memory range. We map a full page starting at the page boundary.
3834 */
3835 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3836 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3837
3838 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3839 info->phys_sca_base &= ~(PAGE_SIZE-1);
3840
3841 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3842 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3843
3844 info->bus_type = MGSL_BUS_TYPE_PCI;
3845 info->irq_flags = IRQF_SHARED;
3846
3847 init_timer(&info->tx_timer);
3848 info->tx_timer.data = (unsigned long)info;
3849 info->tx_timer.function = tx_timeout;
3850
3851 init_timer(&info->status_timer);
3852 info->status_timer.data = (unsigned long)info;
3853 info->status_timer.function = status_timeout;
3854
3855 /* Store the PCI9050 misc control register value because a flaw
3856 * in the PCI9050 prevents LCR registers from being read if
3857 * BIOS assigns an LCR base address with bit 7 set.
3858 *
3859 * Only the misc control register is accessed for which only
3860 * write access is needed, so set an initial value and change
3861 * bits to the device instance data as we write the value
3862 * to the actual misc control register.
3863 */
3864 info->misc_ctrl_value = 0x087e4546;
3865
3866 /* initial port state is unknown - if startup errors
3867 * occur, init_error will be set to indicate the
3868 * problem. Once the port is fully initialized,
3869 * this value will be set to 0 to indicate the
3870 * port is available.
3871 */
3872 info->init_error = -1;
3873 }
3874
3875 return info;
3876 }
3877
3878 void device_init(int adapter_num, struct pci_dev *pdev)
3879 {
3880 SLMP_INFO *port_array[SCA_MAX_PORTS];
3881 int port;
3882
3883 /* allocate device instances for up to SCA_MAX_PORTS devices */
3884 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3885 port_array[port] = alloc_dev(adapter_num,port,pdev);
3886 if( port_array[port] == NULL ) {
3887 for ( --port; port >= 0; --port )
3888 kfree(port_array[port]);
3889 return;
3890 }
3891 }
3892
3893 /* give copy of port_array to all ports and add to device list */
3894 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3895 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3896 add_device( port_array[port] );
3897 spin_lock_init(&port_array[port]->lock);
3898 }
3899
3900 /* Allocate and claim adapter resources */
3901 if ( !claim_resources(port_array[0]) ) {
3902
3903 alloc_dma_bufs(port_array[0]);
3904
3905 /* copy resource information from first port to others */
3906 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3907 port_array[port]->lock = port_array[0]->lock;
3908 port_array[port]->irq_level = port_array[0]->irq_level;
3909 port_array[port]->memory_base = port_array[0]->memory_base;
3910 port_array[port]->sca_base = port_array[0]->sca_base;
3911 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3912 port_array[port]->lcr_base = port_array[0]->lcr_base;
3913 alloc_dma_bufs(port_array[port]);
3914 }
3915
3916 if ( request_irq(port_array[0]->irq_level,
3917 synclinkmp_interrupt,
3918 port_array[0]->irq_flags,
3919 port_array[0]->device_name,
3920 port_array[0]) < 0 ) {
3921 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3922 __FILE__,__LINE__,
3923 port_array[0]->device_name,
3924 port_array[0]->irq_level );
3925 }
3926 else {
3927 port_array[0]->irq_requested = 1;
3928 adapter_test(port_array[0]);
3929 }
3930 }
3931 }
3932
3933 static const struct tty_operations ops = {
3934 .open = open,
3935 .close = close,
3936 .write = write,
3937 .put_char = put_char,
3938 .flush_chars = flush_chars,
3939 .write_room = write_room,
3940 .chars_in_buffer = chars_in_buffer,
3941 .flush_buffer = flush_buffer,
3942 .ioctl = ioctl,
3943 .throttle = throttle,
3944 .unthrottle = unthrottle,
3945 .send_xchar = send_xchar,
3946 .break_ctl = set_break,
3947 .wait_until_sent = wait_until_sent,
3948 .read_proc = read_proc,
3949 .set_termios = set_termios,
3950 .stop = tx_hold,
3951 .start = tx_release,
3952 .hangup = hangup,
3953 .tiocmget = tiocmget,
3954 .tiocmset = tiocmset,
3955 };
3956
3957 static void synclinkmp_cleanup(void)
3958 {
3959 int rc;
3960 SLMP_INFO *info;
3961 SLMP_INFO *tmp;
3962
3963 printk("Unloading %s %s\n", driver_name, driver_version);
3964
3965 if (serial_driver) {
3966 if ((rc = tty_unregister_driver(serial_driver)))
3967 printk("%s(%d) failed to unregister tty driver err=%d\n",
3968 __FILE__,__LINE__,rc);
3969 put_tty_driver(serial_driver);
3970 }
3971
3972 /* reset devices */
3973 info = synclinkmp_device_list;
3974 while(info) {
3975 reset_port(info);
3976 info = info->next_device;
3977 }
3978
3979 /* release devices */
3980 info = synclinkmp_device_list;
3981 while(info) {
3982 #if SYNCLINK_GENERIC_HDLC
3983 hdlcdev_exit(info);
3984 #endif
3985 free_dma_bufs(info);
3986 free_tmp_rx_buf(info);
3987 if ( info->port_num == 0 ) {
3988 if (info->sca_base)
3989 write_reg(info, LPR, 1); /* set low power mode */
3990 release_resources(info);
3991 }
3992 tmp = info;
3993 info = info->next_device;
3994 kfree(tmp);
3995 }
3996
3997 pci_unregister_driver(&synclinkmp_pci_driver);
3998 }
3999
4000 /* Driver initialization entry point.
4001 */
4002
4003 static int __init synclinkmp_init(void)
4004 {
4005 int rc;
4006
4007 if (break_on_load) {
4008 synclinkmp_get_text_ptr();
4009 BREAKPOINT();
4010 }
4011
4012 printk("%s %s\n", driver_name, driver_version);
4013
4014 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4015 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4016 return rc;
4017 }
4018
4019 serial_driver = alloc_tty_driver(128);
4020 if (!serial_driver) {
4021 rc = -ENOMEM;
4022 goto error;
4023 }
4024
4025 /* Initialize the tty_driver structure */
4026
4027 serial_driver->owner = THIS_MODULE;
4028 serial_driver->driver_name = "synclinkmp";
4029 serial_driver->name = "ttySLM";
4030 serial_driver->major = ttymajor;
4031 serial_driver->minor_start = 64;
4032 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4033 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4034 serial_driver->init_termios = tty_std_termios;
4035 serial_driver->init_termios.c_cflag =
4036 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4037 serial_driver->init_termios.c_ispeed = 9600;
4038 serial_driver->init_termios.c_ospeed = 9600;
4039 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4040 tty_set_operations(serial_driver, &ops);
4041 if ((rc = tty_register_driver(serial_driver)) < 0) {
4042 printk("%s(%d):Couldn't register serial driver\n",
4043 __FILE__,__LINE__);
4044 put_tty_driver(serial_driver);
4045 serial_driver = NULL;
4046 goto error;
4047 }
4048
4049 printk("%s %s, tty major#%d\n",
4050 driver_name, driver_version,
4051 serial_driver->major);
4052
4053 return 0;
4054
4055 error:
4056 synclinkmp_cleanup();
4057 return rc;
4058 }
4059
4060 static void __exit synclinkmp_exit(void)
4061 {
4062 synclinkmp_cleanup();
4063 }
4064
4065 module_init(synclinkmp_init);
4066 module_exit(synclinkmp_exit);
4067
4068 /* Set the port for internal loopback mode.
4069 * The TxCLK and RxCLK signals are generated from the BRG and
4070 * the TxD is looped back to the RxD internally.
4071 */
4072 void enable_loopback(SLMP_INFO *info, int enable)
4073 {
4074 if (enable) {
4075 /* MD2 (Mode Register 2)
4076 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4077 */
4078 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4079
4080 /* degate external TxC clock source */
4081 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4082 write_control_reg(info);
4083
4084 /* RXS/TXS (Rx/Tx clock source)
4085 * 07 Reserved, must be 0
4086 * 06..04 Clock Source, 100=BRG
4087 * 03..00 Clock Divisor, 0000=1
4088 */
4089 write_reg(info, RXS, 0x40);
4090 write_reg(info, TXS, 0x40);
4091
4092 } else {
4093 /* MD2 (Mode Register 2)
4094 * 01..00 CNCT<1..0> Channel connection, 0=normal
4095 */
4096 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4097
4098 /* RXS/TXS (Rx/Tx clock source)
4099 * 07 Reserved, must be 0
4100 * 06..04 Clock Source, 000=RxC/TxC Pin
4101 * 03..00 Clock Divisor, 0000=1
4102 */
4103 write_reg(info, RXS, 0x00);
4104 write_reg(info, TXS, 0x00);
4105 }
4106
4107 /* set LinkSpeed if available, otherwise default to 2Mbps */
4108 if (info->params.clock_speed)
4109 set_rate(info, info->params.clock_speed);
4110 else
4111 set_rate(info, 3686400);
4112 }
4113
4114 /* Set the baud rate register to the desired speed
4115 *
4116 * data_rate data rate of clock in bits per second
4117 * A data rate of 0 disables the AUX clock.
4118 */
4119 void set_rate( SLMP_INFO *info, u32 data_rate )
4120 {
4121 u32 TMCValue;
4122 unsigned char BRValue;
4123 u32 Divisor=0;
4124
4125 /* fBRG = fCLK/(TMC * 2^BR)
4126 */
4127 if (data_rate != 0) {
4128 Divisor = 14745600/data_rate;
4129 if (!Divisor)
4130 Divisor = 1;
4131
4132 TMCValue = Divisor;
4133
4134 BRValue = 0;
4135 if (TMCValue != 1 && TMCValue != 2) {
4136 /* BRValue of 0 provides 50/50 duty cycle *only* when
4137 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4138 * 50/50 duty cycle.
4139 */
4140 BRValue = 1;
4141 TMCValue >>= 1;
4142 }
4143
4144 /* while TMCValue is too big for TMC register, divide
4145 * by 2 and increment BR exponent.
4146 */
4147 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4148 TMCValue >>= 1;
4149
4150 write_reg(info, TXS,
4151 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4152 write_reg(info, RXS,
4153 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4154 write_reg(info, TMC, (unsigned char)TMCValue);
4155 }
4156 else {
4157 write_reg(info, TXS,0);
4158 write_reg(info, RXS,0);
4159 write_reg(info, TMC, 0);
4160 }
4161 }
4162
4163 /* Disable receiver
4164 */
4165 void rx_stop(SLMP_INFO *info)
4166 {
4167 if (debug_level >= DEBUG_LEVEL_ISR)
4168 printk("%s(%d):%s rx_stop()\n",
4169 __FILE__,__LINE__, info->device_name );
4170
4171 write_reg(info, CMD, RXRESET);
4172
4173 info->ie0_value &= ~RXRDYE;
4174 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4175
4176 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4177 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4178 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4179
4180 info->rx_enabled = 0;
4181 info->rx_overflow = 0;
4182 }
4183
4184 /* enable the receiver
4185 */
4186 void rx_start(SLMP_INFO *info)
4187 {
4188 int i;
4189
4190 if (debug_level >= DEBUG_LEVEL_ISR)
4191 printk("%s(%d):%s rx_start()\n",
4192 __FILE__,__LINE__, info->device_name );
4193
4194 write_reg(info, CMD, RXRESET);
4195
4196 if ( info->params.mode == MGSL_MODE_HDLC ) {
4197 /* HDLC, disabe IRQ on rxdata */
4198 info->ie0_value &= ~RXRDYE;
4199 write_reg(info, IE0, info->ie0_value);
4200
4201 /* Reset all Rx DMA buffers and program rx dma */
4202 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4203 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4204
4205 for (i = 0; i < info->rx_buf_count; i++) {
4206 info->rx_buf_list[i].status = 0xff;
4207
4208 // throttle to 4 shared memory writes at a time to prevent
4209 // hogging local bus (keep latency time for DMA requests low).
4210 if (!(i % 4))
4211 read_status_reg(info);
4212 }
4213 info->current_rx_buf = 0;
4214
4215 /* set current/1st descriptor address */
4216 write_reg16(info, RXDMA + CDA,
4217 info->rx_buf_list_ex[0].phys_entry);
4218
4219 /* set new last rx descriptor address */
4220 write_reg16(info, RXDMA + EDA,
4221 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4222
4223 /* set buffer length (shared by all rx dma data buffers) */
4224 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4225
4226 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4227 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4228 } else {
4229 /* async, enable IRQ on rxdata */
4230 info->ie0_value |= RXRDYE;
4231 write_reg(info, IE0, info->ie0_value);
4232 }
4233
4234 write_reg(info, CMD, RXENABLE);
4235
4236 info->rx_overflow = FALSE;
4237 info->rx_enabled = 1;
4238 }
4239
4240 /* Enable the transmitter and send a transmit frame if
4241 * one is loaded in the DMA buffers.
4242 */
4243 void tx_start(SLMP_INFO *info)
4244 {
4245 if (debug_level >= DEBUG_LEVEL_ISR)
4246 printk("%s(%d):%s tx_start() tx_count=%d\n",
4247 __FILE__,__LINE__, info->device_name,info->tx_count );
4248
4249 if (!info->tx_enabled ) {
4250 write_reg(info, CMD, TXRESET);
4251 write_reg(info, CMD, TXENABLE);
4252 info->tx_enabled = TRUE;
4253 }
4254
4255 if ( info->tx_count ) {
4256
4257 /* If auto RTS enabled and RTS is inactive, then assert */
4258 /* RTS and set a flag indicating that the driver should */
4259 /* negate RTS when the transmission completes. */
4260
4261 info->drop_rts_on_tx_done = 0;
4262
4263 if (info->params.mode != MGSL_MODE_ASYNC) {
4264
4265 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4266 get_signals( info );
4267 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4268 info->serial_signals |= SerialSignal_RTS;
4269 set_signals( info );
4270 info->drop_rts_on_tx_done = 1;
4271 }
4272 }
4273
4274 write_reg16(info, TRC0,
4275 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4276
4277 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4278 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4279
4280 /* set TX CDA (current descriptor address) */
4281 write_reg16(info, TXDMA + CDA,
4282 info->tx_buf_list_ex[0].phys_entry);
4283
4284 /* set TX EDA (last descriptor address) */
4285 write_reg16(info, TXDMA + EDA,
4286 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4287
4288 /* enable underrun IRQ */
4289 info->ie1_value &= ~IDLE;
4290 info->ie1_value |= UDRN;
4291 write_reg(info, IE1, info->ie1_value);
4292 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4293
4294 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4295 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4296
4297 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
4298 add_timer(&info->tx_timer);
4299 }
4300 else {
4301 tx_load_fifo(info);
4302 /* async, enable IRQ on txdata */
4303 info->ie0_value |= TXRDYE;
4304 write_reg(info, IE0, info->ie0_value);
4305 }
4306
4307 info->tx_active = 1;
4308 }
4309 }
4310
4311 /* stop the transmitter and DMA
4312 */
4313 void tx_stop( SLMP_INFO *info )
4314 {
4315 if (debug_level >= DEBUG_LEVEL_ISR)
4316 printk("%s(%d):%s tx_stop()\n",
4317 __FILE__,__LINE__, info->device_name );
4318
4319 del_timer(&info->tx_timer);
4320
4321 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4322 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4323
4324 write_reg(info, CMD, TXRESET);
4325
4326 info->ie1_value &= ~(UDRN + IDLE);
4327 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4328 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4329
4330 info->ie0_value &= ~TXRDYE;
4331 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4332
4333 info->tx_enabled = 0;
4334 info->tx_active = 0;
4335 }
4336
4337 /* Fill the transmit FIFO until the FIFO is full or
4338 * there is no more data to load.
4339 */
4340 void tx_load_fifo(SLMP_INFO *info)
4341 {
4342 u8 TwoBytes[2];
4343
4344 /* do nothing is now tx data available and no XON/XOFF pending */
4345
4346 if ( !info->tx_count && !info->x_char )
4347 return;
4348
4349 /* load the Transmit FIFO until FIFOs full or all data sent */
4350
4351 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4352
4353 /* there is more space in the transmit FIFO and */
4354 /* there is more data in transmit buffer */
4355
4356 if ( (info->tx_count > 1) && !info->x_char ) {
4357 /* write 16-bits */
4358 TwoBytes[0] = info->tx_buf[info->tx_get++];
4359 if (info->tx_get >= info->max_frame_size)
4360 info->tx_get -= info->max_frame_size;
4361 TwoBytes[1] = info->tx_buf[info->tx_get++];
4362 if (info->tx_get >= info->max_frame_size)
4363 info->tx_get -= info->max_frame_size;
4364
4365 write_reg16(info, TRB, *((u16 *)TwoBytes));
4366
4367 info->tx_count -= 2;
4368 info->icount.tx += 2;
4369 } else {
4370 /* only 1 byte left to transmit or 1 FIFO slot left */
4371
4372 if (info->x_char) {
4373 /* transmit pending high priority char */
4374 write_reg(info, TRB, info->x_char);
4375 info->x_char = 0;
4376 } else {
4377 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4378 if (info->tx_get >= info->max_frame_size)
4379 info->tx_get -= info->max_frame_size;
4380 info->tx_count--;
4381 }
4382 info->icount.tx++;
4383 }
4384 }
4385 }
4386
4387 /* Reset a port to a known state
4388 */
4389 void reset_port(SLMP_INFO *info)
4390 {
4391 if (info->sca_base) {
4392
4393 tx_stop(info);
4394 rx_stop(info);
4395
4396 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4397 set_signals(info);
4398
4399 /* disable all port interrupts */
4400 info->ie0_value = 0;
4401 info->ie1_value = 0;
4402 info->ie2_value = 0;
4403 write_reg(info, IE0, info->ie0_value);
4404 write_reg(info, IE1, info->ie1_value);
4405 write_reg(info, IE2, info->ie2_value);
4406
4407 write_reg(info, CMD, CHRESET);
4408 }
4409 }
4410
4411 /* Reset all the ports to a known state.
4412 */
4413 void reset_adapter(SLMP_INFO *info)
4414 {
4415 int i;
4416
4417 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4418 if (info->port_array[i])
4419 reset_port(info->port_array[i]);
4420 }
4421 }
4422
4423 /* Program port for asynchronous communications.
4424 */
4425 void async_mode(SLMP_INFO *info)
4426 {
4427
4428 unsigned char RegValue;
4429
4430 tx_stop(info);
4431 rx_stop(info);
4432
4433 /* MD0, Mode Register 0
4434 *
4435 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4436 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4437 * 03 Reserved, must be 0
4438 * 02 CRCCC, CRC Calculation, 0=disabled
4439 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4440 *
4441 * 0000 0000
4442 */
4443 RegValue = 0x00;
4444 if (info->params.stop_bits != 1)
4445 RegValue |= BIT1;
4446 write_reg(info, MD0, RegValue);
4447
4448 /* MD1, Mode Register 1
4449 *
4450 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4451 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4452 * 03..02 RXCHR<1..0>, rx char size
4453 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4454 *
4455 * 0100 0000
4456 */
4457 RegValue = 0x40;
4458 switch (info->params.data_bits) {
4459 case 7: RegValue |= BIT4 + BIT2; break;
4460 case 6: RegValue |= BIT5 + BIT3; break;
4461 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4462 }
4463 if (info->params.parity != ASYNC_PARITY_NONE) {
4464 RegValue |= BIT1;
4465 if (info->params.parity == ASYNC_PARITY_ODD)
4466 RegValue |= BIT0;
4467 }
4468 write_reg(info, MD1, RegValue);
4469
4470 /* MD2, Mode Register 2
4471 *
4472 * 07..02 Reserved, must be 0
4473 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4474 *
4475 * 0000 0000
4476 */
4477 RegValue = 0x00;
4478 if (info->params.loopback)
4479 RegValue |= (BIT1 + BIT0);
4480 write_reg(info, MD2, RegValue);
4481
4482 /* RXS, Receive clock source
4483 *
4484 * 07 Reserved, must be 0
4485 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4486 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4487 */
4488 RegValue=BIT6;
4489 write_reg(info, RXS, RegValue);
4490
4491 /* TXS, Transmit clock source
4492 *
4493 * 07 Reserved, must be 0
4494 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4495 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4496 */
4497 RegValue=BIT6;
4498 write_reg(info, TXS, RegValue);
4499
4500 /* Control Register
4501 *
4502 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4503 */
4504 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4505 write_control_reg(info);
4506
4507 tx_set_idle(info);
4508
4509 /* RRC Receive Ready Control 0
4510 *
4511 * 07..05 Reserved, must be 0
4512 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4513 */
4514 write_reg(info, RRC, 0x00);
4515
4516 /* TRC0 Transmit Ready Control 0
4517 *
4518 * 07..05 Reserved, must be 0
4519 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4520 */
4521 write_reg(info, TRC0, 0x10);
4522
4523 /* TRC1 Transmit Ready Control 1
4524 *
4525 * 07..05 Reserved, must be 0
4526 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4527 */
4528 write_reg(info, TRC1, 0x1e);
4529
4530 /* CTL, MSCI control register
4531 *
4532 * 07..06 Reserved, set to 0
4533 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4534 * 04 IDLC, idle control, 0=mark 1=idle register
4535 * 03 BRK, break, 0=off 1 =on (async)
4536 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4537 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4538 * 00 RTS, RTS output control, 0=active 1=inactive
4539 *
4540 * 0001 0001
4541 */
4542 RegValue = 0x10;
4543 if (!(info->serial_signals & SerialSignal_RTS))
4544 RegValue |= 0x01;
4545 write_reg(info, CTL, RegValue);
4546
4547 /* enable status interrupts */
4548 info->ie0_value |= TXINTE + RXINTE;
4549 write_reg(info, IE0, info->ie0_value);
4550
4551 /* enable break detect interrupt */
4552 info->ie1_value = BRKD;
4553 write_reg(info, IE1, info->ie1_value);
4554
4555 /* enable rx overrun interrupt */
4556 info->ie2_value = OVRN;
4557 write_reg(info, IE2, info->ie2_value);
4558
4559 set_rate( info, info->params.data_rate * 16 );
4560 }
4561
4562 /* Program the SCA for HDLC communications.
4563 */
4564 void hdlc_mode(SLMP_INFO *info)
4565 {
4566 unsigned char RegValue;
4567 u32 DpllDivisor;
4568
4569 // Can't use DPLL because SCA outputs recovered clock on RxC when
4570 // DPLL mode selected. This causes output contention with RxC receiver.
4571 // Use of DPLL would require external hardware to disable RxC receiver
4572 // when DPLL mode selected.
4573 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4574
4575 /* disable DMA interrupts */
4576 write_reg(info, TXDMA + DIR, 0);
4577 write_reg(info, RXDMA + DIR, 0);
4578
4579 /* MD0, Mode Register 0
4580 *
4581 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4582 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4583 * 03 Reserved, must be 0
4584 * 02 CRCCC, CRC Calculation, 1=enabled
4585 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4586 * 00 CRC0, CRC initial value, 1 = all 1s
4587 *
4588 * 1000 0001
4589 */
4590 RegValue = 0x81;
4591 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4592 RegValue |= BIT4;
4593 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4594 RegValue |= BIT4;
4595 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4596 RegValue |= BIT2 + BIT1;
4597 write_reg(info, MD0, RegValue);
4598
4599 /* MD1, Mode Register 1
4600 *
4601 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4602 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4603 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4604 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4605 *
4606 * 0000 0000
4607 */
4608 RegValue = 0x00;
4609 write_reg(info, MD1, RegValue);
4610
4611 /* MD2, Mode Register 2
4612 *
4613 * 07 NRZFM, 0=NRZ, 1=FM
4614 * 06..05 CODE<1..0> Encoding, 00=NRZ
4615 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4616 * 02 Reserved, must be 0
4617 * 01..00 CNCT<1..0> Channel connection, 0=normal
4618 *
4619 * 0000 0000
4620 */
4621 RegValue = 0x00;
4622 switch(info->params.encoding) {
4623 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4624 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4625 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4626 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4627 #if 0
4628 case HDLC_ENCODING_NRZB: /* not supported */
4629 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4630 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4631 #endif
4632 }
4633 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4634 DpllDivisor = 16;
4635 RegValue |= BIT3;
4636 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4637 DpllDivisor = 8;
4638 } else {
4639 DpllDivisor = 32;
4640 RegValue |= BIT4;
4641 }
4642 write_reg(info, MD2, RegValue);
4643
4644
4645 /* RXS, Receive clock source
4646 *
4647 * 07 Reserved, must be 0
4648 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4649 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4650 */
4651 RegValue=0;
4652 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4653 RegValue |= BIT6;
4654 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4655 RegValue |= BIT6 + BIT5;
4656 write_reg(info, RXS, RegValue);
4657
4658 /* TXS, Transmit clock source
4659 *
4660 * 07 Reserved, must be 0
4661 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4662 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4663 */
4664 RegValue=0;
4665 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4666 RegValue |= BIT6;
4667 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4668 RegValue |= BIT6 + BIT5;
4669 write_reg(info, TXS, RegValue);
4670
4671 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4672 set_rate(info, info->params.clock_speed * DpllDivisor);
4673 else
4674 set_rate(info, info->params.clock_speed);
4675
4676 /* GPDATA (General Purpose I/O Data Register)
4677 *
4678 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4679 */
4680 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4681 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4682 else
4683 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4684 write_control_reg(info);
4685
4686 /* RRC Receive Ready Control 0
4687 *
4688 * 07..05 Reserved, must be 0
4689 * 04..00 RRC<4..0> Rx FIFO trigger active
4690 */
4691 write_reg(info, RRC, rx_active_fifo_level);
4692
4693 /* TRC0 Transmit Ready Control 0
4694 *
4695 * 07..05 Reserved, must be 0
4696 * 04..00 TRC<4..0> Tx FIFO trigger active
4697 */
4698 write_reg(info, TRC0, tx_active_fifo_level);
4699
4700 /* TRC1 Transmit Ready Control 1
4701 *
4702 * 07..05 Reserved, must be 0
4703 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4704 */
4705 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4706
4707 /* DMR, DMA Mode Register
4708 *
4709 * 07..05 Reserved, must be 0
4710 * 04 TMOD, Transfer Mode: 1=chained-block
4711 * 03 Reserved, must be 0
4712 * 02 NF, Number of Frames: 1=multi-frame
4713 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4714 * 00 Reserved, must be 0
4715 *
4716 * 0001 0100
4717 */
4718 write_reg(info, TXDMA + DMR, 0x14);
4719 write_reg(info, RXDMA + DMR, 0x14);
4720
4721 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4722 write_reg(info, RXDMA + CPB,
4723 (unsigned char)(info->buffer_list_phys >> 16));
4724
4725 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4726 write_reg(info, TXDMA + CPB,
4727 (unsigned char)(info->buffer_list_phys >> 16));
4728
4729 /* enable status interrupts. other code enables/disables
4730 * the individual sources for these two interrupt classes.
4731 */
4732 info->ie0_value |= TXINTE + RXINTE;
4733 write_reg(info, IE0, info->ie0_value);
4734
4735 /* CTL, MSCI control register
4736 *
4737 * 07..06 Reserved, set to 0
4738 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4739 * 04 IDLC, idle control, 0=mark 1=idle register
4740 * 03 BRK, break, 0=off 1 =on (async)
4741 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4742 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4743 * 00 RTS, RTS output control, 0=active 1=inactive
4744 *
4745 * 0001 0001
4746 */
4747 RegValue = 0x10;
4748 if (!(info->serial_signals & SerialSignal_RTS))
4749 RegValue |= 0x01;
4750 write_reg(info, CTL, RegValue);
4751
4752 /* preamble not supported ! */
4753
4754 tx_set_idle(info);
4755 tx_stop(info);
4756 rx_stop(info);
4757
4758 set_rate(info, info->params.clock_speed);
4759
4760 if (info->params.loopback)
4761 enable_loopback(info,1);
4762 }
4763
4764 /* Set the transmit HDLC idle mode
4765 */
4766 void tx_set_idle(SLMP_INFO *info)
4767 {
4768 unsigned char RegValue = 0xff;
4769
4770 /* Map API idle mode to SCA register bits */
4771 switch(info->idle_mode) {
4772 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4773 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4774 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4775 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4776 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4777 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4778 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4779 }
4780
4781 write_reg(info, IDL, RegValue);
4782 }
4783
4784 /* Query the adapter for the state of the V24 status (input) signals.
4785 */
4786 void get_signals(SLMP_INFO *info)
4787 {
4788 u16 status = read_reg(info, SR3);
4789 u16 gpstatus = read_status_reg(info);
4790 u16 testbit;
4791
4792 /* clear all serial signals except DTR and RTS */
4793 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4794
4795 /* set serial signal bits to reflect MISR */
4796
4797 if (!(status & BIT3))
4798 info->serial_signals |= SerialSignal_CTS;
4799
4800 if ( !(status & BIT2))
4801 info->serial_signals |= SerialSignal_DCD;
4802
4803 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4804 if (!(gpstatus & testbit))
4805 info->serial_signals |= SerialSignal_RI;
4806
4807 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4808 if (!(gpstatus & testbit))
4809 info->serial_signals |= SerialSignal_DSR;
4810 }
4811
4812 /* Set the state of DTR and RTS based on contents of
4813 * serial_signals member of device context.
4814 */
4815 void set_signals(SLMP_INFO *info)
4816 {
4817 unsigned char RegValue;
4818 u16 EnableBit;
4819
4820 RegValue = read_reg(info, CTL);
4821 if (info->serial_signals & SerialSignal_RTS)
4822 RegValue &= ~BIT0;
4823 else
4824 RegValue |= BIT0;
4825 write_reg(info, CTL, RegValue);
4826
4827 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4828 EnableBit = BIT1 << (info->port_num*2);
4829 if (info->serial_signals & SerialSignal_DTR)
4830 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4831 else
4832 info->port_array[0]->ctrlreg_value |= EnableBit;
4833 write_control_reg(info);
4834 }
4835
4836 /*******************/
4837 /* DMA Buffer Code */
4838 /*******************/
4839
4840 /* Set the count for all receive buffers to SCABUFSIZE
4841 * and set the current buffer to the first buffer. This effectively
4842 * makes all buffers free and discards any data in buffers.
4843 */
4844 void rx_reset_buffers(SLMP_INFO *info)
4845 {
4846 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4847 }
4848
4849 /* Free the buffers used by a received frame
4850 *
4851 * info pointer to device instance data
4852 * first index of 1st receive buffer of frame
4853 * last index of last receive buffer of frame
4854 */
4855 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4856 {
4857 int done = 0;
4858
4859 while(!done) {
4860 /* reset current buffer for reuse */
4861 info->rx_buf_list[first].status = 0xff;
4862
4863 if (first == last) {
4864 done = 1;
4865 /* set new last rx descriptor address */
4866 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4867 }
4868
4869 first++;
4870 if (first == info->rx_buf_count)
4871 first = 0;
4872 }
4873
4874 /* set current buffer to next buffer after last buffer of frame */
4875 info->current_rx_buf = first;
4876 }
4877
4878 /* Return a received frame from the receive DMA buffers.
4879 * Only frames received without errors are returned.
4880 *
4881 * Return Value: 1 if frame returned, otherwise 0
4882 */
4883 int rx_get_frame(SLMP_INFO *info)
4884 {
4885 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4886 unsigned short status;
4887 unsigned int framesize = 0;
4888 int ReturnCode = 0;
4889 unsigned long flags;
4890 struct tty_struct *tty = info->tty;
4891 unsigned char addr_field = 0xff;
4892 SCADESC *desc;
4893 SCADESC_EX *desc_ex;
4894
4895 CheckAgain:
4896 /* assume no frame returned, set zero length */
4897 framesize = 0;
4898 addr_field = 0xff;
4899
4900 /*
4901 * current_rx_buf points to the 1st buffer of the next available
4902 * receive frame. To find the last buffer of the frame look for
4903 * a non-zero status field in the buffer entries. (The status
4904 * field is set by the 16C32 after completing a receive frame.
4905 */
4906 StartIndex = EndIndex = info->current_rx_buf;
4907
4908 for ( ;; ) {
4909 desc = &info->rx_buf_list[EndIndex];
4910 desc_ex = &info->rx_buf_list_ex[EndIndex];
4911
4912 if (desc->status == 0xff)
4913 goto Cleanup; /* current desc still in use, no frames available */
4914
4915 if (framesize == 0 && info->params.addr_filter != 0xff)
4916 addr_field = desc_ex->virt_addr[0];
4917
4918 framesize += desc->length;
4919
4920 /* Status != 0 means last buffer of frame */
4921 if (desc->status)
4922 break;
4923
4924 EndIndex++;
4925 if (EndIndex == info->rx_buf_count)
4926 EndIndex = 0;
4927
4928 if (EndIndex == info->current_rx_buf) {
4929 /* all buffers have been 'used' but none mark */
4930 /* the end of a frame. Reset buffers and receiver. */
4931 if ( info->rx_enabled ){
4932 spin_lock_irqsave(&info->lock,flags);
4933 rx_start(info);
4934 spin_unlock_irqrestore(&info->lock,flags);
4935 }
4936 goto Cleanup;
4937 }
4938
4939 }
4940
4941 /* check status of receive frame */
4942
4943 /* frame status is byte stored after frame data
4944 *
4945 * 7 EOM (end of msg), 1 = last buffer of frame
4946 * 6 Short Frame, 1 = short frame
4947 * 5 Abort, 1 = frame aborted
4948 * 4 Residue, 1 = last byte is partial
4949 * 3 Overrun, 1 = overrun occurred during frame reception
4950 * 2 CRC, 1 = CRC error detected
4951 *
4952 */
4953 status = desc->status;
4954
4955 /* ignore CRC bit if not using CRC (bit is undefined) */
4956 /* Note:CRC is not save to data buffer */
4957 if (info->params.crc_type == HDLC_CRC_NONE)
4958 status &= ~BIT2;
4959
4960 if (framesize == 0 ||
4961 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4962 /* discard 0 byte frames, this seems to occur sometime
4963 * when remote is idling flags.
4964 */
4965 rx_free_frame_buffers(info, StartIndex, EndIndex);
4966 goto CheckAgain;
4967 }
4968
4969 if (framesize < 2)
4970 status |= BIT6;
4971
4972 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4973 /* received frame has errors,
4974 * update counts and mark frame size as 0
4975 */
4976 if (status & BIT6)
4977 info->icount.rxshort++;
4978 else if (status & BIT5)
4979 info->icount.rxabort++;
4980 else if (status & BIT3)
4981 info->icount.rxover++;
4982 else
4983 info->icount.rxcrc++;
4984
4985 framesize = 0;
4986 #if SYNCLINK_GENERIC_HDLC
4987 {
4988 struct net_device_stats *stats = hdlc_stats(info->netdev);
4989 stats->rx_errors++;
4990 stats->rx_frame_errors++;
4991 }
4992 #endif
4993 }
4994
4995 if ( debug_level >= DEBUG_LEVEL_BH )
4996 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4997 __FILE__,__LINE__,info->device_name,status,framesize);
4998
4999 if ( debug_level >= DEBUG_LEVEL_DATA )
5000 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
5001 min_t(int, framesize,SCABUFSIZE),0);
5002
5003 if (framesize) {
5004 if (framesize > info->max_frame_size)
5005 info->icount.rxlong++;
5006 else {
5007 /* copy dma buffer(s) to contiguous intermediate buffer */
5008 int copy_count = framesize;
5009 int index = StartIndex;
5010 unsigned char *ptmp = info->tmp_rx_buf;
5011 info->tmp_rx_buf_count = framesize;
5012
5013 info->icount.rxok++;
5014
5015 while(copy_count) {
5016 int partial_count = min(copy_count,SCABUFSIZE);
5017 memcpy( ptmp,
5018 info->rx_buf_list_ex[index].virt_addr,
5019 partial_count );
5020 ptmp += partial_count;
5021 copy_count -= partial_count;
5022
5023 if ( ++index == info->rx_buf_count )
5024 index = 0;
5025 }
5026
5027 #if SYNCLINK_GENERIC_HDLC
5028 if (info->netcount)
5029 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5030 else
5031 #endif
5032 ldisc_receive_buf(tty,info->tmp_rx_buf,
5033 info->flag_buf, framesize);
5034 }
5035 }
5036 /* Free the buffers used by this frame. */
5037 rx_free_frame_buffers( info, StartIndex, EndIndex );
5038
5039 ReturnCode = 1;
5040
5041 Cleanup:
5042 if ( info->rx_enabled && info->rx_overflow ) {
5043 /* Receiver is enabled, but needs to restarted due to
5044 * rx buffer overflow. If buffers are empty, restart receiver.
5045 */
5046 if (info->rx_buf_list[EndIndex].status == 0xff) {
5047 spin_lock_irqsave(&info->lock,flags);
5048 rx_start(info);
5049 spin_unlock_irqrestore(&info->lock,flags);
5050 }
5051 }
5052
5053 return ReturnCode;
5054 }
5055
5056 /* load the transmit DMA buffer with data
5057 */
5058 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5059 {
5060 unsigned short copy_count;
5061 unsigned int i = 0;
5062 SCADESC *desc;
5063 SCADESC_EX *desc_ex;
5064
5065 if ( debug_level >= DEBUG_LEVEL_DATA )
5066 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5067
5068 /* Copy source buffer to one or more DMA buffers, starting with
5069 * the first transmit dma buffer.
5070 */
5071 for(i=0;;)
5072 {
5073 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5074
5075 desc = &info->tx_buf_list[i];
5076 desc_ex = &info->tx_buf_list_ex[i];
5077
5078 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5079
5080 desc->length = copy_count;
5081 desc->status = 0;
5082
5083 buf += copy_count;
5084 count -= copy_count;
5085
5086 if (!count)
5087 break;
5088
5089 i++;
5090 if (i >= info->tx_buf_count)
5091 i = 0;
5092 }
5093
5094 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5095 info->last_tx_buf = ++i;
5096 }
5097
5098 int register_test(SLMP_INFO *info)
5099 {
5100 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5101 static unsigned int count = ARRAY_SIZE(testval);
5102 unsigned int i;
5103 int rc = TRUE;
5104 unsigned long flags;
5105
5106 spin_lock_irqsave(&info->lock,flags);
5107 reset_port(info);
5108
5109 /* assume failure */
5110 info->init_error = DiagStatus_AddressFailure;
5111
5112 /* Write bit patterns to various registers but do it out of */
5113 /* sync, then read back and verify values. */
5114
5115 for (i = 0 ; i < count ; i++) {
5116 write_reg(info, TMC, testval[i]);
5117 write_reg(info, IDL, testval[(i+1)%count]);
5118 write_reg(info, SA0, testval[(i+2)%count]);
5119 write_reg(info, SA1, testval[(i+3)%count]);
5120
5121 if ( (read_reg(info, TMC) != testval[i]) ||
5122 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5123 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5124 (read_reg(info, SA1) != testval[(i+3)%count]) )
5125 {
5126 rc = FALSE;
5127 break;
5128 }
5129 }
5130
5131 reset_port(info);
5132 spin_unlock_irqrestore(&info->lock,flags);
5133
5134 return rc;
5135 }
5136
5137 int irq_test(SLMP_INFO *info)
5138 {
5139 unsigned long timeout;
5140 unsigned long flags;
5141
5142 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5143
5144 spin_lock_irqsave(&info->lock,flags);
5145 reset_port(info);
5146
5147 /* assume failure */
5148 info->init_error = DiagStatus_IrqFailure;
5149 info->irq_occurred = FALSE;
5150
5151 /* setup timer0 on SCA0 to interrupt */
5152
5153 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5154 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5155
5156 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5157 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5158
5159
5160 /* TMCS, Timer Control/Status Register
5161 *
5162 * 07 CMF, Compare match flag (read only) 1=match
5163 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5164 * 05 Reserved, must be 0
5165 * 04 TME, Timer Enable
5166 * 03..00 Reserved, must be 0
5167 *
5168 * 0101 0000
5169 */
5170 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5171
5172 spin_unlock_irqrestore(&info->lock,flags);
5173
5174 timeout=100;
5175 while( timeout-- && !info->irq_occurred ) {
5176 msleep_interruptible(10);
5177 }
5178
5179 spin_lock_irqsave(&info->lock,flags);
5180 reset_port(info);
5181 spin_unlock_irqrestore(&info->lock,flags);
5182
5183 return info->irq_occurred;
5184 }
5185
5186 /* initialize individual SCA device (2 ports)
5187 */
5188 static int sca_init(SLMP_INFO *info)
5189 {
5190 /* set wait controller to single mem partition (low), no wait states */
5191 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5192 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5193 write_reg(info, WCRL, 0); /* wait controller low range */
5194 write_reg(info, WCRM, 0); /* wait controller mid range */
5195 write_reg(info, WCRH, 0); /* wait controller high range */
5196
5197 /* DPCR, DMA Priority Control
5198 *
5199 * 07..05 Not used, must be 0
5200 * 04 BRC, bus release condition: 0=all transfers complete
5201 * 03 CCC, channel change condition: 0=every cycle
5202 * 02..00 PR<2..0>, priority 100=round robin
5203 *
5204 * 00000100 = 0x04
5205 */
5206 write_reg(info, DPCR, dma_priority);
5207
5208 /* DMA Master Enable, BIT7: 1=enable all channels */
5209 write_reg(info, DMER, 0x80);
5210
5211 /* enable all interrupt classes */
5212 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5213 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5214 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5215
5216 /* ITCR, interrupt control register
5217 * 07 IPC, interrupt priority, 0=MSCI->DMA
5218 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5219 * 04 VOS, Vector Output, 0=unmodified vector
5220 * 03..00 Reserved, must be 0
5221 */
5222 write_reg(info, ITCR, 0);
5223
5224 return TRUE;
5225 }
5226
5227 /* initialize adapter hardware
5228 */
5229 int init_adapter(SLMP_INFO *info)
5230 {
5231 int i;
5232
5233 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5234 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5235 u32 readval;
5236
5237 info->misc_ctrl_value |= BIT30;
5238 *MiscCtrl = info->misc_ctrl_value;
5239
5240 /*
5241 * Force at least 170ns delay before clearing
5242 * reset bit. Each read from LCR takes at least
5243 * 30ns so 10 times for 300ns to be safe.
5244 */
5245 for(i=0;i<10;i++)
5246 readval = *MiscCtrl;
5247
5248 info->misc_ctrl_value &= ~BIT30;
5249 *MiscCtrl = info->misc_ctrl_value;
5250
5251 /* init control reg (all DTRs off, all clksel=input) */
5252 info->ctrlreg_value = 0xaa;
5253 write_control_reg(info);
5254
5255 {
5256 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5257 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5258
5259 switch(read_ahead_count)
5260 {
5261 case 16:
5262 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5263 break;
5264 case 8:
5265 lcr1_brdr_value |= BIT5 + BIT4;
5266 break;
5267 case 4:
5268 lcr1_brdr_value |= BIT5 + BIT3;
5269 break;
5270 case 0:
5271 lcr1_brdr_value |= BIT5;
5272 break;
5273 }
5274
5275 *LCR1BRDR = lcr1_brdr_value;
5276 *MiscCtrl = misc_ctrl_value;
5277 }
5278
5279 sca_init(info->port_array[0]);
5280 sca_init(info->port_array[2]);
5281
5282 return TRUE;
5283 }
5284
5285 /* Loopback an HDLC frame to test the hardware
5286 * interrupt and DMA functions.
5287 */
5288 int loopback_test(SLMP_INFO *info)
5289 {
5290 #define TESTFRAMESIZE 20
5291
5292 unsigned long timeout;
5293 u16 count = TESTFRAMESIZE;
5294 unsigned char buf[TESTFRAMESIZE];
5295 int rc = FALSE;
5296 unsigned long flags;
5297
5298 struct tty_struct *oldtty = info->tty;
5299 u32 speed = info->params.clock_speed;
5300
5301 info->params.clock_speed = 3686400;
5302 info->tty = NULL;
5303
5304 /* assume failure */
5305 info->init_error = DiagStatus_DmaFailure;
5306
5307 /* build and send transmit frame */
5308 for (count = 0; count < TESTFRAMESIZE;++count)
5309 buf[count] = (unsigned char)count;
5310
5311 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5312
5313 /* program hardware for HDLC and enabled receiver */
5314 spin_lock_irqsave(&info->lock,flags);
5315 hdlc_mode(info);
5316 enable_loopback(info,1);
5317 rx_start(info);
5318 info->tx_count = count;
5319 tx_load_dma_buffer(info,buf,count);
5320 tx_start(info);
5321 spin_unlock_irqrestore(&info->lock,flags);
5322
5323 /* wait for receive complete */
5324 /* Set a timeout for waiting for interrupt. */
5325 for ( timeout = 100; timeout; --timeout ) {
5326 msleep_interruptible(10);
5327
5328 if (rx_get_frame(info)) {
5329 rc = TRUE;
5330 break;
5331 }
5332 }
5333
5334 /* verify received frame length and contents */
5335 if (rc == TRUE &&
5336 ( info->tmp_rx_buf_count != count ||
5337 memcmp(buf, info->tmp_rx_buf,count))) {
5338 rc = FALSE;
5339 }
5340
5341 spin_lock_irqsave(&info->lock,flags);
5342 reset_adapter(info);
5343 spin_unlock_irqrestore(&info->lock,flags);
5344
5345 info->params.clock_speed = speed;
5346 info->tty = oldtty;
5347
5348 return rc;
5349 }
5350
5351 /* Perform diagnostics on hardware
5352 */
5353 int adapter_test( SLMP_INFO *info )
5354 {
5355 unsigned long flags;
5356 if ( debug_level >= DEBUG_LEVEL_INFO )
5357 printk( "%s(%d):Testing device %s\n",
5358 __FILE__,__LINE__,info->device_name );
5359
5360 spin_lock_irqsave(&info->lock,flags);
5361 init_adapter(info);
5362 spin_unlock_irqrestore(&info->lock,flags);
5363
5364 info->port_array[0]->port_count = 0;
5365
5366 if ( register_test(info->port_array[0]) &&
5367 register_test(info->port_array[1])) {
5368
5369 info->port_array[0]->port_count = 2;
5370
5371 if ( register_test(info->port_array[2]) &&
5372 register_test(info->port_array[3]) )
5373 info->port_array[0]->port_count += 2;
5374 }
5375 else {
5376 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5377 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5378 return -ENODEV;
5379 }
5380
5381 if ( !irq_test(info->port_array[0]) ||
5382 !irq_test(info->port_array[1]) ||
5383 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5384 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5385 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5386 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5387 return -ENODEV;
5388 }
5389
5390 if (!loopback_test(info->port_array[0]) ||
5391 !loopback_test(info->port_array[1]) ||
5392 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5393 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5394 printk( "%s(%d):DMA test failure for device %s\n",
5395 __FILE__,__LINE__,info->device_name);
5396 return -ENODEV;
5397 }
5398
5399 if ( debug_level >= DEBUG_LEVEL_INFO )
5400 printk( "%s(%d):device %s passed diagnostics\n",
5401 __FILE__,__LINE__,info->device_name );
5402
5403 info->port_array[0]->init_error = 0;
5404 info->port_array[1]->init_error = 0;
5405 if ( info->port_count > 2 ) {
5406 info->port_array[2]->init_error = 0;
5407 info->port_array[3]->init_error = 0;
5408 }
5409
5410 return 0;
5411 }
5412
5413 /* Test the shared memory on a PCI adapter.
5414 */
5415 int memory_test(SLMP_INFO *info)
5416 {
5417 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5418 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5419 unsigned long count = ARRAY_SIZE(testval);
5420 unsigned long i;
5421 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5422 unsigned long * addr = (unsigned long *)info->memory_base;
5423
5424 /* Test data lines with test pattern at one location. */
5425
5426 for ( i = 0 ; i < count ; i++ ) {
5427 *addr = testval[i];
5428 if ( *addr != testval[i] )
5429 return FALSE;
5430 }
5431
5432 /* Test address lines with incrementing pattern over */
5433 /* entire address range. */
5434
5435 for ( i = 0 ; i < limit ; i++ ) {
5436 *addr = i * 4;
5437 addr++;
5438 }
5439
5440 addr = (unsigned long *)info->memory_base;
5441
5442 for ( i = 0 ; i < limit ; i++ ) {
5443 if ( *addr != i * 4 )
5444 return FALSE;
5445 addr++;
5446 }
5447
5448 memset( info->memory_base, 0, SCA_MEM_SIZE );
5449 return TRUE;
5450 }
5451
5452 /* Load data into PCI adapter shared memory.
5453 *
5454 * The PCI9050 releases control of the local bus
5455 * after completing the current read or write operation.
5456 *
5457 * While the PCI9050 write FIFO not empty, the
5458 * PCI9050 treats all of the writes as a single transaction
5459 * and does not release the bus. This causes DMA latency problems
5460 * at high speeds when copying large data blocks to the shared memory.
5461 *
5462 * This function breaks a write into multiple transations by
5463 * interleaving a read which flushes the write FIFO and 'completes'
5464 * the write transation. This allows any pending DMA request to gain control
5465 * of the local bus in a timely fasion.
5466 */
5467 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5468 {
5469 /* A load interval of 16 allows for 4 32-bit writes at */
5470 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5471
5472 unsigned short interval = count / sca_pci_load_interval;
5473 unsigned short i;
5474
5475 for ( i = 0 ; i < interval ; i++ )
5476 {
5477 memcpy(dest, src, sca_pci_load_interval);
5478 read_status_reg(info);
5479 dest += sca_pci_load_interval;
5480 src += sca_pci_load_interval;
5481 }
5482
5483 memcpy(dest, src, count % sca_pci_load_interval);
5484 }
5485
5486 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5487 {
5488 int i;
5489 int linecount;
5490 if (xmit)
5491 printk("%s tx data:\n",info->device_name);
5492 else
5493 printk("%s rx data:\n",info->device_name);
5494
5495 while(count) {
5496 if (count > 16)
5497 linecount = 16;
5498 else
5499 linecount = count;
5500
5501 for(i=0;i<linecount;i++)
5502 printk("%02X ",(unsigned char)data[i]);
5503 for(;i<17;i++)
5504 printk(" ");
5505 for(i=0;i<linecount;i++) {
5506 if (data[i]>=040 && data[i]<=0176)
5507 printk("%c",data[i]);
5508 else
5509 printk(".");
5510 }
5511 printk("\n");
5512
5513 data += linecount;
5514 count -= linecount;
5515 }
5516 } /* end of trace_block() */
5517
5518 /* called when HDLC frame times out
5519 * update stats and do tx completion processing
5520 */
5521 void tx_timeout(unsigned long context)
5522 {
5523 SLMP_INFO *info = (SLMP_INFO*)context;
5524 unsigned long flags;
5525
5526 if ( debug_level >= DEBUG_LEVEL_INFO )
5527 printk( "%s(%d):%s tx_timeout()\n",
5528 __FILE__,__LINE__,info->device_name);
5529 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5530 info->icount.txtimeout++;
5531 }
5532 spin_lock_irqsave(&info->lock,flags);
5533 info->tx_active = 0;
5534 info->tx_count = info->tx_put = info->tx_get = 0;
5535
5536 spin_unlock_irqrestore(&info->lock,flags);
5537
5538 #if SYNCLINK_GENERIC_HDLC
5539 if (info->netcount)
5540 hdlcdev_tx_done(info);
5541 else
5542 #endif
5543 bh_transmit(info);
5544 }
5545
5546 /* called to periodically check the DSR/RI modem signal input status
5547 */
5548 void status_timeout(unsigned long context)
5549 {
5550 u16 status = 0;
5551 SLMP_INFO *info = (SLMP_INFO*)context;
5552 unsigned long flags;
5553 unsigned char delta;
5554
5555
5556 spin_lock_irqsave(&info->lock,flags);
5557 get_signals(info);
5558 spin_unlock_irqrestore(&info->lock,flags);
5559
5560 /* check for DSR/RI state change */
5561
5562 delta = info->old_signals ^ info->serial_signals;
5563 info->old_signals = info->serial_signals;
5564
5565 if (delta & SerialSignal_DSR)
5566 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5567
5568 if (delta & SerialSignal_RI)
5569 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5570
5571 if (delta & SerialSignal_DCD)
5572 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5573
5574 if (delta & SerialSignal_CTS)
5575 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5576
5577 if (status)
5578 isr_io_pin(info,status);
5579
5580 info->status_timer.data = (unsigned long)info;
5581 info->status_timer.function = status_timeout;
5582 info->status_timer.expires = jiffies + msecs_to_jiffies(10);
5583 add_timer(&info->status_timer);
5584 }
5585
5586
5587 /* Register Access Routines -
5588 * All registers are memory mapped
5589 */
5590 #define CALC_REGADDR() \
5591 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5592 if (info->port_num > 1) \
5593 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5594 if ( info->port_num & 1) { \
5595 if (Addr > 0x7f) \
5596 RegAddr += 0x40; /* DMA access */ \
5597 else if (Addr > 0x1f && Addr < 0x60) \
5598 RegAddr += 0x20; /* MSCI access */ \
5599 }
5600
5601
5602 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5603 {
5604 CALC_REGADDR();
5605 return *RegAddr;
5606 }
5607 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5608 {
5609 CALC_REGADDR();
5610 *RegAddr = Value;
5611 }
5612
5613 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5614 {
5615 CALC_REGADDR();
5616 return *((u16 *)RegAddr);
5617 }
5618
5619 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5620 {
5621 CALC_REGADDR();
5622 *((u16 *)RegAddr) = Value;
5623 }
5624
5625 unsigned char read_status_reg(SLMP_INFO * info)
5626 {
5627 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5628 return *RegAddr;
5629 }
5630
5631 void write_control_reg(SLMP_INFO * info)
5632 {
5633 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5634 *RegAddr = info->port_array[0]->ctrlreg_value;
5635 }
5636
5637
5638 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5639 const struct pci_device_id *ent)
5640 {
5641 if (pci_enable_device(dev)) {
5642 printk("error enabling pci device %p\n", dev);
5643 return -EIO;
5644 }
5645 device_init( ++synclinkmp_adapter_count, dev );
5646 return 0;
5647 }
5648
5649 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5650 {
5651 }
Linux with added FPC-III support