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Linux 2.6.20.7
[linux/fpc-iii.git] / drivers / ide / pci / aec62xx.c
blobd261bfbad2227206505ae2c52fa079bf2a0c6a25
1 /*
2 * linux/drivers/ide/pci/aec62xx.c Version 0.11 March 27, 2002
3 *
4 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
5 *
6 */
7
8 #include <linux/module.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/delay.h>
12 #include <linux/hdreg.h>
13 #include <linux/ide.h>
14 #include <linux/init.h>
15
16 #include <asm/io.h>
17
18 struct chipset_bus_clock_list_entry {
19 u8 xfer_speed;
20 u8 chipset_settings;
21 u8 ultra_settings;
22 };
23
24 static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
25 { XFER_UDMA_6, 0x31, 0x07 },
26 { XFER_UDMA_5, 0x31, 0x06 },
27 { XFER_UDMA_4, 0x31, 0x05 },
28 { XFER_UDMA_3, 0x31, 0x04 },
29 { XFER_UDMA_2, 0x31, 0x03 },
30 { XFER_UDMA_1, 0x31, 0x02 },
31 { XFER_UDMA_0, 0x31, 0x01 },
32
33 { XFER_MW_DMA_2, 0x31, 0x00 },
34 { XFER_MW_DMA_1, 0x31, 0x00 },
35 { XFER_MW_DMA_0, 0x0a, 0x00 },
36 { XFER_PIO_4, 0x31, 0x00 },
37 { XFER_PIO_3, 0x33, 0x00 },
38 { XFER_PIO_2, 0x08, 0x00 },
39 { XFER_PIO_1, 0x0a, 0x00 },
40 { XFER_PIO_0, 0x00, 0x00 },
41 { 0, 0x00, 0x00 }
42 };
43
44 static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
45 { XFER_UDMA_6, 0x41, 0x06 },
46 { XFER_UDMA_5, 0x41, 0x05 },
47 { XFER_UDMA_4, 0x41, 0x04 },
48 { XFER_UDMA_3, 0x41, 0x03 },
49 { XFER_UDMA_2, 0x41, 0x02 },
50 { XFER_UDMA_1, 0x41, 0x01 },
51 { XFER_UDMA_0, 0x41, 0x01 },
52
53 { XFER_MW_DMA_2, 0x41, 0x00 },
54 { XFER_MW_DMA_1, 0x42, 0x00 },
55 { XFER_MW_DMA_0, 0x7a, 0x00 },
56 { XFER_PIO_4, 0x41, 0x00 },
57 { XFER_PIO_3, 0x43, 0x00 },
58 { XFER_PIO_2, 0x78, 0x00 },
59 { XFER_PIO_1, 0x7a, 0x00 },
60 { XFER_PIO_0, 0x70, 0x00 },
61 { 0, 0x00, 0x00 }
62 };
63
64 #define BUSCLOCK(D) \
65 ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
66
67
68 /*
69 * TO DO: active tuning and correction of cards without a bios.
70 */
71 static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
72 {
73 for ( ; chipset_table->xfer_speed ; chipset_table++)
74 if (chipset_table->xfer_speed == speed) {
75 return chipset_table->chipset_settings;
76 }
77 return chipset_table->chipset_settings;
78 }
79
80 static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
81 {
82 for ( ; chipset_table->xfer_speed ; chipset_table++)
83 if (chipset_table->xfer_speed == speed) {
84 return chipset_table->ultra_settings;
85 }
86 return chipset_table->ultra_settings;
87 }
88
89 static u8 aec62xx_ratemask (ide_drive_t *drive)
90 {
91 ide_hwif_t *hwif = HWIF(drive);
92 u8 mode;
93
94 switch(hwif->pci_dev->device) {
95 case PCI_DEVICE_ID_ARTOP_ATP865:
96 case PCI_DEVICE_ID_ARTOP_ATP865R:
97 mode = (hwif->INB(((hwif->channel) ?
98 hwif->mate->dma_status :
99 hwif->dma_status)) & 0x10) ? 4 : 3;
100 break;
101 case PCI_DEVICE_ID_ARTOP_ATP860:
102 case PCI_DEVICE_ID_ARTOP_ATP860R:
103 mode = 2;
104 break;
105 case PCI_DEVICE_ID_ARTOP_ATP850UF:
106 default:
107 return 1;
108 }
109
110 if (!eighty_ninty_three(drive))
111 mode = min(mode, (u8)1);
112 return mode;
113 }
114
115 static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
116 {
117 ide_hwif_t *hwif = HWIF(drive);
118 struct pci_dev *dev = hwif->pci_dev;
119 u16 d_conf = 0;
120 u8 speed = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
121 u8 ultra = 0, ultra_conf = 0;
122 u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
123 unsigned long flags;
124
125 local_irq_save(flags);
126 /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
127 pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
128 tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
129 d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
130 pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
131
132 tmp1 = 0x00;
133 tmp2 = 0x00;
134 pci_read_config_byte(dev, 0x54, &ultra);
135 tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
136 ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
137 tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
138 pci_write_config_byte(dev, 0x54, tmp2);
139 local_irq_restore(flags);
140 return(ide_config_drive_speed(drive, speed));
141 }
142
143 static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
144 {
145 ide_hwif_t *hwif = HWIF(drive);
146 struct pci_dev *dev = hwif->pci_dev;
147 u8 speed = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
148 u8 unit = (drive->select.b.unit & 0x01);
149 u8 tmp1 = 0, tmp2 = 0;
150 u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
151 unsigned long flags;
152
153 local_irq_save(flags);
154 /* high 4-bits: Active, low 4-bits: Recovery */
155 pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
156 drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
157 pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
158
159 pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
160 tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
161 ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
162 tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
163 pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
164 local_irq_restore(flags);
165 return(ide_config_drive_speed(drive, speed));
166 }
167
168 static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed)
169 {
170 switch (HWIF(drive)->pci_dev->device) {
171 case PCI_DEVICE_ID_ARTOP_ATP865:
172 case PCI_DEVICE_ID_ARTOP_ATP865R:
173 case PCI_DEVICE_ID_ARTOP_ATP860:
174 case PCI_DEVICE_ID_ARTOP_ATP860R:
175 return ((int) aec6260_tune_chipset(drive, speed));
176 case PCI_DEVICE_ID_ARTOP_ATP850UF:
177 return ((int) aec6210_tune_chipset(drive, speed));
178 default:
179 return -1;
180 }
181 }
182
183 static int config_chipset_for_dma (ide_drive_t *drive)
184 {
185 u8 speed = ide_dma_speed(drive, aec62xx_ratemask(drive));
186
187 if (!(speed))
188 return 0;
189
190 (void) aec62xx_tune_chipset(drive, speed);
191 return ide_dma_enable(drive);
192 }
193
194 static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
195 {
196 u8 speed = 0;
197 u8 new_pio = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
198
199 switch(pio) {
200 case 5: speed = new_pio; break;
201 case 4: speed = XFER_PIO_4; break;
202 case 3: speed = XFER_PIO_3; break;
203 case 2: speed = XFER_PIO_2; break;
204 case 1: speed = XFER_PIO_1; break;
205 default: speed = XFER_PIO_0; break;
206 }
207 (void) aec62xx_tune_chipset(drive, speed);
208 }
209
210 static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
211 {
212 ide_hwif_t *hwif = HWIF(drive);
213 struct hd_driveid *id = drive->id;
214
215 if ((id->capability & 1) && drive->autodma) {
216
217 if (ide_use_dma(drive)) {
218 if (config_chipset_for_dma(drive))
219 return hwif->ide_dma_on(drive);
220 }
221
222 goto fast_ata_pio;
223
224 } else if ((id->capability & 8) || (id->field_valid & 2)) {
225 fast_ata_pio:
226 aec62xx_tune_drive(drive, 5);
227 return hwif->ide_dma_off_quietly(drive);
228 }
229 /* IORDY not supported */
230 return 0;
231 }
232
233 static int aec62xx_irq_timeout (ide_drive_t *drive)
234 {
235 ide_hwif_t *hwif = HWIF(drive);
236 struct pci_dev *dev = hwif->pci_dev;
237
238 switch(dev->device) {
239 case PCI_DEVICE_ID_ARTOP_ATP860:
240 case PCI_DEVICE_ID_ARTOP_ATP860R:
241 case PCI_DEVICE_ID_ARTOP_ATP865:
242 case PCI_DEVICE_ID_ARTOP_ATP865R:
243 printk(" AEC62XX time out ");
244 default:
245 break;
246 }
247 return 0;
248 }
249
250 static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
251 {
252 int bus_speed = system_bus_clock();
253
254 if (dev->resource[PCI_ROM_RESOURCE].start) {
255 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
256 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
257 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
258 }
259
260 if (bus_speed <= 33)
261 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
262 else
263 pci_set_drvdata(dev, (void *) aec6xxx_34_base);
264
265 /* These are necessary to get AEC6280 Macintosh cards to work */
266 if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
267 (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
268 u8 reg49h = 0, reg4ah = 0;
269 /* Clear reset and test bits. */
270 pci_read_config_byte(dev, 0x49, &reg49h);
271 pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
272 /* Enable chip interrupt output. */
273 pci_read_config_byte(dev, 0x4a, &reg4ah);
274 pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
275 /* Enable burst mode. */
276 pci_read_config_byte(dev, 0x4a, &reg4ah);
277 pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
278 }
279
280 return dev->irq;
281 }
282
283 static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
284 {
285 hwif->autodma = 0;
286 hwif->tuneproc = &aec62xx_tune_drive;
287 hwif->speedproc = &aec62xx_tune_chipset;
288
289 if (hwif->pci_dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
290 hwif->serialized = hwif->channel;
291 hwif->no_dsc = 1;
292 }
293
294 if (hwif->mate)
295 hwif->mate->serialized = hwif->serialized;
296
297 if (!hwif->dma_base) {
298 hwif->drives[0].autotune = 1;
299 hwif->drives[1].autotune = 1;
300 return;
301 }
302
303 hwif->ultra_mask = 0x7f;
304 hwif->mwdma_mask = 0x07;
305 hwif->swdma_mask = 0x07;
306
307 hwif->ide_dma_check = &aec62xx_config_drive_xfer_rate;
308 hwif->ide_dma_lostirq = &aec62xx_irq_timeout;
309 hwif->ide_dma_timeout = &aec62xx_irq_timeout;
310 if (!noautodma)
311 hwif->autodma = 1;
312 hwif->drives[0].autodma = hwif->autodma;
313 hwif->drives[1].autodma = hwif->autodma;
314 }
315
316 static void __devinit init_dma_aec62xx(ide_hwif_t *hwif, unsigned long dmabase)
317 {
318 struct pci_dev *dev = hwif->pci_dev;
319
320 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
321 u8 reg54h = 0;
322 unsigned long flags;
323
324 spin_lock_irqsave(&ide_lock, flags);
325 pci_read_config_byte(dev, 0x54, &reg54h);
326 pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F));
327 spin_unlock_irqrestore(&ide_lock, flags);
328 } else {
329 u8 ata66 = 0;
330 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
331 if (!(hwif->udma_four))
332 hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1;
333 }
334
335 ide_setup_dma(hwif, dmabase, 8);
336 }
337
338 static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
339 {
340 return ide_setup_pci_device(dev, d);
341 }
342
343 static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
344 {
345 unsigned long bar4reg = pci_resource_start(dev, 4);
346
347 if (inb(bar4reg+2) & 0x10) {
348 strcpy(d->name, "AEC6880");
349 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
350 strcpy(d->name, "AEC6880R");
351 } else {
352 strcpy(d->name, "AEC6280");
353 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
354 strcpy(d->name, "AEC6280R");
355 }
356
357 return ide_setup_pci_device(dev, d);
358 }
359
360 static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
361 { /* 0 */
362 .name = "AEC6210",
363 .init_setup = init_setup_aec62xx,
364 .init_chipset = init_chipset_aec62xx,
365 .init_hwif = init_hwif_aec62xx,
366 .init_dma = init_dma_aec62xx,
367 .channels = 2,
368 .autodma = AUTODMA,
369 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
370 .bootable = OFF_BOARD,
371 },{ /* 1 */
372 .name = "AEC6260",
373 .init_setup = init_setup_aec62xx,
374 .init_chipset = init_chipset_aec62xx,
375 .init_hwif = init_hwif_aec62xx,
376 .init_dma = init_dma_aec62xx,
377 .channels = 2,
378 .autodma = NOAUTODMA,
379 .bootable = OFF_BOARD,
380 },{ /* 2 */
381 .name = "AEC6260R",
382 .init_setup = init_setup_aec62xx,
383 .init_chipset = init_chipset_aec62xx,
384 .init_hwif = init_hwif_aec62xx,
385 .init_dma = init_dma_aec62xx,
386 .channels = 2,
387 .autodma = AUTODMA,
388 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
389 .bootable = NEVER_BOARD,
390 },{ /* 3 */
391 .name = "AEC6X80",
392 .init_setup = init_setup_aec6x80,
393 .init_chipset = init_chipset_aec62xx,
394 .init_hwif = init_hwif_aec62xx,
395 .init_dma = init_dma_aec62xx,
396 .channels = 2,
397 .autodma = AUTODMA,
398 .bootable = OFF_BOARD,
399 },{ /* 4 */
400 .name = "AEC6X80R",
401 .init_setup = init_setup_aec6x80,
402 .init_chipset = init_chipset_aec62xx,
403 .init_hwif = init_hwif_aec62xx,
404 .init_dma = init_dma_aec62xx,
405 .channels = 2,
406 .autodma = AUTODMA,
407 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
408 .bootable = OFF_BOARD,
409 }
410 };
411
412 /**
413 * aec62xx_init_one - called when a AEC is found
414 * @dev: the aec62xx device
415 * @id: the matching pci id
416 *
417 * Called when the PCI registration layer (or the IDE initialization)
418 * finds a device matching our IDE device tables.
419 */
420
421 static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
422 {
423 ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data];
424
425 return d->init_setup(dev, d);
426 }
427
428 static struct pci_device_id aec62xx_pci_tbl[] = {
429 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
430 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
431 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
432 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
433 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
434 { 0, },
435 };
436 MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
437
438 static struct pci_driver driver = {
439 .name = "AEC62xx_IDE",
440 .id_table = aec62xx_pci_tbl,
441 .probe = aec62xx_init_one,
442 };
443
444 static int __init aec62xx_ide_init(void)
445 {
446 return ide_pci_register_driver(&driver);
447 }
448
449 module_init(aec62xx_ide_init);
450
451 MODULE_AUTHOR("Andre Hedrick");
452 MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
453 MODULE_LICENSE("GPL");
Linux with added FPC-III support