drivers/ide/pci/cs5535.c

   1 /*
   2  * linux/drivers/ide/pci/cs5535.c
   3  *
   4  * Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
   5  *
   6  * History:
   7  * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
   8  * - Reworked tuneproc, set_drive, misc mods to prep for mainline
   9  * - Work was sponsored by CIS (M) Sdn Bhd.
  10  * Ported to Kernel 2.6.11 on June 26, 2005 by
  11  *   Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
  12  *   Alexander Kiausch <alex.kiausch@t-online.de>
  13  * Originally developed by AMD for 2.4/2.6
  14  *
  15  * Development of this chipset driver was funded
  16  * by the nice folks at National Semiconductor/AMD.
  17  *
  18  * This program is free software; you can redistribute it and/or modify it
  19  * under the terms of the GNU General Public License version 2 as published by
  20  * the Free Software Foundation.
  21  *
  22  * Documentation:
  23  *  CS5535 documentation available from AMD
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include <linux/ide.h>
  29
  30 #include "ide-timing.h"
  31
  32 #define MSR_ATAC_BASE           0x51300000
  33 #define ATAC_GLD_MSR_CAP        (MSR_ATAC_BASE+0)
  34 #define ATAC_GLD_MSR_CONFIG     (MSR_ATAC_BASE+0x01)
  35 #define ATAC_GLD_MSR_SMI        (MSR_ATAC_BASE+0x02)
  36 #define ATAC_GLD_MSR_ERROR      (MSR_ATAC_BASE+0x03)
  37 #define ATAC_GLD_MSR_PM         (MSR_ATAC_BASE+0x04)
  38 #define ATAC_GLD_MSR_DIAG       (MSR_ATAC_BASE+0x05)
  39 #define ATAC_IO_BAR             (MSR_ATAC_BASE+0x08)
  40 #define ATAC_RESET              (MSR_ATAC_BASE+0x10)
  41 #define ATAC_CH0D0_PIO          (MSR_ATAC_BASE+0x20)
  42 #define ATAC_CH0D0_DMA          (MSR_ATAC_BASE+0x21)
  43 #define ATAC_CH0D1_PIO          (MSR_ATAC_BASE+0x22)
  44 #define ATAC_CH0D1_DMA          (MSR_ATAC_BASE+0x23)
  45 #define ATAC_PCI_ABRTERR        (MSR_ATAC_BASE+0x24)
  46 #define ATAC_BM0_CMD_PRIM       0x00
  47 #define ATAC_BM0_STS_PRIM       0x02
  48 #define ATAC_BM0_PRD            0x04
  49 #define CS5535_CABLE_DETECT     0x48
  50
  51 /* Format I PIO settings. We seperate out cmd and data for safer timings */
  52
  53 static unsigned int cs5535_pio_cmd_timings[5] =
  54 { 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
  55 static unsigned int cs5535_pio_dta_timings[5] =
  56 { 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };
  57
  58 static unsigned int cs5535_mwdma_timings[3] =
  59 { 0x7F0FFFF3, 0x7F035352, 0x7f024241 };
  60
  61 static unsigned int cs5535_udma_timings[5] =
  62 { 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };
  63
  64 /* Macros to check if the register is the reset value -  reset value is an
  65    invalid timing and indicates the register has not been set previously */
  66
  67 #define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
  68 #define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
  69
  70 /****
  71  *      cs5535_set_speed         -     Configure the chipset to the new speed
  72  *      @drive: Drive to set up
  73  *      @speed: desired speed
  74  *
  75  *      cs5535_set_speed() configures the chipset to a new speed.
  76  */
  77 static void cs5535_set_speed(ide_drive_t *drive, u8 speed)
  78 {
  79
  80         u32 reg = 0, dummy;
  81         int unit = drive->select.b.unit;
  82
  83
  84         /* Set the PIO timings */
  85         if ((speed & XFER_MODE) == XFER_PIO) {
  86                 u8 pioa;
  87                 u8 piob;
  88                 u8 cmd;
  89
  90                 pioa = speed - XFER_PIO_0;
  91                 piob = ide_get_best_pio_mode(&(drive->hwif->drives[!unit]),
  92                                                 255, 4, NULL);
  93                 cmd = pioa < piob ? pioa : piob;
  94
  95                 /* Write the speed of the current drive */
  96                 reg = (cs5535_pio_cmd_timings[cmd] << 16) |
  97                         cs5535_pio_dta_timings[pioa];
  98                 wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);
  99
 100                 /* And if nessesary - change the speed of the other drive */
 101                 rdmsr(unit ?  ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);
 102
 103                 if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
 104                         cs5535_pio_cmd_timings[cmd]) {
 105                         reg &= 0x0000FFFF;
 106                         reg |= cs5535_pio_cmd_timings[cmd] << 16;
 107                         wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
 108                 }
 109
 110                 /* Set bit 31 of the DMA register for PIO format 1 timings */
 111                 rdmsr(unit ?  ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
 112                 wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
 113                                         reg | 0x80000000UL, 0);
 114         } else {
 115                 rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
 116
 117                 reg &= 0x80000000UL;  /* Preserve the PIO format bit */
 118
 119                 if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_7)
 120                         reg |= cs5535_udma_timings[speed - XFER_UDMA_0];
 121                 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
 122                         reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
 123                 else
 124                         return;
 125
 126                 wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
 127         }
 128 }
 129
 130 static u8 cs5535_ratemask(ide_drive_t *drive)
 131 {
 132         /* eighty93 will return 1 if it's 80core and capable of
 133         exceeding udma2, 0 otherwise. we need ratemask to set
 134         the max speed and if we can > udma2 then we return 2
 135         which selects speed_max as udma4 which is the 5535's max
 136         speed, and 1 selects udma2 which is the max for 40c */
 137         if (!eighty_ninty_three(drive))
 138                 return 1;
 139
 140         return 2;
 141 }
 142
 143
 144 /****
 145  *      cs5535_set_drive         -     Configure the drive to the new speed
 146  *      @drive: Drive to set up
 147  *      @speed: desired speed
 148  *
 149  *      cs5535_set_drive() configures the drive and the chipset to a
 150  *      new speed. It also can be called by upper layers.
 151  */
 152 static int cs5535_set_drive(ide_drive_t *drive, u8 speed)
 153 {
 154         speed = ide_rate_filter(cs5535_ratemask(drive), speed);
 155         ide_config_drive_speed(drive, speed);
 156         cs5535_set_speed(drive, speed);
 157
 158         return 0;
 159 }
 160
 161 /****
 162  *      cs5535_tuneproc    -       PIO setup
 163  *      @drive: drive to set up
 164  *      @pio: mode to use (255 for 'best possible')
 165  *
 166  *      A callback from the upper layers for PIO-only tuning.
 167  */
 168 static void cs5535_tuneproc(ide_drive_t *drive, u8 xferspeed)
 169 {
 170         u8 modes[] = {  XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3,
 171                         XFER_PIO_4 };
 172
 173         /* cs5535 max pio is pio 4, best_pio will check the blacklist.
 174         i think we don't need to rate_filter the incoming xferspeed
 175         since we know we're only going to choose pio */
 176         xferspeed = ide_get_best_pio_mode(drive, xferspeed, 4, NULL);
 177         ide_config_drive_speed(drive, modes[xferspeed]);
 178         cs5535_set_speed(drive, xferspeed);
 179 }
 180
 181 static int cs5535_config_drive_for_dma(ide_drive_t *drive)
 182 {
 183         u8 speed;
 184
 185         speed = ide_dma_speed(drive, cs5535_ratemask(drive));
 186
 187         /* If no DMA speed was available then let dma_check hit pio */
 188         if (!speed) {
 189                 return 0;
 190         }
 191
 192         cs5535_set_drive(drive, speed);
 193         return ide_dma_enable(drive);
 194 }
 195
 196 static int cs5535_dma_check(ide_drive_t *drive)
 197 {
 198         ide_hwif_t *hwif        = drive->hwif;
 199         struct hd_driveid *id   = drive->id;
 200         u8 speed;
 201
 202         drive->init_speed = 0;
 203
 204         if ((id->capability & 1) && drive->autodma) {
 205                 if (ide_use_dma(drive)) {
 206                         if (cs5535_config_drive_for_dma(drive))
 207                                 return hwif->ide_dma_on(drive);
 208                 }
 209
 210                 goto fast_ata_pio;
 211
 212         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 213 fast_ata_pio:
 214                 speed = ide_get_best_pio_mode(drive, 255, 4, NULL);
 215                 cs5535_set_drive(drive, speed);
 216                 return hwif->ide_dma_off_quietly(drive);
 217         }
 218         /* IORDY not supported */
 219         return 0;
 220 }
 221
 222 static u8 __devinit cs5535_cable_detect(struct pci_dev *dev)
 223 {
 224         u8 bit;
 225
 226         /* if a 80 wire cable was detected */
 227         pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);
 228         return (bit & 1);
 229 }
 230
 231 /****
 232  *      init_hwif_cs5535        -       Initialize one ide cannel
 233  *      @hwif: Channel descriptor
 234  *
 235  *      This gets invoked by the IDE driver once for each channel. It
 236  *      performs channel-specific pre-initialization before drive probing.
 237  *
 238  */
 239 static void __devinit init_hwif_cs5535(ide_hwif_t *hwif)
 240 {
 241         int i;
 242
 243         hwif->autodma = 0;
 244
 245         hwif->tuneproc = &cs5535_tuneproc;
 246         hwif->speedproc = &cs5535_set_drive;
 247         hwif->ide_dma_check = &cs5535_dma_check;
 248
 249         hwif->atapi_dma = 1;
 250         hwif->ultra_mask = 0x1F;
 251         hwif->mwdma_mask = 0x07;
 252
 253
 254         hwif->udma_four = cs5535_cable_detect(hwif->pci_dev);
 255
 256         if (!noautodma)
 257                 hwif->autodma = 1;
 258
 259         /* just setting autotune and not worrying about bios timings */
 260         for (i = 0; i < 2; i++) {
 261                 hwif->drives[i].autotune = 1;
 262                 hwif->drives[i].autodma = hwif->autodma;
 263         }
 264 }
 265
 266 static ide_pci_device_t cs5535_chipset __devinitdata = {
 267         .name           = "CS5535",
 268         .init_hwif      = init_hwif_cs5535,
 269         .channels       = 1,
 270         .autodma        = AUTODMA,
 271         .bootable       = ON_BOARD,
 272 };
 273
 274 static int __devinit cs5535_init_one(struct pci_dev *dev,
 275                                         const struct pci_device_id *id)
 276 {
 277         return ide_setup_pci_device(dev, &cs5535_chipset);
 278 }
 279
 280 static struct pci_device_id cs5535_pci_tbl[] =
 281 {
 282         { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_IDE, PCI_ANY_ID,
 283                 PCI_ANY_ID, 0, 0, 0},
 284         { 0, },
 285 };
 286
 287 MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);
 288
 289 static struct pci_driver driver = {
 290         .name       = "CS5535_IDE",
 291         .id_table   = cs5535_pci_tbl,
 292         .probe      = cs5535_init_one,
 293 };
 294
 295 static int __init cs5535_ide_init(void)
 296 {
 297         return ide_pci_register_driver(&driver);
 298 }
 299
 300 module_init(cs5535_ide_init);
 301
 302 MODULE_AUTHOR("AMD");
 303 MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
 304 MODULE_LICENSE("GPL");