2 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2005-2006 MontaVista Software, Inc.
9 * Thanks to HighPoint Technologies for their assistance, and hardware.
10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
12 * development and support.
15 * HighPoint has its own drivers (open source except for the RAID part)
16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
21 * Note that final HPT370 support was done by force extraction of GPL.
23 * - add function for getting/setting power status of drive
24 * - the HPT370's state machine can get confused. reset it before each dma
25 * xfer to prevent that from happening.
26 * - reset state engine whenever we get an error.
27 * - check for busmaster state at end of dma.
28 * - use new highpoint timings.
29 * - detect bus speed using highpoint register.
30 * - use pll if we don't have a clock table. added a 66MHz table that's
31 * just 2x the 33MHz table.
32 * - removed turnaround. NOTE: we never want to switch between pll and
33 * pci clocks as the chip can glitch in those cases. the highpoint
34 * approved workaround slows everything down too much to be useful. in
35 * addition, we would have to serialize access to each chip.
36 * Adrian Sun <a.sun@sun.com>
38 * add drive timings for 66MHz PCI bus,
39 * fix ATA Cable signal detection, fix incorrect /proc info
40 * add /proc display for per-drive PIO/DMA/UDMA mode and
41 * per-channel ATA-33/66 Cable detect.
42 * Duncan Laurie <void@sun.com>
44 * fixup /proc output for multiple controllers
45 * Tim Hockin <thockin@sun.com>
48 * Reset the hpt366 on error, reset on dma
49 * Fix disabling Fast Interrupt hpt366.
50 * Mike Waychison <crlf@sun.com>
52 * Added support for 372N clocking and clock switching. The 372N needs
53 * different clocks on read/write. This requires overloading rw_disk and
54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
56 * Alan Cox <alan@redhat.com>
58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
63 * - avoid calibrating PLL twice as the second time results in a wrong PCI
64 * frequency and thus in the wrong timings for the secondary channel
65 * - disable UltraATA/133 for HPT372 by default (50 MHz DPLL clock do not
66 * allow for this speed anyway)
67 * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
68 * - HPT371/N are single channel chips, so avoid touching the primary channel
69 * which exists only virtually (there's no pins for it)
70 * - fix/remove bad/unused timing tables and use one set of tables for the whole
71 * HPT37x chip family; save space by introducing the separate transfer mode
72 * table in which the mode lookup is done
73 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
74 * the wrong PCI frequency since DPLL has already been calibrated by BIOS
75 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
76 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
77 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
78 * they tamper with its fields
84 #include <linux/types.h>
85 #include <linux/module.h>
86 #include <linux/kernel.h>
87 #include <linux/delay.h>
88 #include <linux/timer.h>
90 #include <linux/ioport.h>
91 #include <linux/blkdev.h>
92 #include <linux/hdreg.h>
94 #include <linux/interrupt.h>
95 #include <linux/pci.h>
96 #include <linux/init.h>
97 #include <linux/ide.h>
99 #include <asm/uaccess.h>
103 /* various tuning parameters */
104 #define HPT_RESET_STATE_ENGINE
105 #undef HPT_DELAY_INTERRUPT
106 #define HPT_SERIALIZE_IO 0
108 static const char *quirk_drives
[] = {
109 "QUANTUM FIREBALLlct08 08",
110 "QUANTUM FIREBALLP KA6.4",
111 "QUANTUM FIREBALLP LM20.4",
112 "QUANTUM FIREBALLP LM20.5",
116 static const char *bad_ata100_5
[] = {
135 static const char *bad_ata66_4
[] = {
154 static const char *bad_ata66_3
[] = {
159 static const char *bad_ata33
[] = {
160 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
161 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
162 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
164 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
165 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
166 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
170 static u8 xfer_speeds
[] = {
190 /* Key for bus clock timings
193 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
195 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
197 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
199 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
201 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
202 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
203 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
205 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
206 * task file register access.
209 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
214 static u32 forty_base_hpt36x
[] = {
215 /* XFER_UDMA_6 */ 0x900fd943,
216 /* XFER_UDMA_5 */ 0x900fd943,
217 /* XFER_UDMA_4 */ 0x900fd943,
218 /* XFER_UDMA_3 */ 0x900ad943,
219 /* XFER_UDMA_2 */ 0x900bd943,
220 /* XFER_UDMA_1 */ 0x9008d943,
221 /* XFER_UDMA_0 */ 0x9008d943,
223 /* XFER_MW_DMA_2 */ 0xa008d943,
224 /* XFER_MW_DMA_1 */ 0xa010d955,
225 /* XFER_MW_DMA_0 */ 0xa010d9fc,
227 /* XFER_PIO_4 */ 0xc008d963,
228 /* XFER_PIO_3 */ 0xc010d974,
229 /* XFER_PIO_2 */ 0xc010d997,
230 /* XFER_PIO_1 */ 0xc010d9c7,
231 /* XFER_PIO_0 */ 0xc018d9d9
234 static u32 thirty_three_base_hpt36x
[] = {
235 /* XFER_UDMA_6 */ 0x90c9a731,
236 /* XFER_UDMA_5 */ 0x90c9a731,
237 /* XFER_UDMA_4 */ 0x90c9a731,
238 /* XFER_UDMA_3 */ 0x90cfa731,
239 /* XFER_UDMA_2 */ 0x90caa731,
240 /* XFER_UDMA_1 */ 0x90cba731,
241 /* XFER_UDMA_0 */ 0x90c8a731,
243 /* XFER_MW_DMA_2 */ 0xa0c8a731,
244 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
245 /* XFER_MW_DMA_0 */ 0xa0c8a797,
247 /* XFER_PIO_4 */ 0xc0c8a731,
248 /* XFER_PIO_3 */ 0xc0c8a742,
249 /* XFER_PIO_2 */ 0xc0d0a753,
250 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
251 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
254 static u32 twenty_five_base_hpt36x
[] = {
255 /* XFER_UDMA_6 */ 0x90c98521,
256 /* XFER_UDMA_5 */ 0x90c98521,
257 /* XFER_UDMA_4 */ 0x90c98521,
258 /* XFER_UDMA_3 */ 0x90cf8521,
259 /* XFER_UDMA_2 */ 0x90cf8521,
260 /* XFER_UDMA_1 */ 0x90cb8521,
261 /* XFER_UDMA_0 */ 0x90cb8521,
263 /* XFER_MW_DMA_2 */ 0xa0ca8521,
264 /* XFER_MW_DMA_1 */ 0xa0ca8532,
265 /* XFER_MW_DMA_0 */ 0xa0ca8575,
267 /* XFER_PIO_4 */ 0xc0ca8521,
268 /* XFER_PIO_3 */ 0xc0ca8532,
269 /* XFER_PIO_2 */ 0xc0ca8542,
270 /* XFER_PIO_1 */ 0xc0d08572,
271 /* XFER_PIO_0 */ 0xc0d08585
274 static u32 thirty_three_base_hpt37x
[] = {
275 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
276 /* XFER_UDMA_5 */ 0x12446231,
277 /* XFER_UDMA_4 */ 0x12446231,
278 /* XFER_UDMA_3 */ 0x126c6231,
279 /* XFER_UDMA_2 */ 0x12486231,
280 /* XFER_UDMA_1 */ 0x124c6233,
281 /* XFER_UDMA_0 */ 0x12506297,
283 /* XFER_MW_DMA_2 */ 0x22406c31,
284 /* XFER_MW_DMA_1 */ 0x22406c33,
285 /* XFER_MW_DMA_0 */ 0x22406c97,
287 /* XFER_PIO_4 */ 0x06414e31,
288 /* XFER_PIO_3 */ 0x06414e42,
289 /* XFER_PIO_2 */ 0x06414e53,
290 /* XFER_PIO_1 */ 0x06814e93,
291 /* XFER_PIO_0 */ 0x06814ea7
294 static u32 fifty_base_hpt37x
[] = {
295 /* XFER_UDMA_6 */ 0x12848242,
296 /* XFER_UDMA_5 */ 0x12848242,
297 /* XFER_UDMA_4 */ 0x12ac8242,
298 /* XFER_UDMA_3 */ 0x128c8242,
299 /* XFER_UDMA_2 */ 0x120c8242,
300 /* XFER_UDMA_1 */ 0x12148254,
301 /* XFER_UDMA_0 */ 0x121882ea,
303 /* XFER_MW_DMA_2 */ 0x22808242,
304 /* XFER_MW_DMA_1 */ 0x22808254,
305 /* XFER_MW_DMA_0 */ 0x228082ea,
307 /* XFER_PIO_4 */ 0x0a81f442,
308 /* XFER_PIO_3 */ 0x0a81f443,
309 /* XFER_PIO_2 */ 0x0a81f454,
310 /* XFER_PIO_1 */ 0x0ac1f465,
311 /* XFER_PIO_0 */ 0x0ac1f48a
314 static u32 sixty_six_base_hpt37x
[] = {
315 /* XFER_UDMA_6 */ 0x1c869c62,
316 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
317 /* XFER_UDMA_4 */ 0x1c8a9c62,
318 /* XFER_UDMA_3 */ 0x1c8e9c62,
319 /* XFER_UDMA_2 */ 0x1c929c62,
320 /* XFER_UDMA_1 */ 0x1c9a9c62,
321 /* XFER_UDMA_0 */ 0x1c829c62,
323 /* XFER_MW_DMA_2 */ 0x2c829c62,
324 /* XFER_MW_DMA_1 */ 0x2c829c66,
325 /* XFER_MW_DMA_0 */ 0x2c829d2e,
327 /* XFER_PIO_4 */ 0x0c829c62,
328 /* XFER_PIO_3 */ 0x0c829c84,
329 /* XFER_PIO_2 */ 0x0c829ca6,
330 /* XFER_PIO_1 */ 0x0d029d26,
331 /* XFER_PIO_0 */ 0x0d029d5e
334 #define HPT366_DEBUG_DRIVE_INFO 0
335 #define HPT374_ALLOW_ATA133_6 0
336 #define HPT371_ALLOW_ATA133_6 0
337 #define HPT302_ALLOW_ATA133_6 0
338 #define HPT372_ALLOW_ATA133_6 0
339 #define HPT370_ALLOW_ATA100_5 1
340 #define HPT366_ALLOW_ATA66_4 1
341 #define HPT366_ALLOW_ATA66_3 1
342 #define HPT366_MAX_DEVS 8
344 #define F_LOW_PCI_33 0x23
345 #define F_LOW_PCI_40 0x29
346 #define F_LOW_PCI_50 0x2d
347 #define F_LOW_PCI_66 0x42
350 * Hold all the highpoint quirks and revision information in one
356 u8 max_mode
; /* Speeds allowed */
357 int revision
; /* Chipset revision */
358 int flags
; /* Chipset properties */
367 * This wants fixing so that we do everything not by classrev
368 * (which breaks on the newest chips) but by creating an
369 * enumeration of chip variants and using that
372 static __devinit u32
hpt_revision (struct pci_dev
*dev
)
375 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
378 switch(dev
->device
) {
379 /* Remap new 372N onto 372 */
380 case PCI_DEVICE_ID_TTI_HPT372N
:
381 class_rev
= PCI_DEVICE_ID_TTI_HPT372
; break;
382 case PCI_DEVICE_ID_TTI_HPT374
:
383 class_rev
= PCI_DEVICE_ID_TTI_HPT374
; break;
384 case PCI_DEVICE_ID_TTI_HPT371
:
385 class_rev
= PCI_DEVICE_ID_TTI_HPT371
; break;
386 case PCI_DEVICE_ID_TTI_HPT302
:
387 class_rev
= PCI_DEVICE_ID_TTI_HPT302
; break;
388 case PCI_DEVICE_ID_TTI_HPT372
:
389 class_rev
= PCI_DEVICE_ID_TTI_HPT372
; break;
396 static int check_in_drive_lists(ide_drive_t
*drive
, const char **list
);
398 static u8
hpt3xx_ratemask (ide_drive_t
*drive
)
400 ide_hwif_t
*hwif
= drive
->hwif
;
401 struct hpt_info
*info
= ide_get_hwifdata(hwif
);
404 /* FIXME: TODO - move this to set info->mode once at boot */
406 if (info
->revision
>= 8) { /* HPT374 */
407 mode
= (HPT374_ALLOW_ATA133_6
) ? 4 : 3;
408 } else if (info
->revision
>= 7) { /* HPT371 */
409 mode
= (HPT371_ALLOW_ATA133_6
) ? 4 : 3;
410 } else if (info
->revision
>= 6) { /* HPT302 */
411 mode
= (HPT302_ALLOW_ATA133_6
) ? 4 : 3;
412 } else if (info
->revision
>= 5) { /* HPT372 */
413 mode
= (HPT372_ALLOW_ATA133_6
) ? 4 : 3;
414 } else if (info
->revision
>= 4) { /* HPT370A */
415 mode
= (HPT370_ALLOW_ATA100_5
) ? 3 : 2;
416 } else if (info
->revision
>= 3) { /* HPT370 */
417 mode
= (HPT370_ALLOW_ATA100_5
) ? 3 : 2;
418 mode
= (check_in_drive_lists(drive
, bad_ata33
)) ? 0 : mode
;
419 } else { /* HPT366 and HPT368 */
420 mode
= (check_in_drive_lists(drive
, bad_ata33
)) ? 0 : 2;
422 if (!eighty_ninty_three(drive
) && mode
)
423 mode
= min(mode
, (u8
)1);
428 * Note for the future; the SATA hpt37x we must set
429 * either PIO or UDMA modes 0,4,5
432 static u8
hpt3xx_ratefilter (ide_drive_t
*drive
, u8 speed
)
434 ide_hwif_t
*hwif
= drive
->hwif
;
435 struct hpt_info
*info
= ide_get_hwifdata(hwif
);
436 u8 mode
= hpt3xx_ratemask(drive
);
438 if (drive
->media
!= ide_disk
)
439 return min(speed
, (u8
)XFER_PIO_4
);
443 speed
= min(speed
, (u8
)XFER_UDMA_6
);
446 speed
= min(speed
, (u8
)XFER_UDMA_5
);
447 if (info
->revision
>= 5)
449 if (check_in_drive_lists(drive
, bad_ata100_5
))
450 speed
= min(speed
, (u8
)XFER_UDMA_4
);
453 speed
= min(speed
, (u8
)XFER_UDMA_4
);
455 * CHECK ME, Does this need to be set to 5 ??
457 if (info
->revision
>= 3)
459 if ((check_in_drive_lists(drive
, bad_ata66_4
)) ||
460 (!(HPT366_ALLOW_ATA66_4
)))
461 speed
= min(speed
, (u8
)XFER_UDMA_3
);
462 if ((check_in_drive_lists(drive
, bad_ata66_3
)) ||
463 (!(HPT366_ALLOW_ATA66_3
)))
464 speed
= min(speed
, (u8
)XFER_UDMA_2
);
467 speed
= min(speed
, (u8
)XFER_UDMA_2
);
469 * CHECK ME, Does this need to be set to 5 ??
471 if (info
->revision
>= 3)
473 if (check_in_drive_lists(drive
, bad_ata33
))
474 speed
= min(speed
, (u8
)XFER_MW_DMA_2
);
478 speed
= min(speed
, (u8
)XFER_MW_DMA_2
);
484 static int check_in_drive_lists (ide_drive_t
*drive
, const char **list
)
486 struct hd_driveid
*id
= drive
->id
;
488 if (quirk_drives
== list
) {
490 if (strstr(id
->model
, *list
++))
494 if (!strcmp(*list
++,id
->model
))
500 static u32
pci_bus_clock_list(u8 speed
, u32
*chipset_table
)
505 * Lookup the transfer mode table to get the index into
508 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
510 for (i
= 0; i
< ARRAY_SIZE(xfer_speeds
) - 1; i
++)
511 if (xfer_speeds
[i
] == speed
)
513 return chipset_table
[i
];
516 static int hpt36x_tune_chipset(ide_drive_t
*drive
, u8 xferspeed
)
518 ide_hwif_t
*hwif
= drive
->hwif
;
519 struct pci_dev
*dev
= hwif
->pci_dev
;
520 struct hpt_info
*info
= ide_get_hwifdata(hwif
);
521 u8 speed
= hpt3xx_ratefilter(drive
, xferspeed
);
522 u8 regtime
= (drive
->select
.b
.unit
& 0x01) ? 0x44 : 0x40;
523 u8 regfast
= (hwif
->channel
) ? 0x55 : 0x51;
525 u32 reg1
= 0, reg2
= 0;
528 * Disable the "fast interrupt" prediction.
530 pci_read_config_byte(dev
, regfast
, &drive_fast
);
531 if (drive_fast
& 0x80)
532 pci_write_config_byte(dev
, regfast
, drive_fast
& ~0x80);
534 reg2
= pci_bus_clock_list(speed
, info
->speed
);
537 * Disable on-chip PIO FIFO/buffer
538 * (to avoid problems handling I/O errors later)
540 pci_read_config_dword(dev
, regtime
, ®1
);
541 if (speed
>= XFER_MW_DMA_0
) {
542 reg2
= (reg2
& ~0xc0000000) | (reg1
& 0xc0000000);
544 reg2
= (reg2
& ~0x30070000) | (reg1
& 0x30070000);
548 pci_write_config_dword(dev
, regtime
, reg2
);
550 return ide_config_drive_speed(drive
, speed
);
553 static int hpt370_tune_chipset(ide_drive_t
*drive
, u8 xferspeed
)
555 ide_hwif_t
*hwif
= drive
->hwif
;
556 struct pci_dev
*dev
= hwif
->pci_dev
;
557 struct hpt_info
*info
= ide_get_hwifdata(hwif
);
558 u8 speed
= hpt3xx_ratefilter(drive
, xferspeed
);
559 u8 regfast
= (drive
->hwif
->channel
) ? 0x55 : 0x51;
560 u8 drive_pci
= 0x40 + (drive
->dn
* 4);
561 u8 new_fast
= 0, drive_fast
= 0;
562 u32 list_conf
= 0, drive_conf
= 0;
563 u32 conf_mask
= (speed
>= XFER_MW_DMA_0
) ? 0xc0000000 : 0x30070000;
566 * Disable the "fast interrupt" prediction.
567 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
569 pci_read_config_byte(dev
, regfast
, &drive_fast
);
570 new_fast
= drive_fast
;
574 #ifdef HPT_DELAY_INTERRUPT
578 if ((new_fast
& 0x01) == 0)
581 if (new_fast
!= drive_fast
)
582 pci_write_config_byte(dev
, regfast
, new_fast
);
584 list_conf
= pci_bus_clock_list(speed
, info
->speed
);
586 pci_read_config_dword(dev
, drive_pci
, &drive_conf
);
587 list_conf
= (list_conf
& ~conf_mask
) | (drive_conf
& conf_mask
);
589 if (speed
< XFER_MW_DMA_0
)
590 list_conf
&= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
591 pci_write_config_dword(dev
, drive_pci
, list_conf
);
593 return ide_config_drive_speed(drive
, speed
);
596 static int hpt372_tune_chipset(ide_drive_t
*drive
, u8 xferspeed
)
598 ide_hwif_t
*hwif
= drive
->hwif
;
599 struct pci_dev
*dev
= hwif
->pci_dev
;
600 struct hpt_info
*info
= ide_get_hwifdata(hwif
);
601 u8 speed
= hpt3xx_ratefilter(drive
, xferspeed
);
602 u8 regfast
= (drive
->hwif
->channel
) ? 0x55 : 0x51;
603 u8 drive_fast
= 0, drive_pci
= 0x40 + (drive
->dn
* 4);
604 u32 list_conf
= 0, drive_conf
= 0;
605 u32 conf_mask
= (speed
>= XFER_MW_DMA_0
) ? 0xc0000000 : 0x30070000;
608 * Disable the "fast interrupt" prediction.
609 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
611 pci_read_config_byte(dev
, regfast
, &drive_fast
);
613 pci_write_config_byte(dev
, regfast
, drive_fast
);
615 list_conf
= pci_bus_clock_list(speed
, info
->speed
);
616 pci_read_config_dword(dev
, drive_pci
, &drive_conf
);
617 list_conf
= (list_conf
& ~conf_mask
) | (drive_conf
& conf_mask
);
618 if (speed
< XFER_MW_DMA_0
)
619 list_conf
&= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
620 pci_write_config_dword(dev
, drive_pci
, list_conf
);
622 return ide_config_drive_speed(drive
, speed
);
625 static int hpt3xx_tune_chipset (ide_drive_t
*drive
, u8 speed
)
627 ide_hwif_t
*hwif
= drive
->hwif
;
628 struct hpt_info
*info
= ide_get_hwifdata(hwif
);
630 if (info
->revision
>= 8)
631 return hpt372_tune_chipset(drive
, speed
); /* not a typo */
632 else if (info
->revision
>= 5)
633 return hpt372_tune_chipset(drive
, speed
);
634 else if (info
->revision
>= 3)
635 return hpt370_tune_chipset(drive
, speed
);
636 else /* hpt368: hpt_minimum_revision(dev, 2) */
637 return hpt36x_tune_chipset(drive
, speed
);
640 static void hpt3xx_tune_drive (ide_drive_t
*drive
, u8 pio
)
642 pio
= ide_get_best_pio_mode(drive
, 255, pio
, NULL
);
643 (void) hpt3xx_tune_chipset(drive
, (XFER_PIO_0
+ pio
));
647 * This allows the configuration of ide_pci chipset registers
648 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
649 * after the drive is reported by the OS. Initially for designed for
650 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
652 * check_in_drive_lists(drive, bad_ata66_4)
653 * check_in_drive_lists(drive, bad_ata66_3)
654 * check_in_drive_lists(drive, bad_ata33)
657 static int config_chipset_for_dma (ide_drive_t
*drive
)
659 u8 speed
= ide_dma_speed(drive
, hpt3xx_ratemask(drive
));
660 ide_hwif_t
*hwif
= drive
->hwif
;
661 struct hpt_info
*info
= ide_get_hwifdata(hwif
);
666 /* If we don't have any timings we can't do a lot */
667 if (info
->speed
== NULL
)
670 (void) hpt3xx_tune_chipset(drive
, speed
);
671 return ide_dma_enable(drive
);
674 static int hpt3xx_quirkproc (ide_drive_t
*drive
)
676 return ((int) check_in_drive_lists(drive
, quirk_drives
));
679 static void hpt3xx_intrproc (ide_drive_t
*drive
)
681 ide_hwif_t
*hwif
= drive
->hwif
;
683 if (drive
->quirk_list
)
685 /* drives in the quirk_list may not like intr setups/cleanups */
686 hwif
->OUTB(drive
->ctl
|2, IDE_CONTROL_REG
);
689 static void hpt3xx_maskproc (ide_drive_t
*drive
, int mask
)
691 ide_hwif_t
*hwif
= drive
->hwif
;
692 struct hpt_info
*info
= ide_get_hwifdata(hwif
);
693 struct pci_dev
*dev
= hwif
->pci_dev
;
695 if (drive
->quirk_list
) {
696 if (info
->revision
>= 3) {
698 pci_read_config_byte(dev
, 0x5a, ®5a
);
699 if (((reg5a
& 0x10) >> 4) != mask
)
700 pci_write_config_byte(dev
, 0x5a, mask
? (reg5a
| 0x10) : (reg5a
& ~0x10));
703 disable_irq(hwif
->irq
);
705 enable_irq(hwif
->irq
);
710 hwif
->OUTB(mask
? (drive
->ctl
| 2) :
716 static int hpt366_config_drive_xfer_rate (ide_drive_t
*drive
)
718 ide_hwif_t
*hwif
= drive
->hwif
;
719 struct hd_driveid
*id
= drive
->id
;
721 drive
->init_speed
= 0;
723 if ((id
->capability
& 1) && drive
->autodma
) {
725 if (ide_use_dma(drive
)) {
726 if (config_chipset_for_dma(drive
))
727 return hwif
->ide_dma_on(drive
);
732 } else if ((id
->capability
& 8) || (id
->field_valid
& 2)) {
734 hpt3xx_tune_drive(drive
, 5);
735 return hwif
->ide_dma_off_quietly(drive
);
737 /* IORDY not supported */
742 * This is specific to the HPT366 UDMA bios chipset
743 * by HighPoint|Triones Technologies, Inc.
745 static int hpt366_ide_dma_lostirq (ide_drive_t
*drive
)
747 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
748 u8 reg50h
= 0, reg52h
= 0, reg5ah
= 0;
750 pci_read_config_byte(dev
, 0x50, ®50h
);
751 pci_read_config_byte(dev
, 0x52, ®52h
);
752 pci_read_config_byte(dev
, 0x5a, ®5ah
);
753 printk("%s: (%s) reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
754 drive
->name
, __FUNCTION__
, reg50h
, reg52h
, reg5ah
);
756 pci_write_config_byte(dev
, 0x5a, reg5ah
& ~0x10);
757 return __ide_dma_lostirq(drive
);
760 static void hpt370_clear_engine (ide_drive_t
*drive
)
762 u8 regstate
= HWIF(drive
)->channel
? 0x54 : 0x50;
763 pci_write_config_byte(HWIF(drive
)->pci_dev
, regstate
, 0x37);
767 static void hpt370_ide_dma_start(ide_drive_t
*drive
)
769 #ifdef HPT_RESET_STATE_ENGINE
770 hpt370_clear_engine(drive
);
772 ide_dma_start(drive
);
775 static int hpt370_ide_dma_end (ide_drive_t
*drive
)
777 ide_hwif_t
*hwif
= HWIF(drive
);
778 u8 dma_stat
= hwif
->INB(hwif
->dma_status
);
780 if (dma_stat
& 0x01) {
783 dma_stat
= hwif
->INB(hwif
->dma_status
);
785 if ((dma_stat
& 0x01) != 0)
787 (void) HWIF(drive
)->ide_dma_timeout(drive
);
789 return __ide_dma_end(drive
);
792 static void hpt370_lostirq_timeout (ide_drive_t
*drive
)
794 ide_hwif_t
*hwif
= HWIF(drive
);
795 u8 bfifo
= 0, reginfo
= hwif
->channel
? 0x56 : 0x52;
796 u8 dma_stat
= 0, dma_cmd
= 0;
798 pci_read_config_byte(HWIF(drive
)->pci_dev
, reginfo
, &bfifo
);
799 printk(KERN_DEBUG
"%s: %d bytes in FIFO\n", drive
->name
, bfifo
);
800 hpt370_clear_engine(drive
);
801 /* get dma command mode */
802 dma_cmd
= hwif
->INB(hwif
->dma_command
);
804 hwif
->OUTB(dma_cmd
& ~0x1, hwif
->dma_command
);
805 dma_stat
= hwif
->INB(hwif
->dma_status
);
807 hwif
->OUTB(dma_stat
| 0x6, hwif
->dma_status
);
810 static int hpt370_ide_dma_timeout (ide_drive_t
*drive
)
812 hpt370_lostirq_timeout(drive
);
813 hpt370_clear_engine(drive
);
814 return __ide_dma_timeout(drive
);
817 static int hpt370_ide_dma_lostirq (ide_drive_t
*drive
)
819 hpt370_lostirq_timeout(drive
);
820 hpt370_clear_engine(drive
);
821 return __ide_dma_lostirq(drive
);
824 /* returns 1 if DMA IRQ issued, 0 otherwise */
825 static int hpt374_ide_dma_test_irq(ide_drive_t
*drive
)
827 ide_hwif_t
*hwif
= HWIF(drive
);
829 u8 reginfo
= hwif
->channel
? 0x56 : 0x52;
832 pci_read_config_word(hwif
->pci_dev
, reginfo
, &bfifo
);
834 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
838 dma_stat
= hwif
->INB(hwif
->dma_status
);
839 /* return 1 if INTR asserted */
840 if ((dma_stat
& 4) == 4)
843 if (!drive
->waiting_for_dma
)
844 printk(KERN_WARNING
"%s: (%s) called while not waiting\n",
845 drive
->name
, __FUNCTION__
);
849 static int hpt374_ide_dma_end (ide_drive_t
*drive
)
851 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
852 ide_hwif_t
*hwif
= HWIF(drive
);
853 u8 msc_stat
= 0, mscreg
= hwif
->channel
? 0x54 : 0x50;
854 u8 bwsr_stat
= 0, bwsr_mask
= hwif
->channel
? 0x02 : 0x01;
856 pci_read_config_byte(dev
, 0x6a, &bwsr_stat
);
857 pci_read_config_byte(dev
, mscreg
, &msc_stat
);
858 if ((bwsr_stat
& bwsr_mask
) == bwsr_mask
)
859 pci_write_config_byte(dev
, mscreg
, msc_stat
|0x30);
860 return __ide_dma_end(drive
);
864 * hpt3xxn_set_clock - perform clock switching dance
865 * @hwif: hwif to switch
866 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
868 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
869 * NOTE: avoid touching the disabled primary channel on HPT371N -- it
870 * doesn't physically exist anyway...
873 static void hpt3xxn_set_clock(ide_hwif_t
*hwif
, u8 mode
)
875 u8 mcr1
, scr2
= hwif
->INB(hwif
->dma_master
+ 0x7b);
877 if ((scr2
& 0x7f) == mode
)
880 /* MISC. control register 1 has the channel enable bit... */
881 mcr1
= hwif
->INB(hwif
->dma_master
+ 0x70);
883 /* Tristate the bus */
885 hwif
->OUTB(0x80, hwif
->dma_master
+ 0x73);
886 hwif
->OUTB(0x80, hwif
->dma_master
+ 0x77);
888 /* Switch clock and reset channels */
889 hwif
->OUTB(mode
, hwif
->dma_master
+ 0x7b);
890 hwif
->OUTB(0xc0, hwif
->dma_master
+ 0x79);
892 /* Reset state machines */
894 hwif
->OUTB(0x37, hwif
->dma_master
+ 0x70);
895 hwif
->OUTB(0x37, hwif
->dma_master
+ 0x74);
898 hwif
->OUTB(0x00, hwif
->dma_master
+ 0x79);
900 /* Reconnect channels to bus */
902 hwif
->OUTB(0x00, hwif
->dma_master
+ 0x73);
903 hwif
->OUTB(0x00, hwif
->dma_master
+ 0x77);
907 * hpt3xxn_rw_disk - prepare for I/O
908 * @drive: drive for command
909 * @rq: block request structure
911 * This is called when a disk I/O is issued to HPT3xxN.
912 * We need it because of the clock switching.
915 static void hpt3xxn_rw_disk(ide_drive_t
*drive
, struct request
*rq
)
917 ide_hwif_t
*hwif
= HWIF(drive
);
918 u8 wantclock
= rq_data_dir(rq
) ? 0x23 : 0x21;
920 hpt3xxn_set_clock(hwif
, wantclock
);
924 * Set/get power state for a drive.
926 * When we turn the power back on, we need to re-initialize things.
928 #define TRISTATE_BIT 0x8000
930 static int hpt3xx_busproc(ide_drive_t
*drive
, int state
)
932 ide_hwif_t
*hwif
= drive
->hwif
;
933 struct pci_dev
*dev
= hwif
->pci_dev
;
934 u8 tristate
, resetmask
, bus_reg
= 0;
937 hwif
->bus_state
= state
;
940 /* secondary channel */
944 /* primary channel */
949 /* Grab the status. */
950 pci_read_config_word(dev
, tristate
, &tri_reg
);
951 pci_read_config_byte(dev
, 0x59, &bus_reg
);
954 * Set the state. We don't set it if we don't need to do so.
955 * Make sure that the drive knows that it has failed if it's off.
959 if (!(bus_reg
& resetmask
))
961 hwif
->drives
[0].failures
= hwif
->drives
[1].failures
= 0;
963 pci_write_config_byte(dev
, 0x59, bus_reg
& ~resetmask
);
964 pci_write_config_word(dev
, tristate
, tri_reg
& ~TRISTATE_BIT
);
967 if ((bus_reg
& resetmask
) && !(tri_reg
& TRISTATE_BIT
))
969 tri_reg
&= ~TRISTATE_BIT
;
971 case BUSSTATE_TRISTATE
:
972 if ((bus_reg
& resetmask
) && (tri_reg
& TRISTATE_BIT
))
974 tri_reg
|= TRISTATE_BIT
;
980 hwif
->drives
[0].failures
= hwif
->drives
[0].max_failures
+ 1;
981 hwif
->drives
[1].failures
= hwif
->drives
[1].max_failures
+ 1;
983 pci_write_config_word(dev
, tristate
, tri_reg
);
984 pci_write_config_byte(dev
, 0x59, bus_reg
| resetmask
);
988 static void __devinit
hpt366_clocking(ide_hwif_t
*hwif
)
991 struct hpt_info
*info
= ide_get_hwifdata(hwif
);
993 pci_read_config_dword(hwif
->pci_dev
, 0x40, ®1
);
995 /* detect bus speed by looking at control reg timing: */
996 switch((reg1
>> 8) & 7) {
998 info
->speed
= forty_base_hpt36x
;
1001 info
->speed
= twenty_five_base_hpt36x
;
1005 info
->speed
= thirty_three_base_hpt36x
;
1010 static void __devinit
hpt37x_clocking(ide_hwif_t
*hwif
)
1012 struct hpt_info
*info
= ide_get_hwifdata(hwif
);
1013 struct pci_dev
*dev
= hwif
->pci_dev
;
1017 u8 reg5bh
= 0, mcr1
= 0;
1020 * default to pci clock. make sure MA15/16 are set to output
1021 * to prevent drives having problems with 40-pin cables. Needed
1022 * for some drives such as IBM-DTLA which will not enter ready
1023 * state on reset when PDIAG is a input.
1025 * ToDo: should we set 0x21 when using PLL mode ?
1027 pci_write_config_byte(dev
, 0x5b, 0x23);
1030 * We'll have to read f_CNT value in order to determine
1031 * the PCI clock frequency according to the following ratio:
1033 * f_CNT = Fpci * 192 / Fdpll
1035 * First try reading the register in which the HighPoint BIOS
1036 * saves f_CNT value before reprogramming the DPLL from its
1037 * default setting (which differs for the various chips).
1038 * NOTE: This register is only accessible via I/O space.
1040 * In case the signature check fails, we'll have to resort to
1041 * reading the f_CNT register itself in hopes that nobody has
1042 * touched the DPLL yet...
1044 temp
= inl(pci_resource_start(dev
, 4) + 0x90);
1045 if ((temp
& 0xFFFFF000) != 0xABCDE000) {
1046 printk(KERN_WARNING
"HPT37X: no clock data saved by BIOS\n");
1048 /* Calculate the average value of f_CNT */
1049 for (temp
= i
= 0; i
< 128; i
++) {
1050 pci_read_config_word(dev
, 0x78, &freq
);
1051 temp
+= freq
& 0x1ff;
1056 freq
= temp
& 0x1ff;
1059 * HPT3xxN chips use different PCI clock information.
1060 * Currently we always set up the PLL for them.
1063 if (info
->flags
& IS_3xxN
) {
1066 else if(freq
< 0x70)
1068 else if(freq
< 0x7F)
1073 printk(KERN_INFO
"HPT3xxN detected, FREQ: %d, PLL: %d\n", freq
, pll
);
1079 else if(freq
< 0xb0)
1086 if (pll
== F_LOW_PCI_33
) {
1087 info
->speed
= thirty_three_base_hpt37x
;
1088 printk(KERN_DEBUG
"HPT37X: using 33MHz PCI clock\n");
1089 } else if (pll
== F_LOW_PCI_40
) {
1091 } else if (pll
== F_LOW_PCI_50
) {
1092 info
->speed
= fifty_base_hpt37x
;
1093 printk(KERN_DEBUG
"HPT37X: using 50MHz PCI clock\n");
1095 info
->speed
= sixty_six_base_hpt37x
;
1096 printk(KERN_DEBUG
"HPT37X: using 66MHz PCI clock\n");
1100 if (pll
== F_LOW_PCI_66
)
1101 info
->flags
|= PCI_66MHZ
;
1104 * only try the pll if we don't have a table for the clock
1105 * speed that we're running at. NOTE: the internal PLL will
1106 * result in slow reads when using a 33MHz PCI clock. we also
1107 * don't like to use the PLL because it will cause glitches
1108 * on PRST/SRST when the HPT state engine gets reset.
1110 * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1111 * 372 device so we can get ATA133 support
1114 goto init_hpt37X_done
;
1116 info
->flags
|= PLL_MODE
;
1119 * Adjust the PLL based upon the PCI clock, enable it, and
1120 * wait for stabilization...
1123 freq
= (pll
< F_LOW_PCI_50
) ? 2 : 4;
1124 while (adjust
++ < 6) {
1125 pci_write_config_dword(dev
, 0x5c, (freq
+ pll
) << 16 |
1128 /* wait for clock stabilization */
1129 for (i
= 0; i
< 0x50000; i
++) {
1130 pci_read_config_byte(dev
, 0x5b, ®5bh
);
1131 if (reg5bh
& 0x80) {
1132 /* spin looking for the clock to destabilize */
1133 for (i
= 0; i
< 0x1000; ++i
) {
1134 pci_read_config_byte(dev
, 0x5b,
1136 if ((reg5bh
& 0x80) == 0)
1139 pci_read_config_dword(dev
, 0x5c, &pll
);
1140 pci_write_config_dword(dev
, 0x5c,
1142 pci_write_config_byte(dev
, 0x5b, 0x21);
1144 info
->speed
= fifty_base_hpt37x
;
1145 printk("HPT37X: using 50MHz internal PLL\n");
1146 goto init_hpt37X_done
;
1151 pll
-= (adjust
>> 1);
1153 pll
+= (adjust
>> 1);
1158 printk(KERN_ERR
"HPT37x%s: unknown bus timing [%d %d].\n",
1159 (info
->flags
& IS_3xxN
) ? "N" : "", pll
, freq
);
1161 * Reset the state engines.
1162 * NOTE: avoid accidentally enabling the primary channel on HPT371N.
1164 pci_read_config_byte(dev
, 0x50, &mcr1
);
1166 pci_write_config_byte(dev
, 0x50, 0x37);
1167 pci_write_config_byte(dev
, 0x54, 0x37);
1171 static int __devinit
init_hpt37x(struct pci_dev
*dev
)
1175 pci_read_config_byte(dev
, 0x5a, ®5ah
);
1176 /* interrupt force enable */
1177 pci_write_config_byte(dev
, 0x5a, (reg5ah
& ~0x10));
1181 static int __devinit
init_hpt366(struct pci_dev
*dev
)
1187 * Disable the "fast interrupt" prediction.
1189 pci_read_config_byte(dev
, 0x51, &drive_fast
);
1190 if (drive_fast
& 0x80)
1191 pci_write_config_byte(dev
, 0x51, drive_fast
& ~0x80);
1192 pci_read_config_dword(dev
, 0x40, ®1
);
1197 static unsigned int __devinit
init_chipset_hpt366(struct pci_dev
*dev
, const char *name
)
1202 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1203 * We don't seem to be using it.
1205 if (dev
->resource
[PCI_ROM_RESOURCE
].start
)
1206 pci_write_config_dword(dev
, PCI_ROM_ADDRESS
,
1207 dev
->resource
[PCI_ROM_RESOURCE
].start
| PCI_ROM_ADDRESS_ENABLE
);
1209 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, (L1_CACHE_BYTES
/ 4));
1210 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x78);
1211 pci_write_config_byte(dev
, PCI_MIN_GNT
, 0x08);
1212 pci_write_config_byte(dev
, PCI_MAX_LAT
, 0x08);
1214 if (hpt_revision(dev
) >= 3)
1215 ret
= init_hpt37x(dev
);
1217 ret
= init_hpt366(dev
);
1225 static void __devinit
init_hwif_hpt366(ide_hwif_t
*hwif
)
1227 struct pci_dev
*dev
= hwif
->pci_dev
;
1228 struct hpt_info
*info
= ide_get_hwifdata(hwif
);
1229 u8 ata66
= 0, regmask
= (hwif
->channel
) ? 0x01 : 0x02;
1230 int serialize
= HPT_SERIALIZE_IO
;
1232 hwif
->tuneproc
= &hpt3xx_tune_drive
;
1233 hwif
->speedproc
= &hpt3xx_tune_chipset
;
1234 hwif
->quirkproc
= &hpt3xx_quirkproc
;
1235 hwif
->intrproc
= &hpt3xx_intrproc
;
1236 hwif
->maskproc
= &hpt3xx_maskproc
;
1239 * HPT3xxN chips have some complications:
1241 * - on 33 MHz PCI we must clock switch
1242 * - on 66 MHz PCI we must NOT use the PCI clock
1244 if ((info
->flags
& (IS_3xxN
| PCI_66MHZ
)) == IS_3xxN
) {
1246 * Clock is shared between the channels,
1247 * so we'll have to serialize them... :-(
1250 hwif
->rw_disk
= &hpt3xxn_rw_disk
;
1254 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1255 * address lines to access an external eeprom. To read valid
1256 * cable detect state the pins must be enabled as inputs.
1258 if (info
->revision
>= 8 && (PCI_FUNC(dev
->devfn
) & 1)) {
1260 * HPT374 PCI function 1
1261 * - set bit 15 of reg 0x52 to enable TCBLID as input
1262 * - set bit 15 of reg 0x56 to enable FCBLID as input
1265 pci_read_config_word(dev
, 0x52, &mcr3
);
1266 pci_read_config_word(dev
, 0x56, &mcr6
);
1267 pci_write_config_word(dev
, 0x52, mcr3
| 0x8000);
1268 pci_write_config_word(dev
, 0x56, mcr6
| 0x8000);
1269 /* now read cable id register */
1270 pci_read_config_byte(dev
, 0x5a, &ata66
);
1271 pci_write_config_word(dev
, 0x52, mcr3
);
1272 pci_write_config_word(dev
, 0x56, mcr6
);
1273 } else if (info
->revision
>= 3) {
1275 * HPT370/372 and 374 pcifn 0
1276 * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1279 pci_read_config_byte(dev
, 0x5b, &scr2
);
1280 pci_write_config_byte(dev
, 0x5b, scr2
& ~1);
1281 /* now read cable id register */
1282 pci_read_config_byte(dev
, 0x5a, &ata66
);
1283 pci_write_config_byte(dev
, 0x5b, scr2
);
1285 pci_read_config_byte(dev
, 0x5a, &ata66
);
1289 printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1290 ata66
, (ata66
& regmask
) ? "33" : "66",
1291 PCI_FUNC(hwif
->pci_dev
->devfn
));
1294 /* Serialize access to this device */
1295 if (serialize
&& hwif
->mate
)
1296 hwif
->serialized
= hwif
->mate
->serialized
= 1;
1299 * Set up ioctl for power status.
1300 * NOTE: power affects both drives on each channel.
1302 hwif
->busproc
= &hpt3xx_busproc
;
1304 if (!hwif
->dma_base
) {
1305 hwif
->drives
[0].autotune
= 1;
1306 hwif
->drives
[1].autotune
= 1;
1310 hwif
->ultra_mask
= 0x7f;
1311 hwif
->mwdma_mask
= 0x07;
1313 if (!(hwif
->udma_four
))
1314 hwif
->udma_four
= ((ata66
& regmask
) ? 0 : 1);
1315 hwif
->ide_dma_check
= &hpt366_config_drive_xfer_rate
;
1317 if (info
->revision
>= 8) {
1318 hwif
->ide_dma_test_irq
= &hpt374_ide_dma_test_irq
;
1319 hwif
->ide_dma_end
= &hpt374_ide_dma_end
;
1320 } else if (info
->revision
>= 5) {
1321 hwif
->ide_dma_test_irq
= &hpt374_ide_dma_test_irq
;
1322 hwif
->ide_dma_end
= &hpt374_ide_dma_end
;
1323 } else if (info
->revision
>= 3) {
1324 hwif
->dma_start
= &hpt370_ide_dma_start
;
1325 hwif
->ide_dma_end
= &hpt370_ide_dma_end
;
1326 hwif
->ide_dma_timeout
= &hpt370_ide_dma_timeout
;
1327 hwif
->ide_dma_lostirq
= &hpt370_ide_dma_lostirq
;
1328 } else if (info
->revision
>= 2)
1329 hwif
->ide_dma_lostirq
= &hpt366_ide_dma_lostirq
;
1331 hwif
->ide_dma_lostirq
= &hpt366_ide_dma_lostirq
;
1335 hwif
->drives
[0].autodma
= hwif
->autodma
;
1336 hwif
->drives
[1].autodma
= hwif
->autodma
;
1339 static void __devinit
init_dma_hpt366(ide_hwif_t
*hwif
, unsigned long dmabase
)
1341 struct hpt_info
*info
= ide_get_hwifdata(hwif
);
1342 u8 masterdma
= 0, slavedma
= 0;
1343 u8 dma_new
= 0, dma_old
= 0;
1344 u8 primary
= hwif
->channel
? 0x4b : 0x43;
1345 u8 secondary
= hwif
->channel
? 0x4f : 0x47;
1346 unsigned long flags
;
1351 if(info
->speed
== NULL
) {
1352 printk(KERN_WARNING
"hpt366: no known IDE timings, disabling DMA.\n");
1356 dma_old
= hwif
->INB(dmabase
+2);
1358 local_irq_save(flags
);
1361 pci_read_config_byte(hwif
->pci_dev
, primary
, &masterdma
);
1362 pci_read_config_byte(hwif
->pci_dev
, secondary
, &slavedma
);
1364 if (masterdma
& 0x30) dma_new
|= 0x20;
1365 if (slavedma
& 0x30) dma_new
|= 0x40;
1366 if (dma_new
!= dma_old
)
1367 hwif
->OUTB(dma_new
, dmabase
+2);
1369 local_irq_restore(flags
);
1371 ide_setup_dma(hwif
, dmabase
, 8);
1375 * We "borrow" this hook in order to set the data structures
1376 * up early enough before dma or init_hwif calls are made.
1379 static void __devinit
init_iops_hpt366(ide_hwif_t
*hwif
)
1381 struct hpt_info
*info
= kzalloc(sizeof(struct hpt_info
), GFP_KERNEL
);
1382 struct pci_dev
*dev
= hwif
->pci_dev
;
1383 u16 did
= dev
->device
;
1387 printk(KERN_WARNING
"hpt366: out of memory.\n");
1390 ide_set_hwifdata(hwif
, info
);
1392 /* Avoid doing the same thing twice. */
1393 if (hwif
->channel
&& hwif
->mate
) {
1394 memcpy(info
, ide_get_hwifdata(hwif
->mate
), sizeof(struct hpt_info
));
1398 pci_read_config_byte(dev
, PCI_CLASS_REVISION
, &rid
);
1400 if (( did
== PCI_DEVICE_ID_TTI_HPT366
&& rid
== 6) ||
1401 ((did
== PCI_DEVICE_ID_TTI_HPT372
||
1402 did
== PCI_DEVICE_ID_TTI_HPT302
||
1403 did
== PCI_DEVICE_ID_TTI_HPT371
) && rid
> 1) ||
1404 did
== PCI_DEVICE_ID_TTI_HPT372N
)
1405 info
->flags
|= IS_3xxN
;
1407 info
->revision
= hpt_revision(dev
);
1409 if (info
->revision
>= 3)
1410 hpt37x_clocking(hwif
);
1412 hpt366_clocking(hwif
);
1415 static int __devinit
init_setup_hpt374(struct pci_dev
*dev
, ide_pci_device_t
*d
)
1417 struct pci_dev
*findev
= NULL
;
1419 if (PCI_FUNC(dev
->devfn
) & 1)
1422 while ((findev
= pci_find_device(PCI_ANY_ID
, PCI_ANY_ID
, findev
)) != NULL
) {
1423 if ((findev
->vendor
== dev
->vendor
) &&
1424 (findev
->device
== dev
->device
) &&
1425 ((findev
->devfn
- dev
->devfn
) == 1) &&
1426 (PCI_FUNC(findev
->devfn
) & 1)) {
1427 if (findev
->irq
!= dev
->irq
) {
1428 /* FIXME: we need a core pci_set_interrupt() */
1429 findev
->irq
= dev
->irq
;
1430 printk(KERN_WARNING
"%s: pci-config space interrupt "
1431 "fixed.\n", d
->name
);
1433 return ide_setup_pci_devices(dev
, findev
, d
);
1436 return ide_setup_pci_device(dev
, d
);
1439 static int __devinit
init_setup_hpt37x(struct pci_dev
*dev
, ide_pci_device_t
*d
)
1441 return ide_setup_pci_device(dev
, d
);
1444 static int __devinit
init_setup_hpt371(struct pci_dev
*dev
, ide_pci_device_t
*d
)
1449 * HPT371 chips physically have only one channel, the secondary one,
1450 * but the primary channel registers do exist! Go figure...
1451 * So, we manually disable the non-existing channel here
1452 * (if the BIOS hasn't done this already).
1454 pci_read_config_byte(dev
, 0x50, &mcr1
);
1456 pci_write_config_byte(dev
, 0x50, (mcr1
& ~0x04));
1458 return ide_setup_pci_device(dev
, d
);
1461 static int __devinit
init_setup_hpt366(struct pci_dev
*dev
, ide_pci_device_t
*d
)
1463 struct pci_dev
*findev
= NULL
;
1464 u8 pin1
= 0, pin2
= 0;
1465 unsigned int class_rev
;
1466 char *chipset_names
[] = {"HPT366", "HPT366", "HPT368",
1467 "HPT370", "HPT370A", "HPT372",
1470 if (PCI_FUNC(dev
->devfn
) & 1)
1473 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
1476 if(dev
->device
== PCI_DEVICE_ID_TTI_HPT372N
)
1480 d
->name
= chipset_names
[class_rev
];
1494 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin1
);
1495 while ((findev
= pci_find_device(PCI_ANY_ID
, PCI_ANY_ID
, findev
)) != NULL
) {
1496 if ((findev
->vendor
== dev
->vendor
) &&
1497 (findev
->device
== dev
->device
) &&
1498 ((findev
->devfn
- dev
->devfn
) == 1) &&
1499 (PCI_FUNC(findev
->devfn
) & 1)) {
1500 pci_read_config_byte(findev
, PCI_INTERRUPT_PIN
, &pin2
);
1501 if ((pin1
!= pin2
) && (dev
->irq
== findev
->irq
)) {
1502 d
->bootable
= ON_BOARD
;
1503 printk("%s: onboard version of chipset, "
1504 "pin1=%d pin2=%d\n", d
->name
,
1507 return ide_setup_pci_devices(dev
, findev
, d
);
1511 return ide_setup_pci_device(dev
, d
);
1514 static ide_pci_device_t hpt366_chipsets
[] __devinitdata
= {
1517 .init_setup
= init_setup_hpt366
,
1518 .init_chipset
= init_chipset_hpt366
,
1519 .init_iops
= init_iops_hpt366
,
1520 .init_hwif
= init_hwif_hpt366
,
1521 .init_dma
= init_dma_hpt366
,
1524 .bootable
= OFF_BOARD
,
1528 .init_setup
= init_setup_hpt37x
,
1529 .init_chipset
= init_chipset_hpt366
,
1530 .init_iops
= init_iops_hpt366
,
1531 .init_hwif
= init_hwif_hpt366
,
1532 .init_dma
= init_dma_hpt366
,
1535 .bootable
= OFF_BOARD
,
1538 .init_setup
= init_setup_hpt37x
,
1539 .init_chipset
= init_chipset_hpt366
,
1540 .init_iops
= init_iops_hpt366
,
1541 .init_hwif
= init_hwif_hpt366
,
1542 .init_dma
= init_dma_hpt366
,
1545 .bootable
= OFF_BOARD
,
1548 .init_setup
= init_setup_hpt371
,
1549 .init_chipset
= init_chipset_hpt366
,
1550 .init_iops
= init_iops_hpt366
,
1551 .init_hwif
= init_hwif_hpt366
,
1552 .init_dma
= init_dma_hpt366
,
1555 .enablebits
= {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1556 .bootable
= OFF_BOARD
,
1559 .init_setup
= init_setup_hpt374
,
1560 .init_chipset
= init_chipset_hpt366
,
1561 .init_iops
= init_iops_hpt366
,
1562 .init_hwif
= init_hwif_hpt366
,
1563 .init_dma
= init_dma_hpt366
,
1564 .channels
= 2, /* 4 */
1566 .bootable
= OFF_BOARD
,
1569 .init_setup
= init_setup_hpt37x
,
1570 .init_chipset
= init_chipset_hpt366
,
1571 .init_iops
= init_iops_hpt366
,
1572 .init_hwif
= init_hwif_hpt366
,
1573 .init_dma
= init_dma_hpt366
,
1574 .channels
= 2, /* 4 */
1576 .bootable
= OFF_BOARD
,
1581 * hpt366_init_one - called when an HPT366 is found
1582 * @dev: the hpt366 device
1583 * @id: the matching pci id
1585 * Called when the PCI registration layer (or the IDE initialization)
1586 * finds a device matching our IDE device tables.
1588 * NOTE: since we'll have to modify some fields of the ide_pci_device_t
1589 * structure depending on the chip's revision, we'd better pass a local
1590 * copy down the call chain...
1592 static int __devinit
hpt366_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
1594 ide_pci_device_t d
= hpt366_chipsets
[id
->driver_data
];
1596 return d
.init_setup(dev
, &d
);
1599 static struct pci_device_id hpt366_pci_tbl
[] = {
1600 { PCI_VENDOR_ID_TTI
, PCI_DEVICE_ID_TTI_HPT366
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1601 { PCI_VENDOR_ID_TTI
, PCI_DEVICE_ID_TTI_HPT372
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 1},
1602 { PCI_VENDOR_ID_TTI
, PCI_DEVICE_ID_TTI_HPT302
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 2},
1603 { PCI_VENDOR_ID_TTI
, PCI_DEVICE_ID_TTI_HPT371
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 3},
1604 { PCI_VENDOR_ID_TTI
, PCI_DEVICE_ID_TTI_HPT374
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 4},
1605 { PCI_VENDOR_ID_TTI
, PCI_DEVICE_ID_TTI_HPT372N
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 5},
1608 MODULE_DEVICE_TABLE(pci
, hpt366_pci_tbl
);
1610 static struct pci_driver driver
= {
1611 .name
= "HPT366_IDE",
1612 .id_table
= hpt366_pci_tbl
,
1613 .probe
= hpt366_init_one
,
1616 static int __init
hpt366_ide_init(void)
1618 return ide_pci_register_driver(&driver
);
1621 module_init(hpt366_ide_init
);
1623 MODULE_AUTHOR("Andre Hedrick");
1624 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1625 MODULE_LICENSE("GPL");