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Linux 2.6.20.7
[linux/fpc-iii.git] / drivers / ide / pci / pdc202xx_new.c
blob77a9aaa7dab988377b78df4a86829e543c4b1f93
1 /*
2 * Promise TX2/TX4/TX2000/133 IDE driver
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Split from:
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2005-2006 MontaVista Software, Inc.
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * Author: Frank Tiernan (frankt@promise.com)
15 * Released under terms of General Public License
16 */
17
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/timer.h>
23 #include <linux/mm.h>
24 #include <linux/ioport.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/ide.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34
35 #ifdef CONFIG_PPC_PMAC
36 #include <asm/prom.h>
37 #include <asm/pci-bridge.h>
38 #endif
39
40 #define PDC202_DEBUG_CABLE 0
41
42 #undef DEBUG
43
44 #ifdef DEBUG
45 #define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
46 #else
47 #define DBG(fmt, args...)
48 #endif
49
50 static const char *pdc_quirk_drives[] = {
51 "QUANTUM FIREBALLlct08 08",
52 "QUANTUM FIREBALLP KA6.4",
53 "QUANTUM FIREBALLP KA9.1",
54 "QUANTUM FIREBALLP LM20.4",
55 "QUANTUM FIREBALLP KX13.6",
56 "QUANTUM FIREBALLP KX20.5",
57 "QUANTUM FIREBALLP KX27.3",
58 "QUANTUM FIREBALLP LM20.5",
59 NULL
60 };
61
62 static u8 max_dma_rate(struct pci_dev *pdev)
63 {
64 u8 mode;
65
66 switch(pdev->device) {
67 case PCI_DEVICE_ID_PROMISE_20277:
68 case PCI_DEVICE_ID_PROMISE_20276:
69 case PCI_DEVICE_ID_PROMISE_20275:
70 case PCI_DEVICE_ID_PROMISE_20271:
71 case PCI_DEVICE_ID_PROMISE_20269:
72 mode = 4;
73 break;
74 case PCI_DEVICE_ID_PROMISE_20270:
75 case PCI_DEVICE_ID_PROMISE_20268:
76 mode = 3;
77 break;
78 default:
79 return 0;
80 }
81
82 return mode;
83 }
84
85 static u8 pdcnew_ratemask(ide_drive_t *drive)
86 {
87 u8 mode = max_dma_rate(HWIF(drive)->pci_dev);
88
89 if (!eighty_ninty_three(drive))
90 mode = min_t(u8, mode, 1);
91
92 return mode;
93 }
94
95 static int check_in_drive_lists(ide_drive_t *drive, const char **list)
96 {
97 struct hd_driveid *id = drive->id;
98
99 if (pdc_quirk_drives == list) {
100 while (*list) {
101 if (strstr(id->model, *list++)) {
102 return 2;
103 }
104 }
105 } else {
106 while (*list) {
107 if (!strcmp(*list++,id->model)) {
108 return 1;
109 }
110 }
111 }
112 return 0;
113 }
114
115 /**
116 * get_indexed_reg - Get indexed register
117 * @hwif: for the port address
118 * @index: index of the indexed register
119 */
120 static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
121 {
122 u8 value;
123
124 hwif->OUTB(index, hwif->dma_vendor1);
125 value = hwif->INB(hwif->dma_vendor3);
126
127 DBG("index[%02X] value[%02X]\n", index, value);
128 return value;
129 }
130
131 /**
132 * set_indexed_reg - Set indexed register
133 * @hwif: for the port address
134 * @index: index of the indexed register
135 */
136 static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
137 {
138 hwif->OUTB(index, hwif->dma_vendor1);
139 hwif->OUTB(value, hwif->dma_vendor3);
140 DBG("index[%02X] value[%02X]\n", index, value);
141 }
142
143 /*
144 * ATA Timing Tables based on 133 MHz PLL output clock.
145 *
146 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
147 * the timing registers automatically when "set features" command is
148 * issued to the device. However, if the PLL output clock is 133 MHz,
149 * the following tables must be used.
150 */
151 static struct pio_timing {
152 u8 reg0c, reg0d, reg13;
153 } pio_timings [] = {
154 { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
155 { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
156 { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
157 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
158 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
159 };
160
161 static struct mwdma_timing {
162 u8 reg0e, reg0f;
163 } mwdma_timings [] = {
164 { 0xdf, 0x5f }, /* MWDMA mode 0 */
165 { 0x6b, 0x27 }, /* MWDMA mode 1 */
166 { 0x69, 0x25 }, /* MWDMA mode 2 */
167 };
168
169 static struct udma_timing {
170 u8 reg10, reg11, reg12;
171 } udma_timings [] = {
172 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
173 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
174 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
175 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
176 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
177 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
178 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
179 };
180
181 static int pdcnew_tune_chipset(ide_drive_t *drive, u8 speed)
182 {
183 ide_hwif_t *hwif = HWIF(drive);
184 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
185 int err;
186
187 speed = ide_rate_filter(pdcnew_ratemask(drive), speed);
188
189 /*
190 * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
191 * automatically set the timing registers based on 100 MHz PLL output.
192 */
193 err = ide_config_drive_speed(drive, speed);
194
195 /*
196 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
197 * chips, we must override the default register settings...
198 */
199 if (max_dma_rate(hwif->pci_dev) == 4) {
200 u8 mode = speed & 0x07;
201
202 switch (speed) {
203 case XFER_UDMA_6:
204 case XFER_UDMA_5:
205 case XFER_UDMA_4:
206 case XFER_UDMA_3:
207 case XFER_UDMA_2:
208 case XFER_UDMA_1:
209 case XFER_UDMA_0:
210 set_indexed_reg(hwif, 0x10 + adj,
211 udma_timings[mode].reg10);
212 set_indexed_reg(hwif, 0x11 + adj,
213 udma_timings[mode].reg11);
214 set_indexed_reg(hwif, 0x12 + adj,
215 udma_timings[mode].reg12);
216 break;
217
218 case XFER_MW_DMA_2:
219 case XFER_MW_DMA_1:
220 case XFER_MW_DMA_0:
221 set_indexed_reg(hwif, 0x0e + adj,
222 mwdma_timings[mode].reg0e);
223 set_indexed_reg(hwif, 0x0f + adj,
224 mwdma_timings[mode].reg0f);
225 break;
226 case XFER_PIO_4:
227 case XFER_PIO_3:
228 case XFER_PIO_2:
229 case XFER_PIO_1:
230 case XFER_PIO_0:
231 set_indexed_reg(hwif, 0x0c + adj,
232 pio_timings[mode].reg0c);
233 set_indexed_reg(hwif, 0x0d + adj,
234 pio_timings[mode].reg0d);
235 set_indexed_reg(hwif, 0x13 + adj,
236 pio_timings[mode].reg13);
237 break;
238 default:
239 printk(KERN_ERR "pdc202xx_new: "
240 "Unknown speed %d ignored\n", speed);
241 }
242 } else if (speed == XFER_UDMA_2) {
243 /* Set tHOLD bit to 0 if using UDMA mode 2 */
244 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
245
246 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
247 }
248
249 return err;
250 }
251
252 /* 0 1 2 3 4 5 6 7 8
253 * 960, 480, 390, 300, 240, 180, 120, 90, 60
254 * 180, 150, 120, 90, 60
255 * DMA_Speed
256 * 180, 120, 90, 90, 90, 60, 30
257 * 11, 5, 4, 3, 2, 1, 0
258 */
259 static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
260 {
261 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
262 (void)pdcnew_tune_chipset(drive, XFER_PIO_0 + pio);
263 }
264
265 static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
266 {
267 return get_indexed_reg(hwif, 0x0b) & 0x04;
268 }
269
270 static int config_chipset_for_dma(ide_drive_t *drive)
271 {
272 struct hd_driveid *id = drive->id;
273 ide_hwif_t *hwif = HWIF(drive);
274 u8 ultra_66 = (id->dma_ultra & 0x0078) ? 1 : 0;
275 u8 cable = pdcnew_cable_detect(hwif);
276 u8 speed;
277
278 if (ultra_66 && cable) {
279 printk(KERN_WARNING "Warning: %s channel "
280 "requires an 80-pin cable for operation.\n",
281 hwif->channel ? "Secondary" : "Primary");
282 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
283 }
284
285 if (drive->media != ide_disk)
286 return 0;
287
288 if (id->capability & 4) {
289 /*
290 * Set IORDY_EN & PREFETCH_EN (this seems to have
291 * NO real effect since this register is reloaded
292 * by hardware when the transfer mode is selected)
293 */
294 u8 tmp, adj = (drive->dn & 1) ? 0x08 : 0x00;
295
296 tmp = get_indexed_reg(hwif, 0x13 + adj);
297 set_indexed_reg(hwif, 0x13 + adj, tmp | 0x03);
298 }
299
300 speed = ide_dma_speed(drive, pdcnew_ratemask(drive));
301
302 if (!speed)
303 return 0;
304
305 (void) hwif->speedproc(drive, speed);
306 return ide_dma_enable(drive);
307 }
308
309 static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
310 {
311 ide_hwif_t *hwif = HWIF(drive);
312 struct hd_driveid *id = drive->id;
313
314 drive->init_speed = 0;
315
316 if (id && (id->capability & 1) && drive->autodma) {
317
318 if (ide_use_dma(drive)) {
319 if (config_chipset_for_dma(drive))
320 return hwif->ide_dma_on(drive);
321 }
322
323 goto fast_ata_pio;
324
325 } else if ((id->capability & 8) || (id->field_valid & 2)) {
326 fast_ata_pio:
327 hwif->tuneproc(drive, 255);
328 return hwif->ide_dma_off_quietly(drive);
329 }
330 /* IORDY not supported */
331 return 0;
332 }
333
334 static int pdcnew_quirkproc(ide_drive_t *drive)
335 {
336 return check_in_drive_lists(drive, pdc_quirk_drives);
337 }
338
339 static int pdcnew_ide_dma_lostirq(ide_drive_t *drive)
340 {
341 if (HWIF(drive)->resetproc != NULL)
342 HWIF(drive)->resetproc(drive);
343 return __ide_dma_lostirq(drive);
344 }
345
346 static int pdcnew_ide_dma_timeout(ide_drive_t *drive)
347 {
348 if (HWIF(drive)->resetproc != NULL)
349 HWIF(drive)->resetproc(drive);
350 return __ide_dma_timeout(drive);
351 }
352
353 static void pdcnew_reset(ide_drive_t *drive)
354 {
355 /*
356 * Deleted this because it is redundant from the caller.
357 */
358 printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
359 HWIF(drive)->channel ? "Secondary" : "Primary");
360 }
361
362 /**
363 * read_counter - Read the byte count registers
364 * @dma_base: for the port address
365 */
366 static long __devinit read_counter(u32 dma_base)
367 {
368 u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
369 u8 cnt0, cnt1, cnt2, cnt3;
370 long count = 0, last;
371 int retry = 3;
372
373 do {
374 last = count;
375
376 /* Read the current count */
377 outb(0x20, pri_dma_base + 0x01);
378 cnt0 = inb(pri_dma_base + 0x03);
379 outb(0x21, pri_dma_base + 0x01);
380 cnt1 = inb(pri_dma_base + 0x03);
381 outb(0x20, sec_dma_base + 0x01);
382 cnt2 = inb(sec_dma_base + 0x03);
383 outb(0x21, sec_dma_base + 0x01);
384 cnt3 = inb(sec_dma_base + 0x03);
385
386 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
387
388 /*
389 * The 30-bit decrementing counter is read in 4 pieces.
390 * Incorrect value may be read when the most significant bytes
391 * are changing...
392 */
393 } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
394
395 DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
396 cnt0, cnt1, cnt2, cnt3);
397
398 return count;
399 }
400
401 /**
402 * detect_pll_input_clock - Detect the PLL input clock in Hz.
403 * @dma_base: for the port address
404 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
405 */
406 static long __devinit detect_pll_input_clock(unsigned long dma_base)
407 {
408 long start_count, end_count;
409 long pll_input;
410 u8 scr1;
411
412 start_count = read_counter(dma_base);
413
414 /* Start the test mode */
415 outb(0x01, dma_base + 0x01);
416 scr1 = inb(dma_base + 0x03);
417 DBG("scr1[%02X]\n", scr1);
418 outb(scr1 | 0x40, dma_base + 0x03);
419
420 /* Let the counter run for 10 ms. */
421 mdelay(10);
422
423 end_count = read_counter(dma_base);
424
425 /* Stop the test mode */
426 outb(0x01, dma_base + 0x01);
427 scr1 = inb(dma_base + 0x03);
428 DBG("scr1[%02X]\n", scr1);
429 outb(scr1 & ~0x40, dma_base + 0x03);
430
431 /*
432 * Calculate the input clock in Hz
433 * (the clock counter is 30 bit wide and counts down)
434 */
435 pll_input = ((start_count - end_count) & 0x3ffffff) * 100;
436
437 DBG("start[%ld] end[%ld]\n", start_count, end_count);
438
439 return pll_input;
440 }
441
442 #ifdef CONFIG_PPC_PMAC
443 static void __devinit apple_kiwi_init(struct pci_dev *pdev)
444 {
445 struct device_node *np = pci_device_to_OF_node(pdev);
446 unsigned int class_rev = 0;
447 u8 conf;
448
449 if (np == NULL || !device_is_compatible(np, "kiwi-root"))
450 return;
451
452 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
453 class_rev &= 0xff;
454
455 if (class_rev >= 0x03) {
456 /* Setup chip magic config stuff (from darwin) */
457 pci_read_config_byte (pdev, 0x40, &conf);
458 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
459 }
460 }
461 #endif /* CONFIG_PPC_PMAC */
462
463 static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
464 {
465 unsigned long dma_base = pci_resource_start(dev, 4);
466 unsigned long sec_dma_base = dma_base + 0x08;
467 long pll_input, pll_output, ratio;
468 int f, r;
469 u8 pll_ctl0, pll_ctl1;
470
471 if (dev->resource[PCI_ROM_RESOURCE].start) {
472 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
473 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
474 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
475 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
476 }
477
478 #ifdef CONFIG_PPC_PMAC
479 apple_kiwi_init(dev);
480 #endif
481
482 /* Calculate the required PLL output frequency */
483 switch(max_dma_rate(dev)) {
484 case 4: /* it's 133 MHz for Ultra133 chips */
485 pll_output = 133333333;
486 break;
487 case 3: /* and 100 MHz for Ultra100 chips */
488 default:
489 pll_output = 100000000;
490 break;
491 }
492
493 /*
494 * Detect PLL input clock.
495 * On some systems, where PCI bus is running at non-standard clock rate
496 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
497 * PDC20268 and newer chips employ PLL circuit to help correct timing
498 * registers setting.
499 */
500 pll_input = detect_pll_input_clock(dma_base);
501 printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
502
503 /* Sanity check */
504 if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
505 printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
506 name, pll_input);
507 goto out;
508 }
509
510 #ifdef DEBUG
511 DBG("pll_output is %ld Hz\n", pll_output);
512
513 /* Show the current clock value of PLL control register
514 * (maybe already configured by the BIOS)
515 */
516 outb(0x02, sec_dma_base + 0x01);
517 pll_ctl0 = inb(sec_dma_base + 0x03);
518 outb(0x03, sec_dma_base + 0x01);
519 pll_ctl1 = inb(sec_dma_base + 0x03);
520
521 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
522 #endif
523
524 /*
525 * Calculate the ratio of F, R and NO
526 * POUT = (F + 2) / (( R + 2) * NO)
527 */
528 ratio = pll_output / (pll_input / 1000);
529 if (ratio < 8600L) { /* 8.6x */
530 /* Using NO = 0x01, R = 0x0d */
531 r = 0x0d;
532 } else if (ratio < 12900L) { /* 12.9x */
533 /* Using NO = 0x01, R = 0x08 */
534 r = 0x08;
535 } else if (ratio < 16100L) { /* 16.1x */
536 /* Using NO = 0x01, R = 0x06 */
537 r = 0x06;
538 } else if (ratio < 64000L) { /* 64x */
539 r = 0x00;
540 } else {
541 /* Invalid ratio */
542 printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
543 goto out;
544 }
545
546 f = (ratio * (r + 2)) / 1000 - 2;
547
548 DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
549
550 if (unlikely(f < 0 || f > 127)) {
551 /* Invalid F */
552 printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
553 goto out;
554 }
555
556 pll_ctl0 = (u8) f;
557 pll_ctl1 = (u8) r;
558
559 DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
560
561 outb(0x02, sec_dma_base + 0x01);
562 outb(pll_ctl0, sec_dma_base + 0x03);
563 outb(0x03, sec_dma_base + 0x01);
564 outb(pll_ctl1, sec_dma_base + 0x03);
565
566 /* Wait the PLL circuit to be stable */
567 mdelay(30);
568
569 #ifdef DEBUG
570 /*
571 * Show the current clock value of PLL control register
572 */
573 outb(0x02, sec_dma_base + 0x01);
574 pll_ctl0 = inb(sec_dma_base + 0x03);
575 outb(0x03, sec_dma_base + 0x01);
576 pll_ctl1 = inb(sec_dma_base + 0x03);
577
578 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
579 #endif
580
581 out:
582 return dev->irq;
583 }
584
585 static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
586 {
587 hwif->autodma = 0;
588
589 hwif->tuneproc = &pdcnew_tune_drive;
590 hwif->quirkproc = &pdcnew_quirkproc;
591 hwif->speedproc = &pdcnew_tune_chipset;
592 hwif->resetproc = &pdcnew_reset;
593
594 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
595
596 hwif->ultra_mask = 0x7f;
597 hwif->mwdma_mask = 0x07;
598
599 hwif->err_stops_fifo = 1;
600
601 hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
602 hwif->ide_dma_lostirq = &pdcnew_ide_dma_lostirq;
603 hwif->ide_dma_timeout = &pdcnew_ide_dma_timeout;
604
605 if (!hwif->udma_four)
606 hwif->udma_four = pdcnew_cable_detect(hwif) ? 0 : 1;
607
608 if (!noautodma)
609 hwif->autodma = 1;
610 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
611
612 #if PDC202_DEBUG_CABLE
613 printk(KERN_DEBUG "%s: %s-pin cable\n",
614 hwif->name, hwif->udma_four ? "80" : "40");
615 #endif /* PDC202_DEBUG_CABLE */
616 }
617
618 static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
619 {
620 return ide_setup_pci_device(dev, d);
621 }
622
623 static int __devinit init_setup_pdc20270(struct pci_dev *dev,
624 ide_pci_device_t *d)
625 {
626 struct pci_dev *findev = NULL;
627 int ret;
628
629 if ((dev->bus->self &&
630 dev->bus->self->vendor == PCI_VENDOR_ID_DEC) &&
631 (dev->bus->self->device == PCI_DEVICE_ID_DEC_21150)) {
632 if (PCI_SLOT(dev->devfn) & 2)
633 return -ENODEV;
634 d->extra = 0;
635 while ((findev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
636 if ((findev->vendor == dev->vendor) &&
637 (findev->device == dev->device) &&
638 (PCI_SLOT(findev->devfn) & 2)) {
639 if (findev->irq != dev->irq) {
640 findev->irq = dev->irq;
641 }
642 ret = ide_setup_pci_devices(dev, findev, d);
643 pci_dev_put(findev);
644 return ret;
645 }
646 }
647 }
648 return ide_setup_pci_device(dev, d);
649 }
650
651 static int __devinit init_setup_pdc20276(struct pci_dev *dev,
652 ide_pci_device_t *d)
653 {
654 if ((dev->bus->self) &&
655 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
656 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
657 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
658 printk(KERN_INFO "ide: Skipping Promise PDC20276 "
659 "attached to I2O RAID controller.\n");
660 return -ENODEV;
661 }
662 return ide_setup_pci_device(dev, d);
663 }
664
665 static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
666 { /* 0 */
667 .name = "PDC20268",
668 .init_setup = init_setup_pdcnew,
669 .init_chipset = init_chipset_pdcnew,
670 .init_hwif = init_hwif_pdc202new,
671 .channels = 2,
672 .autodma = AUTODMA,
673 .bootable = OFF_BOARD,
674 },{ /* 1 */
675 .name = "PDC20269",
676 .init_setup = init_setup_pdcnew,
677 .init_chipset = init_chipset_pdcnew,
678 .init_hwif = init_hwif_pdc202new,
679 .channels = 2,
680 .autodma = AUTODMA,
681 .bootable = OFF_BOARD,
682 },{ /* 2 */
683 .name = "PDC20270",
684 .init_setup = init_setup_pdc20270,
685 .init_chipset = init_chipset_pdcnew,
686 .init_hwif = init_hwif_pdc202new,
687 .channels = 2,
688 .autodma = AUTODMA,
689 .bootable = OFF_BOARD,
690 },{ /* 3 */
691 .name = "PDC20271",
692 .init_setup = init_setup_pdcnew,
693 .init_chipset = init_chipset_pdcnew,
694 .init_hwif = init_hwif_pdc202new,
695 .channels = 2,
696 .autodma = AUTODMA,
697 .bootable = OFF_BOARD,
698 },{ /* 4 */
699 .name = "PDC20275",
700 .init_setup = init_setup_pdcnew,
701 .init_chipset = init_chipset_pdcnew,
702 .init_hwif = init_hwif_pdc202new,
703 .channels = 2,
704 .autodma = AUTODMA,
705 .bootable = OFF_BOARD,
706 },{ /* 5 */
707 .name = "PDC20276",
708 .init_setup = init_setup_pdc20276,
709 .init_chipset = init_chipset_pdcnew,
710 .init_hwif = init_hwif_pdc202new,
711 .channels = 2,
712 .autodma = AUTODMA,
713 .bootable = OFF_BOARD,
714 },{ /* 6 */
715 .name = "PDC20277",
716 .init_setup = init_setup_pdcnew,
717 .init_chipset = init_chipset_pdcnew,
718 .init_hwif = init_hwif_pdc202new,
719 .channels = 2,
720 .autodma = AUTODMA,
721 .bootable = OFF_BOARD,
722 }
723 };
724
725 /**
726 * pdc202new_init_one - called when a pdc202xx is found
727 * @dev: the pdc202new device
728 * @id: the matching pci id
729 *
730 * Called when the PCI registration layer (or the IDE initialization)
731 * finds a device matching our IDE device tables.
732 */
733
734 static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
735 {
736 ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
737
738 return d->init_setup(dev, d);
739 }
740
741 static struct pci_device_id pdc202new_pci_tbl[] = {
742 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
743 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
744 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
745 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
746 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
747 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
748 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
749 { 0, },
750 };
751 MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
752
753 static struct pci_driver driver = {
754 .name = "Promise_IDE",
755 .id_table = pdc202new_pci_tbl,
756 .probe = pdc202new_init_one,
757 };
758
759 static int __init pdc202new_ide_init(void)
760 {
761 return ide_pci_register_driver(&driver);
762 }
763
764 module_init(pdc202new_ide_init);
765
766 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
767 MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
768 MODULE_LICENSE("GPL");
Linux with added FPC-III support