drivers/ide/pci/siimage.c

   1 /*
   2  * linux/drivers/ide/pci/siimage.c              Version 1.07    Nov 30, 2003
   3  *
   4  * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2003           Red Hat <alan@redhat.com>
   6  *
   7  *  May be copied or modified under the terms of the GNU General Public License
   8  *
   9  *  Documentation for CMD680:
  10  *  http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
  11  *
  12  *  Documentation for SiI 3112:
  13  *  http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
  14  *
  15  *  Errata and other documentation only available under NDA.
  16  *
  17  *
  18  *  FAQ Items:
  19  *      If you are using Marvell SATA-IDE adapters with Maxtor drives
  20  *      ensure the system is set up for ATA100/UDMA5 not UDMA6.
  21  *
  22  *      If you are using WD drives with SATA bridges you must set the
  23  *      drive to "Single". "Master" will hang
  24  *
  25  *      If you have strange problems with nVidia chipset systems please
  26  *      see the SI support documentation and update your system BIOS
  27  *      if neccessary
  28  */
  29
  30 #include <linux/types.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/delay.h>
  34 #include <linux/hdreg.h>
  35 #include <linux/ide.h>
  36 #include <linux/init.h>
  37
  38 #include <asm/io.h>
  39
  40 /**
  41  *      pdev_is_sata            -       check if device is SATA
  42  *      @pdev:  PCI device to check
  43  *
  44  *      Returns true if this is a SATA controller
  45  */
  46
  47 static int pdev_is_sata(struct pci_dev *pdev)
  48 {
  49         switch(pdev->device)
  50         {
  51                 case PCI_DEVICE_ID_SII_3112:
  52                 case PCI_DEVICE_ID_SII_1210SA:
  53                         return 1;
  54                 case PCI_DEVICE_ID_SII_680:
  55                         return 0;
  56         }
  57         BUG();
  58         return 0;
  59 }
  60
  61 /**
  62  *      is_sata                 -       check if hwif is SATA
  63  *      @hwif:  interface to check
  64  *
  65  *      Returns true if this is a SATA controller
  66  */
  67
  68 static inline int is_sata(ide_hwif_t *hwif)
  69 {
  70         return pdev_is_sata(hwif->pci_dev);
  71 }
  72
  73 /**
  74  *      siimage_selreg          -       return register base
  75  *      @hwif: interface
  76  *      @r: config offset
  77  *
  78  *      Turn a config register offset into the right address in either
  79  *      PCI space or MMIO space to access the control register in question
  80  *      Thankfully this is a configuration operation so isnt performance
  81  *      criticial.
  82  */
  83
  84 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
  85 {
  86         unsigned long base = (unsigned long)hwif->hwif_data;
  87         base += 0xA0 + r;
  88         if(hwif->mmio)
  89                 base += (hwif->channel << 6);
  90         else
  91                 base += (hwif->channel << 4);
  92         return base;
  93 }
  94
  95 /**
  96  *      siimage_seldev          -       return register base
  97  *      @hwif: interface
  98  *      @r: config offset
  99  *
 100  *      Turn a config register offset into the right address in either
 101  *      PCI space or MMIO space to access the control register in question
 102  *      including accounting for the unit shift.
 103  */
 104
 105 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
 106 {
 107         ide_hwif_t *hwif        = HWIF(drive);
 108         unsigned long base = (unsigned long)hwif->hwif_data;
 109         base += 0xA0 + r;
 110         if(hwif->mmio)
 111                 base += (hwif->channel << 6);
 112         else
 113                 base += (hwif->channel << 4);
 114         base |= drive->select.b.unit << drive->select.b.unit;
 115         return base;
 116 }
 117
 118 /**
 119  *      siimage_ratemask        -       Compute available modes
 120  *      @drive: IDE drive
 121  *
 122  *      Compute the available speeds for the devices on the interface.
 123  *      For the CMD680 this depends on the clocking mode (scsc), for the
 124  *      SI3312 SATA controller life is a bit simpler. Enforce UDMA33
 125  *      as a limit if there is no 80pin cable present.
 126  */
 127
 128 static byte siimage_ratemask (ide_drive_t *drive)
 129 {
 130         ide_hwif_t *hwif        = HWIF(drive);
 131         u8 mode = 0, scsc = 0;
 132         unsigned long base = (unsigned long) hwif->hwif_data;
 133
 134         if (hwif->mmio)
 135                 scsc = hwif->INB(base + 0x4A);
 136         else
 137                 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
 138
 139         if(is_sata(hwif))
 140         {
 141                 if(strstr(drive->id->model, "Maxtor"))
 142                         return 3;
 143                 return 4;
 144         }
 145
 146         if ((scsc & 0x30) == 0x10)      /* 133 */
 147                 mode = 4;
 148         else if ((scsc & 0x30) == 0x20) /* 2xPCI */
 149                 mode = 4;
 150         else if ((scsc & 0x30) == 0x00) /* 100 */
 151                 mode = 3;
 152         else    /* Disabled ? */
 153                 BUG();
 154
 155         if (!eighty_ninty_three(drive))
 156                 mode = min(mode, (u8)1);
 157         return mode;
 158 }
 159
 160 /**
 161  *      siimage_taskfile_timing -       turn timing data to a mode
 162  *      @hwif: interface to query
 163  *
 164  *      Read the timing data for the interface and return the
 165  *      mode that is being used.
 166  */
 167
 168 static byte siimage_taskfile_timing (ide_hwif_t *hwif)
 169 {
 170         u16 timing      = 0x328a;
 171         unsigned long addr = siimage_selreg(hwif, 2);
 172
 173         if (hwif->mmio)
 174                 timing = hwif->INW(addr);
 175         else
 176                 pci_read_config_word(hwif->pci_dev, addr, &timing);
 177
 178         switch (timing) {
 179                 case 0x10c1:    return 4;
 180                 case 0x10c3:    return 3;
 181                 case 0x1104:
 182                 case 0x1281:    return 2;
 183                 case 0x2283:    return 1;
 184                 case 0x328a:
 185                 default:        return 0;
 186         }
 187 }
 188
 189 /**
 190  *      simmage_tuneproc        -       tune a drive
 191  *      @drive: drive to tune
 192  *      @mode_wanted: the target operating mode
 193  *
 194  *      Load the timing settings for this device mode into the
 195  *      controller. If we are in PIO mode 3 or 4 turn on IORDY
 196  *      monitoring (bit 9). The TF timing is bits 31:16
 197  */
 198
 199 static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted)
 200 {
 201         ide_hwif_t *hwif        = HWIF(drive);
 202         u32 speedt              = 0;
 203         u16 speedp              = 0;
 204         unsigned long addr      = siimage_seldev(drive, 0x04);
 205         unsigned long tfaddr    = siimage_selreg(hwif, 0x02);
 206
 207         /* cheat for now and use the docs */
 208         switch(mode_wanted) {
 209                 case 4:
 210                         speedp = 0x10c1;
 211                         speedt = 0x10c1;
 212                         break;
 213                 case 3:
 214                         speedp = 0x10C3;
 215                         speedt = 0x10C3;
 216                         break;
 217                 case 2:
 218                         speedp = 0x1104;
 219                         speedt = 0x1281;
 220                         break;
 221                 case 1:
 222                         speedp = 0x2283;
 223                         speedt = 0x1281;
 224                         break;
 225                 case 0:
 226                 default:
 227                         speedp = 0x328A;
 228                         speedt = 0x328A;
 229                         break;
 230         }
 231         if (hwif->mmio)
 232         {
 233                 hwif->OUTW(speedt, addr);
 234                 hwif->OUTW(speedp, tfaddr);
 235                 /* Now set up IORDY */
 236                 if(mode_wanted == 3 || mode_wanted == 4)
 237                         hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
 238                 else
 239                         hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
 240         }
 241         else
 242         {
 243                 pci_write_config_word(hwif->pci_dev, addr, speedp);
 244                 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
 245                 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
 246                 speedp &= ~0x200;
 247                 /* Set IORDY for mode 3 or 4 */
 248                 if(mode_wanted == 3 || mode_wanted == 4)
 249                         speedp |= 0x200;
 250                 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
 251         }
 252 }
 253
 254 /**
 255  *      config_siimage_chipset_for_pio  -       set drive timings
 256  *      @drive: drive to tune
 257  *      @speed we want
 258  *
 259  *      Compute the best pio mode we can for a given device. Also honour
 260  *      the timings for the driver when dealing with mixed devices. Some
 261  *      of this is ugly but its all wrapped up here
 262  *
 263  *      The SI680 can also do VDMA - we need to start using that
 264  *
 265  *      FIXME: we use the BIOS channel timings to avoid driving the task
 266  *      files too fast at the disk. We need to compute the master/slave
 267  *      drive PIO mode properly so that we can up the speed on a hotplug
 268  *      system.
 269  */
 270
 271 static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
 272 {
 273         u8 channel_timings      = siimage_taskfile_timing(HWIF(drive));
 274         u8 speed = 0, set_pio   = ide_get_best_pio_mode(drive, 4, 5, NULL);
 275
 276         /* WARNING PIO timing mess is going to happen b/w devices, argh */
 277         if ((channel_timings != set_pio) && (set_pio > channel_timings))
 278                 set_pio = channel_timings;
 279
 280         siimage_tuneproc(drive, set_pio);
 281         speed = XFER_PIO_0 + set_pio;
 282         if (set_speed)
 283                 (void) ide_config_drive_speed(drive, speed);
 284 }
 285
 286 static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
 287 {
 288         config_siimage_chipset_for_pio(drive, set_speed);
 289 }
 290
 291 /**
 292  *      siimage_tune_chipset    -       set controller timings
 293  *      @drive: Drive to set up
 294  *      @xferspeed: speed we want to achieve
 295  *
 296  *      Tune the SII chipset for the desired mode. If we can't achieve
 297  *      the desired mode then tune for a lower one, but ultimately
 298  *      make the thing work.
 299  */
 300
 301 static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed)
 302 {
 303         u8 ultra6[]             = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
 304         u8 ultra5[]             = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
 305         u16 dma[]               = { 0x2208, 0x10C2, 0x10C1 };
 306
 307         ide_hwif_t *hwif        = HWIF(drive);
 308         u16 ultra = 0, multi    = 0;
 309         u8 mode = 0, unit       = drive->select.b.unit;
 310         u8 speed                = ide_rate_filter(siimage_ratemask(drive), xferspeed);
 311         unsigned long base      = (unsigned long)hwif->hwif_data;
 312         u8 scsc = 0, addr_mask  = ((hwif->channel) ?
 313                                     ((hwif->mmio) ? 0xF4 : 0x84) :
 314                                     ((hwif->mmio) ? 0xB4 : 0x80));
 315
 316         unsigned long ma        = siimage_seldev(drive, 0x08);
 317         unsigned long ua        = siimage_seldev(drive, 0x0C);
 318
 319         if (hwif->mmio) {
 320                 scsc = hwif->INB(base + 0x4A);
 321                 mode = hwif->INB(base + addr_mask);
 322                 multi = hwif->INW(ma);
 323                 ultra = hwif->INW(ua);
 324         } else {
 325                 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
 326                 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
 327                 pci_read_config_word(hwif->pci_dev, ma, &multi);
 328                 pci_read_config_word(hwif->pci_dev, ua, &ultra);
 329         }
 330
 331         mode &= ~((unit) ? 0x30 : 0x03);
 332         ultra &= ~0x3F;
 333         scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
 334
 335         scsc = is_sata(hwif) ? 1 : scsc;
 336
 337         switch(speed) {
 338                 case XFER_PIO_4:
 339                 case XFER_PIO_3:
 340                 case XFER_PIO_2:
 341                 case XFER_PIO_1:
 342                 case XFER_PIO_0:
 343                         siimage_tuneproc(drive, (speed - XFER_PIO_0));
 344                         mode |= ((unit) ? 0x10 : 0x01);
 345                         break;
 346                 case XFER_MW_DMA_2:
 347                 case XFER_MW_DMA_1:
 348                 case XFER_MW_DMA_0:
 349                         multi = dma[speed - XFER_MW_DMA_0];
 350                         mode |= ((unit) ? 0x20 : 0x02);
 351                         config_siimage_chipset_for_pio(drive, 0);
 352                         break;
 353                 case XFER_UDMA_6:
 354                 case XFER_UDMA_5:
 355                 case XFER_UDMA_4:
 356                 case XFER_UDMA_3:
 357                 case XFER_UDMA_2:
 358                 case XFER_UDMA_1:
 359                 case XFER_UDMA_0:
 360                         multi = dma[2];
 361                         ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
 362                                            (ultra5[speed - XFER_UDMA_0]));
 363                         mode |= ((unit) ? 0x30 : 0x03);
 364                         config_siimage_chipset_for_pio(drive, 0);
 365                         break;
 366                 default:
 367                         return 1;
 368         }
 369
 370         if (hwif->mmio) {
 371                 hwif->OUTB(mode, base + addr_mask);
 372                 hwif->OUTW(multi, ma);
 373                 hwif->OUTW(ultra, ua);
 374         } else {
 375                 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
 376                 pci_write_config_word(hwif->pci_dev, ma, multi);
 377                 pci_write_config_word(hwif->pci_dev, ua, ultra);
 378         }
 379         return (ide_config_drive_speed(drive, speed));
 380 }
 381
 382 /**
 383  *      config_chipset_for_dma  -       configure for DMA
 384  *      @drive: drive to configure
 385  *
 386  *      Called by the IDE layer when it wants the timings set up.
 387  *      For the CMD680 we also need to set up the PIO timings and
 388  *      enable DMA.
 389  */
 390
 391 static int config_chipset_for_dma (ide_drive_t *drive)
 392 {
 393         u8 speed        = ide_dma_speed(drive, siimage_ratemask(drive));
 394
 395         config_chipset_for_pio(drive, !speed);
 396
 397         if (!speed)
 398                 return 0;
 399
 400         if (ide_set_xfer_rate(drive, speed))
 401                 return 0;
 402
 403         if (!drive->init_speed)
 404                 drive->init_speed = speed;
 405
 406         return ide_dma_enable(drive);
 407 }
 408
 409 /**
 410  *      siimage_configure_drive_for_dma -       set up for DMA transfers
 411  *      @drive: drive we are going to set up
 412  *
 413  *      Set up the drive for DMA, tune the controller and drive as
 414  *      required. If the drive isn't suitable for DMA or we hit
 415  *      other problems then we will drop down to PIO and set up
 416  *      PIO appropriately
 417  */
 418
 419 static int siimage_config_drive_for_dma (ide_drive_t *drive)
 420 {
 421         ide_hwif_t *hwif        = HWIF(drive);
 422         struct hd_driveid *id   = drive->id;
 423
 424         if ((id->capability & 1) != 0 && drive->autodma) {
 425
 426                 if (ide_use_dma(drive)) {
 427                         if (config_chipset_for_dma(drive))
 428                                 return hwif->ide_dma_on(drive);
 429                 }
 430
 431                 goto fast_ata_pio;
 432
 433         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 434 fast_ata_pio:
 435                 config_chipset_for_pio(drive, 1);
 436                 return hwif->ide_dma_off_quietly(drive);
 437         }
 438         /* IORDY not supported */
 439         return 0;
 440 }
 441
 442 /* returns 1 if dma irq issued, 0 otherwise */
 443 static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
 444 {
 445         ide_hwif_t *hwif        = HWIF(drive);
 446         u8 dma_altstat          = 0;
 447         unsigned long addr      = siimage_selreg(hwif, 1);
 448
 449         /* return 1 if INTR asserted */
 450         if ((hwif->INB(hwif->dma_status) & 4) == 4)
 451                 return 1;
 452
 453         /* return 1 if Device INTR asserted */
 454         pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
 455         if (dma_altstat & 8)
 456                 return 0;       //return 1;
 457         return 0;
 458 }
 459
 460 /**
 461  *      siimage_mmio_ide_dma_test_irq   -       check we caused an IRQ
 462  *      @drive: drive we are testing
 463  *
 464  *      Check if we caused an IDE DMA interrupt. We may also have caused
 465  *      SATA status interrupts, if so we clean them up and continue.
 466  */
 467
 468 static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
 469 {
 470         ide_hwif_t *hwif        = HWIF(drive);
 471         unsigned long base      = (unsigned long)hwif->hwif_data;
 472         unsigned long addr      = siimage_selreg(hwif, 0x1);
 473
 474         if (SATA_ERROR_REG) {
 475                 u32 ext_stat = hwif->INL(base + 0x10);
 476                 u8 watchdog = 0;
 477                 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
 478                         u32 sata_error = hwif->INL(SATA_ERROR_REG);
 479                         hwif->OUTL(sata_error, SATA_ERROR_REG);
 480                         watchdog = (sata_error & 0x00680000) ? 1 : 0;
 481                         printk(KERN_WARNING "%s: sata_error = 0x%08x, "
 482                                 "watchdog = %d, %s\n",
 483                                 drive->name, sata_error, watchdog,
 484                                 __FUNCTION__);
 485
 486                 } else {
 487                         watchdog = (ext_stat & 0x8000) ? 1 : 0;
 488                 }
 489                 ext_stat >>= 16;
 490
 491                 if (!(ext_stat & 0x0404) && !watchdog)
 492                         return 0;
 493         }
 494
 495         /* return 1 if INTR asserted */
 496         if ((hwif->INB(hwif->dma_status) & 0x04) == 0x04)
 497                 return 1;
 498
 499         /* return 1 if Device INTR asserted */
 500         if ((hwif->INB(addr) & 8) == 8)
 501                 return 0;       //return 1;
 502
 503         return 0;
 504 }
 505
 506 /**
 507  *      siimage_busproc         -       bus isolation ioctl
 508  *      @drive: drive to isolate/restore
 509  *      @state: bus state to set
 510  *
 511  *      Used by the SII3112 to handle bus isolation. As this is a
 512  *      SATA controller the work required is quite limited, we
 513  *      just have to clean up the statistics
 514  */
 515
 516 static int siimage_busproc (ide_drive_t * drive, int state)
 517 {
 518         ide_hwif_t *hwif        = HWIF(drive);
 519         u32 stat_config         = 0;
 520         unsigned long addr      = siimage_selreg(hwif, 0);
 521
 522         if (hwif->mmio) {
 523                 stat_config = hwif->INL(addr);
 524         } else
 525                 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
 526
 527         switch (state) {
 528                 case BUSSTATE_ON:
 529                         hwif->drives[0].failures = 0;
 530                         hwif->drives[1].failures = 0;
 531                         break;
 532                 case BUSSTATE_OFF:
 533                         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 534                         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 535                         break;
 536                 case BUSSTATE_TRISTATE:
 537                         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 538                         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 539                         break;
 540                 default:
 541                         return -EINVAL;
 542         }
 543         hwif->bus_state = state;
 544         return 0;
 545 }
 546
 547 /**
 548  *      siimage_reset_poll      -       wait for sata reset
 549  *      @drive: drive we are resetting
 550  *
 551  *      Poll the SATA phy and see whether it has come back from the dead
 552  *      yet.
 553  */
 554
 555 static int siimage_reset_poll (ide_drive_t *drive)
 556 {
 557         if (SATA_STATUS_REG) {
 558                 ide_hwif_t *hwif        = HWIF(drive);
 559
 560                 if ((hwif->INL(SATA_STATUS_REG) & 0x03) != 0x03) {
 561                         printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
 562                                 hwif->name, hwif->INL(SATA_STATUS_REG));
 563                         HWGROUP(drive)->polling = 0;
 564                         return ide_started;
 565                 }
 566                 return 0;
 567         } else {
 568                 return 0;
 569         }
 570 }
 571
 572 /**
 573  *      siimage_pre_reset       -       reset hook
 574  *      @drive: IDE device being reset
 575  *
 576  *      For the SATA devices we need to handle recalibration/geometry
 577  *      differently
 578  */
 579
 580 static void siimage_pre_reset (ide_drive_t *drive)
 581 {
 582         if (drive->media != ide_disk)
 583                 return;
 584
 585         if (is_sata(HWIF(drive)))
 586         {
 587                 drive->special.b.set_geometry = 0;
 588                 drive->special.b.recalibrate = 0;
 589         }
 590 }
 591
 592 /**
 593  *      siimage_reset   -       reset a device on an siimage controller
 594  *      @drive: drive to reset
 595  *
 596  *      Perform a controller level reset fo the device. For
 597  *      SATA we must also check the PHY.
 598  */
 599
 600 static void siimage_reset (ide_drive_t *drive)
 601 {
 602         ide_hwif_t *hwif        = HWIF(drive);
 603         u8 reset                = 0;
 604         unsigned long addr      = siimage_selreg(hwif, 0);
 605
 606         if (hwif->mmio) {
 607                 reset = hwif->INB(addr);
 608                 hwif->OUTB((reset|0x03), addr);
 609                 /* FIXME:posting */
 610                 udelay(25);
 611                 hwif->OUTB(reset, addr);
 612                 (void) hwif->INB(addr);
 613         } else {
 614                 pci_read_config_byte(hwif->pci_dev, addr, &reset);
 615                 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
 616                 udelay(25);
 617                 pci_write_config_byte(hwif->pci_dev, addr, reset);
 618                 pci_read_config_byte(hwif->pci_dev, addr, &reset);
 619         }
 620
 621         if (SATA_STATUS_REG) {
 622                 u32 sata_stat = hwif->INL(SATA_STATUS_REG);
 623                 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
 624                         hwif->name, sata_stat, __FUNCTION__);
 625                 if (!(sata_stat)) {
 626                         printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
 627                                 hwif->name, sata_stat);
 628                         drive->failures++;
 629                 }
 630         }
 631
 632 }
 633
 634 /**
 635  *      proc_reports_siimage            -       add siimage controller to proc
 636  *      @dev: PCI device
 637  *      @clocking: SCSC value
 638  *      @name: controller name
 639  *
 640  *      Report the clocking mode of the controller and add it to
 641  *      the /proc interface layer
 642  */
 643
 644 static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
 645 {
 646         if (!pdev_is_sata(dev)) {
 647                 printk(KERN_INFO "%s: BASE CLOCK ", name);
 648                 clocking &= 0x03;
 649                 switch (clocking) {
 650                         case 0x03: printk("DISABLED!\n"); break;
 651                         case 0x02: printk("== 2X PCI\n"); break;
 652                         case 0x01: printk("== 133\n"); break;
 653                         case 0x00: printk("== 100\n"); break;
 654                 }
 655         }
 656 }
 657
 658 /**
 659  *      setup_mmio_siimage      -       switch an SI controller into MMIO
 660  *      @dev: PCI device we are configuring
 661  *      @name: device name
 662  *
 663  *      Attempt to put the device into mmio mode. There are some slight
 664  *      complications here with certain systems where the mmio bar isnt
 665  *      mapped so we have to be sure we can fall back to I/O.
 666  */
 667
 668 static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
 669 {
 670         unsigned long bar5      = pci_resource_start(dev, 5);
 671         unsigned long barsize   = pci_resource_len(dev, 5);
 672         u8 tmpbyte      = 0;
 673         void __iomem *ioaddr;
 674         u32 tmp, irq_mask;
 675
 676         /*
 677          *      Drop back to PIO if we can't map the mmio. Some
 678          *      systems seem to get terminally confused in the PCI
 679          *      spaces.
 680          */
 681
 682         if(!request_mem_region(bar5, barsize, name))
 683         {
 684                 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
 685                 return 0;
 686         }
 687
 688         ioaddr = ioremap(bar5, barsize);
 689
 690         if (ioaddr == NULL)
 691         {
 692                 release_mem_region(bar5, barsize);
 693                 return 0;
 694         }
 695
 696         pci_set_master(dev);
 697         pci_set_drvdata(dev, (void *) ioaddr);
 698
 699         if (pdev_is_sata(dev)) {
 700                 /* make sure IDE0/1 interrupts are not masked */
 701                 irq_mask = (1 << 22) | (1 << 23);
 702                 tmp = readl(ioaddr + 0x48);
 703                 if (tmp & irq_mask) {
 704                         tmp &= ~irq_mask;
 705                         writel(tmp, ioaddr + 0x48);
 706                         readl(ioaddr + 0x48); /* flush */
 707                 }
 708                 writel(0, ioaddr + 0x148);
 709                 writel(0, ioaddr + 0x1C8);
 710         }
 711
 712         writeb(0, ioaddr + 0xB4);
 713         writeb(0, ioaddr + 0xF4);
 714         tmpbyte = readb(ioaddr + 0x4A);
 715
 716         switch(tmpbyte & 0x30) {
 717                 case 0x00:
 718                         /* In 100 MHz clocking, try and switch to 133 */
 719                         writeb(tmpbyte|0x10, ioaddr + 0x4A);
 720                         break;
 721                 case 0x10:
 722                         /* On 133Mhz clocking */
 723                         break;
 724                 case 0x20:
 725                         /* On PCIx2 clocking */
 726                         break;
 727                 case 0x30:
 728                         /* Clocking is disabled */
 729                         /* 133 clock attempt to force it on */
 730                         writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
 731                         break;
 732         }
 733
 734         writeb(      0x72, ioaddr + 0xA1);
 735         writew(    0x328A, ioaddr + 0xA2);
 736         writel(0x62DD62DD, ioaddr + 0xA4);
 737         writel(0x43924392, ioaddr + 0xA8);
 738         writel(0x40094009, ioaddr + 0xAC);
 739         writeb(      0x72, ioaddr + 0xE1);
 740         writew(    0x328A, ioaddr + 0xE2);
 741         writel(0x62DD62DD, ioaddr + 0xE4);
 742         writel(0x43924392, ioaddr + 0xE8);
 743         writel(0x40094009, ioaddr + 0xEC);
 744
 745         if (pdev_is_sata(dev)) {
 746                 writel(0xFFFF0000, ioaddr + 0x108);
 747                 writel(0xFFFF0000, ioaddr + 0x188);
 748                 writel(0x00680000, ioaddr + 0x148);
 749                 writel(0x00680000, ioaddr + 0x1C8);
 750         }
 751
 752         tmpbyte = readb(ioaddr + 0x4A);
 753
 754         proc_reports_siimage(dev, (tmpbyte>>4), name);
 755         return 1;
 756 }
 757
 758 /**
 759  *      init_chipset_siimage    -       set up an SI device
 760  *      @dev: PCI device
 761  *      @name: device name
 762  *
 763  *      Perform the initial PCI set up for this device. Attempt to switch
 764  *      to 133MHz clocking if the system isn't already set up to do it.
 765  */
 766
 767 static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
 768 {
 769         u32 class_rev   = 0;
 770         u8 tmpbyte      = 0;
 771         u8 BA5_EN       = 0;
 772
 773         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 774         class_rev &= 0xff;
 775         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
 776
 777         pci_read_config_byte(dev, 0x8A, &BA5_EN);
 778         if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
 779                 if (setup_mmio_siimage(dev, name)) {
 780                         return 0;
 781                 }
 782         }
 783
 784         pci_write_config_byte(dev, 0x80, 0x00);
 785         pci_write_config_byte(dev, 0x84, 0x00);
 786         pci_read_config_byte(dev, 0x8A, &tmpbyte);
 787         switch(tmpbyte & 0x30) {
 788                 case 0x00:
 789                         /* 133 clock attempt to force it on */
 790                         pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
 791                 case 0x30:
 792                         /* if clocking is disabled */
 793                         /* 133 clock attempt to force it on */
 794                         pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
 795                 case 0x10:
 796                         /* 133 already */
 797                         break;
 798                 case 0x20:
 799                         /* BIOS set PCI x2 clocking */
 800                         break;
 801         }
 802
 803         pci_read_config_byte(dev,   0x8A, &tmpbyte);
 804
 805         pci_write_config_byte(dev,  0xA1, 0x72);
 806         pci_write_config_word(dev,  0xA2, 0x328A);
 807         pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
 808         pci_write_config_dword(dev, 0xA8, 0x43924392);
 809         pci_write_config_dword(dev, 0xAC, 0x40094009);
 810         pci_write_config_byte(dev,  0xB1, 0x72);
 811         pci_write_config_word(dev,  0xB2, 0x328A);
 812         pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
 813         pci_write_config_dword(dev, 0xB8, 0x43924392);
 814         pci_write_config_dword(dev, 0xBC, 0x40094009);
 815
 816         proc_reports_siimage(dev, (tmpbyte>>4), name);
 817         return 0;
 818 }
 819
 820 /**
 821  *      init_mmio_iops_siimage  -       set up the iops for MMIO
 822  *      @hwif: interface to set up
 823  *
 824  *      The basic setup here is fairly simple, we can use standard MMIO
 825  *      operations. However we do have to set the taskfile register offsets
 826  *      by hand as there isnt a standard defined layout for them this
 827  *      time.
 828  *
 829  *      The hardware supports buffered taskfiles and also some rather nice
 830  *      extended PRD tables. For better SI3112 support use the libata driver
 831  */
 832
 833 static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
 834 {
 835         struct pci_dev *dev     = hwif->pci_dev;
 836         void *addr              = pci_get_drvdata(dev);
 837         u8 ch                   = hwif->channel;
 838         hw_regs_t               hw;
 839         unsigned long           base;
 840
 841         /*
 842          *      Fill in the basic HWIF bits
 843          */
 844
 845         default_hwif_mmiops(hwif);
 846         hwif->hwif_data                 = addr;
 847
 848         /*
 849          *      Now set up the hw. We have to do this ourselves as
 850          *      the MMIO layout isnt the same as the the standard port
 851          *      based I/O
 852          */
 853
 854         memset(&hw, 0, sizeof(hw_regs_t));
 855
 856         base = (unsigned long)addr;
 857         if (ch)
 858                 base += 0xC0;
 859         else
 860                 base += 0x80;
 861
 862         /*
 863          *      The buffered task file doesn't have status/control
 864          *      so we can't currently use it sanely since we want to
 865          *      use LBA48 mode.
 866          */
 867         hw.io_ports[IDE_DATA_OFFSET]    = base;
 868         hw.io_ports[IDE_ERROR_OFFSET]   = base + 1;
 869         hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
 870         hw.io_ports[IDE_SECTOR_OFFSET]  = base + 3;
 871         hw.io_ports[IDE_LCYL_OFFSET]    = base + 4;
 872         hw.io_ports[IDE_HCYL_OFFSET]    = base + 5;
 873         hw.io_ports[IDE_SELECT_OFFSET]  = base + 6;
 874         hw.io_ports[IDE_STATUS_OFFSET]  = base + 7;
 875         hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
 876
 877         hw.io_ports[IDE_IRQ_OFFSET]     = 0;
 878
 879         if (pdev_is_sata(dev)) {
 880                 base = (unsigned long)addr;
 881                 if (ch)
 882                         base += 0x80;
 883                 hwif->sata_scr[SATA_STATUS_OFFSET]      = base + 0x104;
 884                 hwif->sata_scr[SATA_ERROR_OFFSET]       = base + 0x108;
 885                 hwif->sata_scr[SATA_CONTROL_OFFSET]     = base + 0x100;
 886                 hwif->sata_misc[SATA_MISC_OFFSET]       = base + 0x140;
 887                 hwif->sata_misc[SATA_PHY_OFFSET]        = base + 0x144;
 888                 hwif->sata_misc[SATA_IEN_OFFSET]        = base + 0x148;
 889         }
 890
 891         hw.irq                          = hwif->pci_dev->irq;
 892
 893         memcpy(&hwif->hw, &hw, sizeof(hw));
 894         memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
 895
 896         hwif->irq                       = hw.irq;
 897
 898         base = (unsigned long) addr;
 899
 900         hwif->dma_base                  = base + (ch ? 0x08 : 0x00);
 901         hwif->mmio                      = 2;
 902 }
 903
 904 static int is_dev_seagate_sata(ide_drive_t *drive)
 905 {
 906         const char *s = &drive->id->model[0];
 907         unsigned len;
 908
 909         if (!drive->present)
 910                 return 0;
 911
 912         len = strnlen(s, sizeof(drive->id->model));
 913
 914         if ((len > 4) && (!memcmp(s, "ST", 2))) {
 915                 if ((!memcmp(s + len - 2, "AS", 2)) ||
 916                     (!memcmp(s + len - 3, "ASL", 3))) {
 917                         printk(KERN_INFO "%s: applying pessimistic Seagate "
 918                                          "errata fix\n", drive->name);
 919                         return 1;
 920                 }
 921         }
 922         return 0;
 923 }
 924
 925 /**
 926  *      siimage_fixup           -       post probe fixups
 927  *      @hwif: interface to fix up
 928  *
 929  *      Called after drive probe we use this to decide whether the
 930  *      Seagate fixup must be applied. This used to be in init_iops but
 931  *      that can occur before we know what drives are present.
 932  */
 933
 934 static void __devinit siimage_fixup(ide_hwif_t *hwif)
 935 {
 936         /* Try and raise the rqsize */
 937         if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0]))
 938                 hwif->rqsize = 128;
 939 }
 940
 941 /**
 942  *      init_iops_siimage       -       set up iops
 943  *      @hwif: interface to set up
 944  *
 945  *      Do the basic setup for the SIIMAGE hardware interface
 946  *      and then do the MMIO setup if we can. This is the first
 947  *      look in we get for setting up the hwif so that we
 948  *      can get the iops right before using them.
 949  */
 950
 951 static void __devinit init_iops_siimage(ide_hwif_t *hwif)
 952 {
 953         struct pci_dev *dev     = hwif->pci_dev;
 954         u32 class_rev           = 0;
 955
 956         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 957         class_rev &= 0xff;
 958
 959         hwif->hwif_data = NULL;
 960
 961         /* Pessimal until we finish probing */
 962         hwif->rqsize = 15;
 963
 964         if (pci_get_drvdata(dev) == NULL)
 965                 return;
 966         init_mmio_iops_siimage(hwif);
 967 }
 968
 969 /**
 970  *      ata66_siimage   -       check for 80 pin cable
 971  *      @hwif: interface to check
 972  *
 973  *      Check for the presence of an ATA66 capable cable on the
 974  *      interface.
 975  */
 976
 977 static unsigned int __devinit ata66_siimage(ide_hwif_t *hwif)
 978 {
 979         unsigned long addr = siimage_selreg(hwif, 0);
 980         if (pci_get_drvdata(hwif->pci_dev) == NULL) {
 981                 u8 ata66 = 0;
 982                 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
 983                 return (ata66 & 0x01) ? 1 : 0;
 984         }
 985
 986         return (hwif->INB(addr) & 0x01) ? 1 : 0;
 987 }
 988
 989 /**
 990  *      init_hwif_siimage       -       set up hwif structs
 991  *      @hwif: interface to set up
 992  *
 993  *      We do the basic set up of the interface structure. The SIIMAGE
 994  *      requires several custom handlers so we override the default
 995  *      ide DMA handlers appropriately
 996  */
 997
 998 static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
 999 {
1000         hwif->autodma = 0;
1001
1002         hwif->resetproc = &siimage_reset;
1003         hwif->speedproc = &siimage_tune_chipset;
1004         hwif->tuneproc  = &siimage_tuneproc;
1005         hwif->reset_poll = &siimage_reset_poll;
1006         hwif->pre_reset = &siimage_pre_reset;
1007
1008         if(is_sata(hwif)) {
1009                 static int first = 1;
1010
1011                 hwif->busproc   = &siimage_busproc;
1012
1013                 if (first) {
1014                         printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n");
1015                         first = 0;
1016                 }
1017         }
1018         if (!hwif->dma_base) {
1019                 hwif->drives[0].autotune = 1;
1020                 hwif->drives[1].autotune = 1;
1021                 return;
1022         }
1023
1024         hwif->ultra_mask = 0x7f;
1025         hwif->mwdma_mask = 0x07;
1026         hwif->swdma_mask = 0x07;
1027
1028         if (!is_sata(hwif))
1029                 hwif->atapi_dma = 1;
1030
1031         hwif->ide_dma_check = &siimage_config_drive_for_dma;
1032         if (!(hwif->udma_four))
1033                 hwif->udma_four = ata66_siimage(hwif);
1034
1035         if (hwif->mmio) {
1036                 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
1037         } else {
1038                 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
1039         }
1040
1041         /*
1042          *      The BIOS often doesn't set up DMA on this controller
1043          *      so we always do it.
1044          */
1045
1046         hwif->autodma = 1;
1047         hwif->drives[0].autodma = hwif->autodma;
1048         hwif->drives[1].autodma = hwif->autodma;
1049 }
1050
1051 #define DECLARE_SII_DEV(name_str)                       \
1052         {                                               \
1053                 .name           = name_str,             \
1054                 .init_chipset   = init_chipset_siimage, \
1055                 .init_iops      = init_iops_siimage,    \
1056                 .init_hwif      = init_hwif_siimage,    \
1057                 .fixup          = siimage_fixup,        \
1058                 .channels       = 2,                    \
1059                 .autodma        = AUTODMA,              \
1060                 .bootable       = ON_BOARD,             \
1061         }
1062
1063 static ide_pci_device_t siimage_chipsets[] __devinitdata = {
1064         /* 0 */ DECLARE_SII_DEV("SiI680"),
1065         /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
1066         /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
1067 };
1068
1069 /**
1070  *      siimage_init_one        -       pci layer discovery entry
1071  *      @dev: PCI device
1072  *      @id: ident table entry
1073  *
1074  *      Called by the PCI code when it finds an SI680 or SI3112 controller.
1075  *      We then use the IDE PCI generic helper to do most of the work.
1076  */
1077
1078 static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1079 {
1080         return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]);
1081 }
1082
1083 static struct pci_device_id siimage_pci_tbl[] = {
1084         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1085 #ifdef CONFIG_BLK_DEV_IDE_SATA
1086         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1087         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1088 #endif
1089         { 0, },
1090 };
1091 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
1092
1093 static struct pci_driver driver = {
1094         .name           = "SiI_IDE",
1095         .id_table       = siimage_pci_tbl,
1096         .probe          = siimage_init_one,
1097 };
1098
1099 static int __init siimage_ide_init(void)
1100 {
1101         return ide_pci_register_driver(&driver);
1102 }
1103
1104 module_init(siimage_ide_init);
1105
1106 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1107 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1108 MODULE_LICENSE("GPL");