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Linux 2.6.20.7
[linux/fpc-iii.git] / drivers / net / 8139too.c
blob99304b2aa86e3d70d40520a9332e9a57930d4350
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.28"
94
95
96 #include <linux/module.h>
97 #include <linux/kernel.h>
98 #include <linux/compiler.h>
99 #include <linux/pci.h>
100 #include <linux/init.h>
101 #include <linux/ioport.h>
102 #include <linux/netdevice.h>
103 #include <linux/etherdevice.h>
104 #include <linux/rtnetlink.h>
105 #include <linux/delay.h>
106 #include <linux/ethtool.h>
107 #include <linux/mii.h>
108 #include <linux/completion.h>
109 #include <linux/crc32.h>
110 #include <asm/io.h>
111 #include <asm/uaccess.h>
112 #include <asm/irq.h>
113
114 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
115 #define PFX DRV_NAME ": "
116
117 /* Default Message level */
118 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
119 NETIF_MSG_PROBE | \
120 NETIF_MSG_LINK)
121
122
123 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
124 #ifdef CONFIG_8139TOO_PIO
125 #define USE_IO_OPS 1
126 #endif
127
128 /* define to 1, 2 or 3 to enable copious debugging info */
129 #define RTL8139_DEBUG 0
130
131 /* define to 1 to disable lightweight runtime debugging checks */
132 #undef RTL8139_NDEBUG
133
134
135 #if RTL8139_DEBUG
136 /* note: prints function name for you */
137 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
138 #else
139 # define DPRINTK(fmt, args...)
140 #endif
141
142 #ifdef RTL8139_NDEBUG
143 # define assert(expr) do {} while (0)
144 #else
145 # define assert(expr) \
146 if(unlikely(!(expr))) { \
147 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
148 #expr,__FILE__,__FUNCTION__,__LINE__); \
149 }
150 #endif
151
152
153 /* A few user-configurable values. */
154 /* media options */
155 #define MAX_UNITS 8
156 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
157 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
158
159 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
160 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
161 static int multicast_filter_limit = 32;
162
163 /* bitmapped message enable number */
164 static int debug = -1;
165
166 /*
167 * Receive ring size
168 * Warning: 64K ring has hardware issues and may lock up.
169 */
170 #if defined(CONFIG_SH_DREAMCAST)
171 #define RX_BUF_IDX 1 /* 16K ring */
172 #else
173 #define RX_BUF_IDX 2 /* 32K ring */
174 #endif
175 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
176 #define RX_BUF_PAD 16
177 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
178
179 #if RX_BUF_LEN == 65536
180 #define RX_BUF_TOT_LEN RX_BUF_LEN
181 #else
182 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
183 #endif
184
185 /* Number of Tx descriptor registers. */
186 #define NUM_TX_DESC 4
187
188 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
189 #define MAX_ETH_FRAME_SIZE 1536
190
191 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
192 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
193 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
194
195 /* PCI Tuning Parameters
196 Threshold is bytes transferred to chip before transmission starts. */
197 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
198
199 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
200 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
201 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
202 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
203 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
204
205 /* Operational parameters that usually are not changed. */
206 /* Time in jiffies before concluding the transmitter is hung. */
207 #define TX_TIMEOUT (6*HZ)
208
209
210 enum {
211 HAS_MII_XCVR = 0x010000,
212 HAS_CHIP_XCVR = 0x020000,
213 HAS_LNK_CHNG = 0x040000,
214 };
215
216 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
217 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
218 #define RTL_MIN_IO_SIZE 0x80
219 #define RTL8139B_IO_SIZE 256
220
221 #define RTL8129_CAPS HAS_MII_XCVR
222 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
223
224 typedef enum {
225 RTL8139 = 0,
226 RTL8129,
227 } board_t;
228
229
230 /* indexed by board_t, above */
231 static const struct {
232 const char *name;
233 u32 hw_flags;
234 } board_info[] __devinitdata = {
235 { "RealTek RTL8139", RTL8139_CAPS },
236 { "RealTek RTL8129", RTL8129_CAPS },
237 };
238
239
240 static struct pci_device_id rtl8139_pci_tbl[] = {
241 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260
261 #ifdef CONFIG_SH_SECUREEDGE5410
262 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
264 #endif
265 #ifdef CONFIG_8139TOO_8129
266 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
267 #endif
268
269 /* some crazy cards report invalid vendor ids like
270 * 0x0001 here. The other ids are valid and constant,
271 * so we simply don't match on the main vendor id.
272 */
273 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
274 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
275 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
276
277 {0,}
278 };
279 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
280
281 static struct {
282 const char str[ETH_GSTRING_LEN];
283 } ethtool_stats_keys[] = {
284 { "early_rx" },
285 { "tx_buf_mapped" },
286 { "tx_timeouts" },
287 { "rx_lost_in_ring" },
288 };
289
290 /* The rest of these values should never change. */
291
292 /* Symbolic offsets to registers. */
293 enum RTL8139_registers {
294 MAC0 = 0, /* Ethernet hardware address. */
295 MAR0 = 8, /* Multicast filter. */
296 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
297 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
298 RxBuf = 0x30,
299 ChipCmd = 0x37,
300 RxBufPtr = 0x38,
301 RxBufAddr = 0x3A,
302 IntrMask = 0x3C,
303 IntrStatus = 0x3E,
304 TxConfig = 0x40,
305 RxConfig = 0x44,
306 Timer = 0x48, /* A general-purpose counter. */
307 RxMissed = 0x4C, /* 24 bits valid, write clears. */
308 Cfg9346 = 0x50,
309 Config0 = 0x51,
310 Config1 = 0x52,
311 FlashReg = 0x54,
312 MediaStatus = 0x58,
313 Config3 = 0x59,
314 Config4 = 0x5A, /* absent on RTL-8139A */
315 HltClk = 0x5B,
316 MultiIntr = 0x5C,
317 TxSummary = 0x60,
318 BasicModeCtrl = 0x62,
319 BasicModeStatus = 0x64,
320 NWayAdvert = 0x66,
321 NWayLPAR = 0x68,
322 NWayExpansion = 0x6A,
323 /* Undocumented registers, but required for proper operation. */
324 FIFOTMS = 0x70, /* FIFO Control and test. */
325 CSCR = 0x74, /* Chip Status and Configuration Register. */
326 PARA78 = 0x78,
327 PARA7c = 0x7c, /* Magic transceiver parameter register. */
328 Config5 = 0xD8, /* absent on RTL-8139A */
329 };
330
331 enum ClearBitMasks {
332 MultiIntrClear = 0xF000,
333 ChipCmdClear = 0xE2,
334 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
335 };
336
337 enum ChipCmdBits {
338 CmdReset = 0x10,
339 CmdRxEnb = 0x08,
340 CmdTxEnb = 0x04,
341 RxBufEmpty = 0x01,
342 };
343
344 /* Interrupt register bits, using my own meaningful names. */
345 enum IntrStatusBits {
346 PCIErr = 0x8000,
347 PCSTimeout = 0x4000,
348 RxFIFOOver = 0x40,
349 RxUnderrun = 0x20,
350 RxOverflow = 0x10,
351 TxErr = 0x08,
352 TxOK = 0x04,
353 RxErr = 0x02,
354 RxOK = 0x01,
355
356 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
357 };
358
359 enum TxStatusBits {
360 TxHostOwns = 0x2000,
361 TxUnderrun = 0x4000,
362 TxStatOK = 0x8000,
363 TxOutOfWindow = 0x20000000,
364 TxAborted = 0x40000000,
365 TxCarrierLost = 0x80000000,
366 };
367 enum RxStatusBits {
368 RxMulticast = 0x8000,
369 RxPhysical = 0x4000,
370 RxBroadcast = 0x2000,
371 RxBadSymbol = 0x0020,
372 RxRunt = 0x0010,
373 RxTooLong = 0x0008,
374 RxCRCErr = 0x0004,
375 RxBadAlign = 0x0002,
376 RxStatusOK = 0x0001,
377 };
378
379 /* Bits in RxConfig. */
380 enum rx_mode_bits {
381 AcceptErr = 0x20,
382 AcceptRunt = 0x10,
383 AcceptBroadcast = 0x08,
384 AcceptMulticast = 0x04,
385 AcceptMyPhys = 0x02,
386 AcceptAllPhys = 0x01,
387 };
388
389 /* Bits in TxConfig. */
390 enum tx_config_bits {
391
392 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
393 TxIFGShift = 24,
394 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
395 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
396 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
397 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
398
399 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
400 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
401 TxClearAbt = (1 << 0), /* Clear abort (WO) */
402 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
403 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
404
405 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
406 };
407
408 /* Bits in Config1 */
409 enum Config1Bits {
410 Cfg1_PM_Enable = 0x01,
411 Cfg1_VPD_Enable = 0x02,
412 Cfg1_PIO = 0x04,
413 Cfg1_MMIO = 0x08,
414 LWAKE = 0x10, /* not on 8139, 8139A */
415 Cfg1_Driver_Load = 0x20,
416 Cfg1_LED0 = 0x40,
417 Cfg1_LED1 = 0x80,
418 SLEEP = (1 << 1), /* only on 8139, 8139A */
419 PWRDN = (1 << 0), /* only on 8139, 8139A */
420 };
421
422 /* Bits in Config3 */
423 enum Config3Bits {
424 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
425 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
426 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
427 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
428 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
429 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
430 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
431 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
432 };
433
434 /* Bits in Config4 */
435 enum Config4Bits {
436 LWPTN = (1 << 2), /* not on 8139, 8139A */
437 };
438
439 /* Bits in Config5 */
440 enum Config5Bits {
441 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
442 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
443 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
444 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
445 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
446 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
447 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
448 };
449
450 enum RxConfigBits {
451 /* rx fifo threshold */
452 RxCfgFIFOShift = 13,
453 RxCfgFIFONone = (7 << RxCfgFIFOShift),
454
455 /* Max DMA burst */
456 RxCfgDMAShift = 8,
457 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
458
459 /* rx ring buffer length */
460 RxCfgRcv8K = 0,
461 RxCfgRcv16K = (1 << 11),
462 RxCfgRcv32K = (1 << 12),
463 RxCfgRcv64K = (1 << 11) | (1 << 12),
464
465 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
466 RxNoWrap = (1 << 7),
467 };
468
469 /* Twister tuning parameters from RealTek.
470 Completely undocumented, but required to tune bad links on some boards. */
471 enum CSCRBits {
472 CSCR_LinkOKBit = 0x0400,
473 CSCR_LinkChangeBit = 0x0800,
474 CSCR_LinkStatusBits = 0x0f000,
475 CSCR_LinkDownOffCmd = 0x003c0,
476 CSCR_LinkDownCmd = 0x0f3c0,
477 };
478
479 enum Cfg9346Bits {
480 Cfg9346_Lock = 0x00,
481 Cfg9346_Unlock = 0xC0,
482 };
483
484 typedef enum {
485 CH_8139 = 0,
486 CH_8139_K,
487 CH_8139A,
488 CH_8139A_G,
489 CH_8139B,
490 CH_8130,
491 CH_8139C,
492 CH_8100,
493 CH_8100B_8139D,
494 CH_8101,
495 } chip_t;
496
497 enum chip_flags {
498 HasHltClk = (1 << 0),
499 HasLWake = (1 << 1),
500 };
501
502 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
503 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
504 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
505
506 /* directly indexed by chip_t, above */
507 static const struct {
508 const char *name;
509 u32 version; /* from RTL8139C/RTL8139D docs */
510 u32 flags;
511 } rtl_chip_info[] = {
512 { "RTL-8139",
513 HW_REVID(1, 0, 0, 0, 0, 0, 0),
514 HasHltClk,
515 },
516
517 { "RTL-8139 rev K",
518 HW_REVID(1, 1, 0, 0, 0, 0, 0),
519 HasHltClk,
520 },
521
522 { "RTL-8139A",
523 HW_REVID(1, 1, 1, 0, 0, 0, 0),
524 HasHltClk, /* XXX undocumented? */
525 },
526
527 { "RTL-8139A rev G",
528 HW_REVID(1, 1, 1, 0, 0, 1, 0),
529 HasHltClk, /* XXX undocumented? */
530 },
531
532 { "RTL-8139B",
533 HW_REVID(1, 1, 1, 1, 0, 0, 0),
534 HasLWake,
535 },
536
537 { "RTL-8130",
538 HW_REVID(1, 1, 1, 1, 1, 0, 0),
539 HasLWake,
540 },
541
542 { "RTL-8139C",
543 HW_REVID(1, 1, 1, 0, 1, 0, 0),
544 HasLWake,
545 },
546
547 { "RTL-8100",
548 HW_REVID(1, 1, 1, 1, 0, 1, 0),
549 HasLWake,
550 },
551
552 { "RTL-8100B/8139D",
553 HW_REVID(1, 1, 1, 0, 1, 0, 1),
554 HasHltClk /* XXX undocumented? */
555 | HasLWake,
556 },
557
558 { "RTL-8101",
559 HW_REVID(1, 1, 1, 0, 1, 1, 1),
560 HasLWake,
561 },
562 };
563
564 struct rtl_extra_stats {
565 unsigned long early_rx;
566 unsigned long tx_buf_mapped;
567 unsigned long tx_timeouts;
568 unsigned long rx_lost_in_ring;
569 };
570
571 struct rtl8139_private {
572 void __iomem *mmio_addr;
573 int drv_flags;
574 struct pci_dev *pci_dev;
575 u32 msg_enable;
576 struct net_device_stats stats;
577 unsigned char *rx_ring;
578 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
579 unsigned int tx_flag;
580 unsigned long cur_tx;
581 unsigned long dirty_tx;
582 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
583 unsigned char *tx_bufs; /* Tx bounce buffer region. */
584 dma_addr_t rx_ring_dma;
585 dma_addr_t tx_bufs_dma;
586 signed char phys[4]; /* MII device addresses. */
587 char twistie, twist_row, twist_col; /* Twister tune state. */
588 unsigned int watchdog_fired : 1;
589 unsigned int default_port : 4; /* Last dev->if_port value. */
590 unsigned int have_thread : 1;
591 spinlock_t lock;
592 spinlock_t rx_lock;
593 chip_t chipset;
594 u32 rx_config;
595 struct rtl_extra_stats xstats;
596
597 struct delayed_work thread;
598
599 struct mii_if_info mii;
600 unsigned int regs_len;
601 unsigned long fifo_copy_timeout;
602 };
603
604 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
605 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
606 MODULE_LICENSE("GPL");
607 MODULE_VERSION(DRV_VERSION);
608
609 module_param(multicast_filter_limit, int, 0);
610 module_param_array(media, int, NULL, 0);
611 module_param_array(full_duplex, int, NULL, 0);
612 module_param(debug, int, 0);
613 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
614 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
615 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
616 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
617
618 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
619 static int rtl8139_open (struct net_device *dev);
620 static int mdio_read (struct net_device *dev, int phy_id, int location);
621 static void mdio_write (struct net_device *dev, int phy_id, int location,
622 int val);
623 static void rtl8139_start_thread(struct rtl8139_private *tp);
624 static void rtl8139_tx_timeout (struct net_device *dev);
625 static void rtl8139_init_ring (struct net_device *dev);
626 static int rtl8139_start_xmit (struct sk_buff *skb,
627 struct net_device *dev);
628 static int rtl8139_poll(struct net_device *dev, int *budget);
629 #ifdef CONFIG_NET_POLL_CONTROLLER
630 static void rtl8139_poll_controller(struct net_device *dev);
631 #endif
632 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
633 static int rtl8139_close (struct net_device *dev);
634 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
635 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
636 static void rtl8139_set_rx_mode (struct net_device *dev);
637 static void __set_rx_mode (struct net_device *dev);
638 static void rtl8139_hw_start (struct net_device *dev);
639 static void rtl8139_thread (struct work_struct *work);
640 static void rtl8139_tx_timeout_task(struct work_struct *work);
641 static const struct ethtool_ops rtl8139_ethtool_ops;
642
643 /* write MMIO register, with flush */
644 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
645 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
646 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
647 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
648
649
650 #define MMIO_FLUSH_AUDIT_COMPLETE 1
651 #if MMIO_FLUSH_AUDIT_COMPLETE
652
653 /* write MMIO register */
654 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
655 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
656 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
657
658 #else
659
660 /* write MMIO register, then flush */
661 #define RTL_W8 RTL_W8_F
662 #define RTL_W16 RTL_W16_F
663 #define RTL_W32 RTL_W32_F
664
665 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
666
667 /* read MMIO register */
668 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
669 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
670 #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
671
672
673 static const u16 rtl8139_intr_mask =
674 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
675 TxErr | TxOK | RxErr | RxOK;
676
677 static const u16 rtl8139_norx_intr_mask =
678 PCIErr | PCSTimeout | RxUnderrun |
679 TxErr | TxOK | RxErr ;
680
681 #if RX_BUF_IDX == 0
682 static const unsigned int rtl8139_rx_config =
683 RxCfgRcv8K | RxNoWrap |
684 (RX_FIFO_THRESH << RxCfgFIFOShift) |
685 (RX_DMA_BURST << RxCfgDMAShift);
686 #elif RX_BUF_IDX == 1
687 static const unsigned int rtl8139_rx_config =
688 RxCfgRcv16K | RxNoWrap |
689 (RX_FIFO_THRESH << RxCfgFIFOShift) |
690 (RX_DMA_BURST << RxCfgDMAShift);
691 #elif RX_BUF_IDX == 2
692 static const unsigned int rtl8139_rx_config =
693 RxCfgRcv32K | RxNoWrap |
694 (RX_FIFO_THRESH << RxCfgFIFOShift) |
695 (RX_DMA_BURST << RxCfgDMAShift);
696 #elif RX_BUF_IDX == 3
697 static const unsigned int rtl8139_rx_config =
698 RxCfgRcv64K |
699 (RX_FIFO_THRESH << RxCfgFIFOShift) |
700 (RX_DMA_BURST << RxCfgDMAShift);
701 #else
702 #error "Invalid configuration for 8139_RXBUF_IDX"
703 #endif
704
705 static const unsigned int rtl8139_tx_config =
706 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
707
708 static void __rtl8139_cleanup_dev (struct net_device *dev)
709 {
710 struct rtl8139_private *tp = netdev_priv(dev);
711 struct pci_dev *pdev;
712
713 assert (dev != NULL);
714 assert (tp->pci_dev != NULL);
715 pdev = tp->pci_dev;
716
717 #ifdef USE_IO_OPS
718 if (tp->mmio_addr)
719 ioport_unmap (tp->mmio_addr);
720 #else
721 if (tp->mmio_addr)
722 pci_iounmap (pdev, tp->mmio_addr);
723 #endif /* USE_IO_OPS */
724
725 /* it's ok to call this even if we have no regions to free */
726 pci_release_regions (pdev);
727
728 free_netdev(dev);
729 pci_set_drvdata (pdev, NULL);
730 }
731
732
733 static void rtl8139_chip_reset (void __iomem *ioaddr)
734 {
735 int i;
736
737 /* Soft reset the chip. */
738 RTL_W8 (ChipCmd, CmdReset);
739
740 /* Check that the chip has finished the reset. */
741 for (i = 1000; i > 0; i--) {
742 barrier();
743 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
744 break;
745 udelay (10);
746 }
747 }
748
749
750 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
751 struct net_device **dev_out)
752 {
753 void __iomem *ioaddr;
754 struct net_device *dev;
755 struct rtl8139_private *tp;
756 u8 tmp8;
757 int rc, disable_dev_on_err = 0;
758 unsigned int i;
759 unsigned long pio_start, pio_end, pio_flags, pio_len;
760 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
761 u32 version;
762
763 assert (pdev != NULL);
764
765 *dev_out = NULL;
766
767 /* dev and priv zeroed in alloc_etherdev */
768 dev = alloc_etherdev (sizeof (*tp));
769 if (dev == NULL) {
770 dev_err(&pdev->dev, "Unable to alloc new net device\n");
771 return -ENOMEM;
772 }
773 SET_MODULE_OWNER(dev);
774 SET_NETDEV_DEV(dev, &pdev->dev);
775
776 tp = netdev_priv(dev);
777 tp->pci_dev = pdev;
778
779 /* enable device (incl. PCI PM wakeup and hotplug setup) */
780 rc = pci_enable_device (pdev);
781 if (rc)
782 goto err_out;
783
784 pio_start = pci_resource_start (pdev, 0);
785 pio_end = pci_resource_end (pdev, 0);
786 pio_flags = pci_resource_flags (pdev, 0);
787 pio_len = pci_resource_len (pdev, 0);
788
789 mmio_start = pci_resource_start (pdev, 1);
790 mmio_end = pci_resource_end (pdev, 1);
791 mmio_flags = pci_resource_flags (pdev, 1);
792 mmio_len = pci_resource_len (pdev, 1);
793
794 /* set this immediately, we need to know before
795 * we talk to the chip directly */
796 DPRINTK("PIO region size == 0x%02X\n", pio_len);
797 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
798
799 #ifdef USE_IO_OPS
800 /* make sure PCI base addr 0 is PIO */
801 if (!(pio_flags & IORESOURCE_IO)) {
802 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
803 rc = -ENODEV;
804 goto err_out;
805 }
806 /* check for weird/broken PCI region reporting */
807 if (pio_len < RTL_MIN_IO_SIZE) {
808 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
809 rc = -ENODEV;
810 goto err_out;
811 }
812 #else
813 /* make sure PCI base addr 1 is MMIO */
814 if (!(mmio_flags & IORESOURCE_MEM)) {
815 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
816 rc = -ENODEV;
817 goto err_out;
818 }
819 if (mmio_len < RTL_MIN_IO_SIZE) {
820 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
821 rc = -ENODEV;
822 goto err_out;
823 }
824 #endif
825
826 rc = pci_request_regions (pdev, DRV_NAME);
827 if (rc)
828 goto err_out;
829 disable_dev_on_err = 1;
830
831 /* enable PCI bus-mastering */
832 pci_set_master (pdev);
833
834 #ifdef USE_IO_OPS
835 ioaddr = ioport_map(pio_start, pio_len);
836 if (!ioaddr) {
837 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
838 rc = -EIO;
839 goto err_out;
840 }
841 dev->base_addr = pio_start;
842 tp->mmio_addr = ioaddr;
843 tp->regs_len = pio_len;
844 #else
845 /* ioremap MMIO region */
846 ioaddr = pci_iomap(pdev, 1, 0);
847 if (ioaddr == NULL) {
848 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
849 rc = -EIO;
850 goto err_out;
851 }
852 dev->base_addr = (long) ioaddr;
853 tp->mmio_addr = ioaddr;
854 tp->regs_len = mmio_len;
855 #endif /* USE_IO_OPS */
856
857 /* Bring old chips out of low-power mode. */
858 RTL_W8 (HltClk, 'R');
859
860 /* check for missing/broken hardware */
861 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
862 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
863 rc = -EIO;
864 goto err_out;
865 }
866
867 /* identify chip attached to board */
868 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
869 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
870 if (version == rtl_chip_info[i].version) {
871 tp->chipset = i;
872 goto match;
873 }
874
875 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
876 dev_printk (KERN_DEBUG, &pdev->dev,
877 "unknown chip version, assuming RTL-8139\n");
878 dev_printk (KERN_DEBUG, &pdev->dev,
879 "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
880 tp->chipset = 0;
881
882 match:
883 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
884 version, i, rtl_chip_info[i].name);
885
886 if (tp->chipset >= CH_8139B) {
887 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
888 DPRINTK("PCI PM wakeup\n");
889 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
890 (tmp8 & LWAKE))
891 new_tmp8 &= ~LWAKE;
892 new_tmp8 |= Cfg1_PM_Enable;
893 if (new_tmp8 != tmp8) {
894 RTL_W8 (Cfg9346, Cfg9346_Unlock);
895 RTL_W8 (Config1, tmp8);
896 RTL_W8 (Cfg9346, Cfg9346_Lock);
897 }
898 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
899 tmp8 = RTL_R8 (Config4);
900 if (tmp8 & LWPTN) {
901 RTL_W8 (Cfg9346, Cfg9346_Unlock);
902 RTL_W8 (Config4, tmp8 & ~LWPTN);
903 RTL_W8 (Cfg9346, Cfg9346_Lock);
904 }
905 }
906 } else {
907 DPRINTK("Old chip wakeup\n");
908 tmp8 = RTL_R8 (Config1);
909 tmp8 &= ~(SLEEP | PWRDN);
910 RTL_W8 (Config1, tmp8);
911 }
912
913 rtl8139_chip_reset (ioaddr);
914
915 *dev_out = dev;
916 return 0;
917
918 err_out:
919 __rtl8139_cleanup_dev (dev);
920 if (disable_dev_on_err)
921 pci_disable_device (pdev);
922 return rc;
923 }
924
925
926 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
927 const struct pci_device_id *ent)
928 {
929 struct net_device *dev = NULL;
930 struct rtl8139_private *tp;
931 int i, addr_len, option;
932 void __iomem *ioaddr;
933 static int board_idx = -1;
934 u8 pci_rev;
935
936 assert (pdev != NULL);
937 assert (ent != NULL);
938
939 board_idx++;
940
941 /* when we're built into the kernel, the driver version message
942 * is only printed if at least one 8139 board has been found
943 */
944 #ifndef MODULE
945 {
946 static int printed_version;
947 if (!printed_version++)
948 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
949 }
950 #endif
951
952 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
953
954 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
955 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
956 dev_info(&pdev->dev,
957 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
958 pdev->vendor, pdev->device, pci_rev);
959 dev_info(&pdev->dev,
960 "Use the \"8139cp\" driver for improved performance and stability.\n");
961 }
962
963 i = rtl8139_init_board (pdev, &dev);
964 if (i < 0)
965 return i;
966
967 assert (dev != NULL);
968 tp = netdev_priv(dev);
969
970 ioaddr = tp->mmio_addr;
971 assert (ioaddr != NULL);
972
973 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
974 for (i = 0; i < 3; i++)
975 ((u16 *) (dev->dev_addr))[i] =
976 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
977 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
978
979 /* The Rtl8139-specific entries in the device structure. */
980 dev->open = rtl8139_open;
981 dev->hard_start_xmit = rtl8139_start_xmit;
982 dev->poll = rtl8139_poll;
983 dev->weight = 64;
984 dev->stop = rtl8139_close;
985 dev->get_stats = rtl8139_get_stats;
986 dev->set_multicast_list = rtl8139_set_rx_mode;
987 dev->do_ioctl = netdev_ioctl;
988 dev->ethtool_ops = &rtl8139_ethtool_ops;
989 dev->tx_timeout = rtl8139_tx_timeout;
990 dev->watchdog_timeo = TX_TIMEOUT;
991 #ifdef CONFIG_NET_POLL_CONTROLLER
992 dev->poll_controller = rtl8139_poll_controller;
993 #endif
994
995 /* note: the hardware is not capable of sg/csum/highdma, however
996 * through the use of skb_copy_and_csum_dev we enable these
997 * features
998 */
999 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1000
1001 dev->irq = pdev->irq;
1002
1003 /* tp zeroed and aligned in alloc_etherdev */
1004 tp = netdev_priv(dev);
1005
1006 /* note: tp->chipset set in rtl8139_init_board */
1007 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1008 tp->mmio_addr = ioaddr;
1009 tp->msg_enable =
1010 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1011 spin_lock_init (&tp->lock);
1012 spin_lock_init (&tp->rx_lock);
1013 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1014 tp->mii.dev = dev;
1015 tp->mii.mdio_read = mdio_read;
1016 tp->mii.mdio_write = mdio_write;
1017 tp->mii.phy_id_mask = 0x3f;
1018 tp->mii.reg_num_mask = 0x1f;
1019
1020 /* dev is fully set up and ready to use now */
1021 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1022 i = register_netdev (dev);
1023 if (i) goto err_out;
1024
1025 pci_set_drvdata (pdev, dev);
1026
1027 printk (KERN_INFO "%s: %s at 0x%lx, "
1028 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1029 "IRQ %d\n",
1030 dev->name,
1031 board_info[ent->driver_data].name,
1032 dev->base_addr,
1033 dev->dev_addr[0], dev->dev_addr[1],
1034 dev->dev_addr[2], dev->dev_addr[3],
1035 dev->dev_addr[4], dev->dev_addr[5],
1036 dev->irq);
1037
1038 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1039 dev->name, rtl_chip_info[tp->chipset].name);
1040
1041 /* Find the connected MII xcvrs.
1042 Doing this in open() would allow detecting external xcvrs later, but
1043 takes too much time. */
1044 #ifdef CONFIG_8139TOO_8129
1045 if (tp->drv_flags & HAS_MII_XCVR) {
1046 int phy, phy_idx = 0;
1047 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1048 int mii_status = mdio_read(dev, phy, 1);
1049 if (mii_status != 0xffff && mii_status != 0x0000) {
1050 u16 advertising = mdio_read(dev, phy, 4);
1051 tp->phys[phy_idx++] = phy;
1052 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1053 "advertising %4.4x.\n",
1054 dev->name, phy, mii_status, advertising);
1055 }
1056 }
1057 if (phy_idx == 0) {
1058 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1059 "transceiver.\n",
1060 dev->name);
1061 tp->phys[0] = 32;
1062 }
1063 } else
1064 #endif
1065 tp->phys[0] = 32;
1066 tp->mii.phy_id = tp->phys[0];
1067
1068 /* The lower four bits are the media type. */
1069 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1070 if (option > 0) {
1071 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1072 tp->default_port = option & 0xFF;
1073 if (tp->default_port)
1074 tp->mii.force_media = 1;
1075 }
1076 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1077 tp->mii.full_duplex = full_duplex[board_idx];
1078 if (tp->mii.full_duplex) {
1079 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1080 /* Changing the MII-advertised media because might prevent
1081 re-connection. */
1082 tp->mii.force_media = 1;
1083 }
1084 if (tp->default_port) {
1085 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1086 (option & 0x20 ? 100 : 10),
1087 (option & 0x10 ? "full" : "half"));
1088 mdio_write(dev, tp->phys[0], 0,
1089 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1090 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1091 }
1092
1093 /* Put the chip into low-power mode. */
1094 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1095 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1096
1097 return 0;
1098
1099 err_out:
1100 __rtl8139_cleanup_dev (dev);
1101 pci_disable_device (pdev);
1102 return i;
1103 }
1104
1105
1106 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1107 {
1108 struct net_device *dev = pci_get_drvdata (pdev);
1109
1110 assert (dev != NULL);
1111
1112 flush_scheduled_work();
1113
1114 unregister_netdev (dev);
1115
1116 __rtl8139_cleanup_dev (dev);
1117 pci_disable_device (pdev);
1118 }
1119
1120
1121 /* Serial EEPROM section. */
1122
1123 /* EEPROM_Ctrl bits. */
1124 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1125 #define EE_CS 0x08 /* EEPROM chip select. */
1126 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1127 #define EE_WRITE_0 0x00
1128 #define EE_WRITE_1 0x02
1129 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1130 #define EE_ENB (0x80 | EE_CS)
1131
1132 /* Delay between EEPROM clock transitions.
1133 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1134 */
1135
1136 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1137
1138 /* The EEPROM commands include the alway-set leading bit. */
1139 #define EE_WRITE_CMD (5)
1140 #define EE_READ_CMD (6)
1141 #define EE_ERASE_CMD (7)
1142
1143 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1144 {
1145 int i;
1146 unsigned retval = 0;
1147 int read_cmd = location | (EE_READ_CMD << addr_len);
1148
1149 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1150 RTL_W8 (Cfg9346, EE_ENB);
1151 eeprom_delay ();
1152
1153 /* Shift the read command bits out. */
1154 for (i = 4 + addr_len; i >= 0; i--) {
1155 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1156 RTL_W8 (Cfg9346, EE_ENB | dataval);
1157 eeprom_delay ();
1158 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1159 eeprom_delay ();
1160 }
1161 RTL_W8 (Cfg9346, EE_ENB);
1162 eeprom_delay ();
1163
1164 for (i = 16; i > 0; i--) {
1165 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1166 eeprom_delay ();
1167 retval =
1168 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1169 0);
1170 RTL_W8 (Cfg9346, EE_ENB);
1171 eeprom_delay ();
1172 }
1173
1174 /* Terminate the EEPROM access. */
1175 RTL_W8 (Cfg9346, ~EE_CS);
1176 eeprom_delay ();
1177
1178 return retval;
1179 }
1180
1181 /* MII serial management: mostly bogus for now. */
1182 /* Read and write the MII management registers using software-generated
1183 serial MDIO protocol.
1184 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1185 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1186 "overclocking" issues. */
1187 #define MDIO_DIR 0x80
1188 #define MDIO_DATA_OUT 0x04
1189 #define MDIO_DATA_IN 0x02
1190 #define MDIO_CLK 0x01
1191 #define MDIO_WRITE0 (MDIO_DIR)
1192 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1193
1194 #define mdio_delay() RTL_R8(Config4)
1195
1196
1197 static const char mii_2_8139_map[8] = {
1198 BasicModeCtrl,
1199 BasicModeStatus,
1200 0,
1201 0,
1202 NWayAdvert,
1203 NWayLPAR,
1204 NWayExpansion,
1205 0
1206 };
1207
1208
1209 #ifdef CONFIG_8139TOO_8129
1210 /* Syncronize the MII management interface by shifting 32 one bits out. */
1211 static void mdio_sync (void __iomem *ioaddr)
1212 {
1213 int i;
1214
1215 for (i = 32; i >= 0; i--) {
1216 RTL_W8 (Config4, MDIO_WRITE1);
1217 mdio_delay ();
1218 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1219 mdio_delay ();
1220 }
1221 }
1222 #endif
1223
1224 static int mdio_read (struct net_device *dev, int phy_id, int location)
1225 {
1226 struct rtl8139_private *tp = netdev_priv(dev);
1227 int retval = 0;
1228 #ifdef CONFIG_8139TOO_8129
1229 void __iomem *ioaddr = tp->mmio_addr;
1230 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1231 int i;
1232 #endif
1233
1234 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1235 void __iomem *ioaddr = tp->mmio_addr;
1236 return location < 8 && mii_2_8139_map[location] ?
1237 RTL_R16 (mii_2_8139_map[location]) : 0;
1238 }
1239
1240 #ifdef CONFIG_8139TOO_8129
1241 mdio_sync (ioaddr);
1242 /* Shift the read command bits out. */
1243 for (i = 15; i >= 0; i--) {
1244 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1245
1246 RTL_W8 (Config4, MDIO_DIR | dataval);
1247 mdio_delay ();
1248 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1249 mdio_delay ();
1250 }
1251
1252 /* Read the two transition, 16 data, and wire-idle bits. */
1253 for (i = 19; i > 0; i--) {
1254 RTL_W8 (Config4, 0);
1255 mdio_delay ();
1256 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1257 RTL_W8 (Config4, MDIO_CLK);
1258 mdio_delay ();
1259 }
1260 #endif
1261
1262 return (retval >> 1) & 0xffff;
1263 }
1264
1265
1266 static void mdio_write (struct net_device *dev, int phy_id, int location,
1267 int value)
1268 {
1269 struct rtl8139_private *tp = netdev_priv(dev);
1270 #ifdef CONFIG_8139TOO_8129
1271 void __iomem *ioaddr = tp->mmio_addr;
1272 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1273 int i;
1274 #endif
1275
1276 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1277 void __iomem *ioaddr = tp->mmio_addr;
1278 if (location == 0) {
1279 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1280 RTL_W16 (BasicModeCtrl, value);
1281 RTL_W8 (Cfg9346, Cfg9346_Lock);
1282 } else if (location < 8 && mii_2_8139_map[location])
1283 RTL_W16 (mii_2_8139_map[location], value);
1284 return;
1285 }
1286
1287 #ifdef CONFIG_8139TOO_8129
1288 mdio_sync (ioaddr);
1289
1290 /* Shift the command bits out. */
1291 for (i = 31; i >= 0; i--) {
1292 int dataval =
1293 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1294 RTL_W8 (Config4, dataval);
1295 mdio_delay ();
1296 RTL_W8 (Config4, dataval | MDIO_CLK);
1297 mdio_delay ();
1298 }
1299 /* Clear out extra bits. */
1300 for (i = 2; i > 0; i--) {
1301 RTL_W8 (Config4, 0);
1302 mdio_delay ();
1303 RTL_W8 (Config4, MDIO_CLK);
1304 mdio_delay ();
1305 }
1306 #endif
1307 }
1308
1309
1310 static int rtl8139_open (struct net_device *dev)
1311 {
1312 struct rtl8139_private *tp = netdev_priv(dev);
1313 int retval;
1314 void __iomem *ioaddr = tp->mmio_addr;
1315
1316 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1317 if (retval)
1318 return retval;
1319
1320 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1321 &tp->tx_bufs_dma);
1322 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1323 &tp->rx_ring_dma);
1324 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1325 free_irq(dev->irq, dev);
1326
1327 if (tp->tx_bufs)
1328 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1329 tp->tx_bufs, tp->tx_bufs_dma);
1330 if (tp->rx_ring)
1331 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1332 tp->rx_ring, tp->rx_ring_dma);
1333
1334 return -ENOMEM;
1335
1336 }
1337
1338 tp->mii.full_duplex = tp->mii.force_media;
1339 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1340
1341 rtl8139_init_ring (dev);
1342 rtl8139_hw_start (dev);
1343 netif_start_queue (dev);
1344
1345 if (netif_msg_ifup(tp))
1346 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
1347 " GP Pins %2.2x %s-duplex.\n", dev->name,
1348 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1349 dev->irq, RTL_R8 (MediaStatus),
1350 tp->mii.full_duplex ? "full" : "half");
1351
1352 rtl8139_start_thread(tp);
1353
1354 return 0;
1355 }
1356
1357
1358 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1359 {
1360 struct rtl8139_private *tp = netdev_priv(dev);
1361
1362 if (tp->phys[0] >= 0) {
1363 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1364 }
1365 }
1366
1367 /* Start the hardware at open or resume. */
1368 static void rtl8139_hw_start (struct net_device *dev)
1369 {
1370 struct rtl8139_private *tp = netdev_priv(dev);
1371 void __iomem *ioaddr = tp->mmio_addr;
1372 u32 i;
1373 u8 tmp;
1374
1375 /* Bring old chips out of low-power mode. */
1376 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1377 RTL_W8 (HltClk, 'R');
1378
1379 rtl8139_chip_reset (ioaddr);
1380
1381 /* unlock Config[01234] and BMCR register writes */
1382 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1383 /* Restore our idea of the MAC address. */
1384 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1385 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1386
1387 /* Must enable Tx/Rx before setting transfer thresholds! */
1388 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1389
1390 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1391 RTL_W32 (RxConfig, tp->rx_config);
1392 RTL_W32 (TxConfig, rtl8139_tx_config);
1393
1394 tp->cur_rx = 0;
1395
1396 rtl_check_media (dev, 1);
1397
1398 if (tp->chipset >= CH_8139B) {
1399 /* Disable magic packet scanning, which is enabled
1400 * when PM is enabled in Config1. It can be reenabled
1401 * via ETHTOOL_SWOL if desired. */
1402 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1403 }
1404
1405 DPRINTK("init buffer addresses\n");
1406
1407 /* Lock Config[01234] and BMCR register writes */
1408 RTL_W8 (Cfg9346, Cfg9346_Lock);
1409
1410 /* init Rx ring buffer DMA address */
1411 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1412
1413 /* init Tx buffer DMA addresses */
1414 for (i = 0; i < NUM_TX_DESC; i++)
1415 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1416
1417 RTL_W32 (RxMissed, 0);
1418
1419 rtl8139_set_rx_mode (dev);
1420
1421 /* no early-rx interrupts */
1422 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1423
1424 /* make sure RxTx has started */
1425 tmp = RTL_R8 (ChipCmd);
1426 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1427 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1428
1429 /* Enable all known interrupts by setting the interrupt mask. */
1430 RTL_W16 (IntrMask, rtl8139_intr_mask);
1431 }
1432
1433
1434 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1435 static void rtl8139_init_ring (struct net_device *dev)
1436 {
1437 struct rtl8139_private *tp = netdev_priv(dev);
1438 int i;
1439
1440 tp->cur_rx = 0;
1441 tp->cur_tx = 0;
1442 tp->dirty_tx = 0;
1443
1444 for (i = 0; i < NUM_TX_DESC; i++)
1445 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1446 }
1447
1448
1449 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1450 static int next_tick = 3 * HZ;
1451
1452 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1453 static inline void rtl8139_tune_twister (struct net_device *dev,
1454 struct rtl8139_private *tp) {}
1455 #else
1456 enum TwisterParamVals {
1457 PARA78_default = 0x78fa8388,
1458 PARA7c_default = 0xcb38de43, /* param[0][3] */
1459 PARA7c_xxx = 0xcb38de43,
1460 };
1461
1462 static const unsigned long param[4][4] = {
1463 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1464 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1465 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1466 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1467 };
1468
1469 static void rtl8139_tune_twister (struct net_device *dev,
1470 struct rtl8139_private *tp)
1471 {
1472 int linkcase;
1473 void __iomem *ioaddr = tp->mmio_addr;
1474
1475 /* This is a complicated state machine to configure the "twister" for
1476 impedance/echos based on the cable length.
1477 All of this is magic and undocumented.
1478 */
1479 switch (tp->twistie) {
1480 case 1:
1481 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1482 /* We have link beat, let us tune the twister. */
1483 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1484 tp->twistie = 2; /* Change to state 2. */
1485 next_tick = HZ / 10;
1486 } else {
1487 /* Just put in some reasonable defaults for when beat returns. */
1488 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1489 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1490 RTL_W32 (PARA78, PARA78_default);
1491 RTL_W32 (PARA7c, PARA7c_default);
1492 tp->twistie = 0; /* Bail from future actions. */
1493 }
1494 break;
1495 case 2:
1496 /* Read how long it took to hear the echo. */
1497 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1498 if (linkcase == 0x7000)
1499 tp->twist_row = 3;
1500 else if (linkcase == 0x3000)
1501 tp->twist_row = 2;
1502 else if (linkcase == 0x1000)
1503 tp->twist_row = 1;
1504 else
1505 tp->twist_row = 0;
1506 tp->twist_col = 0;
1507 tp->twistie = 3; /* Change to state 2. */
1508 next_tick = HZ / 10;
1509 break;
1510 case 3:
1511 /* Put out four tuning parameters, one per 100msec. */
1512 if (tp->twist_col == 0)
1513 RTL_W16 (FIFOTMS, 0);
1514 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1515 [(int) tp->twist_col]);
1516 next_tick = HZ / 10;
1517 if (++tp->twist_col >= 4) {
1518 /* For short cables we are done.
1519 For long cables (row == 3) check for mistune. */
1520 tp->twistie =
1521 (tp->twist_row == 3) ? 4 : 0;
1522 }
1523 break;
1524 case 4:
1525 /* Special case for long cables: check for mistune. */
1526 if ((RTL_R16 (CSCR) &
1527 CSCR_LinkStatusBits) == 0x7000) {
1528 tp->twistie = 0;
1529 break;
1530 } else {
1531 RTL_W32 (PARA7c, 0xfb38de03);
1532 tp->twistie = 5;
1533 next_tick = HZ / 10;
1534 }
1535 break;
1536 case 5:
1537 /* Retune for shorter cable (column 2). */
1538 RTL_W32 (FIFOTMS, 0x20);
1539 RTL_W32 (PARA78, PARA78_default);
1540 RTL_W32 (PARA7c, PARA7c_default);
1541 RTL_W32 (FIFOTMS, 0x00);
1542 tp->twist_row = 2;
1543 tp->twist_col = 0;
1544 tp->twistie = 3;
1545 next_tick = HZ / 10;
1546 break;
1547
1548 default:
1549 /* do nothing */
1550 break;
1551 }
1552 }
1553 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1554
1555 static inline void rtl8139_thread_iter (struct net_device *dev,
1556 struct rtl8139_private *tp,
1557 void __iomem *ioaddr)
1558 {
1559 int mii_lpa;
1560
1561 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1562
1563 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1564 int duplex = (mii_lpa & LPA_100FULL)
1565 || (mii_lpa & 0x01C0) == 0x0040;
1566 if (tp->mii.full_duplex != duplex) {
1567 tp->mii.full_duplex = duplex;
1568
1569 if (mii_lpa) {
1570 printk (KERN_INFO
1571 "%s: Setting %s-duplex based on MII #%d link"
1572 " partner ability of %4.4x.\n",
1573 dev->name,
1574 tp->mii.full_duplex ? "full" : "half",
1575 tp->phys[0], mii_lpa);
1576 } else {
1577 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1578 dev->name);
1579 }
1580 #if 0
1581 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1582 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1583 RTL_W8 (Cfg9346, Cfg9346_Lock);
1584 #endif
1585 }
1586 }
1587
1588 next_tick = HZ * 60;
1589
1590 rtl8139_tune_twister (dev, tp);
1591
1592 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1593 dev->name, RTL_R16 (NWayLPAR));
1594 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1595 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1596 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1597 dev->name, RTL_R8 (Config0),
1598 RTL_R8 (Config1));
1599 }
1600
1601 static void rtl8139_thread (struct work_struct *work)
1602 {
1603 struct rtl8139_private *tp =
1604 container_of(work, struct rtl8139_private, thread.work);
1605 struct net_device *dev = tp->mii.dev;
1606 unsigned long thr_delay = next_tick;
1607
1608 rtnl_lock();
1609
1610 if (!netif_running(dev))
1611 goto out_unlock;
1612
1613 if (tp->watchdog_fired) {
1614 tp->watchdog_fired = 0;
1615 rtl8139_tx_timeout_task(work);
1616 } else
1617 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1618
1619 if (tp->have_thread)
1620 schedule_delayed_work(&tp->thread, thr_delay);
1621 out_unlock:
1622 rtnl_unlock ();
1623 }
1624
1625 static void rtl8139_start_thread(struct rtl8139_private *tp)
1626 {
1627 tp->twistie = 0;
1628 if (tp->chipset == CH_8139_K)
1629 tp->twistie = 1;
1630 else if (tp->drv_flags & HAS_LNK_CHNG)
1631 return;
1632
1633 tp->have_thread = 1;
1634 tp->watchdog_fired = 0;
1635
1636 schedule_delayed_work(&tp->thread, next_tick);
1637 }
1638
1639 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1640 {
1641 tp->cur_tx = 0;
1642 tp->dirty_tx = 0;
1643
1644 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1645 }
1646
1647 static void rtl8139_tx_timeout_task (struct work_struct *work)
1648 {
1649 struct rtl8139_private *tp =
1650 container_of(work, struct rtl8139_private, thread.work);
1651 struct net_device *dev = tp->mii.dev;
1652 void __iomem *ioaddr = tp->mmio_addr;
1653 int i;
1654 u8 tmp8;
1655
1656 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1657 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1658 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1659 /* Emit info to figure out what went wrong. */
1660 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1661 dev->name, tp->cur_tx, tp->dirty_tx);
1662 for (i = 0; i < NUM_TX_DESC; i++)
1663 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1664 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1665 i == tp->dirty_tx % NUM_TX_DESC ?
1666 " (queue head)" : "");
1667
1668 tp->xstats.tx_timeouts++;
1669
1670 /* disable Tx ASAP, if not already */
1671 tmp8 = RTL_R8 (ChipCmd);
1672 if (tmp8 & CmdTxEnb)
1673 RTL_W8 (ChipCmd, CmdRxEnb);
1674
1675 spin_lock_bh(&tp->rx_lock);
1676 /* Disable interrupts by clearing the interrupt mask. */
1677 RTL_W16 (IntrMask, 0x0000);
1678
1679 /* Stop a shared interrupt from scavenging while we are. */
1680 spin_lock_irq(&tp->lock);
1681 rtl8139_tx_clear (tp);
1682 spin_unlock_irq(&tp->lock);
1683
1684 /* ...and finally, reset everything */
1685 if (netif_running(dev)) {
1686 rtl8139_hw_start (dev);
1687 netif_wake_queue (dev);
1688 }
1689 spin_unlock_bh(&tp->rx_lock);
1690 }
1691
1692 static void rtl8139_tx_timeout (struct net_device *dev)
1693 {
1694 struct rtl8139_private *tp = netdev_priv(dev);
1695
1696 tp->watchdog_fired = 1;
1697 if (!tp->have_thread) {
1698 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1699 schedule_delayed_work(&tp->thread, next_tick);
1700 }
1701 }
1702
1703 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1704 {
1705 struct rtl8139_private *tp = netdev_priv(dev);
1706 void __iomem *ioaddr = tp->mmio_addr;
1707 unsigned int entry;
1708 unsigned int len = skb->len;
1709 unsigned long flags;
1710
1711 /* Calculate the next Tx descriptor entry. */
1712 entry = tp->cur_tx % NUM_TX_DESC;
1713
1714 /* Note: the chip doesn't have auto-pad! */
1715 if (likely(len < TX_BUF_SIZE)) {
1716 if (len < ETH_ZLEN)
1717 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1718 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1719 dev_kfree_skb(skb);
1720 } else {
1721 dev_kfree_skb(skb);
1722 tp->stats.tx_dropped++;
1723 return 0;
1724 }
1725
1726 spin_lock_irqsave(&tp->lock, flags);
1727 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1728 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1729
1730 dev->trans_start = jiffies;
1731
1732 tp->cur_tx++;
1733 wmb();
1734
1735 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1736 netif_stop_queue (dev);
1737 spin_unlock_irqrestore(&tp->lock, flags);
1738
1739 if (netif_msg_tx_queued(tp))
1740 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1741 dev->name, len, entry);
1742
1743 return 0;
1744 }
1745
1746
1747 static void rtl8139_tx_interrupt (struct net_device *dev,
1748 struct rtl8139_private *tp,
1749 void __iomem *ioaddr)
1750 {
1751 unsigned long dirty_tx, tx_left;
1752
1753 assert (dev != NULL);
1754 assert (ioaddr != NULL);
1755
1756 dirty_tx = tp->dirty_tx;
1757 tx_left = tp->cur_tx - dirty_tx;
1758 while (tx_left > 0) {
1759 int entry = dirty_tx % NUM_TX_DESC;
1760 int txstatus;
1761
1762 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1763
1764 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1765 break; /* It still hasn't been Txed */
1766
1767 /* Note: TxCarrierLost is always asserted at 100mbps. */
1768 if (txstatus & (TxOutOfWindow | TxAborted)) {
1769 /* There was an major error, log it. */
1770 if (netif_msg_tx_err(tp))
1771 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1772 dev->name, txstatus);
1773 tp->stats.tx_errors++;
1774 if (txstatus & TxAborted) {
1775 tp->stats.tx_aborted_errors++;
1776 RTL_W32 (TxConfig, TxClearAbt);
1777 RTL_W16 (IntrStatus, TxErr);
1778 wmb();
1779 }
1780 if (txstatus & TxCarrierLost)
1781 tp->stats.tx_carrier_errors++;
1782 if (txstatus & TxOutOfWindow)
1783 tp->stats.tx_window_errors++;
1784 } else {
1785 if (txstatus & TxUnderrun) {
1786 /* Add 64 to the Tx FIFO threshold. */
1787 if (tp->tx_flag < 0x00300000)
1788 tp->tx_flag += 0x00020000;
1789 tp->stats.tx_fifo_errors++;
1790 }
1791 tp->stats.collisions += (txstatus >> 24) & 15;
1792 tp->stats.tx_bytes += txstatus & 0x7ff;
1793 tp->stats.tx_packets++;
1794 }
1795
1796 dirty_tx++;
1797 tx_left--;
1798 }
1799
1800 #ifndef RTL8139_NDEBUG
1801 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1802 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1803 dev->name, dirty_tx, tp->cur_tx);
1804 dirty_tx += NUM_TX_DESC;
1805 }
1806 #endif /* RTL8139_NDEBUG */
1807
1808 /* only wake the queue if we did work, and the queue is stopped */
1809 if (tp->dirty_tx != dirty_tx) {
1810 tp->dirty_tx = dirty_tx;
1811 mb();
1812 netif_wake_queue (dev);
1813 }
1814 }
1815
1816
1817 /* TODO: clean this up! Rx reset need not be this intensive */
1818 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1819 struct rtl8139_private *tp, void __iomem *ioaddr)
1820 {
1821 u8 tmp8;
1822 #ifdef CONFIG_8139_OLD_RX_RESET
1823 int tmp_work;
1824 #endif
1825
1826 if (netif_msg_rx_err (tp))
1827 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1828 dev->name, rx_status);
1829 tp->stats.rx_errors++;
1830 if (!(rx_status & RxStatusOK)) {
1831 if (rx_status & RxTooLong) {
1832 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1833 dev->name, rx_status);
1834 /* A.C.: The chip hangs here. */
1835 }
1836 if (rx_status & (RxBadSymbol | RxBadAlign))
1837 tp->stats.rx_frame_errors++;
1838 if (rx_status & (RxRunt | RxTooLong))
1839 tp->stats.rx_length_errors++;
1840 if (rx_status & RxCRCErr)
1841 tp->stats.rx_crc_errors++;
1842 } else {
1843 tp->xstats.rx_lost_in_ring++;
1844 }
1845
1846 #ifndef CONFIG_8139_OLD_RX_RESET
1847 tmp8 = RTL_R8 (ChipCmd);
1848 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1849 RTL_W8 (ChipCmd, tmp8);
1850 RTL_W32 (RxConfig, tp->rx_config);
1851 tp->cur_rx = 0;
1852 #else
1853 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1854
1855 /* disable receive */
1856 RTL_W8_F (ChipCmd, CmdTxEnb);
1857 tmp_work = 200;
1858 while (--tmp_work > 0) {
1859 udelay(1);
1860 tmp8 = RTL_R8 (ChipCmd);
1861 if (!(tmp8 & CmdRxEnb))
1862 break;
1863 }
1864 if (tmp_work <= 0)
1865 printk (KERN_WARNING PFX "rx stop wait too long\n");
1866 /* restart receive */
1867 tmp_work = 200;
1868 while (--tmp_work > 0) {
1869 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1870 udelay(1);
1871 tmp8 = RTL_R8 (ChipCmd);
1872 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1873 break;
1874 }
1875 if (tmp_work <= 0)
1876 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1877
1878 /* and reinitialize all rx related registers */
1879 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1880 /* Must enable Tx/Rx before setting transfer thresholds! */
1881 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1882
1883 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1884 RTL_W32 (RxConfig, tp->rx_config);
1885 tp->cur_rx = 0;
1886
1887 DPRINTK("init buffer addresses\n");
1888
1889 /* Lock Config[01234] and BMCR register writes */
1890 RTL_W8 (Cfg9346, Cfg9346_Lock);
1891
1892 /* init Rx ring buffer DMA address */
1893 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1894
1895 /* A.C.: Reset the multicast list. */
1896 __set_rx_mode (dev);
1897 #endif
1898 }
1899
1900 #if RX_BUF_IDX == 3
1901 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1902 u32 offset, unsigned int size)
1903 {
1904 u32 left = RX_BUF_LEN - offset;
1905
1906 if (size > left) {
1907 memcpy(skb->data, ring + offset, left);
1908 memcpy(skb->data+left, ring, size - left);
1909 } else
1910 memcpy(skb->data, ring + offset, size);
1911 }
1912 #endif
1913
1914 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1915 {
1916 void __iomem *ioaddr = tp->mmio_addr;
1917 u16 status;
1918
1919 status = RTL_R16 (IntrStatus) & RxAckBits;
1920
1921 /* Clear out errors and receive interrupts */
1922 if (likely(status != 0)) {
1923 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1924 tp->stats.rx_errors++;
1925 if (status & RxFIFOOver)
1926 tp->stats.rx_fifo_errors++;
1927 }
1928 RTL_W16_F (IntrStatus, RxAckBits);
1929 }
1930 }
1931
1932 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1933 int budget)
1934 {
1935 void __iomem *ioaddr = tp->mmio_addr;
1936 int received = 0;
1937 unsigned char *rx_ring = tp->rx_ring;
1938 unsigned int cur_rx = tp->cur_rx;
1939 unsigned int rx_size = 0;
1940
1941 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1942 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1943 RTL_R16 (RxBufAddr),
1944 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1945
1946 while (netif_running(dev) && received < budget
1947 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1948 u32 ring_offset = cur_rx % RX_BUF_LEN;
1949 u32 rx_status;
1950 unsigned int pkt_size;
1951 struct sk_buff *skb;
1952
1953 rmb();
1954
1955 /* read size+status of next frame from DMA ring buffer */
1956 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1957 rx_size = rx_status >> 16;
1958 pkt_size = rx_size - 4;
1959
1960 if (netif_msg_rx_status(tp))
1961 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1962 " cur %4.4x.\n", dev->name, rx_status,
1963 rx_size, cur_rx);
1964 #if RTL8139_DEBUG > 2
1965 {
1966 int i;
1967 DPRINTK ("%s: Frame contents ", dev->name);
1968 for (i = 0; i < 70; i++)
1969 printk (" %2.2x",
1970 rx_ring[ring_offset + i]);
1971 printk (".\n");
1972 }
1973 #endif
1974
1975 /* Packet copy from FIFO still in progress.
1976 * Theoretically, this should never happen
1977 * since EarlyRx is disabled.
1978 */
1979 if (unlikely(rx_size == 0xfff0)) {
1980 if (!tp->fifo_copy_timeout)
1981 tp->fifo_copy_timeout = jiffies + 2;
1982 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1983 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
1984 rx_size = 0;
1985 goto no_early_rx;
1986 }
1987 if (netif_msg_intr(tp)) {
1988 printk(KERN_DEBUG "%s: fifo copy in progress.",
1989 dev->name);
1990 }
1991 tp->xstats.early_rx++;
1992 break;
1993 }
1994
1995 no_early_rx:
1996 tp->fifo_copy_timeout = 0;
1997
1998 /* If Rx err or invalid rx_size/rx_status received
1999 * (which happens if we get lost in the ring),
2000 * Rx process gets reset, so we abort any further
2001 * Rx processing.
2002 */
2003 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2004 (rx_size < 8) ||
2005 (!(rx_status & RxStatusOK)))) {
2006 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2007 received = -1;
2008 goto out;
2009 }
2010
2011 /* Malloc up new buffer, compatible with net-2e. */
2012 /* Omit the four octet CRC from the length. */
2013
2014 skb = dev_alloc_skb (pkt_size + 2);
2015 if (likely(skb)) {
2016 skb->dev = dev;
2017 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2018 #if RX_BUF_IDX == 3
2019 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2020 #else
2021 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
2022 #endif
2023 skb_put (skb, pkt_size);
2024
2025 skb->protocol = eth_type_trans (skb, dev);
2026
2027 dev->last_rx = jiffies;
2028 tp->stats.rx_bytes += pkt_size;
2029 tp->stats.rx_packets++;
2030
2031 netif_receive_skb (skb);
2032 } else {
2033 if (net_ratelimit())
2034 printk (KERN_WARNING
2035 "%s: Memory squeeze, dropping packet.\n",
2036 dev->name);
2037 tp->stats.rx_dropped++;
2038 }
2039 received++;
2040
2041 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2042 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2043
2044 rtl8139_isr_ack(tp);
2045 }
2046
2047 if (unlikely(!received || rx_size == 0xfff0))
2048 rtl8139_isr_ack(tp);
2049
2050 #if RTL8139_DEBUG > 1
2051 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2052 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2053 RTL_R16 (RxBufAddr),
2054 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2055 #endif
2056
2057 tp->cur_rx = cur_rx;
2058
2059 /*
2060 * The receive buffer should be mostly empty.
2061 * Tell NAPI to reenable the Rx irq.
2062 */
2063 if (tp->fifo_copy_timeout)
2064 received = budget;
2065
2066 out:
2067 return received;
2068 }
2069
2070
2071 static void rtl8139_weird_interrupt (struct net_device *dev,
2072 struct rtl8139_private *tp,
2073 void __iomem *ioaddr,
2074 int status, int link_changed)
2075 {
2076 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2077 dev->name, status);
2078
2079 assert (dev != NULL);
2080 assert (tp != NULL);
2081 assert (ioaddr != NULL);
2082
2083 /* Update the error count. */
2084 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2085 RTL_W32 (RxMissed, 0);
2086
2087 if ((status & RxUnderrun) && link_changed &&
2088 (tp->drv_flags & HAS_LNK_CHNG)) {
2089 rtl_check_media(dev, 0);
2090 status &= ~RxUnderrun;
2091 }
2092
2093 if (status & (RxUnderrun | RxErr))
2094 tp->stats.rx_errors++;
2095
2096 if (status & PCSTimeout)
2097 tp->stats.rx_length_errors++;
2098 if (status & RxUnderrun)
2099 tp->stats.rx_fifo_errors++;
2100 if (status & PCIErr) {
2101 u16 pci_cmd_status;
2102 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2103 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2104
2105 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2106 dev->name, pci_cmd_status);
2107 }
2108 }
2109
2110 static int rtl8139_poll(struct net_device *dev, int *budget)
2111 {
2112 struct rtl8139_private *tp = netdev_priv(dev);
2113 void __iomem *ioaddr = tp->mmio_addr;
2114 int orig_budget = min(*budget, dev->quota);
2115 int done = 1;
2116
2117 spin_lock(&tp->rx_lock);
2118 if (likely(RTL_R16(IntrStatus) & RxAckBits)) {
2119 int work_done;
2120
2121 work_done = rtl8139_rx(dev, tp, orig_budget);
2122 if (likely(work_done > 0)) {
2123 *budget -= work_done;
2124 dev->quota -= work_done;
2125 done = (work_done < orig_budget);
2126 }
2127 }
2128
2129 if (done) {
2130 unsigned long flags;
2131 /*
2132 * Order is important since data can get interrupted
2133 * again when we think we are done.
2134 */
2135 local_irq_save(flags);
2136 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2137 __netif_rx_complete(dev);
2138 local_irq_restore(flags);
2139 }
2140 spin_unlock(&tp->rx_lock);
2141
2142 return !done;
2143 }
2144
2145 /* The interrupt handler does all of the Rx thread work and cleans up
2146 after the Tx thread. */
2147 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2148 {
2149 struct net_device *dev = (struct net_device *) dev_instance;
2150 struct rtl8139_private *tp = netdev_priv(dev);
2151 void __iomem *ioaddr = tp->mmio_addr;
2152 u16 status, ackstat;
2153 int link_changed = 0; /* avoid bogus "uninit" warning */
2154 int handled = 0;
2155
2156 spin_lock (&tp->lock);
2157 status = RTL_R16 (IntrStatus);
2158
2159 /* shared irq? */
2160 if (unlikely((status & rtl8139_intr_mask) == 0))
2161 goto out;
2162
2163 handled = 1;
2164
2165 /* h/w no longer present (hotplug?) or major error, bail */
2166 if (unlikely(status == 0xFFFF))
2167 goto out;
2168
2169 /* close possible race's with dev_close */
2170 if (unlikely(!netif_running(dev))) {
2171 RTL_W16 (IntrMask, 0);
2172 goto out;
2173 }
2174
2175 /* Acknowledge all of the current interrupt sources ASAP, but
2176 an first get an additional status bit from CSCR. */
2177 if (unlikely(status & RxUnderrun))
2178 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2179
2180 ackstat = status & ~(RxAckBits | TxErr);
2181 if (ackstat)
2182 RTL_W16 (IntrStatus, ackstat);
2183
2184 /* Receive packets are processed by poll routine.
2185 If not running start it now. */
2186 if (status & RxAckBits){
2187 if (netif_rx_schedule_prep(dev)) {
2188 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2189 __netif_rx_schedule (dev);
2190 }
2191 }
2192
2193 /* Check uncommon events with one test. */
2194 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2195 rtl8139_weird_interrupt (dev, tp, ioaddr,
2196 status, link_changed);
2197
2198 if (status & (TxOK | TxErr)) {
2199 rtl8139_tx_interrupt (dev, tp, ioaddr);
2200 if (status & TxErr)
2201 RTL_W16 (IntrStatus, TxErr);
2202 }
2203 out:
2204 spin_unlock (&tp->lock);
2205
2206 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2207 dev->name, RTL_R16 (IntrStatus));
2208 return IRQ_RETVAL(handled);
2209 }
2210
2211 #ifdef CONFIG_NET_POLL_CONTROLLER
2212 /*
2213 * Polling receive - used by netconsole and other diagnostic tools
2214 * to allow network i/o with interrupts disabled.
2215 */
2216 static void rtl8139_poll_controller(struct net_device *dev)
2217 {
2218 disable_irq(dev->irq);
2219 rtl8139_interrupt(dev->irq, dev);
2220 enable_irq(dev->irq);
2221 }
2222 #endif
2223
2224 static int rtl8139_close (struct net_device *dev)
2225 {
2226 struct rtl8139_private *tp = netdev_priv(dev);
2227 void __iomem *ioaddr = tp->mmio_addr;
2228 unsigned long flags;
2229
2230 netif_stop_queue (dev);
2231
2232 if (netif_msg_ifdown(tp))
2233 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2234 dev->name, RTL_R16 (IntrStatus));
2235
2236 spin_lock_irqsave (&tp->lock, flags);
2237
2238 /* Stop the chip's Tx and Rx DMA processes. */
2239 RTL_W8 (ChipCmd, 0);
2240
2241 /* Disable interrupts by clearing the interrupt mask. */
2242 RTL_W16 (IntrMask, 0);
2243
2244 /* Update the error counts. */
2245 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2246 RTL_W32 (RxMissed, 0);
2247
2248 spin_unlock_irqrestore (&tp->lock, flags);
2249
2250 synchronize_irq (dev->irq); /* racy, but that's ok here */
2251 free_irq (dev->irq, dev);
2252
2253 rtl8139_tx_clear (tp);
2254
2255 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2256 tp->rx_ring, tp->rx_ring_dma);
2257 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2258 tp->tx_bufs, tp->tx_bufs_dma);
2259 tp->rx_ring = NULL;
2260 tp->tx_bufs = NULL;
2261
2262 /* Green! Put the chip in low-power mode. */
2263 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2264
2265 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2266 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2267
2268 return 0;
2269 }
2270
2271
2272 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2273 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2274 other threads or interrupts aren't messing with the 8139. */
2275 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2276 {
2277 struct rtl8139_private *np = netdev_priv(dev);
2278 void __iomem *ioaddr = np->mmio_addr;
2279
2280 spin_lock_irq(&np->lock);
2281 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2282 u8 cfg3 = RTL_R8 (Config3);
2283 u8 cfg5 = RTL_R8 (Config5);
2284
2285 wol->supported = WAKE_PHY | WAKE_MAGIC
2286 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2287
2288 wol->wolopts = 0;
2289 if (cfg3 & Cfg3_LinkUp)
2290 wol->wolopts |= WAKE_PHY;
2291 if (cfg3 & Cfg3_Magic)
2292 wol->wolopts |= WAKE_MAGIC;
2293 /* (KON)FIXME: See how netdev_set_wol() handles the
2294 following constants. */
2295 if (cfg5 & Cfg5_UWF)
2296 wol->wolopts |= WAKE_UCAST;
2297 if (cfg5 & Cfg5_MWF)
2298 wol->wolopts |= WAKE_MCAST;
2299 if (cfg5 & Cfg5_BWF)
2300 wol->wolopts |= WAKE_BCAST;
2301 }
2302 spin_unlock_irq(&np->lock);
2303 }
2304
2305
2306 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2307 that wol points to kernel memory and other threads or interrupts
2308 aren't messing with the 8139. */
2309 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2310 {
2311 struct rtl8139_private *np = netdev_priv(dev);
2312 void __iomem *ioaddr = np->mmio_addr;
2313 u32 support;
2314 u8 cfg3, cfg5;
2315
2316 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2317 ? (WAKE_PHY | WAKE_MAGIC
2318 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2319 : 0);
2320 if (wol->wolopts & ~support)
2321 return -EINVAL;
2322
2323 spin_lock_irq(&np->lock);
2324 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2325 if (wol->wolopts & WAKE_PHY)
2326 cfg3 |= Cfg3_LinkUp;
2327 if (wol->wolopts & WAKE_MAGIC)
2328 cfg3 |= Cfg3_Magic;
2329 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2330 RTL_W8 (Config3, cfg3);
2331 RTL_W8 (Cfg9346, Cfg9346_Lock);
2332
2333 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2334 /* (KON)FIXME: These are untested. We may have to set the
2335 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2336 documentation. */
2337 if (wol->wolopts & WAKE_UCAST)
2338 cfg5 |= Cfg5_UWF;
2339 if (wol->wolopts & WAKE_MCAST)
2340 cfg5 |= Cfg5_MWF;
2341 if (wol->wolopts & WAKE_BCAST)
2342 cfg5 |= Cfg5_BWF;
2343 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2344 spin_unlock_irq(&np->lock);
2345
2346 return 0;
2347 }
2348
2349 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2350 {
2351 struct rtl8139_private *np = netdev_priv(dev);
2352 strcpy(info->driver, DRV_NAME);
2353 strcpy(info->version, DRV_VERSION);
2354 strcpy(info->bus_info, pci_name(np->pci_dev));
2355 info->regdump_len = np->regs_len;
2356 }
2357
2358 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2359 {
2360 struct rtl8139_private *np = netdev_priv(dev);
2361 spin_lock_irq(&np->lock);
2362 mii_ethtool_gset(&np->mii, cmd);
2363 spin_unlock_irq(&np->lock);
2364 return 0;
2365 }
2366
2367 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2368 {
2369 struct rtl8139_private *np = netdev_priv(dev);
2370 int rc;
2371 spin_lock_irq(&np->lock);
2372 rc = mii_ethtool_sset(&np->mii, cmd);
2373 spin_unlock_irq(&np->lock);
2374 return rc;
2375 }
2376
2377 static int rtl8139_nway_reset(struct net_device *dev)
2378 {
2379 struct rtl8139_private *np = netdev_priv(dev);
2380 return mii_nway_restart(&np->mii);
2381 }
2382
2383 static u32 rtl8139_get_link(struct net_device *dev)
2384 {
2385 struct rtl8139_private *np = netdev_priv(dev);
2386 return mii_link_ok(&np->mii);
2387 }
2388
2389 static u32 rtl8139_get_msglevel(struct net_device *dev)
2390 {
2391 struct rtl8139_private *np = netdev_priv(dev);
2392 return np->msg_enable;
2393 }
2394
2395 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2396 {
2397 struct rtl8139_private *np = netdev_priv(dev);
2398 np->msg_enable = datum;
2399 }
2400
2401 /* TODO: we are too slack to do reg dumping for pio, for now */
2402 #ifdef CONFIG_8139TOO_PIO
2403 #define rtl8139_get_regs_len NULL
2404 #define rtl8139_get_regs NULL
2405 #else
2406 static int rtl8139_get_regs_len(struct net_device *dev)
2407 {
2408 struct rtl8139_private *np = netdev_priv(dev);
2409 return np->regs_len;
2410 }
2411
2412 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2413 {
2414 struct rtl8139_private *np = netdev_priv(dev);
2415
2416 regs->version = RTL_REGS_VER;
2417
2418 spin_lock_irq(&np->lock);
2419 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2420 spin_unlock_irq(&np->lock);
2421 }
2422 #endif /* CONFIG_8139TOO_MMIO */
2423
2424 static int rtl8139_get_stats_count(struct net_device *dev)
2425 {
2426 return RTL_NUM_STATS;
2427 }
2428
2429 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2430 {
2431 struct rtl8139_private *np = netdev_priv(dev);
2432
2433 data[0] = np->xstats.early_rx;
2434 data[1] = np->xstats.tx_buf_mapped;
2435 data[2] = np->xstats.tx_timeouts;
2436 data[3] = np->xstats.rx_lost_in_ring;
2437 }
2438
2439 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2440 {
2441 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2442 }
2443
2444 static const struct ethtool_ops rtl8139_ethtool_ops = {
2445 .get_drvinfo = rtl8139_get_drvinfo,
2446 .get_settings = rtl8139_get_settings,
2447 .set_settings = rtl8139_set_settings,
2448 .get_regs_len = rtl8139_get_regs_len,
2449 .get_regs = rtl8139_get_regs,
2450 .nway_reset = rtl8139_nway_reset,
2451 .get_link = rtl8139_get_link,
2452 .get_msglevel = rtl8139_get_msglevel,
2453 .set_msglevel = rtl8139_set_msglevel,
2454 .get_wol = rtl8139_get_wol,
2455 .set_wol = rtl8139_set_wol,
2456 .get_strings = rtl8139_get_strings,
2457 .get_stats_count = rtl8139_get_stats_count,
2458 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2459 .get_perm_addr = ethtool_op_get_perm_addr,
2460 };
2461
2462 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2463 {
2464 struct rtl8139_private *np = netdev_priv(dev);
2465 int rc;
2466
2467 if (!netif_running(dev))
2468 return -EINVAL;
2469
2470 spin_lock_irq(&np->lock);
2471 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2472 spin_unlock_irq(&np->lock);
2473
2474 return rc;
2475 }
2476
2477
2478 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2479 {
2480 struct rtl8139_private *tp = netdev_priv(dev);
2481 void __iomem *ioaddr = tp->mmio_addr;
2482 unsigned long flags;
2483
2484 if (netif_running(dev)) {
2485 spin_lock_irqsave (&tp->lock, flags);
2486 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2487 RTL_W32 (RxMissed, 0);
2488 spin_unlock_irqrestore (&tp->lock, flags);
2489 }
2490
2491 return &tp->stats;
2492 }
2493
2494 /* Set or clear the multicast filter for this adaptor.
2495 This routine is not state sensitive and need not be SMP locked. */
2496
2497 static void __set_rx_mode (struct net_device *dev)
2498 {
2499 struct rtl8139_private *tp = netdev_priv(dev);
2500 void __iomem *ioaddr = tp->mmio_addr;
2501 u32 mc_filter[2]; /* Multicast hash filter */
2502 int i, rx_mode;
2503 u32 tmp;
2504
2505 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2506 dev->name, dev->flags, RTL_R32 (RxConfig));
2507
2508 /* Note: do not reorder, GCC is clever about common statements. */
2509 if (dev->flags & IFF_PROMISC) {
2510 rx_mode =
2511 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2512 AcceptAllPhys;
2513 mc_filter[1] = mc_filter[0] = 0xffffffff;
2514 } else if ((dev->mc_count > multicast_filter_limit)
2515 || (dev->flags & IFF_ALLMULTI)) {
2516 /* Too many to filter perfectly -- accept all multicasts. */
2517 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2518 mc_filter[1] = mc_filter[0] = 0xffffffff;
2519 } else {
2520 struct dev_mc_list *mclist;
2521 rx_mode = AcceptBroadcast | AcceptMyPhys;
2522 mc_filter[1] = mc_filter[0] = 0;
2523 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2524 i++, mclist = mclist->next) {
2525 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2526
2527 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2528 rx_mode |= AcceptMulticast;
2529 }
2530 }
2531
2532 /* We can safely update without stopping the chip. */
2533 tmp = rtl8139_rx_config | rx_mode;
2534 if (tp->rx_config != tmp) {
2535 RTL_W32_F (RxConfig, tmp);
2536 tp->rx_config = tmp;
2537 }
2538 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2539 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2540 }
2541
2542 static void rtl8139_set_rx_mode (struct net_device *dev)
2543 {
2544 unsigned long flags;
2545 struct rtl8139_private *tp = netdev_priv(dev);
2546
2547 spin_lock_irqsave (&tp->lock, flags);
2548 __set_rx_mode(dev);
2549 spin_unlock_irqrestore (&tp->lock, flags);
2550 }
2551
2552 #ifdef CONFIG_PM
2553
2554 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2555 {
2556 struct net_device *dev = pci_get_drvdata (pdev);
2557 struct rtl8139_private *tp = netdev_priv(dev);
2558 void __iomem *ioaddr = tp->mmio_addr;
2559 unsigned long flags;
2560
2561 pci_save_state (pdev);
2562
2563 if (!netif_running (dev))
2564 return 0;
2565
2566 netif_device_detach (dev);
2567
2568 spin_lock_irqsave (&tp->lock, flags);
2569
2570 /* Disable interrupts, stop Tx and Rx. */
2571 RTL_W16 (IntrMask, 0);
2572 RTL_W8 (ChipCmd, 0);
2573
2574 /* Update the error counts. */
2575 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2576 RTL_W32 (RxMissed, 0);
2577
2578 spin_unlock_irqrestore (&tp->lock, flags);
2579
2580 pci_set_power_state (pdev, PCI_D3hot);
2581
2582 return 0;
2583 }
2584
2585
2586 static int rtl8139_resume (struct pci_dev *pdev)
2587 {
2588 struct net_device *dev = pci_get_drvdata (pdev);
2589
2590 pci_restore_state (pdev);
2591 if (!netif_running (dev))
2592 return 0;
2593 pci_set_power_state (pdev, PCI_D0);
2594 rtl8139_init_ring (dev);
2595 rtl8139_hw_start (dev);
2596 netif_device_attach (dev);
2597 return 0;
2598 }
2599
2600 #endif /* CONFIG_PM */
2601
2602
2603 static struct pci_driver rtl8139_pci_driver = {
2604 .name = DRV_NAME,
2605 .id_table = rtl8139_pci_tbl,
2606 .probe = rtl8139_init_one,
2607 .remove = __devexit_p(rtl8139_remove_one),
2608 #ifdef CONFIG_PM
2609 .suspend = rtl8139_suspend,
2610 .resume = rtl8139_resume,
2611 #endif /* CONFIG_PM */
2612 };
2613
2614
2615 static int __init rtl8139_init_module (void)
2616 {
2617 /* when we're a module, we always print a version message,
2618 * even if no 8139 board is found.
2619 */
2620 #ifdef MODULE
2621 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2622 #endif
2623
2624 return pci_register_driver(&rtl8139_pci_driver);
2625 }
2626
2627
2628 static void __exit rtl8139_cleanup_module (void)
2629 {
2630 pci_unregister_driver (&rtl8139_pci_driver);
2631 }
2632
2633
2634 module_init(rtl8139_init_module);
2635 module_exit(rtl8139_cleanup_module);
Linux with added FPC-III support