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Linux 2.6.20.7
[linux/fpc-iii.git] / drivers / net / arm / ep93xx_eth.c
blobdd698b033a6200070c54d908eb21cc8101a2e2ab
1 /*
2 * EP93xx ethernet network device driver
3 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
4 * Dedicated to Marija Kulikova.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #include <linux/dma-mapping.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/mii.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/init.h>
20 #include <linux/moduleparam.h>
21 #include <linux/platform_device.h>
22 #include <linux/delay.h>
23 #include <asm/arch/ep93xx-regs.h>
24 #include <asm/arch/platform.h>
25 #include <asm/io.h>
26
27 #define DRV_MODULE_NAME "ep93xx-eth"
28 #define DRV_MODULE_VERSION "0.1"
29
30 #define RX_QUEUE_ENTRIES 64
31 #define TX_QUEUE_ENTRIES 8
32
33 #define MAX_PKT_SIZE 2044
34 #define PKT_BUF_SIZE 2048
35
36 #define REG_RXCTL 0x0000
37 #define REG_RXCTL_DEFAULT 0x00073800
38 #define REG_TXCTL 0x0004
39 #define REG_TXCTL_ENABLE 0x00000001
40 #define REG_MIICMD 0x0010
41 #define REG_MIICMD_READ 0x00008000
42 #define REG_MIICMD_WRITE 0x00004000
43 #define REG_MIIDATA 0x0014
44 #define REG_MIISTS 0x0018
45 #define REG_MIISTS_BUSY 0x00000001
46 #define REG_SELFCTL 0x0020
47 #define REG_SELFCTL_RESET 0x00000001
48 #define REG_INTEN 0x0024
49 #define REG_INTEN_TX 0x00000008
50 #define REG_INTEN_RX 0x00000007
51 #define REG_INTSTSP 0x0028
52 #define REG_INTSTS_TX 0x00000008
53 #define REG_INTSTS_RX 0x00000004
54 #define REG_INTSTSC 0x002c
55 #define REG_AFP 0x004c
56 #define REG_INDAD0 0x0050
57 #define REG_INDAD1 0x0051
58 #define REG_INDAD2 0x0052
59 #define REG_INDAD3 0x0053
60 #define REG_INDAD4 0x0054
61 #define REG_INDAD5 0x0055
62 #define REG_GIINTMSK 0x0064
63 #define REG_GIINTMSK_ENABLE 0x00008000
64 #define REG_BMCTL 0x0080
65 #define REG_BMCTL_ENABLE_TX 0x00000100
66 #define REG_BMCTL_ENABLE_RX 0x00000001
67 #define REG_BMSTS 0x0084
68 #define REG_BMSTS_RX_ACTIVE 0x00000008
69 #define REG_RXDQBADD 0x0090
70 #define REG_RXDQBLEN 0x0094
71 #define REG_RXDCURADD 0x0098
72 #define REG_RXDENQ 0x009c
73 #define REG_RXSTSQBADD 0x00a0
74 #define REG_RXSTSQBLEN 0x00a4
75 #define REG_RXSTSQCURADD 0x00a8
76 #define REG_RXSTSENQ 0x00ac
77 #define REG_TXDQBADD 0x00b0
78 #define REG_TXDQBLEN 0x00b4
79 #define REG_TXDQCURADD 0x00b8
80 #define REG_TXDENQ 0x00bc
81 #define REG_TXSTSQBADD 0x00c0
82 #define REG_TXSTSQBLEN 0x00c4
83 #define REG_TXSTSQCURADD 0x00c8
84 #define REG_MAXFRMLEN 0x00e8
85
86 struct ep93xx_rdesc
87 {
88 u32 buf_addr;
89 u32 rdesc1;
90 };
91
92 #define RDESC1_NSOF 0x80000000
93 #define RDESC1_BUFFER_INDEX 0x7fff0000
94 #define RDESC1_BUFFER_LENGTH 0x0000ffff
95
96 struct ep93xx_rstat
97 {
98 u32 rstat0;
99 u32 rstat1;
100 };
101
102 #define RSTAT0_RFP 0x80000000
103 #define RSTAT0_RWE 0x40000000
104 #define RSTAT0_EOF 0x20000000
105 #define RSTAT0_EOB 0x10000000
106 #define RSTAT0_AM 0x00c00000
107 #define RSTAT0_RX_ERR 0x00200000
108 #define RSTAT0_OE 0x00100000
109 #define RSTAT0_FE 0x00080000
110 #define RSTAT0_RUNT 0x00040000
111 #define RSTAT0_EDATA 0x00020000
112 #define RSTAT0_CRCE 0x00010000
113 #define RSTAT0_CRCI 0x00008000
114 #define RSTAT0_HTI 0x00003f00
115 #define RSTAT1_RFP 0x80000000
116 #define RSTAT1_BUFFER_INDEX 0x7fff0000
117 #define RSTAT1_FRAME_LENGTH 0x0000ffff
118
119 struct ep93xx_tdesc
120 {
121 u32 buf_addr;
122 u32 tdesc1;
123 };
124
125 #define TDESC1_EOF 0x80000000
126 #define TDESC1_BUFFER_INDEX 0x7fff0000
127 #define TDESC1_BUFFER_ABORT 0x00008000
128 #define TDESC1_BUFFER_LENGTH 0x00000fff
129
130 struct ep93xx_tstat
131 {
132 u32 tstat0;
133 };
134
135 #define TSTAT0_TXFP 0x80000000
136 #define TSTAT0_TXWE 0x40000000
137 #define TSTAT0_FA 0x20000000
138 #define TSTAT0_LCRS 0x10000000
139 #define TSTAT0_OW 0x04000000
140 #define TSTAT0_TXU 0x02000000
141 #define TSTAT0_ECOLL 0x01000000
142 #define TSTAT0_NCOLL 0x001f0000
143 #define TSTAT0_BUFFER_INDEX 0x00007fff
144
145 struct ep93xx_descs
146 {
147 struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES];
148 struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES];
149 struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES];
150 struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES];
151 };
152
153 struct ep93xx_priv
154 {
155 struct resource *res;
156 void *base_addr;
157 int irq;
158
159 struct ep93xx_descs *descs;
160 dma_addr_t descs_dma_addr;
161
162 void *rx_buf[RX_QUEUE_ENTRIES];
163 void *tx_buf[TX_QUEUE_ENTRIES];
164
165 spinlock_t rx_lock;
166 unsigned int rx_pointer;
167 unsigned int tx_clean_pointer;
168 unsigned int tx_pointer;
169 spinlock_t tx_pending_lock;
170 unsigned int tx_pending;
171
172 struct net_device_stats stats;
173
174 struct mii_if_info mii;
175 u8 mdc_divisor;
176 };
177
178 #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
179 #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
180 #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
181 #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
182 #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
183 #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
184
185 static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg);
186
187 static struct net_device_stats *ep93xx_get_stats(struct net_device *dev)
188 {
189 struct ep93xx_priv *ep = netdev_priv(dev);
190 return &(ep->stats);
191 }
192
193 static int ep93xx_rx(struct net_device *dev, int *budget)
194 {
195 struct ep93xx_priv *ep = netdev_priv(dev);
196 int rx_done;
197 int processed;
198
199 rx_done = 0;
200 processed = 0;
201 while (*budget > 0) {
202 int entry;
203 struct ep93xx_rstat *rstat;
204 u32 rstat0;
205 u32 rstat1;
206 int length;
207 struct sk_buff *skb;
208
209 entry = ep->rx_pointer;
210 rstat = ep->descs->rstat + entry;
211
212 rstat0 = rstat->rstat0;
213 rstat1 = rstat->rstat1;
214 if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP)) {
215 rx_done = 1;
216 break;
217 }
218
219 rstat->rstat0 = 0;
220 rstat->rstat1 = 0;
221
222 if (!(rstat0 & RSTAT0_EOF))
223 printk(KERN_CRIT "ep93xx_rx: not end-of-frame "
224 " %.8x %.8x\n", rstat0, rstat1);
225 if (!(rstat0 & RSTAT0_EOB))
226 printk(KERN_CRIT "ep93xx_rx: not end-of-buffer "
227 " %.8x %.8x\n", rstat0, rstat1);
228 if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry)
229 printk(KERN_CRIT "ep93xx_rx: entry mismatch "
230 " %.8x %.8x\n", rstat0, rstat1);
231
232 if (!(rstat0 & RSTAT0_RWE)) {
233 ep->stats.rx_errors++;
234 if (rstat0 & RSTAT0_OE)
235 ep->stats.rx_fifo_errors++;
236 if (rstat0 & RSTAT0_FE)
237 ep->stats.rx_frame_errors++;
238 if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA))
239 ep->stats.rx_length_errors++;
240 if (rstat0 & RSTAT0_CRCE)
241 ep->stats.rx_crc_errors++;
242 goto err;
243 }
244
245 length = rstat1 & RSTAT1_FRAME_LENGTH;
246 if (length > MAX_PKT_SIZE) {
247 printk(KERN_NOTICE "ep93xx_rx: invalid length "
248 " %.8x %.8x\n", rstat0, rstat1);
249 goto err;
250 }
251
252 /* Strip FCS. */
253 if (rstat0 & RSTAT0_CRCI)
254 length -= 4;
255
256 skb = dev_alloc_skb(length + 2);
257 if (likely(skb != NULL)) {
258 skb->dev = dev;
259 skb_reserve(skb, 2);
260 dma_sync_single(NULL, ep->descs->rdesc[entry].buf_addr,
261 length, DMA_FROM_DEVICE);
262 eth_copy_and_sum(skb, ep->rx_buf[entry], length, 0);
263 skb_put(skb, length);
264 skb->protocol = eth_type_trans(skb, dev);
265
266 dev->last_rx = jiffies;
267
268 netif_receive_skb(skb);
269
270 ep->stats.rx_packets++;
271 ep->stats.rx_bytes += length;
272 } else {
273 ep->stats.rx_dropped++;
274 }
275
276 err:
277 ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1);
278 processed++;
279 dev->quota--;
280 (*budget)--;
281 }
282
283 if (processed) {
284 wrw(ep, REG_RXDENQ, processed);
285 wrw(ep, REG_RXSTSENQ, processed);
286 }
287
288 return !rx_done;
289 }
290
291 static int ep93xx_have_more_rx(struct ep93xx_priv *ep)
292 {
293 struct ep93xx_rstat *rstat = ep->descs->rstat + ep->rx_pointer;
294 return !!((rstat->rstat0 & RSTAT0_RFP) && (rstat->rstat1 & RSTAT1_RFP));
295 }
296
297 static int ep93xx_poll(struct net_device *dev, int *budget)
298 {
299 struct ep93xx_priv *ep = netdev_priv(dev);
300
301 /*
302 * @@@ Have to stop polling if device is downed while we
303 * are polling.
304 */
305
306 poll_some_more:
307 if (ep93xx_rx(dev, budget))
308 return 1;
309
310 netif_rx_complete(dev);
311
312 spin_lock_irq(&ep->rx_lock);
313 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
314 if (ep93xx_have_more_rx(ep)) {
315 wrl(ep, REG_INTEN, REG_INTEN_TX);
316 wrl(ep, REG_INTSTSP, REG_INTSTS_RX);
317 spin_unlock_irq(&ep->rx_lock);
318
319 if (netif_rx_reschedule(dev, 0))
320 goto poll_some_more;
321
322 return 0;
323 }
324 spin_unlock_irq(&ep->rx_lock);
325
326 return 0;
327 }
328
329 static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
330 {
331 struct ep93xx_priv *ep = netdev_priv(dev);
332 int entry;
333
334 if (unlikely(skb->len > MAX_PKT_SIZE)) {
335 ep->stats.tx_dropped++;
336 dev_kfree_skb(skb);
337 return NETDEV_TX_OK;
338 }
339
340 entry = ep->tx_pointer;
341 ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1);
342
343 ep->descs->tdesc[entry].tdesc1 =
344 TDESC1_EOF | (entry << 16) | (skb->len & 0xfff);
345 skb_copy_and_csum_dev(skb, ep->tx_buf[entry]);
346 dma_sync_single(NULL, ep->descs->tdesc[entry].buf_addr,
347 skb->len, DMA_TO_DEVICE);
348 dev_kfree_skb(skb);
349
350 dev->trans_start = jiffies;
351
352 spin_lock_irq(&ep->tx_pending_lock);
353 ep->tx_pending++;
354 if (ep->tx_pending == TX_QUEUE_ENTRIES)
355 netif_stop_queue(dev);
356 spin_unlock_irq(&ep->tx_pending_lock);
357
358 wrl(ep, REG_TXDENQ, 1);
359
360 return NETDEV_TX_OK;
361 }
362
363 static void ep93xx_tx_complete(struct net_device *dev)
364 {
365 struct ep93xx_priv *ep = netdev_priv(dev);
366 int wake;
367
368 wake = 0;
369
370 spin_lock(&ep->tx_pending_lock);
371 while (1) {
372 int entry;
373 struct ep93xx_tstat *tstat;
374 u32 tstat0;
375
376 entry = ep->tx_clean_pointer;
377 tstat = ep->descs->tstat + entry;
378
379 tstat0 = tstat->tstat0;
380 if (!(tstat0 & TSTAT0_TXFP))
381 break;
382
383 tstat->tstat0 = 0;
384
385 if (tstat0 & TSTAT0_FA)
386 printk(KERN_CRIT "ep93xx_tx_complete: frame aborted "
387 " %.8x\n", tstat0);
388 if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry)
389 printk(KERN_CRIT "ep93xx_tx_complete: entry mismatch "
390 " %.8x\n", tstat0);
391
392 if (tstat0 & TSTAT0_TXWE) {
393 int length = ep->descs->tdesc[entry].tdesc1 & 0xfff;
394
395 ep->stats.tx_packets++;
396 ep->stats.tx_bytes += length;
397 } else {
398 ep->stats.tx_errors++;
399 }
400
401 if (tstat0 & TSTAT0_OW)
402 ep->stats.tx_window_errors++;
403 if (tstat0 & TSTAT0_TXU)
404 ep->stats.tx_fifo_errors++;
405 ep->stats.collisions += (tstat0 >> 16) & 0x1f;
406
407 ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1);
408 if (ep->tx_pending == TX_QUEUE_ENTRIES)
409 wake = 1;
410 ep->tx_pending--;
411 }
412 spin_unlock(&ep->tx_pending_lock);
413
414 if (wake)
415 netif_wake_queue(dev);
416 }
417
418 static irqreturn_t ep93xx_irq(int irq, void *dev_id)
419 {
420 struct net_device *dev = dev_id;
421 struct ep93xx_priv *ep = netdev_priv(dev);
422 u32 status;
423
424 status = rdl(ep, REG_INTSTSC);
425 if (status == 0)
426 return IRQ_NONE;
427
428 if (status & REG_INTSTS_RX) {
429 spin_lock(&ep->rx_lock);
430 if (likely(__netif_rx_schedule_prep(dev))) {
431 wrl(ep, REG_INTEN, REG_INTEN_TX);
432 __netif_rx_schedule(dev);
433 }
434 spin_unlock(&ep->rx_lock);
435 }
436
437 if (status & REG_INTSTS_TX)
438 ep93xx_tx_complete(dev);
439
440 return IRQ_HANDLED;
441 }
442
443 static void ep93xx_free_buffers(struct ep93xx_priv *ep)
444 {
445 int i;
446
447 for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) {
448 dma_addr_t d;
449
450 d = ep->descs->rdesc[i].buf_addr;
451 if (d)
452 dma_unmap_single(NULL, d, PAGE_SIZE, DMA_FROM_DEVICE);
453
454 if (ep->rx_buf[i] != NULL)
455 free_page((unsigned long)ep->rx_buf[i]);
456 }
457
458 for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) {
459 dma_addr_t d;
460
461 d = ep->descs->tdesc[i].buf_addr;
462 if (d)
463 dma_unmap_single(NULL, d, PAGE_SIZE, DMA_TO_DEVICE);
464
465 if (ep->tx_buf[i] != NULL)
466 free_page((unsigned long)ep->tx_buf[i]);
467 }
468
469 dma_free_coherent(NULL, sizeof(struct ep93xx_descs), ep->descs,
470 ep->descs_dma_addr);
471 }
472
473 /*
474 * The hardware enforces a sub-2K maximum packet size, so we put
475 * two buffers on every hardware page.
476 */
477 static int ep93xx_alloc_buffers(struct ep93xx_priv *ep)
478 {
479 int i;
480
481 ep->descs = dma_alloc_coherent(NULL, sizeof(struct ep93xx_descs),
482 &ep->descs_dma_addr, GFP_KERNEL | GFP_DMA);
483 if (ep->descs == NULL)
484 return 1;
485
486 for (i = 0; i < RX_QUEUE_ENTRIES; i += 2) {
487 void *page;
488 dma_addr_t d;
489
490 page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
491 if (page == NULL)
492 goto err;
493
494 d = dma_map_single(NULL, page, PAGE_SIZE, DMA_FROM_DEVICE);
495 if (dma_mapping_error(d)) {
496 free_page((unsigned long)page);
497 goto err;
498 }
499
500 ep->rx_buf[i] = page;
501 ep->descs->rdesc[i].buf_addr = d;
502 ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE;
503
504 ep->rx_buf[i + 1] = page + PKT_BUF_SIZE;
505 ep->descs->rdesc[i + 1].buf_addr = d + PKT_BUF_SIZE;
506 ep->descs->rdesc[i + 1].rdesc1 = ((i + 1) << 16) | PKT_BUF_SIZE;
507 }
508
509 for (i = 0; i < TX_QUEUE_ENTRIES; i += 2) {
510 void *page;
511 dma_addr_t d;
512
513 page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
514 if (page == NULL)
515 goto err;
516
517 d = dma_map_single(NULL, page, PAGE_SIZE, DMA_TO_DEVICE);
518 if (dma_mapping_error(d)) {
519 free_page((unsigned long)page);
520 goto err;
521 }
522
523 ep->tx_buf[i] = page;
524 ep->descs->tdesc[i].buf_addr = d;
525
526 ep->tx_buf[i + 1] = page + PKT_BUF_SIZE;
527 ep->descs->tdesc[i + 1].buf_addr = d + PKT_BUF_SIZE;
528 }
529
530 return 0;
531
532 err:
533 ep93xx_free_buffers(ep);
534 return 1;
535 }
536
537 static int ep93xx_start_hw(struct net_device *dev)
538 {
539 struct ep93xx_priv *ep = netdev_priv(dev);
540 unsigned long addr;
541 int i;
542
543 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
544 for (i = 0; i < 10; i++) {
545 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
546 break;
547 msleep(1);
548 }
549
550 if (i == 10) {
551 printk(KERN_CRIT DRV_MODULE_NAME ": hw failed to reset\n");
552 return 1;
553 }
554
555 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
556
557 /* Does the PHY support preamble suppress? */
558 if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0)
559 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
560
561 /* Receive descriptor ring. */
562 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc);
563 wrl(ep, REG_RXDQBADD, addr);
564 wrl(ep, REG_RXDCURADD, addr);
565 wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc));
566
567 /* Receive status ring. */
568 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat);
569 wrl(ep, REG_RXSTSQBADD, addr);
570 wrl(ep, REG_RXSTSQCURADD, addr);
571 wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat));
572
573 /* Transmit descriptor ring. */
574 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc);
575 wrl(ep, REG_TXDQBADD, addr);
576 wrl(ep, REG_TXDQCURADD, addr);
577 wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc));
578
579 /* Transmit status ring. */
580 addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat);
581 wrl(ep, REG_TXSTSQBADD, addr);
582 wrl(ep, REG_TXSTSQCURADD, addr);
583 wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat));
584
585 wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
586 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
587 wrl(ep, REG_GIINTMSK, 0);
588
589 for (i = 0; i < 10; i++) {
590 if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0)
591 break;
592 msleep(1);
593 }
594
595 if (i == 10) {
596 printk(KERN_CRIT DRV_MODULE_NAME ": hw failed to start\n");
597 return 1;
598 }
599
600 wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
601 wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
602
603 wrb(ep, REG_INDAD0, dev->dev_addr[0]);
604 wrb(ep, REG_INDAD1, dev->dev_addr[1]);
605 wrb(ep, REG_INDAD2, dev->dev_addr[2]);
606 wrb(ep, REG_INDAD3, dev->dev_addr[3]);
607 wrb(ep, REG_INDAD4, dev->dev_addr[4]);
608 wrb(ep, REG_INDAD5, dev->dev_addr[5]);
609 wrl(ep, REG_AFP, 0);
610
611 wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
612
613 wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
614 wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
615
616 return 0;
617 }
618
619 static void ep93xx_stop_hw(struct net_device *dev)
620 {
621 struct ep93xx_priv *ep = netdev_priv(dev);
622 int i;
623
624 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
625 for (i = 0; i < 10; i++) {
626 if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
627 break;
628 msleep(1);
629 }
630
631 if (i == 10)
632 printk(KERN_CRIT DRV_MODULE_NAME ": hw failed to reset\n");
633 }
634
635 static int ep93xx_open(struct net_device *dev)
636 {
637 struct ep93xx_priv *ep = netdev_priv(dev);
638 int err;
639
640 if (ep93xx_alloc_buffers(ep))
641 return -ENOMEM;
642
643 if (is_zero_ether_addr(dev->dev_addr)) {
644 random_ether_addr(dev->dev_addr);
645 printk(KERN_INFO "%s: generated random MAC address "
646 "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x.\n", dev->name,
647 dev->dev_addr[0], dev->dev_addr[1],
648 dev->dev_addr[2], dev->dev_addr[3],
649 dev->dev_addr[4], dev->dev_addr[5]);
650 }
651
652 if (ep93xx_start_hw(dev)) {
653 ep93xx_free_buffers(ep);
654 return -EIO;
655 }
656
657 spin_lock_init(&ep->rx_lock);
658 ep->rx_pointer = 0;
659 ep->tx_clean_pointer = 0;
660 ep->tx_pointer = 0;
661 spin_lock_init(&ep->tx_pending_lock);
662 ep->tx_pending = 0;
663
664 err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev);
665 if (err) {
666 ep93xx_stop_hw(dev);
667 ep93xx_free_buffers(ep);
668 return err;
669 }
670
671 wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
672
673 netif_start_queue(dev);
674
675 return 0;
676 }
677
678 static int ep93xx_close(struct net_device *dev)
679 {
680 struct ep93xx_priv *ep = netdev_priv(dev);
681
682 netif_stop_queue(dev);
683
684 wrl(ep, REG_GIINTMSK, 0);
685 free_irq(ep->irq, dev);
686 ep93xx_stop_hw(dev);
687 ep93xx_free_buffers(ep);
688
689 return 0;
690 }
691
692 static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
693 {
694 struct ep93xx_priv *ep = netdev_priv(dev);
695 struct mii_ioctl_data *data = if_mii(ifr);
696
697 return generic_mii_ioctl(&ep->mii, data, cmd, NULL);
698 }
699
700 static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg)
701 {
702 struct ep93xx_priv *ep = netdev_priv(dev);
703 int data;
704 int i;
705
706 wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
707
708 for (i = 0; i < 10; i++) {
709 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
710 break;
711 msleep(1);
712 }
713
714 if (i == 10) {
715 printk(KERN_INFO DRV_MODULE_NAME ": mdio read timed out\n");
716 data = 0xffff;
717 } else {
718 data = rdl(ep, REG_MIIDATA);
719 }
720
721 return data;
722 }
723
724 static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data)
725 {
726 struct ep93xx_priv *ep = netdev_priv(dev);
727 int i;
728
729 wrl(ep, REG_MIIDATA, data);
730 wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
731
732 for (i = 0; i < 10; i++) {
733 if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
734 break;
735 msleep(1);
736 }
737
738 if (i == 10)
739 printk(KERN_INFO DRV_MODULE_NAME ": mdio write timed out\n");
740 }
741
742 static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
743 {
744 strcpy(info->driver, DRV_MODULE_NAME);
745 strcpy(info->version, DRV_MODULE_VERSION);
746 }
747
748 static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
749 {
750 struct ep93xx_priv *ep = netdev_priv(dev);
751 return mii_ethtool_gset(&ep->mii, cmd);
752 }
753
754 static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
755 {
756 struct ep93xx_priv *ep = netdev_priv(dev);
757 return mii_ethtool_sset(&ep->mii, cmd);
758 }
759
760 static int ep93xx_nway_reset(struct net_device *dev)
761 {
762 struct ep93xx_priv *ep = netdev_priv(dev);
763 return mii_nway_restart(&ep->mii);
764 }
765
766 static u32 ep93xx_get_link(struct net_device *dev)
767 {
768 struct ep93xx_priv *ep = netdev_priv(dev);
769 return mii_link_ok(&ep->mii);
770 }
771
772 static struct ethtool_ops ep93xx_ethtool_ops = {
773 .get_drvinfo = ep93xx_get_drvinfo,
774 .get_settings = ep93xx_get_settings,
775 .set_settings = ep93xx_set_settings,
776 .nway_reset = ep93xx_nway_reset,
777 .get_link = ep93xx_get_link,
778 };
779
780 struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
781 {
782 struct net_device *dev;
783
784 dev = alloc_etherdev(sizeof(struct ep93xx_priv));
785 if (dev == NULL)
786 return NULL;
787
788 memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN);
789
790 dev->get_stats = ep93xx_get_stats;
791 dev->ethtool_ops = &ep93xx_ethtool_ops;
792 dev->poll = ep93xx_poll;
793 dev->hard_start_xmit = ep93xx_xmit;
794 dev->open = ep93xx_open;
795 dev->stop = ep93xx_close;
796 dev->do_ioctl = ep93xx_ioctl;
797
798 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
799 dev->weight = 64;
800
801 return dev;
802 }
803
804
805 static int ep93xx_eth_remove(struct platform_device *pdev)
806 {
807 struct net_device *dev;
808 struct ep93xx_priv *ep;
809
810 dev = platform_get_drvdata(pdev);
811 if (dev == NULL)
812 return 0;
813 platform_set_drvdata(pdev, NULL);
814
815 ep = netdev_priv(dev);
816
817 /* @@@ Force down. */
818 unregister_netdev(dev);
819 ep93xx_free_buffers(ep);
820
821 if (ep->base_addr != NULL)
822 iounmap(ep->base_addr);
823
824 if (ep->res != NULL) {
825 release_resource(ep->res);
826 kfree(ep->res);
827 }
828
829 free_netdev(dev);
830
831 return 0;
832 }
833
834 static int ep93xx_eth_probe(struct platform_device *pdev)
835 {
836 struct ep93xx_eth_data *data;
837 struct net_device *dev;
838 struct ep93xx_priv *ep;
839 int err;
840
841 if (pdev == NULL)
842 return -ENODEV;
843 data = pdev->dev.platform_data;
844
845 dev = ep93xx_dev_alloc(data);
846 if (dev == NULL) {
847 err = -ENOMEM;
848 goto err_out;
849 }
850 ep = netdev_priv(dev);
851
852 platform_set_drvdata(pdev, dev);
853
854 ep->res = request_mem_region(pdev->resource[0].start,
855 pdev->resource[0].end - pdev->resource[0].start + 1,
856 pdev->dev.bus_id);
857 if (ep->res == NULL) {
858 dev_err(&pdev->dev, "Could not reserve memory region\n");
859 err = -ENOMEM;
860 goto err_out;
861 }
862
863 ep->base_addr = ioremap(pdev->resource[0].start,
864 pdev->resource[0].end - pdev->resource[0].start);
865 if (ep->base_addr == NULL) {
866 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
867 err = -EIO;
868 goto err_out;
869 }
870 ep->irq = pdev->resource[1].start;
871
872 ep->mii.phy_id = data->phy_id;
873 ep->mii.phy_id_mask = 0x1f;
874 ep->mii.reg_num_mask = 0x1f;
875 ep->mii.dev = dev;
876 ep->mii.mdio_read = ep93xx_mdio_read;
877 ep->mii.mdio_write = ep93xx_mdio_write;
878 ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
879
880 err = register_netdev(dev);
881 if (err) {
882 dev_err(&pdev->dev, "Failed to register netdev\n");
883 goto err_out;
884 }
885
886 printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, "
887 "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x.\n", dev->name,
888 ep->irq, data->dev_addr[0], data->dev_addr[1],
889 data->dev_addr[2], data->dev_addr[3],
890 data->dev_addr[4], data->dev_addr[5]);
891
892 return 0;
893
894 err_out:
895 ep93xx_eth_remove(pdev);
896 return err;
897 }
898
899
900 static struct platform_driver ep93xx_eth_driver = {
901 .probe = ep93xx_eth_probe,
902 .remove = ep93xx_eth_remove,
903 .driver = {
904 .name = "ep93xx-eth",
905 },
906 };
907
908 static int __init ep93xx_eth_init_module(void)
909 {
910 printk(KERN_INFO DRV_MODULE_NAME " version " DRV_MODULE_VERSION " loading\n");
911 return platform_driver_register(&ep93xx_eth_driver);
912 }
913
914 static void __exit ep93xx_eth_cleanup_module(void)
915 {
916 platform_driver_unregister(&ep93xx_eth_driver);
917 }
918
919 module_init(ep93xx_eth_init_module);
920 module_exit(ep93xx_eth_cleanup_module);
921 MODULE_LICENSE("GPL");
Linux with added FPC-III support