| blob | dc3ab3b5c8cb8ef48aca9a586e86b566bde0c9b9 |
1 /*
2 * File Name:
3 * defxx.c
4 *
5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996.
7 *
8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License, incorporated herein by reference.
10 *
11 * Abstract:
12 * A Linux device driver supporting the Digital Equipment Corporation
13 * FDDI EISA and PCI controller families. Supported adapters include:
14 *
15 * DEC FDDIcontroller/EISA (DEFEA)
16 * DEC FDDIcontroller/PCI (DEFPA)
17 *
18 * The original author:
19 * LVS Lawrence V. Stefani <lstefani@yahoo.com>
20 *
21 * Maintainers:
22 * macro Maciej W. Rozycki <macro@linux-mips.org>
23 *
24 * Credits:
25 * I'd like to thank Patricia Cross for helping me get started with
26 * Linux, David Davies for a lot of help upgrading and configuring
27 * my development system and for answering many OS and driver
28 * development questions, and Alan Cox for recommendations and
29 * integration help on getting FDDI support into Linux. LVS
30 *
31 * Driver Architecture:
32 * The driver architecture is largely based on previous driver work
33 * for other operating systems. The upper edge interface and
34 * functions were largely taken from existing Linux device drivers
35 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
36 * driver.
37 *
38 * Adapter Probe -
39 * The driver scans for supported EISA adapters by reading the
40 * SLOT ID register for each EISA slot and making a match
41 * against the expected value.
42 *
43 * Bus-Specific Initialization -
44 * This driver currently supports both EISA and PCI controller
45 * families. While the custom DMA chip and FDDI logic is similar
46 * or identical, the bus logic is very different. After
47 * initialization, the only bus-specific differences is in how the
48 * driver enables and disables interrupts. Other than that, the
49 * run-time critical code behaves the same on both families.
50 * It's important to note that both adapter families are configured
51 * to I/O map, rather than memory map, the adapter registers.
52 *
53 * Driver Open/Close -
54 * In the driver open routine, the driver ISR (interrupt service
55 * routine) is registered and the adapter is brought to an
56 * operational state. In the driver close routine, the opposite
57 * occurs; the driver ISR is deregistered and the adapter is
58 * brought to a safe, but closed state. Users may use consecutive
59 * commands to bring the adapter up and down as in the following
60 * example:
61 * ifconfig fddi0 up
62 * ifconfig fddi0 down
63 * ifconfig fddi0 up
64 *
65 * Driver Shutdown -
66 * Apparently, there is no shutdown or halt routine support under
67 * Linux. This routine would be called during "reboot" or
68 * "shutdown" to allow the driver to place the adapter in a safe
69 * state before a warm reboot occurs. To be really safe, the user
70 * should close the adapter before shutdown (eg. ifconfig fddi0 down)
71 * to ensure that the adapter DMA engine is taken off-line. However,
72 * the current driver code anticipates this problem and always issues
73 * a soft reset of the adapter at the beginning of driver initialization.
74 * A future driver enhancement in this area may occur in 2.1.X where
75 * Alan indicated that a shutdown handler may be implemented.
76 *
77 * Interrupt Service Routine -
78 * The driver supports shared interrupts, so the ISR is registered for
79 * each board with the appropriate flag and the pointer to that board's
80 * device structure. This provides the context during interrupt
81 * processing to support shared interrupts and multiple boards.
82 *
83 * Interrupt enabling/disabling can occur at many levels. At the host
84 * end, you can disable system interrupts, or disable interrupts at the
85 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
86 * have a bus-logic chip interrupt enable/disable as well as a DMA
87 * controller interrupt enable/disable.
88 *
89 * The driver currently enables and disables adapter interrupts at the
90 * bus-logic chip and assumes that Linux will take care of clearing or
91 * acknowledging any host-based interrupt chips.
92 *
93 * Control Functions -
94 * Control functions are those used to support functions such as adding
95 * or deleting multicast addresses, enabling or disabling packet
96 * reception filters, or other custom/proprietary commands. Presently,
97 * the driver supports the "get statistics", "set multicast list", and
98 * "set mac address" functions defined by Linux. A list of possible
99 * enhancements include:
100 *
101 * - Custom ioctl interface for executing port interface commands
102 * - Custom ioctl interface for adding unicast addresses to
103 * adapter CAM (to support bridge functions).
104 * - Custom ioctl interface for supporting firmware upgrades.
105 *
106 * Hardware (port interface) Support Routines -
107 * The driver function names that start with "dfx_hw_" represent
108 * low-level port interface routines that are called frequently. They
109 * include issuing a DMA or port control command to the adapter,
110 * resetting the adapter, or reading the adapter state. Since the
111 * driver initialization and run-time code must make calls into the
112 * port interface, these routines were written to be as generic and
113 * usable as possible.
114 *
115 * Receive Path -
116 * The adapter DMA engine supports a 256 entry receive descriptor block
117 * of which up to 255 entries can be used at any given time. The
118 * architecture is a standard producer, consumer, completion model in
119 * which the driver "produces" receive buffers to the adapter, the
120 * adapter "consumes" the receive buffers by DMAing incoming packet data,
121 * and the driver "completes" the receive buffers by servicing the
122 * incoming packet, then "produces" a new buffer and starts the cycle
123 * again. Receive buffers can be fragmented in up to 16 fragments
124 * (descriptor entries). For simplicity, this driver posts
125 * single-fragment receive buffers of 4608 bytes, then allocates a
126 * sk_buff, copies the data, then reposts the buffer. To reduce CPU
127 * utilization, a better approach would be to pass up the receive
128 * buffer (no extra copy) then allocate and post a replacement buffer.
129 * This is a performance enhancement that should be looked into at
130 * some point.
131 *
132 * Transmit Path -
133 * Like the receive path, the adapter DMA engine supports a 256 entry
134 * transmit descriptor block of which up to 255 entries can be used at
135 * any given time. Transmit buffers can be fragmented in up to 255
136 * fragments (descriptor entries). This driver always posts one
137 * fragment per transmit packet request.
138 *
139 * The fragment contains the entire packet from FC to end of data.
140 * Before posting the buffer to the adapter, the driver sets a three-byte
141 * packet request header (PRH) which is required by the Motorola MAC chip
142 * used on the adapters. The PRH tells the MAC the type of token to
143 * receive/send, whether or not to generate and append the CRC, whether
144 * synchronous or asynchronous framing is used, etc. Since the PRH
145 * definition is not necessarily consistent across all FDDI chipsets,
146 * the driver, rather than the common FDDI packet handler routines,
147 * sets these bytes.
148 *
149 * To reduce the amount of descriptor fetches needed per transmit request,
150 * the driver takes advantage of the fact that there are at least three
151 * bytes available before the skb->data field on the outgoing transmit
152 * request. This is guaranteed by having fddi_setup() in net_init.c set
153 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
154 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
155 * bytes which we'll use to store the PRH.
156 *
157 * There's a subtle advantage to adding these pad bytes to the
158 * hard_header_len, it ensures that the data portion of the packet for
159 * an 802.2 SNAP frame is longword aligned. Other FDDI driver
160 * implementations may not need the extra padding and can start copying
161 * or DMAing directly from the FC byte which starts at skb->data. Should
162 * another driver implementation need ADDITIONAL padding, the net_init.c
163 * module should be updated and dev->hard_header_len should be increased.
164 * NOTE: To maintain the alignment on the data portion of the packet,
165 * dev->hard_header_len should always be evenly divisible by 4 and at
166 * least 24 bytes in size.
167 *
168 * Modification History:
169 * Date Name Description
170 * 16-Aug-96 LVS Created.
171 * 20-Aug-96 LVS Updated dfx_probe so that version information
172 * string is only displayed if 1 or more cards are
173 * found. Changed dfx_rcv_queue_process to copy
174 * 3 NULL bytes before FC to ensure that data is
175 * longword aligned in receive buffer.
176 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
177 * LLC group promiscuous mode if multicast list
178 * is too large. LLC individual/group promiscuous
179 * mode is now disabled if IFF_PROMISC flag not set.
180 * dfx_xmt_queue_pkt no longer checks for NULL skb
181 * on Alan Cox recommendation. Added node address
182 * override support.
183 * 12-Sep-96 LVS Reset current address to factory address during
184 * device open. Updated transmit path to post a
185 * single fragment which includes PRH->end of data.
186 * Mar 2000 AC Did various cleanups for 2.3.x
187 * Jun 2000 jgarzik PCI and resource alloc cleanups
188 * Jul 2000 tjeerd Much cleanup and some bug fixes
189 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup
190 * Feb 2001 Skb allocation fixes
191 * Feb 2001 davej PCI enable cleanups.
192 * 04 Aug 2003 macro Converted to the DMA API.
193 * 14 Aug 2004 macro Fix device names reported.
194 * 14 Jun 2005 macro Use irqreturn_t.
195 * 23 Oct 2006 macro Big-endian host support.
196 */
198 /* Include files */
200 #include <linux/module.h>
201 #include <linux/kernel.h>
202 #include <linux/string.h>
203 #include <linux/errno.h>
204 #include <linux/ioport.h>
205 #include <linux/slab.h>
206 #include <linux/interrupt.h>
207 #include <linux/pci.h>
208 #include <linux/delay.h>
209 #include <linux/init.h>
210 #include <linux/netdevice.h>
211 #include <linux/fddidevice.h>
212 #include <linux/skbuff.h>
213 #include <linux/bitops.h>
215 #include <asm/byteorder.h>
216 #include <asm/io.h>
220 /* Version information string should be updated prior to each new release! */
229 #define DYNAMIC_BUFFERS 1
231 #define SKBUFF_RX_COPYBREAK 200
232 /*
233 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
234 * alignment for compatibility with old EISA boards.
235 */
236 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
238 /* Define module-wide (static) routines */
261 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
274 /* Define module-wide (static) variables */
279 /*
280 * =======================
281 * = dfx_port_write_byte =
282 * = dfx_port_read_byte =
283 * = dfx_port_write_long =
284 * = dfx_port_read_long =
285 * =======================
286 *
287 * Overview:
288 * Routines for reading and writing values from/to adapter
289 *
290 * Returns:
291 * None
292 *
293 * Arguments:
294 * bp - pointer to board information
295 * offset - register offset from base I/O address
296 * data - for dfx_port_write_byte and dfx_port_write_long, this
297 * is a value to write.
298 * for dfx_port_read_byte and dfx_port_read_byte, this
299 * is a pointer to store the read value.
300 *
301 * Functional Description:
302 * These routines perform the correct operation to read or write
303 * the adapter register.
304 *
305 * EISA port block base addresses are based on the slot number in which the
306 * controller is installed. For example, if the EISA controller is installed
307 * in slot 4, the port block base address is 0x4000. If the controller is
308 * installed in slot 2, the port block base address is 0x2000, and so on.
309 * This port block can be used to access PDQ, ESIC, and DEFEA on-board
310 * registers using the register offsets defined in DEFXX.H.
311 *
312 * PCI port block base addresses are assigned by the PCI BIOS or system
313 * firmware. There is one 128 byte port block which can be accessed. It
314 * allows for I/O mapping of both PDQ and PFI registers using the register
315 * offsets defined in DEFXX.H.
316 *
317 * Return Codes:
318 * None
319 *
320 * Assumptions:
321 * bp->base_addr is a valid base I/O address for this adapter.
322 * offset is a valid register offset for this adapter.
323 *
324 * Side Effects:
325 * Rather than produce macros for these functions, these routines
326 * are defined using "inline" to ensure that the compiler will
327 * generate inline code and not waste a procedure call and return.
328 * This provides all the benefits of macros, but with the
329 * advantage of strict data type checking.
330 */
335 u8 data
336 )
338 {
342 }
347 u8 *data
348 )
350 {
354 }
359 u32 data
360 )
362 {
366 }
371 u32 *data
372 )
374 {
378 }
381 /*
382 * =============
383 * = dfx_init_one_pci_or_eisa =
384 * =============
385 *
386 * Overview:
387 * Initializes a supported FDDI EISA or PCI controller
388 *
389 * Returns:
390 * Condition code
391 *
392 * Arguments:
393 * pdev - pointer to pci device information (NULL for EISA)
394 * ioaddr - pointer to port (NULL for PCI)
395 *
396 * Functional Description:
397 *
398 * Return Codes:
399 * 0 - This device (fddi0, fddi1, etc) configured successfully
400 * -EBUSY - Failed to get resources, or dfx_driver_init failed.
401 *
402 * Assumptions:
403 * It compiles so it should work :-( (PCI cards do :-)
404 *
405 * Side Effects:
406 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
407 * initialized and the board resources are read and stored in
408 * the device structure.
409 */
411 {
422 }
430 print_name);
432 }
434 /* Enable PCI device. */
439 }
449 print_name)) {
455 }
457 /* Initialize new device structure */
469 /* EISA board */
474 /* PCI board */
479 }
484 }
493 err_out_kfree:
496 #ifndef DYNAMIC_BUFFERS
498 #endif
504 err_out_region:
506 err_out:
509 }
512 {
514 }
517 {
525 /* Scan for FDDI EISA controllers */
528 {
532 {
536 }
537 }
539 }
541 /*
542 * ================
543 * = dfx_bus_init =
544 * ================
545 *
546 * Overview:
547 * Initializes EISA and PCI controller bus-specific logic.
548 *
549 * Returns:
550 * None
551 *
552 * Arguments:
553 * dev - pointer to device information
554 *
555 * Functional Description:
556 * Determine and save adapter IRQ in device table,
557 * then perform bus-specific logic initialization.
558 *
559 * Return Codes:
560 * None
561 *
562 * Assumptions:
563 * dev->base_addr has already been set with the proper
564 * base I/O address for this device.
565 *
566 * Side Effects:
567 * Interrupts are enabled at the adapter bus-specific logic.
568 * Note: Interrupts at the DMA engine (PDQ chip) are not
569 * enabled yet.
570 */
573 {
579 /*
580 * Initialize base I/O address field in bp structure
581 *
582 * Note: bp->base_addr is the same as dev->base_addr.
583 * It's useful because often we'll need to read
584 * or write registers where we already have the
585 * bp pointer instead of the dev pointer. Having
586 * the base address in the bp structure will
587 * save a pointer dereference.
588 *
589 * IMPORTANT!! This field must be defined before
590 * any of the dfx_port_* inline functions are
591 * called.
592 */
596 /* And a pointer back to the net_device struct */
599 /* Initialize adapter based on bus type */
602 {
603 /* Get the interrupt level from the ESIC chip */
607 {
623 }
625 /* Enable access to I/O on the board by writing 0x03 to Function Control Register */
629 /* Set the I/O decode range of the board */
635 /* Enable access to rest of module (including PDQ and packet memory) */
639 /*
640 * Map PDQ registers into I/O space. This is done by clearing a bit
641 * in Burst Holdoff register.
642 */
647 /* Enable interrupts at EISA bus interface chip (ESIC) */
651 }
652 else
653 {
656 /* Get the interrupt level from the PCI Configuration Table */
660 /* Check Latency Timer and set if less than minimal */
664 {
667 }
669 /* Enable interrupts at PCI bus interface chip (PFI) */
672 }
673 }
676 /*
677 * ========================
678 * = dfx_bus_config_check =
679 * ========================
680 *
681 * Overview:
682 * Checks the configuration (burst size, full-duplex, etc.) If any parameters
683 * are illegal, then this routine will set new defaults.
684 *
685 * Returns:
686 * None
687 *
688 * Arguments:
689 * bp - pointer to board information
690 *
691 * Functional Description:
692 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
693 * PDQ, and all FDDI PCI controllers, all values are legal.
694 *
695 * Return Codes:
696 * None
697 *
698 * Assumptions:
699 * dfx_adap_init has NOT been called yet so burst size and other items have
700 * not been set.
701 *
702 * Side Effects:
703 * None
704 */
707 {
714 /* Configuration check only valid for EISA adapter */
717 {
720 /*
721 * First check if revision 2 EISA controller. Rev. 1 cards used
722 * PDQ revision B, so no workaround needed in this case. Rev. 3
723 * cards used PDQ revision E, so no workaround needed in this
724 * case, either. Only Rev. 2 cards used either Rev. D or E
725 * chips, so we must verify the chip revision on Rev. 2 cards.
726 */
729 {
730 /*
731 * Revision 2 FDDI EISA controller found, so let's check PDQ
732 * revision of adapter.
733 */
736 PI_PCTRL_M_SUB_CMD,
737 PI_SUB_CMD_K_PDQ_REV_GET,
741 {
742 /*
743 * Either we couldn't determine the PDQ revision, or
744 * we determined that it is at revision D. In either case,
745 * we need to implement the workaround.
746 */
748 /* Ensure that the burst size is set to 8 longwords or less */
751 {
759 }
761 /* Ensure that full-duplex mode is not enabled */
764 }
765 }
766 }
767 }
770 /*
771 * ===================
772 * = dfx_driver_init =
773 * ===================
774 *
775 * Overview:
776 * Initializes remaining adapter board structure information
777 * and makes sure adapter is in a safe state prior to dfx_open().
778 *
779 * Returns:
780 * Condition code
781 *
782 * Arguments:
783 * dev - pointer to device information
784 * print_name - printable device name
785 *
786 * Functional Description:
787 * This function allocates additional resources such as the host memory
788 * blocks needed by the adapter (eg. descriptor and consumer blocks).
789 * Remaining bus initialization steps are also completed. The adapter
790 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
791 * must call dfx_open() to open the adapter and bring it on-line.
792 *
793 * Return Codes:
794 * DFX_K_SUCCESS - initialization succeeded
795 * DFX_K_FAILURE - initialization failed - could not allocate memory
796 * or read adapter MAC address
797 *
798 * Assumptions:
799 * Memory allocated from pci_alloc_consistent() call is physically
800 * contiguous, locked memory.
801 *
802 * Side Effects:
803 * Adapter is reset and should be in DMA_UNAVAILABLE state before
804 * returning from this routine.
805 */
809 {
818 /* Initialize bus-specific hardware registers */
822 /*
823 * Initialize default values for configurable parameters
824 *
825 * Note: All of these parameters are ones that a user may
826 * want to customize. It'd be nice to break these
827 * out into Space.c or someplace else that's more
828 * accessible/understandable than this file.
829 */
836 /*
837 * Ensure that HW configuration is OK
838 *
839 * Note: Depending on the hardware revision, we may need to modify
840 * some of the configurable parameters to workaround hardware
841 * limitations. We'll perform this configuration check AFTER
842 * setting the parameters to their default values.
843 */
847 /* Disable PDQ interrupts first */
851 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
855 /* Read the factory MAC address from the adapter then save it */
860 print_name);
862 }
869 print_name);
871 }
875 /*
876 * Set current address to factory address
877 *
878 * Note: Node address override support is handled through
879 * dfx_ctl_set_mac_address.
880 */
890 else
898 /*
899 * Get memory for descriptor block, consumer block, and other buffers
900 * that need to be DMA read or written to by the adapter.
901 */
904 PI_CMD_REQ_K_SIZE_MAX +
905 PI_CMD_RSP_K_SIZE_MAX +
906 #ifndef DYNAMIC_BUFFERS
908 #endif
917 }
921 /*
922 * To guarantee the 8K alignment required for the descriptor block, 8K - 1
923 * plus the amount of memory needed was allocated. The physical address
924 * is now 8K aligned. By carving up the memory in a specific order,
925 * we'll guarantee the alignment requirements for all other structures.
926 *
927 * Note: If the assumptions change regarding the non-paged, non-cached,
928 * physically contiguous nature of the memory block or the address
929 * alignments, then we'll need to implement a different algorithm
930 * for allocating the needed memory.
931 */
936 /* Reserve space for descriptor block */
943 /* Reserve space for command request buffer */
950 /* Reserve space for command response buffer */
957 /* Reserve space for the LLC host receive queue buffers */
962 #ifndef DYNAMIC_BUFFERS
965 #endif
967 /* Reserve space for the consumer block */
972 /* Display virtual and physical addresses if debug driver */
975 print_name,
987 }
990 /*
991 * =================
992 * = dfx_adap_init =
993 * =================
994 *
995 * Overview:
996 * Brings the adapter to the link avail/link unavailable state.
997 *
998 * Returns:
999 * Condition code
1000 *
1001 * Arguments:
1002 * bp - pointer to board information
1003 * get_buffers - non-zero if buffers to be allocated
1004 *
1005 * Functional Description:
1006 * Issues the low-level firmware/hardware calls necessary to bring
1007 * the adapter up, or to properly reset and restore adapter during
1008 * run-time.
1009 *
1010 * Return Codes:
1011 * DFX_K_SUCCESS - Adapter brought up successfully
1012 * DFX_K_FAILURE - Adapter initialization failed
1013 *
1014 * Assumptions:
1015 * bp->reset_type should be set to a valid reset type value before
1016 * calling this routine.
1017 *
1018 * Side Effects:
1019 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1020 * upon a successful return of this routine.
1021 */
1024 {
1027 /* Disable PDQ interrupts first */
1031 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1034 {
1037 }
1039 /*
1040 * When the PDQ is reset, some false Type 0 interrupts may be pending,
1041 * so we'll acknowledge all Type 0 interrupts now before continuing.
1042 */
1046 /*
1047 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1048 *
1049 * Note: We only need to clear host copies of these registers. The PDQ reset
1050 * takes care of the on-board register values.
1051 */
1057 /* Clear consumer block before going to DMA_AVAILABLE state */
1061 /* Initialize the DMA Burst Size */
1064 PI_PCTRL_M_SUB_CMD,
1065 PI_SUB_CMD_K_BURST_SIZE_SET,
1068 {
1071 }
1073 /*
1074 * Set base address of Consumer Block
1075 *
1076 * Assumption: 32-bit physical address of consumer block is 64 byte
1077 * aligned. That is, bits 0-5 of the address must be zero.
1078 */
1081 PI_PCTRL_M_CONS_BLOCK,
1085 {
1088 }
1090 /*
1091 * Set the base address of Descriptor Block and bring adapter
1092 * to DMA_AVAILABLE state.
1093 *
1094 * Note: We also set the literal and data swapping requirements
1095 * in this command.
1096 *
1097 * Assumption: 32-bit physical address of descriptor block
1098 * is 8Kbyte aligned.
1099 */
1102 PI_PDATA_A_INIT_M_BSWAP_INIT),
1107 }
1109 /* Set transmit flush timeout value */
1117 {
1120 }
1122 /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1133 {
1136 }
1138 /* Initialize adapter CAM */
1141 {
1144 }
1146 /* Initialize adapter filters */
1149 {
1152 }
1154 /*
1155 * Remove any existing dynamic buffers (i.e. if the adapter is being
1156 * reinitialized)
1157 */
1162 /* Initialize receive descriptor block and produce buffers */
1165 {
1170 }
1172 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1176 {
1181 }
1183 /* Initialization succeeded, reenable PDQ interrupts */
1187 }
1190 /*
1191 * ============
1192 * = dfx_open =
1193 * ============
1194 *
1195 * Overview:
1196 * Opens the adapter
1197 *
1198 * Returns:
1199 * Condition code
1200 *
1201 * Arguments:
1202 * dev - pointer to device information
1203 *
1204 * Functional Description:
1205 * This function brings the adapter to an operational state.
1206 *
1207 * Return Codes:
1208 * 0 - Adapter was successfully opened
1209 * -EAGAIN - Could not register IRQ or adapter initialization failed
1210 *
1211 * Assumptions:
1212 * This routine should only be called for a device that was
1213 * initialized successfully.
1214 *
1215 * Side Effects:
1216 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1217 * if the open is successful.
1218 */
1221 {
1227 /* Register IRQ - support shared interrupts by passing device ptr */
1233 }
1235 /*
1236 * Set current address to factory MAC address
1237 *
1238 * Note: We've already done this step in dfx_driver_init.
1239 * However, it's possible that a user has set a node
1240 * address override, then closed and reopened the
1241 * adapter. Unless we reset the device address field
1242 * now, we'll continue to use the existing modified
1243 * address.
1244 */
1248 /* Clear local unicast/multicast address tables and counts */
1255 /* Disable promiscuous filter settings */
1262 /* Reset and initialize adapter */
1266 {
1270 }
1272 /* Set device structure info */
1275 }
1278 /*
1279 * =============
1280 * = dfx_close =
1281 * =============
1282 *
1283 * Overview:
1284 * Closes the device/module.
1285 *
1286 * Returns:
1287 * Condition code
1288 *
1289 * Arguments:
1290 * dev - pointer to device information
1291 *
1292 * Functional Description:
1293 * This routine closes the adapter and brings it to a safe state.
1294 * The interrupt service routine is deregistered with the OS.
1295 * The adapter can be opened again with another call to dfx_open().
1296 *
1297 * Return Codes:
1298 * Always return 0.
1299 *
1300 * Assumptions:
1301 * No further requests for this adapter are made after this routine is
1302 * called. dfx_open() can be called to reset and reinitialize the
1303 * adapter.
1304 *
1305 * Side Effects:
1306 * Adapter should be in DMA_UNAVAILABLE state upon completion of this
1307 * routine.
1308 */
1311 {
1316 /* Disable PDQ interrupts first */
1320 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1324 /*
1325 * Flush any pending transmit buffers
1326 *
1327 * Note: It's important that we flush the transmit buffers
1328 * BEFORE we clear our copy of the Type 2 register.
1329 * Otherwise, we'll have no idea how many buffers
1330 * we need to free.
1331 */
1335 /*
1336 * Clear Type 1 and Type 2 registers after adapter reset
1337 *
1338 * Note: Even though we're closing the adapter, it's
1339 * possible that an interrupt will occur after
1340 * dfx_close is called. Without some assurance to
1341 * the contrary we want to make sure that we don't
1342 * process receive and transmit LLC frames and update
1343 * the Type 2 register with bad information.
1344 */
1350 /* Clear consumer block for the same reason given above */
1354 /* Release all dynamically allocate skb in the receive ring. */
1358 /* Clear device structure flags */
1362 /* Deregister (free) IRQ */
1367 }
1370 /*
1371 * ======================
1372 * = dfx_int_pr_halt_id =
1373 * ======================
1374 *
1375 * Overview:
1376 * Displays halt id's in string form.
1377 *
1378 * Returns:
1379 * None
1380 *
1381 * Arguments:
1382 * bp - pointer to board information
1383 *
1384 * Functional Description:
1385 * Determine current halt id and display appropriate string.
1386 *
1387 * Return Codes:
1388 * None
1389 *
1390 * Assumptions:
1391 * None
1392 *
1393 * Side Effects:
1394 * None
1395 */
1398 {
1402 /* Read the latest port status */
1406 /* Display halt state transition information */
1410 {
1450 }
1451 }
1454 /*
1455 * ==========================
1456 * = dfx_int_type_0_process =
1457 * ==========================
1458 *
1459 * Overview:
1460 * Processes Type 0 interrupts.
1461 *
1462 * Returns:
1463 * None
1464 *
1465 * Arguments:
1466 * bp - pointer to board information
1467 *
1468 * Functional Description:
1469 * Processes all enabled Type 0 interrupts. If the reason for the interrupt
1470 * is a serious fault on the adapter, then an error message is displayed
1471 * and the adapter is reset.
1472 *
1473 * One tricky potential timing window is the rapid succession of "link avail"
1474 * "link unavail" state change interrupts. The acknowledgement of the Type 0
1475 * interrupt must be done before reading the state from the Port Status
1476 * register. This is true because a state change could occur after reading
1477 * the data, but before acknowledging the interrupt. If this state change
1478 * does happen, it would be lost because the driver is using the old state,
1479 * and it will never know about the new state because it subsequently
1480 * acknowledges the state change interrupt.
1481 *
1482 * INCORRECT CORRECT
1483 * read type 0 int reasons read type 0 int reasons
1484 * read adapter state ack type 0 interrupts
1485 * ack type 0 interrupts read adapter state
1486 * ... process interrupt ... ... process interrupt ...
1487 *
1488 * Return Codes:
1489 * None
1490 *
1491 * Assumptions:
1492 * None
1493 *
1494 * Side Effects:
1495 * An adapter reset may occur if the adapter has any Type 0 error interrupts
1496 * or if the port status indicates that the adapter is halted. The driver
1497 * is responsible for reinitializing the adapter with the current CAM
1498 * contents and adapter filter settings.
1499 */
1503 {
1507 /*
1508 * Read host interrupt Type 0 register to determine which Type 0
1509 * interrupts are pending. Immediately write it back out to clear
1510 * those interrupts.
1511 */
1516 /* Check for Type 0 error interrupts */
1519 PI_TYPE_0_STAT_M_PM_PAR_ERR |
1520 PI_TYPE_0_STAT_M_BUS_PAR_ERR))
1521 {
1522 /* Check for Non-Existent Memory error */
1527 /* Check for Packet Memory Parity error */
1532 /* Check for Host Bus Parity error */
1537 /* Reset adapter and bring it back on-line */
1543 {
1547 }
1550 }
1552 /* Check for transmit flush interrupt */
1555 {
1556 /* Flush any pending xmt's and acknowledge the flush interrupt */
1561 PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
1564 NULL);
1565 }
1567 /* Check for adapter state change */
1570 {
1571 /* Get latest adapter state */
1575 {
1576 /*
1577 * Adapter has transitioned to HALTED state, try to reset
1578 * adapter to bring it back on-line. If reset fails,
1579 * leave the adapter in the broken state.
1580 */
1585 /* Reset adapter and bring it back on-line */
1591 {
1595 }
1597 }
1599 {
1601 }
1602 }
1603 }
1606 /*
1607 * ==================
1608 * = dfx_int_common =
1609 * ==================
1610 *
1611 * Overview:
1612 * Interrupt service routine (ISR)
1613 *
1614 * Returns:
1615 * None
1616 *
1617 * Arguments:
1618 * bp - pointer to board information
1619 *
1620 * Functional Description:
1621 * This is the ISR which processes incoming adapter interrupts.
1622 *
1623 * Return Codes:
1624 * None
1625 *
1626 * Assumptions:
1627 * This routine assumes PDQ interrupts have not been disabled.
1628 * When interrupts are disabled at the PDQ, the Port Status register
1629 * is automatically cleared. This routine uses the Port Status
1630 * register value to determine whether a Type 0 interrupt occurred,
1631 * so it's important that adapter interrupts are not normally
1632 * enabled/disabled at the PDQ.
1633 *
1634 * It's vital that this routine is NOT reentered for the
1635 * same board and that the OS is not in another section of
1636 * code (eg. dfx_xmt_queue_pkt) for the same board on a
1637 * different thread.
1638 *
1639 * Side Effects:
1640 * Pending interrupts are serviced. Depending on the type of
1641 * interrupt, acknowledging and clearing the interrupt at the
1642 * PDQ involves writing a register to clear the interrupt bit
1643 * or updating completion indices.
1644 */
1647 {
1651 /* Process xmt interrupts - frequent case, so always call this routine */
1656 /* Process rcv interrupts - frequent case, so always call this routine */
1660 /*
1661 * Transmit and receive producer and completion indices are updated on the
1662 * adapter by writing to the Type 2 Producer register. Since the frequent
1663 * case is that we'll be processing either LLC transmit or receive buffers,
1664 * we'll optimize I/O writes by doing a single register write here.
1665 */
1669 /* Read PDQ Port Status register to find out which interrupts need processing */
1673 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1677 }
1680 /*
1681 * =================
1682 * = dfx_interrupt =
1683 * =================
1684 *
1685 * Overview:
1686 * Interrupt processing routine
1687 *
1688 * Returns:
1689 * Whether a valid interrupt was seen.
1690 *
1691 * Arguments:
1692 * irq - interrupt vector
1693 * dev_id - pointer to device information
1694 *
1695 * Functional Description:
1696 * This routine calls the interrupt processing routine for this adapter. It
1697 * disables and reenables adapter interrupts, as appropriate. We can support
1698 * shared interrupts since the incoming dev_id pointer provides our device
1699 * structure context.
1700 *
1701 * Return Codes:
1702 * IRQ_HANDLED - an IRQ was handled.
1703 * IRQ_NONE - no IRQ was handled.
1704 *
1705 * Assumptions:
1706 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1707 * on Intel-based systems) is done by the operating system outside this
1708 * routine.
1709 *
1710 * System interrupts are enabled through this call.
1711 *
1712 * Side Effects:
1713 * Interrupts are disabled, then reenabled at the adapter.
1714 */
1717 {
1721 /* Get board pointer only if device structure is valid */
1725 /* See if we're already servicing an interrupt */
1727 /* Service adapter interrupts */
1730 u32 status;
1738 /* Disable PDQ-PFI interrupts at PFI */
1740 PFI_MODE_M_DMA_ENB);
1742 /* Call interrupt service routine for this adapter */
1745 /* Clear PDQ interrupt status bit and reenable interrupts */
1747 PFI_STATUS_M_PDQ_INT);
1750 PFI_MODE_M_DMA_ENB));
1754 u8 status;
1762 /* Disable interrupts at the ESIC */
1766 /* Call interrupt service routine for this adapter */
1769 /* Reenable interrupts at the ESIC */
1775 }
1778 }
1781 /*
1782 * =====================
1783 * = dfx_ctl_get_stats =
1784 * =====================
1785 *
1786 * Overview:
1787 * Get statistics for FDDI adapter
1788 *
1789 * Returns:
1790 * Pointer to FDDI statistics structure
1791 *
1792 * Arguments:
1793 * dev - pointer to device information
1794 *
1795 * Functional Description:
1796 * Gets current MIB objects from adapter, then
1797 * returns FDDI statistics structure as defined
1798 * in if_fddi.h.
1799 *
1800 * Note: Since the FDDI statistics structure is
1801 * still new and the device structure doesn't
1802 * have an FDDI-specific get statistics handler,
1803 * we'll return the FDDI statistics structure as
1804 * a pointer to an Ethernet statistics structure.
1805 * That way, at least the first part of the statistics
1806 * structure can be decoded properly, and it allows
1807 * "smart" applications to perform a second cast to
1808 * decode the FDDI-specific statistics.
1809 *
1810 * We'll have to pay attention to this routine as the
1811 * device structure becomes more mature and LAN media
1812 * independent.
1813 *
1814 * Return Codes:
1815 * None
1816 *
1817 * Assumptions:
1818 * None
1819 *
1820 * Side Effects:
1821 * None
1822 */
1825 {
1828 /* Fill the bp->stats structure with driver-maintained counters */
1843 /* Get FDDI SMT MIB objects */
1849 /* Fill the bp->stats structure with the SMT MIB object values */
1851 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
1855 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
1870 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
1874 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
1875 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
1880 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
1881 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
1882 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
1883 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
1887 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
1904 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
1909 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
1910 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
1915 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
1916 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
1923 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
1924 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
1944 /* Get FDDI counters */
1950 /* Fill the bp->stats structure with the FDDI counter values */
1965 }
1968 /*
1969 * ==============================
1970 * = dfx_ctl_set_multicast_list =
1971 * ==============================
1972 *
1973 * Overview:
1974 * Enable/Disable LLC frame promiscuous mode reception
1975 * on the adapter and/or update multicast address table.
1976 *
1977 * Returns:
1978 * None
1979 *
1980 * Arguments:
1981 * dev - pointer to device information
1982 *
1983 * Functional Description:
1984 * This routine follows a fairly simple algorithm for setting the
1985 * adapter filters and CAM:
1986 *
1987 * if IFF_PROMISC flag is set
1988 * enable LLC individual/group promiscuous mode
1989 * else
1990 * disable LLC individual/group promiscuous mode
1991 * if number of incoming multicast addresses >
1992 * (CAM max size - number of unicast addresses in CAM)
1993 * enable LLC group promiscuous mode
1994 * set driver-maintained multicast address count to zero
1995 * else
1996 * disable LLC group promiscuous mode
1997 * set driver-maintained multicast address count to incoming count
1998 * update adapter CAM
1999 * update adapter filters
2000 *
2001 * Return Codes:
2002 * None
2003 *
2004 * Assumptions:
2005 * Multicast addresses are presented in canonical (LSB) format.
2006 *
2007 * Side Effects:
2008 * On-board adapter CAM and filters are updated.
2009 */
2012 {
2017 /* Enable LLC frame promiscuous mode, if necessary */
2022 /* Else, update multicast address table */
2024 else
2025 {
2027 /*
2028 * Check whether incoming multicast address count exceeds table size
2029 *
2030 * Note: The adapters utilize an on-board 64 entry CAM for
2031 * supporting perfect filtering of multicast packets
2032 * and bridge functions when adding unicast addresses.
2033 * There is no hash function available. To support
2034 * additional multicast addresses, the all multicast
2035 * filter (LLC group promiscuous mode) must be enabled.
2036 *
2037 * The firmware reserves two CAM entries for SMT-related
2038 * multicast addresses, which leaves 62 entries available.
2039 * The following code ensures that we're not being asked
2040 * to add more than 62 addresses to the CAM. If we are,
2041 * the driver will enable the all multicast filter.
2042 * Should the number of multicast addresses drop below
2043 * the high water mark, the filter will be disabled and
2044 * perfect filtering will be used.
2045 */
2048 {
2051 }
2052 else
2053 {
2056 }
2058 /* Copy addresses to multicast address table, then update adapter CAM */
2062 {
2065 }
2067 {
2069 }
2070 else
2071 {
2072 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count);
2073 }
2074 }
2076 /* Update adapter filters */
2079 {
2081 }
2082 else
2083 {
2085 }
2086 }
2089 /*
2090 * ===========================
2091 * = dfx_ctl_set_mac_address =
2092 * ===========================
2093 *
2094 * Overview:
2095 * Add node address override (unicast address) to adapter
2096 * CAM and update dev_addr field in device table.
2097 *
2098 * Returns:
2099 * None
2100 *
2101 * Arguments:
2102 * dev - pointer to device information
2103 * addr - pointer to sockaddr structure containing unicast address to add
2104 *
2105 * Functional Description:
2106 * The adapter supports node address overrides by adding one or more
2107 * unicast addresses to the adapter CAM. This is similar to adding
2108 * multicast addresses. In this routine we'll update the driver and
2109 * device structures with the new address, then update the adapter CAM
2110 * to ensure that the adapter will copy and strip frames destined and
2111 * sourced by that address.
2112 *
2113 * Return Codes:
2114 * Always returns zero.
2115 *
2116 * Assumptions:
2117 * The address pointed to by addr->sa_data is a valid unicast
2118 * address and is presented in canonical (LSB) format.
2119 *
2120 * Side Effects:
2121 * On-board adapter CAM is updated. On-board adapter filters
2122 * may be updated.
2123 */
2126 {
2130 /* Copy unicast address to driver-maintained structs and update count */
2136 /*
2137 * Verify we're not exceeding the CAM size by adding unicast address
2138 *
2139 * Note: It's possible that before entering this routine we've
2140 * already filled the CAM with 62 multicast addresses.
2141 * Since we need to place the node address override into
2142 * the CAM, we have to check to see that we're not
2143 * exceeding the CAM size. If we are, we have to enable
2144 * the LLC group (multicast) promiscuous mode filter as
2145 * in dfx_ctl_set_multicast_list.
2146 */
2149 {
2153 /* Update adapter filters */
2156 {
2158 }
2159 else
2160 {
2162 }
2163 }
2165 /* Update adapter CAM with new unicast address */
2168 {
2170 }
2171 else
2172 {
2174 }
2176 }
2179 /*
2180 * ======================
2181 * = dfx_ctl_update_cam =
2182 * ======================
2183 *
2184 * Overview:
2185 * Procedure to update adapter CAM (Content Addressable Memory)
2186 * with desired unicast and multicast address entries.
2187 *
2188 * Returns:
2189 * Condition code
2190 *
2191 * Arguments:
2192 * bp - pointer to board information
2193 *
2194 * Functional Description:
2195 * Updates adapter CAM with current contents of board structure
2196 * unicast and multicast address tables. Since there are only 62
2197 * free entries in CAM, this routine ensures that the command
2198 * request buffer is not overrun.
2199 *
2200 * Return Codes:
2201 * DFX_K_SUCCESS - Request succeeded
2202 * DFX_K_FAILURE - Request failed
2203 *
2204 * Assumptions:
2205 * All addresses being added (unicast and multicast) are in canonical
2206 * order.
2207 *
2208 * Side Effects:
2209 * On-board adapter CAM is updated.
2210 */
2213 {
2217 /*
2218 * Fill in command request information
2219 *
2220 * Note: Even though both the unicast and multicast address
2221 * table entries are stored as contiguous 6 byte entries,
2222 * the firmware address filter set command expects each
2223 * entry to be two longwords (8 bytes total). We must be
2224 * careful to only copy the six bytes of each unicast and
2225 * multicast table entry into each command entry. This
2226 * is also why we must first clear the entire command
2227 * request buffer.
2228 */
2234 /* Now add unicast addresses to command request buffer, if any */
2237 {
2239 {
2242 }
2243 }
2245 /* Now add multicast addresses to command request buffer, if any */
2248 {
2250 {
2253 }
2254 }
2256 /* Issue command to update adapter CAM, then return */
2261 }
2264 /*
2265 * ==========================
2266 * = dfx_ctl_update_filters =
2267 * ==========================
2268 *
2269 * Overview:
2270 * Procedure to update adapter filters with desired
2271 * filter settings.
2272 *
2273 * Returns:
2274 * Condition code
2275 *
2276 * Arguments:
2277 * bp - pointer to board information
2278 *
2279 * Functional Description:
2280 * Enables or disables filter using current filter settings.
2281 *
2282 * Return Codes:
2283 * DFX_K_SUCCESS - Request succeeded.
2284 * DFX_K_FAILURE - Request failed.
2285 *
2286 * Assumptions:
2287 * We must always pass up packets destined to the broadcast
2288 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2289 * broadcast filter enabled.
2290 *
2291 * Side Effects:
2292 * On-board adapter filters are updated.
2293 */
2296 {
2299 /* Fill in command request information */
2303 /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2308 /* Initialize LLC Individual/Group Promiscuous filter */
2313 /* Initialize LLC Group Promiscuous filter */
2318 /* Terminate the item code list */
2322 /* Issue command to update adapter filters, then return */
2327 }
2330 /*
2331 * ======================
2332 * = dfx_hw_dma_cmd_req =
2333 * ======================
2334 *
2335 * Overview:
2336 * Sends PDQ DMA command to adapter firmware
2337 *
2338 * Returns:
2339 * Condition code
2340 *
2341 * Arguments:
2342 * bp - pointer to board information
2343 *
2344 * Functional Description:
2345 * The command request and response buffers are posted to the adapter in the manner
2346 * described in the PDQ Port Specification:
2347 *
2348 * 1. Command Response Buffer is posted to adapter.
2349 * 2. Command Request Buffer is posted to adapter.
2350 * 3. Command Request consumer index is polled until it indicates that request
2351 * buffer has been DMA'd to adapter.
2352 * 4. Command Response consumer index is polled until it indicates that response
2353 * buffer has been DMA'd from adapter.
2354 *
2355 * This ordering ensures that a response buffer is already available for the firmware
2356 * to use once it's done processing the request buffer.
2357 *
2358 * Return Codes:
2359 * DFX_K_SUCCESS - DMA command succeeded
2360 * DFX_K_OUTSTATE - Adapter is NOT in proper state
2361 * DFX_K_HW_TIMEOUT - DMA command timed out
2362 *
2363 * Assumptions:
2364 * Command request buffer has already been filled with desired DMA command.
2365 *
2366 * Side Effects:
2367 * None
2368 */
2371 {
2375 /* Make sure the adapter is in a state that we can issue the DMA command in */
2384 /* Put response buffer on the command response queue */
2390 /* Bump (and wrap) the producer index and write out to register */
2396 /* Put request buffer on the command request queue */
2402 /* Bump (and wrap) the producer index and write out to register */
2408 /*
2409 * Here we wait for the command request consumer index to be equal
2410 * to the producer, indicating that the adapter has DMAed the request.
2411 */
2414 {
2418 }
2422 /* Bump (and wrap) the completion index and write out to register */
2428 /*
2429 * Here we wait for the command response consumer index to be equal
2430 * to the producer, indicating that the adapter has DMAed the response.
2431 */
2434 {
2438 }
2442 /* Bump (and wrap) the completion index and write out to register */
2448 }
2451 /*
2452 * ========================
2453 * = dfx_hw_port_ctrl_req =
2454 * ========================
2455 *
2456 * Overview:
2457 * Sends PDQ port control command to adapter firmware
2458 *
2459 * Returns:
2460 * Host data register value in host_data if ptr is not NULL
2461 *
2462 * Arguments:
2463 * bp - pointer to board information
2464 * command - port control command
2465 * data_a - port data A register value
2466 * data_b - port data B register value
2467 * host_data - ptr to host data register value
2468 *
2469 * Functional Description:
2470 * Send generic port control command to adapter by writing
2471 * to various PDQ port registers, then polling for completion.
2472 *
2473 * Return Codes:
2474 * DFX_K_SUCCESS - port control command succeeded
2475 * DFX_K_HW_TIMEOUT - port control command timed out
2476 *
2477 * Assumptions:
2478 * None
2479 *
2480 * Side Effects:
2481 * None
2482 */
2486 PI_UINT32 command,
2487 PI_UINT32 data_a,
2488 PI_UINT32 data_b,
2489 PI_UINT32 *host_data
2490 )
2492 {
2496 /* Set Command Error bit in command longword */
2500 /* Issue port command to the adapter */
2506 /* Now wait for command to complete */
2510 else
2514 {
2519 }
2523 /*
2524 * If the address of host_data is non-zero, assume caller has supplied a
2525 * non NULL pointer, and return the contents of the HOST_DATA register in
2526 * it.
2527 */
2532 }
2535 /*
2536 * =====================
2537 * = dfx_hw_adap_reset =
2538 * =====================
2539 *
2540 * Overview:
2541 * Resets adapter
2542 *
2543 * Returns:
2544 * None
2545 *
2546 * Arguments:
2547 * bp - pointer to board information
2548 * type - type of reset to perform
2549 *
2550 * Functional Description:
2551 * Issue soft reset to adapter by writing to PDQ Port Reset
2552 * register. Use incoming reset type to tell adapter what
2553 * kind of reset operation to perform.
2554 *
2555 * Return Codes:
2556 * None
2557 *
2558 * Assumptions:
2559 * This routine merely issues a soft reset to the adapter.
2560 * It is expected that after this routine returns, the caller
2561 * will appropriately poll the Port Status register for the
2562 * adapter to enter the proper state.
2563 *
2564 * Side Effects:
2565 * Internal adapter registers are cleared.
2566 */
2570 PI_UINT32 type
2571 )
2573 {
2574 /* Set Reset type and assert reset */
2579 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2583 /* Deassert reset */
2586 }
2589 /*
2590 * ========================
2591 * = dfx_hw_adap_state_rd =
2592 * ========================
2593 *
2594 * Overview:
2595 * Returns current adapter state
2596 *
2597 * Returns:
2598 * Adapter state per PDQ Port Specification
2599 *
2600 * Arguments:
2601 * bp - pointer to board information
2602 *
2603 * Functional Description:
2604 * Reads PDQ Port Status register and returns adapter state.
2605 *
2606 * Return Codes:
2607 * None
2608 *
2609 * Assumptions:
2610 * None
2611 *
2612 * Side Effects:
2613 * None
2614 */
2617 {
2622 }
2625 /*
2626 * =====================
2627 * = dfx_hw_dma_uninit =
2628 * =====================
2629 *
2630 * Overview:
2631 * Brings adapter to DMA_UNAVAILABLE state
2632 *
2633 * Returns:
2634 * Condition code
2635 *
2636 * Arguments:
2637 * bp - pointer to board information
2638 * type - type of reset to perform
2639 *
2640 * Functional Description:
2641 * Bring adapter to DMA_UNAVAILABLE state by performing the following:
2642 * 1. Set reset type bit in Port Data A Register then reset adapter.
2643 * 2. Check that adapter is in DMA_UNAVAILABLE state.
2644 *
2645 * Return Codes:
2646 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
2647 * DFX_K_HW_TIMEOUT - adapter did not reset properly
2648 *
2649 * Assumptions:
2650 * None
2651 *
2652 * Side Effects:
2653 * Internal adapter registers are cleared.
2654 */
2657 {
2660 /* Set reset type bit and reset adapter */
2664 /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2667 {
2671 }
2675 }
2677 /*
2678 * Align an sk_buff to a boundary power of 2
2679 *
2680 */
2683 {
2690 }
2693 /*
2694 * ================
2695 * = dfx_rcv_init =
2696 * ================
2697 *
2698 * Overview:
2699 * Produces buffers to adapter LLC Host receive descriptor block
2700 *
2701 * Returns:
2702 * None
2703 *
2704 * Arguments:
2705 * bp - pointer to board information
2706 * get_buffers - non-zero if buffers to be allocated
2707 *
2708 * Functional Description:
2709 * This routine can be called during dfx_adap_init() or during an adapter
2710 * reset. It initializes the descriptor block and produces all allocated
2711 * LLC Host queue receive buffers.
2712 *
2713 * Return Codes:
2714 * Return 0 on success or -ENOMEM if buffer allocation failed (when using
2715 * dynamic buffer allocation). If the buffer allocation failed, the
2716 * already allocated buffers will not be released and the caller should do
2717 * this.
2718 *
2719 * Assumptions:
2720 * The PDQ has been reset and the adapter and driver maintained Type 2
2721 * register indices are cleared.
2722 *
2723 * Side Effects:
2724 * Receive buffers are posted to the adapter LLC queue and the adapter
2725 * is notified.
2726 */
2729 {
2732 /*
2733 * Since each receive buffer is a single fragment of same length, initialize
2734 * first longword in each receive descriptor for entire LLC Host descriptor
2735 * block. Also initialize second longword in each receive descriptor with
2736 * physical address of receive buffer. We'll always allocate receive
2737 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2738 * block and produce new receive buffers by simply updating the receive
2739 * producer index.
2740 *
2741 * Assumptions:
2742 * To support all shipping versions of PDQ, the receive buffer size
2743 * must be mod 128 in length and the physical address must be 128 byte
2744 * aligned. In other words, bits 0-6 of the length and address must
2745 * be zero for the following descriptor field entries to be correct on
2746 * all PDQ-based boards. We guaranteed both requirements during
2747 * driver initialization when we allocated memory for the receive buffers.
2748 */
2751 #ifdef DYNAMIC_BUFFERS
2754 {
2760 /*
2761 * align to 128 bytes for compatibility with
2762 * the old EISA boards.
2763 */
2768 NEW_SKB_SIZE,
2769 PCI_DMA_FROMDEVICE);
2770 /*
2771 * p_rcv_buff_va is only used inside the
2772 * kernel so we put the skb pointer here.
2773 */
2775 }
2776 #else
2779 {
2782 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
2784 }
2785 #endif
2786 }
2788 /* Update receive producer and Type 2 register */
2793 }
2796 /*
2797 * =========================
2798 * = dfx_rcv_queue_process =
2799 * =========================
2800 *
2801 * Overview:
2802 * Process received LLC frames.
2803 *
2804 * Returns:
2805 * None
2806 *
2807 * Arguments:
2808 * bp - pointer to board information
2809 *
2810 * Functional Description:
2811 * Received LLC frames are processed until there are no more consumed frames.
2812 * Once all frames are processed, the receive buffers are returned to the
2813 * adapter. Note that this algorithm fixes the length of time that can be spent
2814 * in this routine, because there are a fixed number of receive buffers to
2815 * process and buffers are not produced until this routine exits and returns
2816 * to the ISR.
2817 *
2818 * Return Codes:
2819 * None
2820 *
2821 * Assumptions:
2822 * None
2823 *
2824 * Side Effects:
2825 * None
2826 */
2829 DFX_board_t *bp
2830 )
2832 {
2838 /* Service all consumed LLC receive frames */
2842 {
2843 /* Process any errors */
2848 #ifdef DYNAMIC_BUFFERS
2850 #else
2852 #endif
2856 {
2859 else
2861 }
2862 else
2863 {
2866 /* The frame was received without errors - verify packet length */
2873 #ifdef DYNAMIC_BUFFERS
2885 NEW_SKB_SIZE,
2886 PCI_DMA_FROMDEVICE);
2892 NEW_SKB_SIZE,
2893 PCI_DMA_FROMDEVICE);
2897 #endif
2900 {
2904 }
2906 #ifndef DYNAMIC_BUFFERS
2908 #endif
2909 {
2910 /* Receive buffer allocated, pass receive packet up */
2913 }
2923 /* Update the rcv counters */
2928 }
2929 }
2930 }
2932 /*
2933 * Advance the producer (for recycling) and advance the completion
2934 * (for servicing received frames). Note that it is okay to
2935 * advance the producer without checking that it passes the
2936 * completion index because they are both advanced at the same
2937 * rate.
2938 */
2942 }
2943 }
2946 /*
2947 * =====================
2948 * = dfx_xmt_queue_pkt =
2949 * =====================
2950 *
2951 * Overview:
2952 * Queues packets for transmission
2953 *
2954 * Returns:
2955 * Condition code
2956 *
2957 * Arguments:
2958 * skb - pointer to sk_buff to queue for transmission
2959 * dev - pointer to device information
2960 *
2961 * Functional Description:
2962 * Here we assume that an incoming skb transmit request
2963 * is contained in a single physically contiguous buffer
2964 * in which the virtual address of the start of packet
2965 * (skb->data) can be converted to a physical address
2966 * by using pci_map_single().
2967 *
2968 * Since the adapter architecture requires a three byte
2969 * packet request header to prepend the start of packet,
2970 * we'll write the three byte field immediately prior to
2971 * the FC byte. This assumption is valid because we've
2972 * ensured that dev->hard_header_len includes three pad
2973 * bytes. By posting a single fragment to the adapter,
2974 * we'll reduce the number of descriptor fetches and
2975 * bus traffic needed to send the request.
2976 *
2977 * Also, we can't free the skb until after it's been DMA'd
2978 * out by the adapter, so we'll queue it in the driver and
2979 * return it in dfx_xmt_done.
2980 *
2981 * Return Codes:
2982 * 0 - driver queued packet, link is unavailable, or skbuff was bad
2983 * 1 - caller should requeue the sk_buff for later transmission
2984 *
2985 * Assumptions:
2986 * First and foremost, we assume the incoming skb pointer
2987 * is NOT NULL and is pointing to a valid sk_buff structure.
2988 *
2989 * The outgoing packet is complete, starting with the
2990 * frame control byte including the last byte of data,
2991 * but NOT including the 4 byte CRC. We'll let the
2992 * adapter hardware generate and append the CRC.
2993 *
2994 * The entire packet is stored in one physically
2995 * contiguous buffer which is not cached and whose
2996 * 32-bit physical address can be determined.
2997 *
2998 * It's vital that this routine is NOT reentered for the
2999 * same board and that the OS is not in another section of
3000 * code (eg. dfx_int_common) for the same board on a
3001 * different thread.
3002 *
3003 * Side Effects:
3004 * None
3005 */
3010 )
3012 {
3021 /*
3022 * Verify that incoming transmit request is OK
3023 *
3024 * Note: The packet size check is consistent with other
3025 * Linux device drivers, although the correct packet
3026 * size should be verified before calling the
3027 * transmit routine.
3028 */
3031 {
3038 }
3039 /*
3040 * See if adapter link is available, if not, free buffer
3041 *
3042 * Note: If the link isn't available, free buffer and return 0
3043 * rather than tell the upper layer to requeue the packet.
3044 * The methodology here is that by the time the link
3045 * becomes available, the packet to be sent will be
3046 * fairly stale. By simply dropping the packet, the
3047 * higher layer protocols will eventually time out
3048 * waiting for response packets which it won't receive.
3049 */
3052 {
3055 else
3056 {
3061 }
3062 }
3066 /* Get the current producer and the next free xmt data descriptor */
3071 /*
3072 * Get pointer to auxiliary queue entry to contain information
3073 * for this packet.
3074 *
3075 * Note: The current xmt producer index will become the
3076 * current xmt completion index when we complete this
3077 * packet later on. So, we'll get the pointer to the
3078 * next auxiliary queue entry now before we bump the
3079 * producer index.
3080 */
3084 /* Write the three PRH bytes immediately before the FC byte */
3091 /*
3092 * Write the descriptor with buffer info and bump producer
3093 *
3094 * Note: Since we need to start DMA from the packet request
3095 * header, we'll add 3 bytes to the DMA buffer length,
3096 * and we'll determine the physical address of the
3097 * buffer from the PRH, not skb->data.
3098 *
3099 * Assumptions:
3100 * 1. Packet starts with the frame control (FC) byte
3101 * at skb->data.
3102 * 2. The 4-byte CRC is not appended to the buffer or
3103 * included in the length.
3104 * 3. Packet length (skb->len) is from FC to end of
3105 * data, inclusive.
3106 * 4. The packet length does not exceed the maximum
3107 * FDDI LLC frame length of 4491 bytes.
3108 * 5. The entire packet is contained in a physically
3109 * contiguous, non-cached, locked memory space
3110 * comprised of a single buffer pointed to by
3111 * skb->data.
3112 * 6. The physical address of the start of packet
3113 * can be determined from the virtual address
3114 * by using pci_map_single() and is only 32-bits
3115 * wide.
3116 */
3118 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
3122 /*
3123 * Verify that descriptor is actually available
3124 *
3125 * Note: If descriptor isn't available, return 1 which tells
3126 * the upper layer to requeue the packet for later
3127 * transmission.
3128 *
3129 * We need to ensure that the producer never reaches the
3130 * completion, except to indicate that the queue is empty.
3131 */
3134 {
3138 }
3140 /*
3141 * Save info for this packet for xmt done indication routine
3142 *
3143 * Normally, we'd save the producer index in the p_xmt_drv_descr
3144 * structure so that we'd have it handy when we complete this
3145 * packet later (in dfx_xmt_done). However, since the current
3146 * transmit architecture guarantees a single fragment for the
3147 * entire packet, we can simply bump the completion index by
3148 * one (1) for each completed packet.
3149 *
3150 * Note: If this assumption changes and we're presented with
3151 * an inconsistent number of transmit fragments for packet
3152 * data, we'll need to modify this code to save the current
3153 * transmit producer index.
3154 */
3158 /* Update Type 2 register */
3165 }
3168 /*
3169 * ================
3170 * = dfx_xmt_done =
3171 * ================
3172 *
3173 * Overview:
3174 * Processes all frames that have been transmitted.
3175 *
3176 * Returns:
3177 * None
3178 *
3179 * Arguments:
3180 * bp - pointer to board information
3181 *
3182 * Functional Description:
3183 * For all consumed transmit descriptors that have not
3184 * yet been completed, we'll free the skb we were holding
3185 * onto using dev_kfree_skb and bump the appropriate
3186 * counters.
3187 *
3188 * Return Codes:
3189 * None
3190 *
3191 * Assumptions:
3192 * The Type 2 register is not updated in this routine. It is
3193 * assumed that it will be updated in the ISR when dfx_xmt_done
3194 * returns.
3195 *
3196 * Side Effects:
3197 * None
3198 */
3201 {
3207 /* Service all consumed transmit frames */
3211 {
3212 /* Get pointer to the transmit driver descriptor block information */
3216 /* Increment transmit counters */
3221 /* Return skb to operating system */
3226 PCI_DMA_TODEVICE);
3229 /*
3230 * Move to start of next packet by updating completion index
3231 *
3232 * Here we assume that a transmit packet request is always
3233 * serviced by posting one fragment. We can therefore
3234 * simplify the completion code by incrementing the
3235 * completion index by one. This code will need to be
3236 * modified if this assumption changes. See comments
3237 * in dfx_xmt_queue_pkt for more details.
3238 */
3241 freed++;
3242 }
3244 }
3247 /*
3248 * =================
3249 * = dfx_rcv_flush =
3250 * =================
3251 *
3252 * Overview:
3253 * Remove all skb's in the receive ring.
3254 *
3255 * Returns:
3256 * None
3257 *
3258 * Arguments:
3259 * bp - pointer to board information
3260 *
3261 * Functional Description:
3262 * Free's all the dynamically allocated skb's that are
3263 * currently attached to the device receive ring. This
3264 * function is typically only used when the device is
3265 * initialized or reinitialized.
3266 *
3267 * Return Codes:
3268 * None
3269 *
3270 * Side Effects:
3271 * None
3272 */
3273 #ifdef DYNAMIC_BUFFERS
3275 {
3280 {
3286 }
3288 }
3289 #else
3291 {
3292 }
3295 /*
3296 * =================
3297 * = dfx_xmt_flush =
3298 * =================
3299 *
3300 * Overview:
3301 * Processes all frames whether they've been transmitted
3302 * or not.
3303 *
3304 * Returns:
3305 * None
3306 *
3307 * Arguments:
3308 * bp - pointer to board information
3309 *
3310 * Functional Description:
3311 * For all produced transmit descriptors that have not
3312 * yet been completed, we'll free the skb we were holding
3313 * onto using dev_kfree_skb and bump the appropriate
3314 * counters. Of course, it's possible that some of
3315 * these transmit requests actually did go out, but we
3316 * won't make that distinction here. Finally, we'll
3317 * update the consumer index to match the producer.
3318 *
3319 * Return Codes:
3320 * None
3321 *
3322 * Assumptions:
3323 * This routine does NOT update the Type 2 register. It
3324 * is assumed that this routine is being called during a
3325 * transmit flush interrupt, or a shutdown or close routine.
3326 *
3327 * Side Effects:
3328 * None
3329 */
3332 {
3337 /* Flush all outstanding transmit frames */
3340 {
3341 /* Get pointer to the transmit driver descriptor block information */
3345 /* Return skb to operating system */
3350 PCI_DMA_TODEVICE);
3353 /* Increment transmit error counter */
3357 /*
3358 * Move to start of next packet by updating completion index
3359 *
3360 * Here we assume that a transmit packet request is always
3361 * serviced by posting one fragment. We can therefore
3362 * simplify the completion code by incrementing the
3363 * completion index by one. This code will need to be
3364 * modified if this assumption changes. See comments
3365 * in dfx_xmt_queue_pkt for more details.
3366 */
3369 }
3371 /* Update the transmit consumer index in the consumer block */
3376 }
3379 {
3388 #ifndef DYNAMIC_BUFFERS
3390 #endif
3397 }
3400 {
3405 }
3410 };
3418 };
3425 {
3429 {
3437 }
3438 }
3441 {
3451 }
3454 {
3460 }
3470 /*
3471 * Local variables:
3472 * kernel-compile-command: "gcc -D__KERNEL__ -I/root/linux/include -Wall -Wstrict-prototypes -O2 -pipe -fomit-frame-pointer -fno-strength-reduce -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -c defxx.c"
3473 * End:
3474 */