2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
8 * Copyright (C) 1999, 2000, 2001, 2003 Ralf Baechle
9 * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
12 * o IOC3 ASIC specification 4.51, 1996-04-18
13 * o IEEE 802.3 specification, 2000 edition
14 * o DP38840A Specification, National Semiconductor, March 1997
18 * o Handle allocation failures in ioc3_alloc_skb() more gracefully.
19 * o Handle allocation failures in ioc3_init_rings().
20 * o Use prefetching for large packets. What is a good lower limit for
22 * o We're probably allocating a bit too much memory.
23 * o Use hardware checksums.
24 * o Convert to using a IOC3 meta driver.
25 * o Which PHYs might possibly be attached to the IOC3 in real live,
26 * which workarounds are required for them? Do we ever have Lucent's?
27 * o For the 2.5 branch kill the mii-tool ioctls.
30 #define IOC3_NAME "ioc3-eth"
31 #define IOC3_VERSION "2.6.3-4"
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/kernel.h>
37 #include <linux/errno.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/crc32.h>
41 #include <linux/mii.h>
44 #include <linux/tcp.h>
45 #include <linux/udp.h>
46 #include <linux/dma-mapping.h>
48 #ifdef CONFIG_SERIAL_8250
49 #include <linux/serial_core.h>
50 #include <linux/serial_8250.h>
53 #include <linux/netdevice.h>
54 #include <linux/etherdevice.h>
55 #include <linux/ethtool.h>
56 #include <linux/skbuff.h>
59 #include <asm/byteorder.h>
61 #include <asm/pgtable.h>
62 #include <asm/uaccess.h>
63 #include <asm/sn/types.h>
64 #include <asm/sn/sn0/addrs.h>
65 #include <asm/sn/sn0/hubni.h>
66 #include <asm/sn/sn0/hubio.h>
67 #include <asm/sn/klconfig.h>
68 #include <asm/sn/ioc3.h>
69 #include <asm/sn/sn0/ip27.h>
70 #include <asm/pci/bridge.h>
73 * 64 RX buffers. This is tunable in the range of 16 <= x < 512. The
74 * value must be a power of two.
78 #define ETCSR_FD ((17<<ETCSR_IPGR2_SHIFT) | (11<<ETCSR_IPGR1_SHIFT) | 21)
79 #define ETCSR_HD ((21<<ETCSR_IPGR2_SHIFT) | (21<<ETCSR_IPGR1_SHIFT) | 21)
81 /* Private per NIC data of the driver. */
84 unsigned long *rxr
; /* pointer to receiver ring */
85 struct ioc3_etxd
*txr
;
86 struct sk_buff
*rx_skbs
[512];
87 struct sk_buff
*tx_skbs
[128];
88 struct net_device_stats stats
;
89 int rx_ci
; /* RX consumer index */
90 int rx_pi
; /* RX producer index */
91 int tx_ci
; /* TX consumer index */
92 int tx_pi
; /* TX producer index */
94 u32 emcr
, ehar_h
, ehar_l
;
96 struct mii_if_info mii
;
99 /* Members used by autonegotiation */
100 struct timer_list ioc3_timer
;
103 static inline struct net_device
*priv_netdev(struct ioc3_private
*dev
)
105 return (void *)dev
- ((sizeof(struct net_device
) + 31) & ~31);
108 static int ioc3_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
109 static void ioc3_set_multicast_list(struct net_device
*dev
);
110 static int ioc3_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
111 static void ioc3_timeout(struct net_device
*dev
);
112 static inline unsigned int ioc3_hash(const unsigned char *addr
);
113 static inline void ioc3_stop(struct ioc3_private
*ip
);
114 static void ioc3_init(struct net_device
*dev
);
116 static const char ioc3_str
[] = "IOC3 Ethernet";
117 static const struct ethtool_ops ioc3_ethtool_ops
;
119 /* We use this to acquire receive skb's that we can DMA directly into. */
121 #define IOC3_CACHELINE 128UL
123 static inline unsigned long aligned_rx_skb_addr(unsigned long addr
)
125 return (~addr
+ 1) & (IOC3_CACHELINE
- 1UL);
128 static inline struct sk_buff
* ioc3_alloc_skb(unsigned long length
,
129 unsigned int gfp_mask
)
133 skb
= alloc_skb(length
+ IOC3_CACHELINE
- 1, gfp_mask
);
135 int offset
= aligned_rx_skb_addr((unsigned long) skb
->data
);
137 skb_reserve(skb
, offset
);
143 static inline unsigned long ioc3_map(void *ptr
, unsigned long vdev
)
145 #ifdef CONFIG_SGI_IP27
146 vdev
<<= 57; /* Shift to PCI64_ATTR_VIRTUAL */
148 return vdev
| (0xaUL
<< PCI64_ATTR_TARG_SHFT
) | PCI64_ATTR_PREF
|
149 ((unsigned long)ptr
& TO_PHYS_MASK
);
151 return virt_to_bus(ptr
);
155 /* BEWARE: The IOC3 documentation documents the size of rx buffers as
156 1644 while it's actually 1664. This one was nasty to track down ... */
158 #define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + IOC3_CACHELINE)
160 /* DMA barrier to separate cached and uncached accesses. */
162 __asm__("sync" ::: "memory")
165 #define IOC3_SIZE 0x100000
168 * IOC3 is a big endian device
170 * Unorthodox but makes the users of these macros more readable - the pointer
171 * to the IOC3's memory mapped registers is expected as struct ioc3 * ioc3
172 * in the environment.
174 #define ioc3_r_mcr() be32_to_cpu(ioc3->mcr)
175 #define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0)
176 #define ioc3_w_gpcr_s(v) do { ioc3->gpcr_s = cpu_to_be32(v); } while (0)
177 #define ioc3_r_emcr() be32_to_cpu(ioc3->emcr)
178 #define ioc3_w_emcr(v) do { ioc3->emcr = cpu_to_be32(v); } while (0)
179 #define ioc3_r_eisr() be32_to_cpu(ioc3->eisr)
180 #define ioc3_w_eisr(v) do { ioc3->eisr = cpu_to_be32(v); } while (0)
181 #define ioc3_r_eier() be32_to_cpu(ioc3->eier)
182 #define ioc3_w_eier(v) do { ioc3->eier = cpu_to_be32(v); } while (0)
183 #define ioc3_r_ercsr() be32_to_cpu(ioc3->ercsr)
184 #define ioc3_w_ercsr(v) do { ioc3->ercsr = cpu_to_be32(v); } while (0)
185 #define ioc3_r_erbr_h() be32_to_cpu(ioc3->erbr_h)
186 #define ioc3_w_erbr_h(v) do { ioc3->erbr_h = cpu_to_be32(v); } while (0)
187 #define ioc3_r_erbr_l() be32_to_cpu(ioc3->erbr_l)
188 #define ioc3_w_erbr_l(v) do { ioc3->erbr_l = cpu_to_be32(v); } while (0)
189 #define ioc3_r_erbar() be32_to_cpu(ioc3->erbar)
190 #define ioc3_w_erbar(v) do { ioc3->erbar = cpu_to_be32(v); } while (0)
191 #define ioc3_r_ercir() be32_to_cpu(ioc3->ercir)
192 #define ioc3_w_ercir(v) do { ioc3->ercir = cpu_to_be32(v); } while (0)
193 #define ioc3_r_erpir() be32_to_cpu(ioc3->erpir)
194 #define ioc3_w_erpir(v) do { ioc3->erpir = cpu_to_be32(v); } while (0)
195 #define ioc3_r_ertr() be32_to_cpu(ioc3->ertr)
196 #define ioc3_w_ertr(v) do { ioc3->ertr = cpu_to_be32(v); } while (0)
197 #define ioc3_r_etcsr() be32_to_cpu(ioc3->etcsr)
198 #define ioc3_w_etcsr(v) do { ioc3->etcsr = cpu_to_be32(v); } while (0)
199 #define ioc3_r_ersr() be32_to_cpu(ioc3->ersr)
200 #define ioc3_w_ersr(v) do { ioc3->ersr = cpu_to_be32(v); } while (0)
201 #define ioc3_r_etcdc() be32_to_cpu(ioc3->etcdc)
202 #define ioc3_w_etcdc(v) do { ioc3->etcdc = cpu_to_be32(v); } while (0)
203 #define ioc3_r_ebir() be32_to_cpu(ioc3->ebir)
204 #define ioc3_w_ebir(v) do { ioc3->ebir = cpu_to_be32(v); } while (0)
205 #define ioc3_r_etbr_h() be32_to_cpu(ioc3->etbr_h)
206 #define ioc3_w_etbr_h(v) do { ioc3->etbr_h = cpu_to_be32(v); } while (0)
207 #define ioc3_r_etbr_l() be32_to_cpu(ioc3->etbr_l)
208 #define ioc3_w_etbr_l(v) do { ioc3->etbr_l = cpu_to_be32(v); } while (0)
209 #define ioc3_r_etcir() be32_to_cpu(ioc3->etcir)
210 #define ioc3_w_etcir(v) do { ioc3->etcir = cpu_to_be32(v); } while (0)
211 #define ioc3_r_etpir() be32_to_cpu(ioc3->etpir)
212 #define ioc3_w_etpir(v) do { ioc3->etpir = cpu_to_be32(v); } while (0)
213 #define ioc3_r_emar_h() be32_to_cpu(ioc3->emar_h)
214 #define ioc3_w_emar_h(v) do { ioc3->emar_h = cpu_to_be32(v); } while (0)
215 #define ioc3_r_emar_l() be32_to_cpu(ioc3->emar_l)
216 #define ioc3_w_emar_l(v) do { ioc3->emar_l = cpu_to_be32(v); } while (0)
217 #define ioc3_r_ehar_h() be32_to_cpu(ioc3->ehar_h)
218 #define ioc3_w_ehar_h(v) do { ioc3->ehar_h = cpu_to_be32(v); } while (0)
219 #define ioc3_r_ehar_l() be32_to_cpu(ioc3->ehar_l)
220 #define ioc3_w_ehar_l(v) do { ioc3->ehar_l = cpu_to_be32(v); } while (0)
221 #define ioc3_r_micr() be32_to_cpu(ioc3->micr)
222 #define ioc3_w_micr(v) do { ioc3->micr = cpu_to_be32(v); } while (0)
223 #define ioc3_r_midr_r() be32_to_cpu(ioc3->midr_r)
224 #define ioc3_w_midr_r(v) do { ioc3->midr_r = cpu_to_be32(v); } while (0)
225 #define ioc3_r_midr_w() be32_to_cpu(ioc3->midr_w)
226 #define ioc3_w_midr_w(v) do { ioc3->midr_w = cpu_to_be32(v); } while (0)
228 static inline u32
mcr_pack(u32 pulse
, u32 sample
)
230 return (pulse
<< 10) | (sample
<< 2);
233 static int nic_wait(struct ioc3
*ioc3
)
239 } while (!(mcr
& 2));
244 static int nic_reset(struct ioc3
*ioc3
)
248 ioc3_w_mcr(mcr_pack(500, 65));
249 presence
= nic_wait(ioc3
);
251 ioc3_w_mcr(mcr_pack(0, 500));
257 static inline int nic_read_bit(struct ioc3
*ioc3
)
261 ioc3_w_mcr(mcr_pack(6, 13));
262 result
= nic_wait(ioc3
);
263 ioc3_w_mcr(mcr_pack(0, 100));
269 static inline void nic_write_bit(struct ioc3
*ioc3
, int bit
)
272 ioc3_w_mcr(mcr_pack(6, 110));
274 ioc3_w_mcr(mcr_pack(80, 30));
280 * Read a byte from an iButton device
282 static u32
nic_read_byte(struct ioc3
*ioc3
)
287 for (i
= 0; i
< 8; i
++)
288 result
= (result
>> 1) | (nic_read_bit(ioc3
) << 7);
294 * Write a byte to an iButton device
296 static void nic_write_byte(struct ioc3
*ioc3
, int byte
)
300 for (i
= 8; i
; i
--) {
304 nic_write_bit(ioc3
, bit
);
308 static u64
nic_find(struct ioc3
*ioc3
, int *last
)
310 int a
, b
, index
, disc
;
315 nic_write_byte(ioc3
, 0xf0);
317 /* Algorithm from ``Book of iButton Standards''. */
318 for (index
= 0, disc
= 0; index
< 64; index
++) {
319 a
= nic_read_bit(ioc3
);
320 b
= nic_read_bit(ioc3
);
323 printk("NIC search failed (not fatal).\n");
329 if (index
== *last
) {
330 address
|= 1UL << index
;
331 } else if (index
> *last
) {
332 address
&= ~(1UL << index
);
334 } else if ((address
& (1UL << index
)) == 0)
336 nic_write_bit(ioc3
, address
& (1UL << index
));
340 address
|= 1UL << index
;
342 address
&= ~(1UL << index
);
343 nic_write_bit(ioc3
, a
);
353 static int nic_init(struct ioc3
*ioc3
)
364 reg
= nic_find(ioc3
, &save
);
366 switch (reg
& 0xff) {
372 /* Let the caller try again. */
381 nic_write_byte(ioc3
, 0x55);
382 for (i
= 0; i
< 8; i
++)
383 nic_write_byte(ioc3
, (reg
>> (i
<< 3)) & 0xff);
385 reg
>>= 8; /* Shift out type. */
386 for (i
= 0; i
< 6; i
++) {
387 serial
[i
] = reg
& 0xff;
394 printk("Found %s NIC", type
);
395 if (type
!= "unknown") {
396 printk (" registration number %02x:%02x:%02x:%02x:%02x:%02x,"
397 " CRC %02x", serial
[0], serial
[1], serial
[2],
398 serial
[3], serial
[4], serial
[5], crc
);
406 * Read the NIC (Number-In-a-Can) device used to store the MAC address on
407 * SN0 / SN00 nodeboards and PCI cards.
409 static void ioc3_get_eaddr_nic(struct ioc3_private
*ip
)
411 struct ioc3
*ioc3
= ip
->regs
;
413 int tries
= 2; /* There may be some problem with the battery? */
416 ioc3_w_gpcr_s(1 << 21);
425 printk("Failed to read MAC address\n");
430 nic_write_byte(ioc3
, 0xf0);
431 nic_write_byte(ioc3
, 0x00);
432 nic_write_byte(ioc3
, 0x00);
434 for (i
= 13; i
>= 0; i
--)
435 nic
[i
] = nic_read_byte(ioc3
);
437 for (i
= 2; i
< 8; i
++)
438 priv_netdev(ip
)->dev_addr
[i
- 2] = nic
[i
];
442 * Ok, this is hosed by design. It's necessary to know what machine the
443 * NIC is in in order to know how to read the NIC address. We also have
444 * to know if it's a PCI card or a NIC in on the node board ...
446 static void ioc3_get_eaddr(struct ioc3_private
*ip
)
451 ioc3_get_eaddr_nic(ip
);
453 printk("Ethernet address is ");
454 for (i
= 0; i
< 6; i
++) {
455 printk("%02x", priv_netdev(ip
)->dev_addr
[i
]);
462 static void __ioc3_set_mac_address(struct net_device
*dev
)
464 struct ioc3_private
*ip
= netdev_priv(dev
);
465 struct ioc3
*ioc3
= ip
->regs
;
467 ioc3_w_emar_h((dev
->dev_addr
[5] << 8) | dev
->dev_addr
[4]);
468 ioc3_w_emar_l((dev
->dev_addr
[3] << 24) | (dev
->dev_addr
[2] << 16) |
469 (dev
->dev_addr
[1] << 8) | dev
->dev_addr
[0]);
472 static int ioc3_set_mac_address(struct net_device
*dev
, void *addr
)
474 struct ioc3_private
*ip
= netdev_priv(dev
);
475 struct sockaddr
*sa
= addr
;
477 memcpy(dev
->dev_addr
, sa
->sa_data
, dev
->addr_len
);
479 spin_lock_irq(&ip
->ioc3_lock
);
480 __ioc3_set_mac_address(dev
);
481 spin_unlock_irq(&ip
->ioc3_lock
);
487 * Caller must hold the ioc3_lock ever for MII readers. This is also
488 * used to protect the transmitter side but it's low contention.
490 static int ioc3_mdio_read(struct net_device
*dev
, int phy
, int reg
)
492 struct ioc3_private
*ip
= netdev_priv(dev
);
493 struct ioc3
*ioc3
= ip
->regs
;
495 while (ioc3_r_micr() & MICR_BUSY
);
496 ioc3_w_micr((phy
<< MICR_PHYADDR_SHIFT
) | reg
| MICR_READTRIG
);
497 while (ioc3_r_micr() & MICR_BUSY
);
499 return ioc3_r_midr_r() & MIDR_DATA_MASK
;
502 static void ioc3_mdio_write(struct net_device
*dev
, int phy
, int reg
, int data
)
504 struct ioc3_private
*ip
= netdev_priv(dev
);
505 struct ioc3
*ioc3
= ip
->regs
;
507 while (ioc3_r_micr() & MICR_BUSY
);
509 ioc3_w_micr((phy
<< MICR_PHYADDR_SHIFT
) | reg
);
510 while (ioc3_r_micr() & MICR_BUSY
);
513 static int ioc3_mii_init(struct ioc3_private
*ip
);
515 static struct net_device_stats
*ioc3_get_stats(struct net_device
*dev
)
517 struct ioc3_private
*ip
= netdev_priv(dev
);
518 struct ioc3
*ioc3
= ip
->regs
;
520 ip
->stats
.collisions
+= (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK
);
524 #ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM
526 static void ioc3_tcpudp_checksum(struct sk_buff
*skb
, uint32_t hwsum
, int len
)
528 struct ethhdr
*eh
= eth_hdr(skb
);
529 uint32_t csum
, ehsum
;
536 * Did hardware handle the checksum at all? The cases we can handle
539 * - TCP and UDP checksums of IPv4 only.
540 * - IPv6 would be doable but we keep that for later ...
541 * - Only unfragmented packets. Did somebody already tell you
542 * fragmentation is evil?
543 * - don't care about packet size. Worst case when processing a
544 * malformed packet we'll try to access the packet at ip header +
545 * 64 bytes which is still inside the skb. Even in the unlikely
546 * case where the checksum is right the higher layers will still
547 * drop the packet as appropriate.
549 if (eh
->h_proto
!= ntohs(ETH_P_IP
))
552 ih
= (struct iphdr
*) ((char *)eh
+ ETH_HLEN
);
553 if (ih
->frag_off
& htons(IP_MF
| IP_OFFSET
))
556 proto
= ih
->protocol
;
557 if (proto
!= IPPROTO_TCP
&& proto
!= IPPROTO_UDP
)
560 /* Same as tx - compute csum of pseudo header */
562 (ih
->tot_len
- (ih
->ihl
<< 2)) +
563 htons((uint16_t)ih
->protocol
) +
564 (ih
->saddr
>> 16) + (ih
->saddr
& 0xffff) +
565 (ih
->daddr
>> 16) + (ih
->daddr
& 0xffff);
567 /* Sum up ethernet dest addr, src addr and protocol */
568 ew
= (uint16_t *) eh
;
569 ehsum
= ew
[0] + ew
[1] + ew
[2] + ew
[3] + ew
[4] + ew
[5] + ew
[6];
571 ehsum
= (ehsum
& 0xffff) + (ehsum
>> 16);
572 ehsum
= (ehsum
& 0xffff) + (ehsum
>> 16);
574 csum
+= 0xffff ^ ehsum
;
576 /* In the next step we also subtract the 1's complement
577 checksum of the trailing ethernet CRC. */
578 cp
= (char *)eh
+ len
; /* points at trailing CRC */
580 csum
+= 0xffff ^ (uint16_t) ((cp
[1] << 8) | cp
[0]);
581 csum
+= 0xffff ^ (uint16_t) ((cp
[3] << 8) | cp
[2]);
583 csum
+= 0xffff ^ (uint16_t) ((cp
[0] << 8) | cp
[1]);
584 csum
+= 0xffff ^ (uint16_t) ((cp
[2] << 8) | cp
[3]);
587 csum
= (csum
& 0xffff) + (csum
>> 16);
588 csum
= (csum
& 0xffff) + (csum
>> 16);
591 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
593 #endif /* CONFIG_SGI_IOC3_ETH_HW_RX_CSUM */
595 static inline void ioc3_rx(struct ioc3_private
*ip
)
597 struct sk_buff
*skb
, *new_skb
;
598 struct ioc3
*ioc3
= ip
->regs
;
599 int rx_entry
, n_entry
, len
;
600 struct ioc3_erxbuf
*rxb
;
604 rxr
= (unsigned long *) ip
->rxr
; /* Ring base */
605 rx_entry
= ip
->rx_ci
; /* RX consume index */
608 skb
= ip
->rx_skbs
[rx_entry
];
609 rxb
= (struct ioc3_erxbuf
*) (skb
->data
- RX_OFFSET
);
610 w0
= be32_to_cpu(rxb
->w0
);
612 while (w0
& ERXBUF_V
) {
613 err
= be32_to_cpu(rxb
->err
); /* It's valid ... */
614 if (err
& ERXBUF_GOODPKT
) {
615 len
= ((w0
>> ERXBUF_BYTECNT_SHIFT
) & 0x7ff) - 4;
617 skb
->protocol
= eth_type_trans(skb
, priv_netdev(ip
));
619 new_skb
= ioc3_alloc_skb(RX_BUF_ALLOC_SIZE
, GFP_ATOMIC
);
621 /* Ouch, drop packet and just recycle packet
622 to keep the ring filled. */
623 ip
->stats
.rx_dropped
++;
628 #ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM
629 ioc3_tcpudp_checksum(skb
, w0
& ERXBUF_IPCKSUM_MASK
,len
);
634 ip
->rx_skbs
[rx_entry
] = NULL
; /* Poison */
636 new_skb
->dev
= priv_netdev(ip
);
638 /* Because we reserve afterwards. */
639 skb_put(new_skb
, (1664 + RX_OFFSET
));
640 rxb
= (struct ioc3_erxbuf
*) new_skb
->data
;
641 skb_reserve(new_skb
, RX_OFFSET
);
643 priv_netdev(ip
)->last_rx
= jiffies
;
644 ip
->stats
.rx_packets
++; /* Statistics */
645 ip
->stats
.rx_bytes
+= len
;
647 /* The frame is invalid and the skb never
648 reached the network layer so we can just
651 ip
->stats
.rx_errors
++;
653 if (err
& ERXBUF_CRCERR
) /* Statistics */
654 ip
->stats
.rx_crc_errors
++;
655 if (err
& ERXBUF_FRAMERR
)
656 ip
->stats
.rx_frame_errors
++;
658 ip
->rx_skbs
[n_entry
] = new_skb
;
659 rxr
[n_entry
] = cpu_to_be64(ioc3_map(rxb
, 1));
660 rxb
->w0
= 0; /* Clear valid flag */
661 n_entry
= (n_entry
+ 1) & 511; /* Update erpir */
663 /* Now go on to the next ring entry. */
664 rx_entry
= (rx_entry
+ 1) & 511;
665 skb
= ip
->rx_skbs
[rx_entry
];
666 rxb
= (struct ioc3_erxbuf
*) (skb
->data
- RX_OFFSET
);
667 w0
= be32_to_cpu(rxb
->w0
);
669 ioc3_w_erpir((n_entry
<< 3) | ERPIR_ARM
);
671 ip
->rx_ci
= rx_entry
;
674 static inline void ioc3_tx(struct ioc3_private
*ip
)
676 unsigned long packets
, bytes
;
677 struct ioc3
*ioc3
= ip
->regs
;
678 int tx_entry
, o_entry
;
682 spin_lock(&ip
->ioc3_lock
);
683 etcir
= ioc3_r_etcir();
685 tx_entry
= (etcir
>> 7) & 127;
690 while (o_entry
!= tx_entry
) {
692 skb
= ip
->tx_skbs
[o_entry
];
694 dev_kfree_skb_irq(skb
);
695 ip
->tx_skbs
[o_entry
] = NULL
;
697 o_entry
= (o_entry
+ 1) & 127; /* Next */
699 etcir
= ioc3_r_etcir(); /* More pkts sent? */
700 tx_entry
= (etcir
>> 7) & 127;
703 ip
->stats
.tx_packets
+= packets
;
704 ip
->stats
.tx_bytes
+= bytes
;
705 ip
->txqlen
-= packets
;
707 if (ip
->txqlen
< 128)
708 netif_wake_queue(priv_netdev(ip
));
711 spin_unlock(&ip
->ioc3_lock
);
715 * Deal with fatal IOC3 errors. This condition might be caused by a hard or
716 * software problems, so we should try to recover
717 * more gracefully if this ever happens. In theory we might be flooded
718 * with such error interrupts if something really goes wrong, so we might
719 * also consider to take the interface down.
721 static void ioc3_error(struct ioc3_private
*ip
, u32 eisr
)
723 struct net_device
*dev
= priv_netdev(ip
);
724 unsigned char *iface
= dev
->name
;
726 spin_lock(&ip
->ioc3_lock
);
728 if (eisr
& EISR_RXOFLO
)
729 printk(KERN_ERR
"%s: RX overflow.\n", iface
);
730 if (eisr
& EISR_RXBUFOFLO
)
731 printk(KERN_ERR
"%s: RX buffer overflow.\n", iface
);
732 if (eisr
& EISR_RXMEMERR
)
733 printk(KERN_ERR
"%s: RX PCI error.\n", iface
);
734 if (eisr
& EISR_RXPARERR
)
735 printk(KERN_ERR
"%s: RX SSRAM parity error.\n", iface
);
736 if (eisr
& EISR_TXBUFUFLO
)
737 printk(KERN_ERR
"%s: TX buffer underflow.\n", iface
);
738 if (eisr
& EISR_TXMEMERR
)
739 printk(KERN_ERR
"%s: TX PCI error.\n", iface
);
745 netif_wake_queue(dev
);
747 spin_unlock(&ip
->ioc3_lock
);
750 /* The interrupt handler does all of the Rx thread work and cleans up
751 after the Tx thread. */
752 static irqreturn_t
ioc3_interrupt(int irq
, void *_dev
)
754 struct net_device
*dev
= (struct net_device
*)_dev
;
755 struct ioc3_private
*ip
= netdev_priv(dev
);
756 struct ioc3
*ioc3
= ip
->regs
;
757 const u32 enabled
= EISR_RXTIMERINT
| EISR_RXOFLO
| EISR_RXBUFOFLO
|
758 EISR_RXMEMERR
| EISR_RXPARERR
| EISR_TXBUFUFLO
|
759 EISR_TXEXPLICIT
| EISR_TXMEMERR
;
762 eisr
= ioc3_r_eisr() & enabled
;
765 (void) ioc3_r_eisr(); /* Flush */
767 if (eisr
& (EISR_RXOFLO
| EISR_RXBUFOFLO
| EISR_RXMEMERR
|
768 EISR_RXPARERR
| EISR_TXBUFUFLO
| EISR_TXMEMERR
))
769 ioc3_error(ip
, eisr
);
770 if (eisr
& EISR_RXTIMERINT
)
772 if (eisr
& EISR_TXEXPLICIT
)
778 static inline void ioc3_setup_duplex(struct ioc3_private
*ip
)
780 struct ioc3
*ioc3
= ip
->regs
;
782 if (ip
->mii
.full_duplex
) {
783 ioc3_w_etcsr(ETCSR_FD
);
784 ip
->emcr
|= EMCR_DUPLEX
;
786 ioc3_w_etcsr(ETCSR_HD
);
787 ip
->emcr
&= ~EMCR_DUPLEX
;
789 ioc3_w_emcr(ip
->emcr
);
792 static void ioc3_timer(unsigned long data
)
794 struct ioc3_private
*ip
= (struct ioc3_private
*) data
;
796 /* Print the link status if it has changed */
797 mii_check_media(&ip
->mii
, 1, 0);
798 ioc3_setup_duplex(ip
);
800 ip
->ioc3_timer
.expires
= jiffies
+ ((12 * HZ
)/10); /* 1.2s */
801 add_timer(&ip
->ioc3_timer
);
805 * Try to find a PHY. There is no apparent relation between the MII addresses
806 * in the SGI documentation and what we find in reality, so we simply probe
807 * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my
808 * onboard IOC3s has the special oddity that probing doesn't seem to find it
809 * yet the interface seems to work fine, so if probing fails we for now will
810 * simply default to PHY 31 instead of bailing out.
812 static int ioc3_mii_init(struct ioc3_private
*ip
)
814 struct net_device
*dev
= priv_netdev(ip
);
815 int i
, found
= 0, res
= 0;
816 int ioc3_phy_workaround
= 1;
819 for (i
= 0; i
< 32; i
++) {
820 word
= ioc3_mdio_read(dev
, i
, MII_PHYSID1
);
822 if (word
!= 0xffff && word
!= 0x0000) {
824 break; /* Found a PHY */
829 if (ioc3_phy_workaround
)
839 ip
->ioc3_timer
.expires
= jiffies
+ (12 * HZ
)/10; /* 1.2 sec. */
840 ip
->ioc3_timer
.data
= (unsigned long) ip
;
841 ip
->ioc3_timer
.function
= &ioc3_timer
;
842 add_timer(&ip
->ioc3_timer
);
848 static inline void ioc3_clean_rx_ring(struct ioc3_private
*ip
)
853 for (i
= ip
->rx_ci
; i
& 15; i
++) {
854 ip
->rx_skbs
[ip
->rx_pi
] = ip
->rx_skbs
[ip
->rx_ci
];
855 ip
->rxr
[ip
->rx_pi
++] = ip
->rxr
[ip
->rx_ci
++];
860 for (i
= ip
->rx_ci
; i
!= ip
->rx_pi
; i
= (i
+1) & 511) {
861 struct ioc3_erxbuf
*rxb
;
862 skb
= ip
->rx_skbs
[i
];
863 rxb
= (struct ioc3_erxbuf
*) (skb
->data
- RX_OFFSET
);
868 static inline void ioc3_clean_tx_ring(struct ioc3_private
*ip
)
873 for (i
=0; i
< 128; i
++) {
874 skb
= ip
->tx_skbs
[i
];
876 ip
->tx_skbs
[i
] = NULL
;
877 dev_kfree_skb_any(skb
);
885 static void ioc3_free_rings(struct ioc3_private
*ip
)
888 int rx_entry
, n_entry
;
891 ioc3_clean_tx_ring(ip
);
892 free_pages((unsigned long)ip
->txr
, 2);
898 rx_entry
= ip
->rx_pi
;
900 while (n_entry
!= rx_entry
) {
901 skb
= ip
->rx_skbs
[n_entry
];
903 dev_kfree_skb_any(skb
);
905 n_entry
= (n_entry
+ 1) & 511;
907 free_page((unsigned long)ip
->rxr
);
912 static void ioc3_alloc_rings(struct net_device
*dev
)
914 struct ioc3_private
*ip
= netdev_priv(dev
);
915 struct ioc3_erxbuf
*rxb
;
919 if (ip
->rxr
== NULL
) {
920 /* Allocate and initialize rx ring. 4kb = 512 entries */
921 ip
->rxr
= (unsigned long *) get_zeroed_page(GFP_ATOMIC
);
922 rxr
= (unsigned long *) ip
->rxr
;
924 printk("ioc3_alloc_rings(): get_zeroed_page() failed!\n");
926 /* Now the rx buffers. The RX ring may be larger but
927 we only allocate 16 buffers for now. Need to tune
928 this for performance and memory later. */
929 for (i
= 0; i
< RX_BUFFS
; i
++) {
932 skb
= ioc3_alloc_skb(RX_BUF_ALLOC_SIZE
, GFP_ATOMIC
);
938 ip
->rx_skbs
[i
] = skb
;
941 /* Because we reserve afterwards. */
942 skb_put(skb
, (1664 + RX_OFFSET
));
943 rxb
= (struct ioc3_erxbuf
*) skb
->data
;
944 rxr
[i
] = cpu_to_be64(ioc3_map(rxb
, 1));
945 skb_reserve(skb
, RX_OFFSET
);
948 ip
->rx_pi
= RX_BUFFS
;
951 if (ip
->txr
== NULL
) {
952 /* Allocate and initialize tx rings. 16kb = 128 bufs. */
953 ip
->txr
= (struct ioc3_etxd
*)__get_free_pages(GFP_KERNEL
, 2);
955 printk("ioc3_alloc_rings(): __get_free_pages() failed!\n");
961 static void ioc3_init_rings(struct net_device
*dev
)
963 struct ioc3_private
*ip
= netdev_priv(dev
);
964 struct ioc3
*ioc3
= ip
->regs
;
968 ioc3_alloc_rings(dev
);
970 ioc3_clean_rx_ring(ip
);
971 ioc3_clean_tx_ring(ip
);
973 /* Now the rx ring base, consume & produce registers. */
974 ring
= ioc3_map(ip
->rxr
, 0);
975 ioc3_w_erbr_h(ring
>> 32);
976 ioc3_w_erbr_l(ring
& 0xffffffff);
977 ioc3_w_ercir(ip
->rx_ci
<< 3);
978 ioc3_w_erpir((ip
->rx_pi
<< 3) | ERPIR_ARM
);
980 ring
= ioc3_map(ip
->txr
, 0);
982 ip
->txqlen
= 0; /* nothing queued */
984 /* Now the tx ring base, consume & produce registers. */
985 ioc3_w_etbr_h(ring
>> 32);
986 ioc3_w_etbr_l(ring
& 0xffffffff);
987 ioc3_w_etpir(ip
->tx_pi
<< 7);
988 ioc3_w_etcir(ip
->tx_ci
<< 7);
989 (void) ioc3_r_etcir(); /* Flush */
992 static inline void ioc3_ssram_disc(struct ioc3_private
*ip
)
994 struct ioc3
*ioc3
= ip
->regs
;
995 volatile u32
*ssram0
= &ioc3
->ssram
[0x0000];
996 volatile u32
*ssram1
= &ioc3
->ssram
[0x4000];
997 unsigned int pattern
= 0x5555;
999 /* Assume the larger size SSRAM and enable parity checking */
1000 ioc3_w_emcr(ioc3_r_emcr() | (EMCR_BUFSIZ
| EMCR_RAMPAR
));
1003 *ssram1
= ~pattern
& IOC3_SSRAM_DM
;
1005 if ((*ssram0
& IOC3_SSRAM_DM
) != pattern
||
1006 (*ssram1
& IOC3_SSRAM_DM
) != (~pattern
& IOC3_SSRAM_DM
)) {
1007 /* set ssram size to 64 KB */
1008 ip
->emcr
= EMCR_RAMPAR
;
1009 ioc3_w_emcr(ioc3_r_emcr() & ~EMCR_BUFSIZ
);
1011 ip
->emcr
= EMCR_BUFSIZ
| EMCR_RAMPAR
;
1014 static void ioc3_init(struct net_device
*dev
)
1016 struct ioc3_private
*ip
= netdev_priv(dev
);
1017 struct ioc3
*ioc3
= ip
->regs
;
1019 del_timer_sync(&ip
->ioc3_timer
); /* Kill if running */
1021 ioc3_w_emcr(EMCR_RST
); /* Reset */
1022 (void) ioc3_r_emcr(); /* Flush WB */
1023 udelay(4); /* Give it time ... */
1025 (void) ioc3_r_emcr();
1027 /* Misc registers */
1028 #ifdef CONFIG_SGI_IP27
1029 ioc3_w_erbar(PCI64_ATTR_BAR
>> 32); /* Barrier on last store */
1031 ioc3_w_erbar(0); /* Let PCI API get it right */
1033 (void) ioc3_r_etcdc(); /* Clear on read */
1034 ioc3_w_ercsr(15); /* RX low watermark */
1035 ioc3_w_ertr(0); /* Interrupt immediately */
1036 __ioc3_set_mac_address(dev
);
1037 ioc3_w_ehar_h(ip
->ehar_h
);
1038 ioc3_w_ehar_l(ip
->ehar_l
);
1039 ioc3_w_ersr(42); /* XXX should be random */
1041 ioc3_init_rings(dev
);
1043 ip
->emcr
|= ((RX_OFFSET
/ 2) << EMCR_RXOFF_SHIFT
) | EMCR_TXDMAEN
|
1044 EMCR_TXEN
| EMCR_RXDMAEN
| EMCR_RXEN
| EMCR_PADEN
;
1045 ioc3_w_emcr(ip
->emcr
);
1046 ioc3_w_eier(EISR_RXTIMERINT
| EISR_RXOFLO
| EISR_RXBUFOFLO
|
1047 EISR_RXMEMERR
| EISR_RXPARERR
| EISR_TXBUFUFLO
|
1048 EISR_TXEXPLICIT
| EISR_TXMEMERR
);
1049 (void) ioc3_r_eier();
1052 static inline void ioc3_stop(struct ioc3_private
*ip
)
1054 struct ioc3
*ioc3
= ip
->regs
;
1056 ioc3_w_emcr(0); /* Shutup */
1057 ioc3_w_eier(0); /* Disable interrupts */
1058 (void) ioc3_r_eier(); /* Flush */
1061 static int ioc3_open(struct net_device
*dev
)
1063 struct ioc3_private
*ip
= netdev_priv(dev
);
1065 if (request_irq(dev
->irq
, ioc3_interrupt
, IRQF_SHARED
, ioc3_str
, dev
)) {
1066 printk(KERN_ERR
"%s: Can't get irq %d\n", dev
->name
, dev
->irq
);
1075 netif_start_queue(dev
);
1079 static int ioc3_close(struct net_device
*dev
)
1081 struct ioc3_private
*ip
= netdev_priv(dev
);
1083 del_timer_sync(&ip
->ioc3_timer
);
1085 netif_stop_queue(dev
);
1088 free_irq(dev
->irq
, dev
);
1090 ioc3_free_rings(ip
);
1095 * MENET cards have four IOC3 chips, which are attached to two sets of
1096 * PCI slot resources each: the primary connections are on slots
1097 * 0..3 and the secondaries are on 4..7
1099 * All four ethernets are brought out to connectors; six serial ports
1100 * (a pair from each of the first three IOC3s) are brought out to
1101 * MiniDINs; all other subdevices are left swinging in the wind, leave
1104 static inline int ioc3_is_menet(struct pci_dev
*pdev
)
1106 struct pci_dev
*dev
;
1108 return pdev
->bus
->parent
== NULL
1109 && (dev
= pci_find_slot(pdev
->bus
->number
, PCI_DEVFN(0, 0)))
1110 && dev
->vendor
== PCI_VENDOR_ID_SGI
1111 && dev
->device
== PCI_DEVICE_ID_SGI_IOC3
1112 && (dev
= pci_find_slot(pdev
->bus
->number
, PCI_DEVFN(1, 0)))
1113 && dev
->vendor
== PCI_VENDOR_ID_SGI
1114 && dev
->device
== PCI_DEVICE_ID_SGI_IOC3
1115 && (dev
= pci_find_slot(pdev
->bus
->number
, PCI_DEVFN(2, 0)))
1116 && dev
->vendor
== PCI_VENDOR_ID_SGI
1117 && dev
->device
== PCI_DEVICE_ID_SGI_IOC3
;
1120 #ifdef CONFIG_SERIAL_8250
1122 * Note about serial ports and consoles:
1123 * For console output, everyone uses the IOC3 UARTA (offset 0x178)
1124 * connected to the master node (look in ip27_setup_console() and
1125 * ip27prom_console_write()).
1127 * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port
1128 * addresses on a partitioned machine. Since we currently use the ioc3
1129 * serial ports, we use dynamic serial port discovery that the serial.c
1130 * driver uses for pci/pnp ports (there is an entry for the SGI ioc3
1131 * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater
1132 * than UARTB's, although UARTA on o200s has traditionally been known as
1133 * port 0. So, we just use one serial port from each ioc3 (since the
1134 * serial driver adds addresses to get to higher ports).
1136 * The first one to do a register_console becomes the preferred console
1137 * (if there is no kernel command line console= directive). /dev/console
1138 * (ie 5, 1) is then "aliased" into the device number returned by the
1139 * "device" routine referred to in this console structure
1140 * (ip27prom_console_dev).
1142 * Also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working
1143 * around ioc3 oddities in this respect.
1145 * The IOC3 serials use a 22MHz clock rate with an additional divider by 3.
1148 static void __devinit
ioc3_serial_probe(struct pci_dev
*pdev
, struct ioc3
*ioc3
)
1150 struct uart_port port
;
1153 * We need to recognice and treat the fourth MENET serial as it
1154 * does not have an SuperIO chip attached to it, therefore attempting
1155 * to access it will result in bus errors. We call something an
1156 * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3
1157 * in it. This is paranoid but we want to avoid blowing up on a
1158 * showhorn PCI box that happens to have 4 IOC3 cards in it so it's
1159 * not paranoid enough ...
1161 if (ioc3_is_menet(pdev
) && PCI_SLOT(pdev
->devfn
) == 3)
1165 * Register to interrupt zero because we share the interrupt with
1166 * the serial driver which we don't properly support yet.
1168 * Can't use UPF_IOREMAP as the whole of IOC3 resources have already
1171 memset(&port
, 0, sizeof(port
));
1173 port
.flags
= UPF_SKIP_TEST
| UPF_BOOT_AUTOCONF
;
1174 port
.iotype
= UPIO_MEM
;
1176 port
.uartclk
= 22000000 / 3;
1178 port
.membase
= (unsigned char *) &ioc3
->sregs
.uarta
;
1179 serial8250_register_port(&port
);
1181 port
.membase
= (unsigned char *) &ioc3
->sregs
.uartb
;
1182 serial8250_register_port(&port
);
1186 static int ioc3_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1188 unsigned int sw_physid1
, sw_physid2
;
1189 struct net_device
*dev
= NULL
;
1190 struct ioc3_private
*ip
;
1192 unsigned long ioc3_base
, ioc3_size
;
1193 u32 vendor
, model
, rev
;
1194 int err
, pci_using_dac
;
1196 /* Configure DMA attributes. */
1197 err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
);
1200 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
1202 printk(KERN_ERR
"%s: Unable to obtain 64 bit DMA "
1203 "for consistent allocations\n", pci_name(pdev
));
1207 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1209 printk(KERN_ERR
"%s: No usable DMA configuration, "
1210 "aborting.\n", pci_name(pdev
));
1216 if (pci_enable_device(pdev
))
1219 dev
= alloc_etherdev(sizeof(struct ioc3_private
));
1226 dev
->features
|= NETIF_F_HIGHDMA
;
1228 err
= pci_request_regions(pdev
, "ioc3");
1232 SET_MODULE_OWNER(dev
);
1233 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1235 ip
= netdev_priv(dev
);
1237 dev
->irq
= pdev
->irq
;
1239 ioc3_base
= pci_resource_start(pdev
, 0);
1240 ioc3_size
= pci_resource_len(pdev
, 0);
1241 ioc3
= (struct ioc3
*) ioremap(ioc3_base
, ioc3_size
);
1243 printk(KERN_CRIT
"ioc3eth(%s): ioremap failed, goodbye.\n",
1250 #ifdef CONFIG_SERIAL_8250
1251 ioc3_serial_probe(pdev
, ioc3
);
1254 spin_lock_init(&ip
->ioc3_lock
);
1255 init_timer(&ip
->ioc3_timer
);
1262 ip
->mii
.phy_id_mask
= 0x1f;
1263 ip
->mii
.reg_num_mask
= 0x1f;
1265 ip
->mii
.mdio_read
= ioc3_mdio_read
;
1266 ip
->mii
.mdio_write
= ioc3_mdio_write
;
1270 if (ip
->mii
.phy_id
== -1) {
1271 printk(KERN_CRIT
"ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
1277 ioc3_ssram_disc(ip
);
1280 /* The IOC3-specific entries in the device structure. */
1281 dev
->open
= ioc3_open
;
1282 dev
->hard_start_xmit
= ioc3_start_xmit
;
1283 dev
->tx_timeout
= ioc3_timeout
;
1284 dev
->watchdog_timeo
= 5 * HZ
;
1285 dev
->stop
= ioc3_close
;
1286 dev
->get_stats
= ioc3_get_stats
;
1287 dev
->do_ioctl
= ioc3_ioctl
;
1288 dev
->set_multicast_list
= ioc3_set_multicast_list
;
1289 dev
->set_mac_address
= ioc3_set_mac_address
;
1290 dev
->ethtool_ops
= &ioc3_ethtool_ops
;
1291 #ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM
1292 dev
->features
= NETIF_F_IP_CSUM
;
1295 sw_physid1
= ioc3_mdio_read(dev
, ip
->mii
.phy_id
, MII_PHYSID1
);
1296 sw_physid2
= ioc3_mdio_read(dev
, ip
->mii
.phy_id
, MII_PHYSID2
);
1298 err
= register_netdev(dev
);
1302 mii_check_media(&ip
->mii
, 1, 1);
1303 ioc3_setup_duplex(ip
);
1305 vendor
= (sw_physid1
<< 12) | (sw_physid2
>> 4);
1306 model
= (sw_physid2
>> 4) & 0x3f;
1307 rev
= sw_physid2
& 0xf;
1308 printk(KERN_INFO
"%s: Using PHY %d, vendor 0x%x, model %d, "
1309 "rev %d.\n", dev
->name
, ip
->mii
.phy_id
, vendor
, model
, rev
);
1310 printk(KERN_INFO
"%s: IOC3 SSRAM has %d kbyte.\n", dev
->name
,
1311 ip
->emcr
& EMCR_BUFSIZ
? 128 : 64);
1317 ioc3_free_rings(ip
);
1319 pci_release_regions(pdev
);
1324 * We should call pci_disable_device(pdev); here if the IOC3 wasn't
1325 * such a weird device ...
1331 static void __devexit
ioc3_remove_one (struct pci_dev
*pdev
)
1333 struct net_device
*dev
= pci_get_drvdata(pdev
);
1334 struct ioc3_private
*ip
= netdev_priv(dev
);
1335 struct ioc3
*ioc3
= ip
->regs
;
1337 unregister_netdev(dev
);
1339 pci_release_regions(pdev
);
1342 * We should call pci_disable_device(pdev); here if the IOC3 wasn't
1343 * such a weird device ...
1347 static struct pci_device_id ioc3_pci_tbl
[] = {
1348 { PCI_VENDOR_ID_SGI
, PCI_DEVICE_ID_SGI_IOC3
, PCI_ANY_ID
, PCI_ANY_ID
},
1351 MODULE_DEVICE_TABLE(pci
, ioc3_pci_tbl
);
1353 static struct pci_driver ioc3_driver
= {
1355 .id_table
= ioc3_pci_tbl
,
1356 .probe
= ioc3_probe
,
1357 .remove
= __devexit_p(ioc3_remove_one
),
1360 static int __init
ioc3_init_module(void)
1362 return pci_register_driver(&ioc3_driver
);
1365 static void __exit
ioc3_cleanup_module(void)
1367 pci_unregister_driver(&ioc3_driver
);
1370 static int ioc3_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1373 struct ioc3_private
*ip
= netdev_priv(dev
);
1374 struct ioc3
*ioc3
= ip
->regs
;
1376 struct ioc3_etxd
*desc
;
1380 #ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM
1382 * IOC3 has a fairly simple minded checksumming hardware which simply
1383 * adds up the 1's complement checksum for the entire packet and
1384 * inserts it at an offset which can be specified in the descriptor
1385 * into the transmit packet. This means we have to compensate for the
1386 * MAC header which should not be summed and the TCP/UDP pseudo headers
1389 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1390 int proto
= ntohs(skb
->nh
.iph
->protocol
);
1392 struct iphdr
*ih
= skb
->nh
.iph
;
1393 uint32_t csum
, ehsum
;
1396 /* The MAC header. skb->mac seem the logic approach
1397 to find the MAC header - except it's a NULL pointer ... */
1398 eh
= (uint16_t *) skb
->data
;
1400 /* Sum up dest addr, src addr and protocol */
1401 ehsum
= eh
[0] + eh
[1] + eh
[2] + eh
[3] + eh
[4] + eh
[5] + eh
[6];
1403 /* Fold ehsum. can't use csum_fold which negates also ... */
1404 ehsum
= (ehsum
& 0xffff) + (ehsum
>> 16);
1405 ehsum
= (ehsum
& 0xffff) + (ehsum
>> 16);
1407 /* Skip IP header; it's sum is always zero and was
1408 already filled in by ip_output.c */
1409 csum
= csum_tcpudp_nofold(ih
->saddr
, ih
->daddr
,
1410 ih
->tot_len
- (ih
->ihl
<< 2),
1411 proto
, 0xffff ^ ehsum
);
1413 csum
= (csum
& 0xffff) + (csum
>> 16); /* Fold again */
1414 csum
= (csum
& 0xffff) + (csum
>> 16);
1416 csoff
= ETH_HLEN
+ (ih
->ihl
<< 2);
1417 if (proto
== IPPROTO_UDP
) {
1418 csoff
+= offsetof(struct udphdr
, check
);
1419 skb
->h
.uh
->check
= csum
;
1421 if (proto
== IPPROTO_TCP
) {
1422 csoff
+= offsetof(struct tcphdr
, check
);
1423 skb
->h
.th
->check
= csum
;
1426 w0
= ETXD_DOCHECKSUM
| (csoff
<< ETXD_CHKOFF_SHIFT
);
1428 #endif /* CONFIG_SGI_IOC3_ETH_HW_TX_CSUM */
1430 spin_lock_irq(&ip
->ioc3_lock
);
1432 data
= (unsigned long) skb
->data
;
1435 produce
= ip
->tx_pi
;
1436 desc
= &ip
->txr
[produce
];
1439 /* Short packet, let's copy it directly into the ring. */
1440 memcpy(desc
->data
, skb
->data
, skb
->len
);
1441 if (len
< ETH_ZLEN
) {
1442 /* Very short packet, pad with zeros at the end. */
1443 memset(desc
->data
+ len
, 0, ETH_ZLEN
- len
);
1446 desc
->cmd
= cpu_to_be32(len
| ETXD_INTWHENDONE
| ETXD_D0V
| w0
);
1447 desc
->bufcnt
= cpu_to_be32(len
);
1448 } else if ((data
^ (data
+ len
- 1)) & 0x4000) {
1449 unsigned long b2
= (data
| 0x3fffUL
) + 1UL;
1450 unsigned long s1
= b2
- data
;
1451 unsigned long s2
= data
+ len
- b2
;
1453 desc
->cmd
= cpu_to_be32(len
| ETXD_INTWHENDONE
|
1454 ETXD_B1V
| ETXD_B2V
| w0
);
1455 desc
->bufcnt
= cpu_to_be32((s1
<< ETXD_B1CNT_SHIFT
) |
1456 (s2
<< ETXD_B2CNT_SHIFT
));
1457 desc
->p1
= cpu_to_be64(ioc3_map(skb
->data
, 1));
1458 desc
->p2
= cpu_to_be64(ioc3_map((void *) b2
, 1));
1460 /* Normal sized packet that doesn't cross a page boundary. */
1461 desc
->cmd
= cpu_to_be32(len
| ETXD_INTWHENDONE
| ETXD_B1V
| w0
);
1462 desc
->bufcnt
= cpu_to_be32(len
<< ETXD_B1CNT_SHIFT
);
1463 desc
->p1
= cpu_to_be64(ioc3_map(skb
->data
, 1));
1468 dev
->trans_start
= jiffies
;
1469 ip
->tx_skbs
[produce
] = skb
; /* Remember skb */
1470 produce
= (produce
+ 1) & 127;
1471 ip
->tx_pi
= produce
;
1472 ioc3_w_etpir(produce
<< 7); /* Fire ... */
1476 if (ip
->txqlen
>= 127)
1477 netif_stop_queue(dev
);
1479 spin_unlock_irq(&ip
->ioc3_lock
);
1484 static void ioc3_timeout(struct net_device
*dev
)
1486 struct ioc3_private
*ip
= netdev_priv(dev
);
1488 printk(KERN_ERR
"%s: transmit timed out, resetting\n", dev
->name
);
1490 spin_lock_irq(&ip
->ioc3_lock
);
1496 spin_unlock_irq(&ip
->ioc3_lock
);
1498 netif_wake_queue(dev
);
1502 * Given a multicast ethernet address, this routine calculates the
1503 * address's bit index in the logical address filter mask
1506 static inline unsigned int ioc3_hash(const unsigned char *addr
)
1508 unsigned int temp
= 0;
1512 crc
= ether_crc_le(ETH_ALEN
, addr
);
1514 crc
&= 0x3f; /* bit reverse lowest 6 bits for hash index */
1515 for (bits
= 6; --bits
>= 0; ) {
1517 temp
|= (crc
& 0x1);
1524 static void ioc3_get_drvinfo (struct net_device
*dev
,
1525 struct ethtool_drvinfo
*info
)
1527 struct ioc3_private
*ip
= netdev_priv(dev
);
1529 strcpy (info
->driver
, IOC3_NAME
);
1530 strcpy (info
->version
, IOC3_VERSION
);
1531 strcpy (info
->bus_info
, pci_name(ip
->pdev
));
1534 static int ioc3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1536 struct ioc3_private
*ip
= netdev_priv(dev
);
1539 spin_lock_irq(&ip
->ioc3_lock
);
1540 rc
= mii_ethtool_gset(&ip
->mii
, cmd
);
1541 spin_unlock_irq(&ip
->ioc3_lock
);
1546 static int ioc3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1548 struct ioc3_private
*ip
= netdev_priv(dev
);
1551 spin_lock_irq(&ip
->ioc3_lock
);
1552 rc
= mii_ethtool_sset(&ip
->mii
, cmd
);
1553 spin_unlock_irq(&ip
->ioc3_lock
);
1558 static int ioc3_nway_reset(struct net_device
*dev
)
1560 struct ioc3_private
*ip
= netdev_priv(dev
);
1563 spin_lock_irq(&ip
->ioc3_lock
);
1564 rc
= mii_nway_restart(&ip
->mii
);
1565 spin_unlock_irq(&ip
->ioc3_lock
);
1570 static u32
ioc3_get_link(struct net_device
*dev
)
1572 struct ioc3_private
*ip
= netdev_priv(dev
);
1575 spin_lock_irq(&ip
->ioc3_lock
);
1576 rc
= mii_link_ok(&ip
->mii
);
1577 spin_unlock_irq(&ip
->ioc3_lock
);
1582 static const struct ethtool_ops ioc3_ethtool_ops
= {
1583 .get_drvinfo
= ioc3_get_drvinfo
,
1584 .get_settings
= ioc3_get_settings
,
1585 .set_settings
= ioc3_set_settings
,
1586 .nway_reset
= ioc3_nway_reset
,
1587 .get_link
= ioc3_get_link
,
1590 static int ioc3_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
1592 struct ioc3_private
*ip
= netdev_priv(dev
);
1595 spin_lock_irq(&ip
->ioc3_lock
);
1596 rc
= generic_mii_ioctl(&ip
->mii
, if_mii(rq
), cmd
, NULL
);
1597 spin_unlock_irq(&ip
->ioc3_lock
);
1602 static void ioc3_set_multicast_list(struct net_device
*dev
)
1604 struct dev_mc_list
*dmi
= dev
->mc_list
;
1605 struct ioc3_private
*ip
= netdev_priv(dev
);
1606 struct ioc3
*ioc3
= ip
->regs
;
1610 netif_stop_queue(dev
); /* Lock out others. */
1612 if (dev
->flags
& IFF_PROMISC
) { /* Set promiscuous. */
1613 ip
->emcr
|= EMCR_PROMISC
;
1614 ioc3_w_emcr(ip
->emcr
);
1615 (void) ioc3_r_emcr();
1617 ip
->emcr
&= ~EMCR_PROMISC
;
1618 ioc3_w_emcr(ip
->emcr
); /* Clear promiscuous. */
1619 (void) ioc3_r_emcr();
1621 if ((dev
->flags
& IFF_ALLMULTI
) || (dev
->mc_count
> 64)) {
1622 /* Too many for hashing to make sense or we want all
1623 multicast packets anyway, so skip computing all the
1624 hashes and just accept all packets. */
1625 ip
->ehar_h
= 0xffffffff;
1626 ip
->ehar_l
= 0xffffffff;
1628 for (i
= 0; i
< dev
->mc_count
; i
++) {
1629 char *addr
= dmi
->dmi_addr
;
1635 ehar
|= (1UL << ioc3_hash(addr
));
1637 ip
->ehar_h
= ehar
>> 32;
1638 ip
->ehar_l
= ehar
& 0xffffffff;
1640 ioc3_w_ehar_h(ip
->ehar_h
);
1641 ioc3_w_ehar_l(ip
->ehar_l
);
1644 netif_wake_queue(dev
); /* Let us get going again. */
1647 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1648 MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
1649 MODULE_LICENSE("GPL");
1651 module_init(ioc3_init_module
);
1652 module_exit(ioc3_cleanup_module
);