1 /*********************************************************************
3 * Filename: w83977af_ir.c
5 * Description: FIR driver for the Winbond W83977AF Super I/O chip
6 * Status: Experimental.
7 * Author: Paul VanderSpek
8 * Created at: Wed Nov 4 11:46:16 1998
9 * Modified at: Fri Jan 28 12:10:59 2000
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
12 * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
13 * Copyright (c) 1998-1999 Rebel.com
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * Neither Paul VanderSpek nor Rebel.com admit liability nor provide
21 * warranty for any of this software. This material is provided "AS-IS"
24 * If you find bugs in this file, its very likely that the same bug
25 * will also be in pc87108.c since the implementations are quite
28 * Notice that all functions that needs to access the chip in _any_
29 * way, must save BSR register on entry, and restore it on exit.
30 * It is _very_ important to follow this policy!
34 * bank = inb( iobase+BSR);
36 * do_your_stuff_here();
38 * outb( bank, iobase+BSR);
40 ********************************************************************/
42 #include <linux/module.h>
43 #include <linux/kernel.h>
44 #include <linux/types.h>
45 #include <linux/skbuff.h>
46 #include <linux/netdevice.h>
47 #include <linux/ioport.h>
48 #include <linux/delay.h>
49 #include <linux/slab.h>
50 #include <linux/init.h>
51 #include <linux/rtnetlink.h>
52 #include <linux/dma-mapping.h>
56 #include <asm/byteorder.h>
58 #include <net/irda/irda.h>
59 #include <net/irda/wrapper.h>
60 #include <net/irda/irda_device.h>
62 #include "w83977af_ir.h"
64 #ifdef CONFIG_ARCH_NETWINDER /* Adjust to NetWinder differences */
65 #undef CONFIG_NETWINDER_TX_DMA_PROBLEMS /* Not needed */
66 #define CONFIG_NETWINDER_RX_DMA_PROBLEMS /* Must have this one! */
68 #undef CONFIG_USE_INTERNAL_TIMER /* Just cannot make that timer work */
69 #define CONFIG_USE_W977_PNP /* Currently needed */
70 #define PIO_MAX_SPEED 115200
72 static char *driver_name
= "w83977af_ir";
73 static int qos_mtt_bits
= 0x07; /* 1 ms or more */
75 #define CHIP_IO_EXTENT 8
77 static unsigned int io
[] = { 0x180, ~0, ~0, ~0 };
78 #ifdef CONFIG_ARCH_NETWINDER /* Adjust to NetWinder differences */
79 static unsigned int irq
[] = { 6, 0, 0, 0 };
81 static unsigned int irq
[] = { 11, 0, 0, 0 };
83 static unsigned int dma
[] = { 1, 0, 0, 0 };
84 static unsigned int efbase
[] = { W977_EFIO_BASE
, W977_EFIO2_BASE
};
85 static unsigned int efio
= W977_EFIO_BASE
;
87 static struct w83977af_ir
*dev_self
[] = { NULL
, NULL
, NULL
, NULL
};
90 static int w83977af_open(int i
, unsigned int iobase
, unsigned int irq
,
92 static int w83977af_close(struct w83977af_ir
*self
);
93 static int w83977af_probe(int iobase
, int irq
, int dma
);
94 static int w83977af_dma_receive(struct w83977af_ir
*self
);
95 static int w83977af_dma_receive_complete(struct w83977af_ir
*self
);
96 static int w83977af_hard_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
97 static int w83977af_pio_write(int iobase
, __u8
*buf
, int len
, int fifo_size
);
98 static void w83977af_dma_write(struct w83977af_ir
*self
, int iobase
);
99 static void w83977af_change_speed(struct w83977af_ir
*self
, __u32 speed
);
100 static int w83977af_is_receiving(struct w83977af_ir
*self
);
102 static int w83977af_net_open(struct net_device
*dev
);
103 static int w83977af_net_close(struct net_device
*dev
);
104 static int w83977af_net_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
105 static struct net_device_stats
*w83977af_net_get_stats(struct net_device
*dev
);
108 * Function w83977af_init ()
110 * Initialize chip. Just try to find out how many chips we are dealing with
113 static int __init
w83977af_init(void)
117 IRDA_DEBUG(0, "%s()\n", __FUNCTION__
);
119 for (i
=0; (io
[i
] < 2000) && (i
< ARRAY_SIZE(dev_self
)); i
++) {
120 if (w83977af_open(i
, io
[i
], irq
[i
], dma
[i
]) == 0)
127 * Function w83977af_cleanup ()
129 * Close all configured chips
132 static void __exit
w83977af_cleanup(void)
136 IRDA_DEBUG(4, "%s()\n", __FUNCTION__
);
138 for (i
=0; i
< ARRAY_SIZE(dev_self
); i
++) {
140 w83977af_close(dev_self
[i
]);
145 * Function w83977af_open (iobase, irq)
147 * Open driver instance
150 int w83977af_open(int i
, unsigned int iobase
, unsigned int irq
,
153 struct net_device
*dev
;
154 struct w83977af_ir
*self
;
157 IRDA_DEBUG(0, "%s()\n", __FUNCTION__
);
159 /* Lock the port that we need */
160 if (!request_region(iobase
, CHIP_IO_EXTENT
, driver_name
)) {
161 IRDA_DEBUG(0, "%s(), can't get iobase of 0x%03x\n",
162 __FUNCTION__
, iobase
);
166 if (w83977af_probe(iobase
, irq
, dma
) == -1) {
171 * Allocate new instance of the driver
173 dev
= alloc_irdadev(sizeof(struct w83977af_ir
));
175 printk( KERN_ERR
"IrDA: Can't allocate memory for "
176 "IrDA control block!\n");
182 spin_lock_init(&self
->lock
);
186 self
->io
.fir_base
= iobase
;
188 self
->io
.fir_ext
= CHIP_IO_EXTENT
;
190 self
->io
.fifo_size
= 32;
192 /* Initialize QoS for this device */
193 irda_init_max_qos_capabilies(&self
->qos
);
195 /* The only value we must override it the baudrate */
197 /* FIXME: The HP HDLS-1100 does not support 1152000! */
198 self
->qos
.baud_rate
.bits
= IR_9600
|IR_19200
|IR_38400
|IR_57600
|
199 IR_115200
|IR_576000
|IR_1152000
|(IR_4000000
<< 8);
201 /* The HP HDLS-1100 needs 1 ms according to the specs */
202 self
->qos
.min_turn_time
.bits
= qos_mtt_bits
;
203 irda_qos_bits_to_value(&self
->qos
);
205 /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
206 self
->rx_buff
.truesize
= 14384;
207 self
->tx_buff
.truesize
= 4000;
209 /* Allocate memory if needed */
211 dma_alloc_coherent(NULL
, self
->rx_buff
.truesize
,
212 &self
->rx_buff_dma
, GFP_KERNEL
);
213 if (self
->rx_buff
.head
== NULL
) {
218 memset(self
->rx_buff
.head
, 0, self
->rx_buff
.truesize
);
221 dma_alloc_coherent(NULL
, self
->tx_buff
.truesize
,
222 &self
->tx_buff_dma
, GFP_KERNEL
);
223 if (self
->tx_buff
.head
== NULL
) {
227 memset(self
->tx_buff
.head
, 0, self
->tx_buff
.truesize
);
229 self
->rx_buff
.in_frame
= FALSE
;
230 self
->rx_buff
.state
= OUTSIDE_FRAME
;
231 self
->tx_buff
.data
= self
->tx_buff
.head
;
232 self
->rx_buff
.data
= self
->rx_buff
.head
;
235 /* Keep track of module usage */
236 SET_MODULE_OWNER(dev
);
238 /* Override the network functions we need to use */
239 dev
->hard_start_xmit
= w83977af_hard_xmit
;
240 dev
->open
= w83977af_net_open
;
241 dev
->stop
= w83977af_net_close
;
242 dev
->do_ioctl
= w83977af_net_ioctl
;
243 dev
->get_stats
= w83977af_net_get_stats
;
245 err
= register_netdev(dev
);
247 IRDA_ERROR("%s(), register_netdevice() failed!\n", __FUNCTION__
);
250 IRDA_MESSAGE("IrDA: Registered device %s\n", dev
->name
);
252 /* Need to store self somewhere */
257 dma_free_coherent(NULL
, self
->tx_buff
.truesize
,
258 self
->tx_buff
.head
, self
->tx_buff_dma
);
260 dma_free_coherent(NULL
, self
->rx_buff
.truesize
,
261 self
->rx_buff
.head
, self
->rx_buff_dma
);
265 release_region(iobase
, CHIP_IO_EXTENT
);
270 * Function w83977af_close (self)
272 * Close driver instance
275 static int w83977af_close(struct w83977af_ir
*self
)
279 IRDA_DEBUG(0, "%s()\n", __FUNCTION__
);
281 iobase
= self
->io
.fir_base
;
283 #ifdef CONFIG_USE_W977_PNP
284 /* enter PnP configuration mode */
285 w977_efm_enter(efio
);
287 w977_select_device(W977_DEVICE_IR
, efio
);
289 /* Deactivate device */
290 w977_write_reg(0x30, 0x00, efio
);
293 #endif /* CONFIG_USE_W977_PNP */
295 /* Remove netdevice */
296 unregister_netdev(self
->netdev
);
298 /* Release the PORT that this driver is using */
299 IRDA_DEBUG(0 , "%s(), Releasing Region %03x\n",
300 __FUNCTION__
, self
->io
.fir_base
);
301 release_region(self
->io
.fir_base
, self
->io
.fir_ext
);
303 if (self
->tx_buff
.head
)
304 dma_free_coherent(NULL
, self
->tx_buff
.truesize
,
305 self
->tx_buff
.head
, self
->tx_buff_dma
);
307 if (self
->rx_buff
.head
)
308 dma_free_coherent(NULL
, self
->rx_buff
.truesize
,
309 self
->rx_buff
.head
, self
->rx_buff_dma
);
311 free_netdev(self
->netdev
);
316 int w83977af_probe( int iobase
, int irq
, int dma
)
321 for (i
=0; i
< 2; i
++) {
322 IRDA_DEBUG( 0, "%s()\n", __FUNCTION__
);
323 #ifdef CONFIG_USE_W977_PNP
324 /* Enter PnP configuration mode */
325 w977_efm_enter(efbase
[i
]);
327 w977_select_device(W977_DEVICE_IR
, efbase
[i
]);
329 /* Configure PnP port, IRQ, and DMA channel */
330 w977_write_reg(0x60, (iobase
>> 8) & 0xff, efbase
[i
]);
331 w977_write_reg(0x61, (iobase
) & 0xff, efbase
[i
]);
333 w977_write_reg(0x70, irq
, efbase
[i
]);
334 #ifdef CONFIG_ARCH_NETWINDER
335 /* Netwinder uses 1 higher than Linux */
336 w977_write_reg(0x74, dma
+1, efbase
[i
]);
338 w977_write_reg(0x74, dma
, efbase
[i
]);
339 #endif /*CONFIG_ARCH_NETWINDER */
340 w977_write_reg(0x75, 0x04, efbase
[i
]); /* Disable Tx DMA */
342 /* Set append hardware CRC, enable IR bank selection */
343 w977_write_reg(0xf0, APEDCRC
|ENBNKSEL
, efbase
[i
]);
345 /* Activate device */
346 w977_write_reg(0x30, 0x01, efbase
[i
]);
348 w977_efm_exit(efbase
[i
]);
349 #endif /* CONFIG_USE_W977_PNP */
350 /* Disable Advanced mode */
351 switch_bank(iobase
, SET2
);
352 outb(iobase
+2, 0x00);
354 /* Turn on UART (global) interrupts */
355 switch_bank(iobase
, SET0
);
356 outb(HCR_EN_IRQ
, iobase
+HCR
);
358 /* Switch to advanced mode */
359 switch_bank(iobase
, SET2
);
360 outb(inb(iobase
+ADCR1
) | ADCR1_ADV_SL
, iobase
+ADCR1
);
362 /* Set default IR-mode */
363 switch_bank(iobase
, SET0
);
364 outb(HCR_SIR
, iobase
+HCR
);
366 /* Read the Advanced IR ID */
367 switch_bank(iobase
, SET3
);
368 version
= inb(iobase
+AUID
);
371 if (0x10 == (version
& 0xf0)) {
374 /* Set FIFO size to 32 */
375 switch_bank(iobase
, SET2
);
376 outb(ADCR2_RXFS32
|ADCR2_TXFS32
, iobase
+ADCR2
);
378 /* Set FIFO threshold to TX17, RX16 */
379 switch_bank(iobase
, SET0
);
380 outb(UFR_RXTL
|UFR_TXTL
|UFR_TXF_RST
|UFR_RXF_RST
|
381 UFR_EN_FIFO
,iobase
+UFR
);
383 /* Receiver frame length */
384 switch_bank(iobase
, SET4
);
385 outb(2048 & 0xff, iobase
+6);
386 outb((2048 >> 8) & 0x1f, iobase
+7);
389 * Init HP HSDL-1100 transceiver.
391 * Set IRX_MSL since we have 2 * receive paths IRRX,
392 * and IRRXH. Clear IRSL0D since we want IRSL0 * to
393 * be a input pin used for IRRXH
395 * IRRX pin 37 connected to receiver
396 * IRTX pin 38 connected to transmitter
397 * FIRRX pin 39 connected to receiver (IRSL0)
398 * CIRRX pin 40 connected to pin 37
400 switch_bank(iobase
, SET7
);
401 outb(0x40, iobase
+7);
403 IRDA_MESSAGE("W83977AF (IR) driver loaded. "
404 "Version: 0x%02x\n", version
);
408 /* Try next extented function register address */
409 IRDA_DEBUG( 0, "%s(), Wrong chip version", __FUNCTION__
);
415 void w83977af_change_speed(struct w83977af_ir
*self
, __u32 speed
)
417 int ir_mode
= HCR_SIR
;
421 iobase
= self
->io
.fir_base
;
423 /* Update accounting for new speed */
424 self
->io
.speed
= speed
;
426 /* Save current bank */
427 set
= inb(iobase
+SSR
);
429 /* Disable interrupts */
430 switch_bank(iobase
, SET0
);
434 switch_bank(iobase
, SET2
);
435 outb(0x00, iobase
+ABHL
);
438 case 9600: outb(0x0c, iobase
+ABLL
); break;
439 case 19200: outb(0x06, iobase
+ABLL
); break;
440 case 38400: outb(0x03, iobase
+ABLL
); break;
441 case 57600: outb(0x02, iobase
+ABLL
); break;
442 case 115200: outb(0x01, iobase
+ABLL
); break;
444 ir_mode
= HCR_MIR_576
;
445 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__
);
448 ir_mode
= HCR_MIR_1152
;
449 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", __FUNCTION__
);
453 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", __FUNCTION__
);
457 IRDA_DEBUG(0, "%s(), unknown baud rate of %d\n", __FUNCTION__
, speed
);
462 switch_bank(iobase
, SET0
);
463 outb(ir_mode
, iobase
+HCR
);
465 /* set FIFO size to 32 */
466 switch_bank(iobase
, SET2
);
467 outb(ADCR2_RXFS32
|ADCR2_TXFS32
, iobase
+ADCR2
);
469 /* set FIFO threshold to TX17, RX16 */
470 switch_bank(iobase
, SET0
);
471 outb(0x00, iobase
+UFR
); /* Reset */
472 outb(UFR_EN_FIFO
, iobase
+UFR
); /* First we must enable FIFO */
473 outb(0xa7, iobase
+UFR
);
475 netif_wake_queue(self
->netdev
);
477 /* Enable some interrupts so we can receive frames */
478 switch_bank(iobase
, SET0
);
479 if (speed
> PIO_MAX_SPEED
) {
480 outb(ICR_EFSFI
, iobase
+ICR
);
481 w83977af_dma_receive(self
);
483 outb(ICR_ERBRI
, iobase
+ICR
);
486 outb(set
, iobase
+SSR
);
490 * Function w83977af_hard_xmit (skb, dev)
492 * Sets up a DMA transfer to send the current frame.
495 int w83977af_hard_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
497 struct w83977af_ir
*self
;
503 self
= (struct w83977af_ir
*) dev
->priv
;
505 iobase
= self
->io
.fir_base
;
507 IRDA_DEBUG(4, "%s(%ld), skb->len=%d\n", __FUNCTION__
, jiffies
,
510 /* Lock transmit buffer */
511 netif_stop_queue(dev
);
513 /* Check if we need to change the speed */
514 speed
= irda_get_next_speed(skb
);
515 if ((speed
!= self
->io
.speed
) && (speed
!= -1)) {
516 /* Check for empty frame */
518 w83977af_change_speed(self
, speed
);
519 dev
->trans_start
= jiffies
;
523 self
->new_speed
= speed
;
526 /* Save current set */
527 set
= inb(iobase
+SSR
);
529 /* Decide if we should use PIO or DMA transfer */
530 if (self
->io
.speed
> PIO_MAX_SPEED
) {
531 self
->tx_buff
.data
= self
->tx_buff
.head
;
532 memcpy(self
->tx_buff
.data
, skb
->data
, skb
->len
);
533 self
->tx_buff
.len
= skb
->len
;
535 mtt
= irda_get_mtt(skb
);
536 #ifdef CONFIG_USE_INTERNAL_TIMER
538 /* Adjust for timer resolution */
542 switch_bank(iobase
, SET4
);
543 outb(mtt
& 0xff, iobase
+TMRL
);
544 outb((mtt
>> 8) & 0x0f, iobase
+TMRH
);
547 outb(IR_MSL_EN_TMR
, iobase
+IR_MSL
);
548 self
->io
.direction
= IO_XMIT
;
550 /* Enable timer interrupt */
551 switch_bank(iobase
, SET0
);
552 outb(ICR_ETMRI
, iobase
+ICR
);
555 IRDA_DEBUG(4, "%s(%ld), mtt=%d\n", __FUNCTION__
, jiffies
, mtt
);
559 /* Enable DMA interrupt */
560 switch_bank(iobase
, SET0
);
561 outb(ICR_EDMAI
, iobase
+ICR
);
562 w83977af_dma_write(self
, iobase
);
563 #ifdef CONFIG_USE_INTERNAL_TIMER
567 self
->tx_buff
.data
= self
->tx_buff
.head
;
568 self
->tx_buff
.len
= async_wrap_skb(skb
, self
->tx_buff
.data
,
569 self
->tx_buff
.truesize
);
571 /* Add interrupt on tx low level (will fire immediately) */
572 switch_bank(iobase
, SET0
);
573 outb(ICR_ETXTHI
, iobase
+ICR
);
575 dev
->trans_start
= jiffies
;
578 /* Restore set register */
579 outb(set
, iobase
+SSR
);
585 * Function w83977af_dma_write (self, iobase)
587 * Send frame using DMA
590 static void w83977af_dma_write(struct w83977af_ir
*self
, int iobase
)
593 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
597 IRDA_DEBUG(4, "%s(), len=%d\n", __FUNCTION__
, self
->tx_buff
.len
);
599 /* Save current set */
600 set
= inb(iobase
+SSR
);
603 switch_bank(iobase
, SET0
);
604 outb(inb(iobase
+HCR
) & ~HCR_EN_DMA
, iobase
+HCR
);
606 /* Choose transmit DMA channel */
607 switch_bank(iobase
, SET2
);
608 outb(ADCR1_D_CHSW
|/*ADCR1_DMA_F|*/ADCR1_ADV_SL
, iobase
+ADCR1
);
609 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
610 spin_lock_irqsave(&self
->lock
, flags
);
612 disable_dma(self
->io
.dma
);
613 clear_dma_ff(self
->io
.dma
);
614 set_dma_mode(self
->io
.dma
, DMA_MODE_READ
);
615 set_dma_addr(self
->io
.dma
, self
->tx_buff_dma
);
616 set_dma_count(self
->io
.dma
, self
->tx_buff
.len
);
618 irda_setup_dma(self
->io
.dma
, self
->tx_buff_dma
, self
->tx_buff
.len
,
621 self
->io
.direction
= IO_XMIT
;
624 switch_bank(iobase
, SET0
);
625 #ifdef CONFIG_NETWINDER_TX_DMA_PROBLEMS
626 hcr
= inb(iobase
+HCR
);
627 outb(hcr
| HCR_EN_DMA
, iobase
+HCR
);
628 enable_dma(self
->io
.dma
);
629 spin_unlock_irqrestore(&self
->lock
, flags
);
631 outb(inb(iobase
+HCR
) | HCR_EN_DMA
| HCR_TX_WT
, iobase
+HCR
);
634 /* Restore set register */
635 outb(set
, iobase
+SSR
);
639 * Function w83977af_pio_write (iobase, buf, len, fifo_size)
644 static int w83977af_pio_write(int iobase
, __u8
*buf
, int len
, int fifo_size
)
649 IRDA_DEBUG(4, "%s()\n", __FUNCTION__
);
651 /* Save current bank */
652 set
= inb(iobase
+SSR
);
654 switch_bank(iobase
, SET0
);
655 if (!(inb_p(iobase
+USR
) & USR_TSRE
)) {
657 "%s(), warning, FIFO not empty yet!\n", __FUNCTION__
);
660 IRDA_DEBUG(4, "%s(), %d bytes left in tx fifo\n",
661 __FUNCTION__
, fifo_size
);
664 /* Fill FIFO with current frame */
665 while ((fifo_size
-- > 0) && (actual
< len
)) {
666 /* Transmit next byte */
667 outb(buf
[actual
++], iobase
+TBR
);
670 IRDA_DEBUG(4, "%s(), fifo_size %d ; %d sent of %d\n",
671 __FUNCTION__
, fifo_size
, actual
, len
);
674 outb(set
, iobase
+SSR
);
680 * Function w83977af_dma_xmit_complete (self)
682 * The transfer of a frame in finished. So do the necessary things
686 static void w83977af_dma_xmit_complete(struct w83977af_ir
*self
)
691 IRDA_DEBUG(4, "%s(%ld)\n", __FUNCTION__
, jiffies
);
693 IRDA_ASSERT(self
!= NULL
, return;);
695 iobase
= self
->io
.fir_base
;
697 /* Save current set */
698 set
= inb(iobase
+SSR
);
701 switch_bank(iobase
, SET0
);
702 outb(inb(iobase
+HCR
) & ~HCR_EN_DMA
, iobase
+HCR
);
704 /* Check for underrrun! */
705 if (inb(iobase
+AUDR
) & AUDR_UNDR
) {
706 IRDA_DEBUG(0, "%s(), Transmit underrun!\n", __FUNCTION__
);
708 self
->stats
.tx_errors
++;
709 self
->stats
.tx_fifo_errors
++;
711 /* Clear bit, by writing 1 to it */
712 outb(AUDR_UNDR
, iobase
+AUDR
);
714 self
->stats
.tx_packets
++;
717 if (self
->new_speed
) {
718 w83977af_change_speed(self
, self
->new_speed
);
722 /* Unlock tx_buff and request another frame */
723 /* Tell the network layer, that we want more frames */
724 netif_wake_queue(self
->netdev
);
727 outb(set
, iobase
+SSR
);
731 * Function w83977af_dma_receive (self)
733 * Get ready for receiving a frame. The device will initiate a DMA
734 * if it starts to receive a frame.
737 int w83977af_dma_receive(struct w83977af_ir
*self
)
741 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
745 IRDA_ASSERT(self
!= NULL
, return -1;);
747 IRDA_DEBUG(4, "%s\n", __FUNCTION__
);
749 iobase
= self
->io
.fir_base
;
751 /* Save current set */
752 set
= inb(iobase
+SSR
);
755 switch_bank(iobase
, SET0
);
756 outb(inb(iobase
+HCR
) & ~HCR_EN_DMA
, iobase
+HCR
);
758 /* Choose DMA Rx, DMA Fairness, and Advanced mode */
759 switch_bank(iobase
, SET2
);
760 outb((inb(iobase
+ADCR1
) & ~ADCR1_D_CHSW
)/*|ADCR1_DMA_F*/|ADCR1_ADV_SL
,
763 self
->io
.direction
= IO_RECV
;
764 self
->rx_buff
.data
= self
->rx_buff
.head
;
766 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
767 spin_lock_irqsave(&self
->lock
, flags
);
769 disable_dma(self
->io
.dma
);
770 clear_dma_ff(self
->io
.dma
);
771 set_dma_mode(self
->io
.dma
, DMA_MODE_READ
);
772 set_dma_addr(self
->io
.dma
, self
->rx_buff_dma
);
773 set_dma_count(self
->io
.dma
, self
->rx_buff
.truesize
);
775 irda_setup_dma(self
->io
.dma
, self
->rx_buff_dma
, self
->rx_buff
.truesize
,
779 * Reset Rx FIFO. This will also flush the ST_FIFO, it's very
780 * important that we don't reset the Tx FIFO since it might not
781 * be finished transmitting yet
783 switch_bank(iobase
, SET0
);
784 outb(UFR_RXTL
|UFR_TXTL
|UFR_RXF_RST
|UFR_EN_FIFO
, iobase
+UFR
);
785 self
->st_fifo
.len
= self
->st_fifo
.tail
= self
->st_fifo
.head
= 0;
788 switch_bank(iobase
, SET0
);
789 #ifdef CONFIG_NETWINDER_RX_DMA_PROBLEMS
790 hcr
= inb(iobase
+HCR
);
791 outb(hcr
| HCR_EN_DMA
, iobase
+HCR
);
792 enable_dma(self
->io
.dma
);
793 spin_unlock_irqrestore(&self
->lock
, flags
);
795 outb(inb(iobase
+HCR
) | HCR_EN_DMA
, iobase
+HCR
);
798 outb(set
, iobase
+SSR
);
804 * Function w83977af_receive_complete (self)
806 * Finished with receiving a frame
809 int w83977af_dma_receive_complete(struct w83977af_ir
*self
)
812 struct st_fifo
*st_fifo
;
818 IRDA_DEBUG(4, "%s\n", __FUNCTION__
);
820 st_fifo
= &self
->st_fifo
;
822 iobase
= self
->io
.fir_base
;
824 /* Save current set */
825 set
= inb(iobase
+SSR
);
827 iobase
= self
->io
.fir_base
;
829 /* Read status FIFO */
830 switch_bank(iobase
, SET5
);
831 while ((status
= inb(iobase
+FS_FO
)) & FS_FO_FSFDR
) {
832 st_fifo
->entries
[st_fifo
->tail
].status
= status
;
834 st_fifo
->entries
[st_fifo
->tail
].len
= inb(iobase
+RFLFL
);
835 st_fifo
->entries
[st_fifo
->tail
].len
|= inb(iobase
+RFLFH
) << 8;
841 while (st_fifo
->len
) {
842 /* Get first entry */
843 status
= st_fifo
->entries
[st_fifo
->head
].status
;
844 len
= st_fifo
->entries
[st_fifo
->head
].len
;
848 /* Check for errors */
849 if (status
& FS_FO_ERR_MSK
) {
850 if (status
& FS_FO_LST_FR
) {
851 /* Add number of lost frames to stats */
852 self
->stats
.rx_errors
+= len
;
855 self
->stats
.rx_errors
++;
857 self
->rx_buff
.data
+= len
;
859 if (status
& FS_FO_MX_LEX
)
860 self
->stats
.rx_length_errors
++;
862 if (status
& FS_FO_PHY_ERR
)
863 self
->stats
.rx_frame_errors
++;
865 if (status
& FS_FO_CRC_ERR
)
866 self
->stats
.rx_crc_errors
++;
868 /* The errors below can be reported in both cases */
869 if (status
& FS_FO_RX_OV
)
870 self
->stats
.rx_fifo_errors
++;
872 if (status
& FS_FO_FSF_OV
)
873 self
->stats
.rx_fifo_errors
++;
876 /* Check if we have transferred all data to memory */
877 switch_bank(iobase
, SET0
);
878 if (inb(iobase
+USR
) & USR_RDR
) {
879 #ifdef CONFIG_USE_INTERNAL_TIMER
880 /* Put this entry back in fifo */
883 st_fifo
->entries
[st_fifo
->head
].status
= status
;
884 st_fifo
->entries
[st_fifo
->head
].len
= len
;
886 /* Restore set register */
887 outb(set
, iobase
+SSR
);
889 return FALSE
; /* I'll be back! */
891 udelay(80); /* Should be enough!? */
895 skb
= dev_alloc_skb(len
+1);
898 "%s(), memory squeeze, dropping frame.\n", __FUNCTION__
);
899 /* Restore set register */
900 outb(set
, iobase
+SSR
);
905 /* Align to 20 bytes */
908 /* Copy frame without CRC */
909 if (self
->io
.speed
< 4000000) {
911 memcpy(skb
->data
, self
->rx_buff
.data
, len
-2);
914 memcpy(skb
->data
, self
->rx_buff
.data
, len
-4);
917 /* Move to next frame */
918 self
->rx_buff
.data
+= len
;
919 self
->stats
.rx_packets
++;
921 skb
->dev
= self
->netdev
;
922 skb
->mac
.raw
= skb
->data
;
923 skb
->protocol
= htons(ETH_P_IRDA
);
925 self
->netdev
->last_rx
= jiffies
;
928 /* Restore set register */
929 outb(set
, iobase
+SSR
);
935 * Function pc87108_pio_receive (self)
937 * Receive all data in receiver FIFO
940 static void w83977af_pio_receive(struct w83977af_ir
*self
)
945 IRDA_DEBUG(4, "%s()\n", __FUNCTION__
);
947 IRDA_ASSERT(self
!= NULL
, return;);
949 iobase
= self
->io
.fir_base
;
951 /* Receive all characters in Rx FIFO */
953 byte
= inb(iobase
+RBR
);
954 async_unwrap_char(self
->netdev
, &self
->stats
, &self
->rx_buff
,
956 } while (inb(iobase
+USR
) & USR_RDR
); /* Data available */
960 * Function w83977af_sir_interrupt (self, eir)
962 * Handle SIR interrupt
965 static __u8
w83977af_sir_interrupt(struct w83977af_ir
*self
, int isr
)
972 IRDA_DEBUG(4, "%s(), isr=%#x\n", __FUNCTION__
, isr
);
974 iobase
= self
->io
.fir_base
;
975 /* Transmit FIFO low on data */
976 if (isr
& ISR_TXTH_I
) {
977 /* Write data left in transmit buffer */
978 actual
= w83977af_pio_write(self
->io
.fir_base
,
983 self
->tx_buff
.data
+= actual
;
984 self
->tx_buff
.len
-= actual
;
986 self
->io
.direction
= IO_XMIT
;
988 /* Check if finished */
989 if (self
->tx_buff
.len
> 0) {
990 new_icr
|= ICR_ETXTHI
;
992 set
= inb(iobase
+SSR
);
993 switch_bank(iobase
, SET0
);
994 outb(AUDR_SFEND
, iobase
+AUDR
);
995 outb(set
, iobase
+SSR
);
997 self
->stats
.tx_packets
++;
999 /* Feed me more packets */
1000 netif_wake_queue(self
->netdev
);
1001 new_icr
|= ICR_ETBREI
;
1004 /* Check if transmission has completed */
1005 if (isr
& ISR_TXEMP_I
) {
1006 /* Check if we need to change the speed? */
1007 if (self
->new_speed
) {
1009 "%s(), Changing speed!\n", __FUNCTION__
);
1010 w83977af_change_speed(self
, self
->new_speed
);
1011 self
->new_speed
= 0;
1014 /* Turn around and get ready to receive some data */
1015 self
->io
.direction
= IO_RECV
;
1016 new_icr
|= ICR_ERBRI
;
1019 /* Rx FIFO threshold or timeout */
1020 if (isr
& ISR_RXTH_I
) {
1021 w83977af_pio_receive(self
);
1023 /* Keep receiving */
1024 new_icr
|= ICR_ERBRI
;
1030 * Function pc87108_fir_interrupt (self, eir)
1032 * Handle MIR/FIR interrupt
1035 static __u8
w83977af_fir_interrupt(struct w83977af_ir
*self
, int isr
)
1041 iobase
= self
->io
.fir_base
;
1042 set
= inb(iobase
+SSR
);
1044 /* End of frame detected in FIFO */
1045 if (isr
& (ISR_FEND_I
|ISR_FSF_I
)) {
1046 if (w83977af_dma_receive_complete(self
)) {
1048 /* Wait for next status FIFO interrupt */
1049 new_icr
|= ICR_EFSFI
;
1051 /* DMA not finished yet */
1053 /* Set timer value, resolution 1 ms */
1054 switch_bank(iobase
, SET4
);
1055 outb(0x01, iobase
+TMRL
); /* 1 ms */
1056 outb(0x00, iobase
+TMRH
);
1059 outb(IR_MSL_EN_TMR
, iobase
+IR_MSL
);
1061 new_icr
|= ICR_ETMRI
;
1064 /* Timer finished */
1065 if (isr
& ISR_TMR_I
) {
1067 switch_bank(iobase
, SET4
);
1068 outb(0, iobase
+IR_MSL
);
1070 /* Clear timer event */
1071 /* switch_bank(iobase, SET0); */
1072 /* outb(ASCR_CTE, iobase+ASCR); */
1074 /* Check if this is a TX timer interrupt */
1075 if (self
->io
.direction
== IO_XMIT
) {
1076 w83977af_dma_write(self
, iobase
);
1078 new_icr
|= ICR_EDMAI
;
1080 /* Check if DMA has now finished */
1081 w83977af_dma_receive_complete(self
);
1083 new_icr
|= ICR_EFSFI
;
1086 /* Finished with DMA */
1087 if (isr
& ISR_DMA_I
) {
1088 w83977af_dma_xmit_complete(self
);
1090 /* Check if there are more frames to be transmitted */
1091 /* if (irda_device_txqueue_empty(self)) { */
1093 /* Prepare for receive
1095 * ** Netwinder Tx DMA likes that we do this anyway **
1097 w83977af_dma_receive(self
);
1098 new_icr
= ICR_EFSFI
;
1103 outb(set
, iobase
+SSR
);
1109 * Function w83977af_interrupt (irq, dev_id, regs)
1111 * An interrupt from the chip has arrived. Time to do some work
1114 static irqreturn_t
w83977af_interrupt(int irq
, void *dev_id
)
1116 struct net_device
*dev
= dev_id
;
1117 struct w83977af_ir
*self
;
1123 iobase
= self
->io
.fir_base
;
1125 /* Save current bank */
1126 set
= inb(iobase
+SSR
);
1127 switch_bank(iobase
, SET0
);
1129 icr
= inb(iobase
+ICR
);
1130 isr
= inb(iobase
+ISR
) & icr
; /* Mask out the interesting ones */
1132 outb(0, iobase
+ICR
); /* Disable interrupts */
1135 /* Dispatch interrupt handler for the current speed */
1136 if (self
->io
.speed
> PIO_MAX_SPEED
)
1137 icr
= w83977af_fir_interrupt(self
, isr
);
1139 icr
= w83977af_sir_interrupt(self
, isr
);
1142 outb(icr
, iobase
+ICR
); /* Restore (new) interrupts */
1143 outb(set
, iobase
+SSR
); /* Restore bank register */
1144 return IRQ_RETVAL(isr
);
1148 * Function w83977af_is_receiving (self)
1150 * Return TRUE is we are currently receiving a frame
1153 static int w83977af_is_receiving(struct w83977af_ir
*self
)
1159 IRDA_ASSERT(self
!= NULL
, return FALSE
;);
1161 if (self
->io
.speed
> 115200) {
1162 iobase
= self
->io
.fir_base
;
1164 /* Check if rx FIFO is not empty */
1165 set
= inb(iobase
+SSR
);
1166 switch_bank(iobase
, SET2
);
1167 if ((inb(iobase
+RXFDTH
) & 0x3f) != 0) {
1168 /* We are receiving something */
1171 outb(set
, iobase
+SSR
);
1173 status
= (self
->rx_buff
.state
!= OUTSIDE_FRAME
);
1179 * Function w83977af_net_open (dev)
1184 static int w83977af_net_open(struct net_device
*dev
)
1186 struct w83977af_ir
*self
;
1191 IRDA_DEBUG(0, "%s()\n", __FUNCTION__
);
1193 IRDA_ASSERT(dev
!= NULL
, return -1;);
1194 self
= (struct w83977af_ir
*) dev
->priv
;
1196 IRDA_ASSERT(self
!= NULL
, return 0;);
1198 iobase
= self
->io
.fir_base
;
1200 if (request_irq(self
->io
.irq
, w83977af_interrupt
, 0, dev
->name
,
1205 * Always allocate the DMA channel after the IRQ,
1206 * and clean up on failure.
1208 if (request_dma(self
->io
.dma
, dev
->name
)) {
1209 free_irq(self
->io
.irq
, self
);
1213 /* Save current set */
1214 set
= inb(iobase
+SSR
);
1216 /* Enable some interrupts so we can receive frames again */
1217 switch_bank(iobase
, SET0
);
1218 if (self
->io
.speed
> 115200) {
1219 outb(ICR_EFSFI
, iobase
+ICR
);
1220 w83977af_dma_receive(self
);
1222 outb(ICR_ERBRI
, iobase
+ICR
);
1224 /* Restore bank register */
1225 outb(set
, iobase
+SSR
);
1227 /* Ready to play! */
1228 netif_start_queue(dev
);
1230 /* Give self a hardware name */
1231 sprintf(hwname
, "w83977af @ 0x%03x", self
->io
.fir_base
);
1234 * Open new IrLAP layer instance, now that everything should be
1235 * initialized properly
1237 self
->irlap
= irlap_open(dev
, &self
->qos
, hwname
);
1243 * Function w83977af_net_close (dev)
1248 static int w83977af_net_close(struct net_device
*dev
)
1250 struct w83977af_ir
*self
;
1254 IRDA_DEBUG(0, "%s()\n", __FUNCTION__
);
1256 IRDA_ASSERT(dev
!= NULL
, return -1;);
1258 self
= (struct w83977af_ir
*) dev
->priv
;
1260 IRDA_ASSERT(self
!= NULL
, return 0;);
1262 iobase
= self
->io
.fir_base
;
1265 netif_stop_queue(dev
);
1267 /* Stop and remove instance of IrLAP */
1269 irlap_close(self
->irlap
);
1272 disable_dma(self
->io
.dma
);
1274 /* Save current set */
1275 set
= inb(iobase
+SSR
);
1277 /* Disable interrupts */
1278 switch_bank(iobase
, SET0
);
1279 outb(0, iobase
+ICR
);
1281 free_irq(self
->io
.irq
, dev
);
1282 free_dma(self
->io
.dma
);
1284 /* Restore bank register */
1285 outb(set
, iobase
+SSR
);
1291 * Function w83977af_net_ioctl (dev, rq, cmd)
1293 * Process IOCTL commands for this device
1296 static int w83977af_net_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
1298 struct if_irda_req
*irq
= (struct if_irda_req
*) rq
;
1299 struct w83977af_ir
*self
;
1300 unsigned long flags
;
1303 IRDA_ASSERT(dev
!= NULL
, return -1;);
1307 IRDA_ASSERT(self
!= NULL
, return -1;);
1309 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__
, dev
->name
, cmd
);
1311 spin_lock_irqsave(&self
->lock
, flags
);
1314 case SIOCSBANDWIDTH
: /* Set bandwidth */
1315 if (!capable(CAP_NET_ADMIN
)) {
1319 w83977af_change_speed(self
, irq
->ifr_baudrate
);
1321 case SIOCSMEDIABUSY
: /* Set media busy */
1322 if (!capable(CAP_NET_ADMIN
)) {
1326 irda_device_set_media_busy(self
->netdev
, TRUE
);
1328 case SIOCGRECEIVING
: /* Check if we are receiving right now */
1329 irq
->ifr_receiving
= w83977af_is_receiving(self
);
1335 spin_unlock_irqrestore(&self
->lock
, flags
);
1339 static struct net_device_stats
*w83977af_net_get_stats(struct net_device
*dev
)
1341 struct w83977af_ir
*self
= (struct w83977af_ir
*) dev
->priv
;
1343 return &self
->stats
;
1346 MODULE_AUTHOR("Dag Brattli <dagb@cs.uit.no>");
1347 MODULE_DESCRIPTION("Winbond W83977AF IrDA Device Driver");
1348 MODULE_LICENSE("GPL");
1351 module_param(qos_mtt_bits
, int, 0);
1352 MODULE_PARM_DESC(qos_mtt_bits
, "Mimimum Turn Time");
1353 module_param_array(io
, int, NULL
, 0);
1354 MODULE_PARM_DESC(io
, "Base I/O addresses");
1355 module_param_array(irq
, int, NULL
, 0);
1356 MODULE_PARM_DESC(irq
, "IRQ lines");
1359 * Function init_module (void)
1364 module_init(w83977af_init
);
1367 * Function cleanup_module (void)
1372 module_exit(w83977af_cleanup
);