Linux 2.6.20.7
[linux/fpc-iii.git] / drivers / net / netxen / netxen_nic_hw.c
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1 /*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
30 * Source file for NIC routines to access the Phantom hardware
34 #include "netxen_nic.h"
35 #include "netxen_nic_hw.h"
36 #include "netxen_nic_phan_reg.h"
38 /* PCI Windowing for DDR regions. */
40 #define ADDR_IN_RANGE(addr, low, high) \
41 (((addr) <= (high)) && ((addr) >= (low)))
43 #define NETXEN_FLASH_BASE (BOOTLD_START)
44 #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
45 #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
46 #define NETXEN_MIN_MTU 64
47 #define NETXEN_ETH_FCS_SIZE 4
48 #define NETXEN_ENET_HEADER_SIZE 14
49 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
50 #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
51 #define NETXEN_NIU_HDRSIZE (0x1 << 6)
52 #define NETXEN_NIU_TLRSIZE (0x1 << 5)
54 #define lower32(x) ((u32)((x) & 0xffffffff))
55 #define upper32(x) \
56 ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
58 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
59 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
60 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
61 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
63 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
65 unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
66 unsigned long long addr);
67 void netxen_free_hw_resources(struct netxen_adapter *adapter);
69 int netxen_nic_set_mac(struct net_device *netdev, void *p)
71 struct netxen_port *port = netdev_priv(netdev);
72 struct netxen_adapter *adapter = port->adapter;
73 struct sockaddr *addr = p;
75 if (netif_running(netdev))
76 return -EBUSY;
78 if (!is_valid_ether_addr(addr->sa_data))
79 return -EADDRNOTAVAIL;
81 DPRINTK(INFO, "valid ether addr\n");
82 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
84 if (adapter->macaddr_set)
85 adapter->macaddr_set(port, addr->sa_data);
87 return 0;
91 * netxen_nic_set_multi - Multicast
93 void netxen_nic_set_multi(struct net_device *netdev)
95 struct netxen_port *port = netdev_priv(netdev);
96 struct netxen_adapter *adapter = port->adapter;
97 struct dev_mc_list *mc_ptr;
98 __u32 netxen_mac_addr_cntl_data = 0;
100 mc_ptr = netdev->mc_list;
101 if (netdev->flags & IFF_PROMISC) {
102 if (adapter->set_promisc)
103 adapter->set_promisc(adapter,
104 port->portnum,
105 NETXEN_NIU_PROMISC_MODE);
106 } else {
107 if (adapter->unset_promisc &&
108 adapter->ahw.boardcfg.board_type
109 != NETXEN_BRDTYPE_P2_SB31_10G_IMEZ)
110 adapter->unset_promisc(adapter,
111 port->portnum,
112 NETXEN_NIU_NON_PROMISC_MODE);
114 if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
115 netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x03);
116 netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
117 netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x00);
118 netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x00);
119 netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x00);
120 netxen_nic_mcr_set_enable_xtnd0(netxen_mac_addr_cntl_data);
121 netxen_nic_mcr_set_enable_xtnd1(netxen_mac_addr_cntl_data);
122 netxen_nic_mcr_set_enable_xtnd2(netxen_mac_addr_cntl_data);
123 netxen_nic_mcr_set_enable_xtnd3(netxen_mac_addr_cntl_data);
124 } else {
125 netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x00);
126 netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
127 netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x01);
128 netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x02);
129 netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x03);
131 writel(netxen_mac_addr_cntl_data,
132 NETXEN_CRB_NORMALIZE(adapter, NETXEN_MAC_ADDR_CNTL_REG));
133 if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
134 writel(netxen_mac_addr_cntl_data,
135 NETXEN_CRB_NORMALIZE(adapter,
136 NETXEN_MULTICAST_ADDR_HI_0));
137 } else {
138 writel(netxen_mac_addr_cntl_data,
139 NETXEN_CRB_NORMALIZE(adapter,
140 NETXEN_MULTICAST_ADDR_HI_1));
142 netxen_mac_addr_cntl_data = 0;
143 writel(netxen_mac_addr_cntl_data,
144 NETXEN_CRB_NORMALIZE(adapter, NETXEN_NIU_GB_DROP_WRONGADDR));
148 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
149 * @returns 0 on success, negative on failure
151 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
153 struct netxen_port *port = netdev_priv(netdev);
154 struct netxen_adapter *adapter = port->adapter;
155 int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
157 if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
158 printk(KERN_ERR "%s: %s %d is not supported.\n",
159 netxen_nic_driver_name, netdev->name, mtu);
160 return -EINVAL;
163 if (adapter->set_mtu)
164 adapter->set_mtu(port, mtu);
165 netdev->mtu = mtu;
167 return 0;
171 * check if the firmware has been downloaded and ready to run and
172 * setup the address for the descriptors in the adapter
174 int netxen_nic_hw_resources(struct netxen_adapter *adapter)
176 struct netxen_hardware_context *hw = &adapter->ahw;
177 u32 state = 0;
178 void *addr;
179 int loops = 0, err = 0;
180 int ctx, ring;
181 u32 card_cmdring = 0;
182 struct netxen_recv_context *recv_ctx;
183 struct netxen_rcv_desc_ctx *rcv_desc;
185 DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
186 PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
187 DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM,
188 pci_base_offset(adapter, NETXEN_CRB_CAM));
189 DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE,
190 pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
192 /* Window 1 call */
193 card_cmdring = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_CMDRING));
195 DPRINTK(INFO, "Command Peg sends 0x%x for cmdring base\n",
196 card_cmdring);
198 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
199 DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
200 loops = 0;
201 state = 0;
202 /* Window 1 call */
203 state = readl(NETXEN_CRB_NORMALIZE(adapter,
204 recv_crb_registers[ctx].
205 crb_rcvpeg_state));
206 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
207 udelay(100);
208 /* Window 1 call */
209 state = readl(NETXEN_CRB_NORMALIZE(adapter,
210 recv_crb_registers
211 [ctx].
212 crb_rcvpeg_state));
213 loops++;
215 if (loops >= 20) {
216 printk(KERN_ERR "Rcv Peg initialization not complete:"
217 "%x.\n", state);
218 err = -EIO;
219 return err;
222 DPRINTK(INFO, "Recieve Peg ready too. starting stuff\n");
224 addr = netxen_alloc(adapter->ahw.pdev,
225 sizeof(struct netxen_ring_ctx) +
226 sizeof(uint32_t),
227 (dma_addr_t *) & adapter->ctx_desc_phys_addr,
228 &adapter->ctx_desc_pdev);
230 printk("ctx_desc_phys_addr: 0x%llx\n",
231 (u64) adapter->ctx_desc_phys_addr);
232 if (addr == NULL) {
233 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
234 err = -ENOMEM;
235 return err;
237 memset(addr, 0, sizeof(struct netxen_ring_ctx));
238 adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
239 adapter->ctx_desc->cmd_consumer_offset =
240 cpu_to_le64(adapter->ctx_desc_phys_addr +
241 sizeof(struct netxen_ring_ctx));
242 adapter->cmd_consumer = (uint32_t *) (((char *)addr) +
243 sizeof(struct netxen_ring_ctx));
245 addr = pci_alloc_consistent(adapter->ahw.pdev,
246 sizeof(struct cmd_desc_type0) *
247 adapter->max_tx_desc_count,
248 (dma_addr_t *) & hw->cmd_desc_phys_addr);
249 printk("cmd_desc_phys_addr: 0x%llx\n", (u64) hw->cmd_desc_phys_addr);
251 if (addr == NULL) {
252 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
253 netxen_free_hw_resources(adapter);
254 return -ENOMEM;
257 adapter->ctx_desc->cmd_ring_addr =
258 cpu_to_le64(hw->cmd_desc_phys_addr);
259 adapter->ctx_desc->cmd_ring_size =
260 cpu_to_le32(adapter->max_tx_desc_count);
262 hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
264 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
265 recv_ctx = &adapter->recv_ctx[ctx];
267 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
268 rcv_desc = &recv_ctx->rcv_desc[ring];
269 addr = netxen_alloc(adapter->ahw.pdev,
270 RCV_DESC_RINGSIZE,
271 &rcv_desc->phys_addr,
272 &rcv_desc->phys_pdev);
273 if (addr == NULL) {
274 DPRINTK(ERR, "bad return from "
275 "pci_alloc_consistent\n");
276 netxen_free_hw_resources(adapter);
277 err = -ENOMEM;
278 return err;
280 rcv_desc->desc_head = (struct rcv_desc *)addr;
281 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
282 cpu_to_le64(rcv_desc->phys_addr);
283 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
284 cpu_to_le32(rcv_desc->max_rx_desc_count);
287 addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE,
288 &recv_ctx->rcv_status_desc_phys_addr,
289 &recv_ctx->rcv_status_desc_pdev);
290 if (addr == NULL) {
291 DPRINTK(ERR, "bad return from"
292 " pci_alloc_consistent\n");
293 netxen_free_hw_resources(adapter);
294 err = -ENOMEM;
295 return err;
297 recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
298 adapter->ctx_desc->sts_ring_addr =
299 cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
300 adapter->ctx_desc->sts_ring_size =
301 cpu_to_le32(adapter->max_rx_desc_count);
304 /* Window = 1 */
306 writel(lower32(adapter->ctx_desc_phys_addr),
307 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO));
308 writel(upper32(adapter->ctx_desc_phys_addr),
309 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI));
310 writel(NETXEN_CTX_SIGNATURE,
311 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG));
312 return err;
315 void netxen_free_hw_resources(struct netxen_adapter *adapter)
317 struct netxen_recv_context *recv_ctx;
318 struct netxen_rcv_desc_ctx *rcv_desc;
319 int ctx, ring;
321 if (adapter->ctx_desc != NULL) {
322 pci_free_consistent(adapter->ctx_desc_pdev,
323 sizeof(struct netxen_ring_ctx) +
324 sizeof(uint32_t),
325 adapter->ctx_desc,
326 adapter->ctx_desc_phys_addr);
327 adapter->ctx_desc = NULL;
330 if (adapter->ahw.cmd_desc_head != NULL) {
331 pci_free_consistent(adapter->ahw.cmd_desc_pdev,
332 sizeof(struct cmd_desc_type0) *
333 adapter->max_tx_desc_count,
334 adapter->ahw.cmd_desc_head,
335 adapter->ahw.cmd_desc_phys_addr);
336 adapter->ahw.cmd_desc_head = NULL;
338 /* Special handling: there are 2 ports on this board */
339 if (adapter->ahw.boardcfg.board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) {
340 adapter->ahw.max_ports = 2;
343 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
344 recv_ctx = &adapter->recv_ctx[ctx];
345 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
346 rcv_desc = &recv_ctx->rcv_desc[ring];
348 if (rcv_desc->desc_head != NULL) {
349 pci_free_consistent(rcv_desc->phys_pdev,
350 RCV_DESC_RINGSIZE,
351 rcv_desc->desc_head,
352 rcv_desc->phys_addr);
353 rcv_desc->desc_head = NULL;
357 if (recv_ctx->rcv_status_desc_head != NULL) {
358 pci_free_consistent(recv_ctx->rcv_status_desc_pdev,
359 STATUS_DESC_RINGSIZE,
360 recv_ctx->rcv_status_desc_head,
361 recv_ctx->
362 rcv_status_desc_phys_addr);
363 recv_ctx->rcv_status_desc_head = NULL;
368 void netxen_tso_check(struct netxen_adapter *adapter,
369 struct cmd_desc_type0 *desc, struct sk_buff *skb)
371 if (desc->mss) {
372 desc->total_hdr_length = sizeof(struct ethhdr) +
373 ((skb->nh.iph)->ihl * sizeof(u32)) +
374 ((skb->h.th)->doff * sizeof(u32));
375 netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
376 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
377 if (skb->nh.iph->protocol == IPPROTO_TCP) {
378 netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
379 } else if (skb->nh.iph->protocol == IPPROTO_UDP) {
380 netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
381 } else {
382 return;
385 adapter->stats.xmitcsummed++;
386 desc->tcp_hdr_offset = skb->h.raw - skb->data;
387 desc->ip_hdr_offset = skb->nh.raw - skb->data;
390 int netxen_is_flash_supported(struct netxen_adapter *adapter)
392 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
393 int addr, val01, val02, i, j;
395 /* if the flash size less than 4Mb, make huge war cry and die */
396 for (j = 1; j < 4; j++) {
397 addr = j * NETXEN_NIC_WINDOW_MARGIN;
398 for (i = 0; i < (sizeof(locs) / sizeof(locs[0])); i++) {
399 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
400 && netxen_rom_fast_read(adapter, (addr + locs[i]),
401 &val02) == 0) {
402 if (val01 == val02)
403 return -1;
404 } else
405 return -1;
409 return 0;
412 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
413 int size, u32 * buf)
415 int i, addr;
416 u32 *ptr32;
418 addr = base;
419 ptr32 = buf;
420 for (i = 0; i < size / sizeof(u32); i++) {
421 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1)
422 return -1;
423 ptr32++;
424 addr += sizeof(u32);
426 if ((char *)buf + size > (char *)ptr32) {
427 u32 local;
429 if (netxen_rom_fast_read(adapter, addr, &local) == -1)
430 return -1;
431 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
434 return 0;
437 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[])
439 u32 *pmac = (u32 *) & mac[0];
441 if (netxen_get_flash_block(adapter,
442 USER_START +
443 offsetof(struct netxen_new_user_info,
444 mac_addr),
445 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
446 return -1;
448 if (*mac == ~0ULL) {
449 if (netxen_get_flash_block(adapter,
450 USER_START_OLD +
451 offsetof(struct netxen_user_old_info,
452 mac_addr),
453 FLASH_NUM_PORTS * sizeof(u64),
454 pmac) == -1)
455 return -1;
456 if (*mac == ~0ULL)
457 return -1;
459 return 0;
463 * Changes the CRB window to the specified window.
465 void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
467 void __iomem *offset;
468 u32 tmp;
469 int count = 0;
471 if (adapter->curr_window == wndw)
472 return;
475 * Move the CRB window.
476 * We need to write to the "direct access" region of PCI
477 * to avoid a race condition where the window register has
478 * not been successfully written across CRB before the target
479 * register address is received by PCI. The direct region bypasses
480 * the CRB bus.
482 offset =
483 PCI_OFFSET_SECOND_RANGE(adapter,
484 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
486 if (wndw & 0x1)
487 wndw = NETXEN_WINDOW_ONE;
489 writel(wndw, offset);
491 /* MUST make sure window is set before we forge on... */
492 while ((tmp = readl(offset)) != wndw) {
493 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
494 "registered properly: 0x%08x.\n",
495 netxen_nic_driver_name, __FUNCTION__, tmp);
496 mdelay(1);
497 if (count >= 10)
498 break;
499 count++;
502 adapter->curr_window = wndw;
505 void netxen_load_firmware(struct netxen_adapter *adapter)
507 int i;
508 long data, size = 0;
509 long flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
510 u64 off;
511 void __iomem *addr;
513 size = NETXEN_FIRMWARE_LEN;
514 writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
516 for (i = 0; i < size; i++) {
517 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) {
518 DPRINTK(ERR,
519 "Error in netxen_rom_fast_read(). Will skip"
520 "loading flash image\n");
521 return;
523 off = netxen_nic_pci_set_window(adapter, memaddr);
524 addr = pci_base_offset(adapter, off);
525 writel(data, addr);
526 flashaddr += 4;
527 memaddr += 4;
529 udelay(100);
530 /* make sure Casper is powered on */
531 writel(0x3fff,
532 NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
533 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
535 udelay(100);
539 netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
540 int len)
542 void __iomem *addr;
544 if (ADDR_IN_WINDOW1(off)) {
545 addr = NETXEN_CRB_NORMALIZE(adapter, off);
546 } else { /* Window 0 */
547 addr = pci_base_offset(adapter, off);
548 netxen_nic_pci_change_crbwindow(adapter, 0);
551 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
552 " data %llx len %d\n",
553 pci_base(adapter, off), off, addr,
554 *(unsigned long long *)data, len);
555 if (!addr) {
556 netxen_nic_pci_change_crbwindow(adapter, 1);
557 return 1;
560 switch (len) {
561 case 1:
562 writeb(*(u8 *) data, addr);
563 break;
564 case 2:
565 writew(*(u16 *) data, addr);
566 break;
567 case 4:
568 writel(*(u32 *) data, addr);
569 break;
570 case 8:
571 writeq(*(u64 *) data, addr);
572 break;
573 default:
574 DPRINTK(INFO,
575 "writing data %lx to offset %llx, num words=%d\n",
576 *(unsigned long *)data, off, (len >> 3));
578 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
579 (len >> 3));
580 break;
582 if (!ADDR_IN_WINDOW1(off))
583 netxen_nic_pci_change_crbwindow(adapter, 1);
585 return 0;
589 netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
590 int len)
592 void __iomem *addr;
594 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
595 addr = NETXEN_CRB_NORMALIZE(adapter, off);
596 } else { /* Window 0 */
597 addr = pci_base_offset(adapter, off);
598 netxen_nic_pci_change_crbwindow(adapter, 0);
601 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
602 pci_base(adapter, off), off, addr);
603 if (!addr) {
604 netxen_nic_pci_change_crbwindow(adapter, 1);
605 return 1;
607 switch (len) {
608 case 1:
609 *(u8 *) data = readb(addr);
610 break;
611 case 2:
612 *(u16 *) data = readw(addr);
613 break;
614 case 4:
615 *(u32 *) data = readl(addr);
616 break;
617 case 8:
618 *(u64 *) data = readq(addr);
619 break;
620 default:
621 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
622 (len >> 3));
623 break;
625 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
627 if (!ADDR_IN_WINDOW1(off))
628 netxen_nic_pci_change_crbwindow(adapter, 1);
630 return 0;
633 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
634 { /* Only for window 1 */
635 void __iomem *addr;
637 addr = NETXEN_CRB_NORMALIZE(adapter, off);
638 DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
639 pci_base(adapter, off), off, addr, val);
640 writel(val, addr);
644 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
645 { /* Only for window 1 */
646 void __iomem *addr;
647 int val;
649 addr = NETXEN_CRB_NORMALIZE(adapter, off);
650 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
651 pci_base(adapter, off), off, addr);
652 val = readl(addr);
653 writel(val, addr);
655 return val;
658 /* Change the window to 0, write and change back to window 1. */
659 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
661 void __iomem *addr;
663 netxen_nic_pci_change_crbwindow(adapter, 0);
664 addr = pci_base_offset(adapter, index);
665 writel(value, addr);
666 netxen_nic_pci_change_crbwindow(adapter, 1);
669 /* Change the window to 0, read and change back to window 1. */
670 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
672 void __iomem *addr;
674 addr = pci_base_offset(adapter, index);
676 netxen_nic_pci_change_crbwindow(adapter, 0);
677 *value = readl(addr);
678 netxen_nic_pci_change_crbwindow(adapter, 1);
681 int netxen_pci_set_window_warning_count = 0;
683 unsigned long
684 netxen_nic_pci_set_window(struct netxen_adapter *adapter,
685 unsigned long long addr)
687 static int ddr_mn_window = -1;
688 static int qdr_sn_window = -1;
689 int window;
691 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
692 /* DDR network side */
693 addr -= NETXEN_ADDR_DDR_NET;
694 window = (addr >> 25) & 0x3ff;
695 if (ddr_mn_window != window) {
696 ddr_mn_window = window;
697 writel(window, PCI_OFFSET_SECOND_RANGE(adapter,
698 NETXEN_PCIX_PH_REG
699 (PCIX_MN_WINDOW)));
700 /* MUST make sure window is set before we forge on... */
701 readl(PCI_OFFSET_SECOND_RANGE(adapter,
702 NETXEN_PCIX_PH_REG
703 (PCIX_MN_WINDOW)));
705 addr -= (window * NETXEN_WINDOW_ONE);
706 addr += NETXEN_PCI_DDR_NET;
707 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
708 addr -= NETXEN_ADDR_OCM0;
709 addr += NETXEN_PCI_OCM0;
710 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
711 addr -= NETXEN_ADDR_OCM1;
712 addr += NETXEN_PCI_OCM1;
713 } else
714 if (ADDR_IN_RANGE
715 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
716 /* QDR network side */
717 addr -= NETXEN_ADDR_QDR_NET;
718 window = (addr >> 22) & 0x3f;
719 if (qdr_sn_window != window) {
720 qdr_sn_window = window;
721 writel((window << 22),
722 PCI_OFFSET_SECOND_RANGE(adapter,
723 NETXEN_PCIX_PH_REG
724 (PCIX_SN_WINDOW)));
725 /* MUST make sure window is set before we forge on... */
726 readl(PCI_OFFSET_SECOND_RANGE(adapter,
727 NETXEN_PCIX_PH_REG
728 (PCIX_SN_WINDOW)));
730 addr -= (window * 0x400000);
731 addr += NETXEN_PCI_QDR_NET;
732 } else {
734 * peg gdb frequently accesses memory that doesn't exist,
735 * this limits the chit chat so debugging isn't slowed down.
737 if ((netxen_pci_set_window_warning_count++ < 8)
738 || (netxen_pci_set_window_warning_count % 64 == 0))
739 printk("%s: Warning:netxen_nic_pci_set_window()"
740 " Unknown address range!\n",
741 netxen_nic_driver_name);
744 return addr;
747 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
749 int rv = 0;
750 int addr = BRDCFG_START;
751 struct netxen_board_info *boardinfo;
752 int index;
753 u32 *ptr32;
755 boardinfo = &adapter->ahw.boardcfg;
756 ptr32 = (u32 *) boardinfo;
758 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
759 index++) {
760 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
761 return -EIO;
763 ptr32++;
764 addr += sizeof(u32);
766 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
767 printk("%s: ERROR reading %s board config."
768 " Read %x, expected %x\n", netxen_nic_driver_name,
769 netxen_nic_driver_name,
770 boardinfo->magic, NETXEN_BDINFO_MAGIC);
771 rv = -1;
773 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
774 printk("%s: Unknown board config version."
775 " Read %x, expected %x\n", netxen_nic_driver_name,
776 boardinfo->header_version, NETXEN_BDINFO_VERSION);
777 rv = -1;
780 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
781 switch ((netxen_brdtype_t) boardinfo->board_type) {
782 case NETXEN_BRDTYPE_P2_SB35_4G:
783 adapter->ahw.board_type = NETXEN_NIC_GBE;
784 break;
785 case NETXEN_BRDTYPE_P2_SB31_10G:
786 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
787 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
788 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
789 adapter->ahw.board_type = NETXEN_NIC_XGBE;
790 break;
791 case NETXEN_BRDTYPE_P1_BD:
792 case NETXEN_BRDTYPE_P1_SB:
793 case NETXEN_BRDTYPE_P1_SMAX:
794 case NETXEN_BRDTYPE_P1_SOCK:
795 adapter->ahw.board_type = NETXEN_NIC_GBE;
796 break;
797 default:
798 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
799 boardinfo->board_type);
800 break;
803 return rv;
806 /* NIU access sections */
808 int netxen_nic_set_mtu_gb(struct netxen_port *port, int new_mtu)
810 struct netxen_adapter *adapter = port->adapter;
811 netxen_nic_write_w0(adapter,
812 NETXEN_NIU_GB_MAX_FRAME_SIZE(port->portnum),
813 new_mtu);
814 return 0;
817 int netxen_nic_set_mtu_xgb(struct netxen_port *port, int new_mtu)
819 struct netxen_adapter *adapter = port->adapter;
820 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
821 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
822 return 0;
825 void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
827 int portno;
828 for (portno = 0; portno < NETXEN_NIU_MAX_GBE_PORTS; portno++)
829 netxen_niu_gbe_init_port(adapter, portno);
832 void netxen_nic_stop_all_ports(struct netxen_adapter *adapter)
834 int port_nr;
835 struct netxen_port *port;
837 for (port_nr = 0; port_nr < adapter->ahw.max_ports; port_nr++) {
838 port = adapter->port[port_nr];
839 if (adapter->stop_port)
840 adapter->stop_port(adapter, port->portnum);
844 void
845 netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
846 int data)
848 void __iomem *addr;
850 if (ADDR_IN_WINDOW1(off)) {
851 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
852 } else {
853 netxen_nic_pci_change_crbwindow(adapter, 0);
854 addr = pci_base_offset(adapter, off);
855 writel(data, addr);
856 netxen_nic_pci_change_crbwindow(adapter, 1);
860 void netxen_nic_set_link_parameters(struct netxen_port *port)
862 struct netxen_adapter *adapter = port->adapter;
863 __u32 status;
864 __u32 autoneg;
865 __u32 mode;
867 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
868 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
869 if (adapter->phy_read
870 && adapter->
871 phy_read(adapter, port->portnum,
872 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
873 &status) == 0) {
874 if (netxen_get_phy_link(status)) {
875 switch (netxen_get_phy_speed(status)) {
876 case 0:
877 port->link_speed = SPEED_10;
878 break;
879 case 1:
880 port->link_speed = SPEED_100;
881 break;
882 case 2:
883 port->link_speed = SPEED_1000;
884 break;
885 default:
886 port->link_speed = -1;
887 break;
889 switch (netxen_get_phy_duplex(status)) {
890 case 0:
891 port->link_duplex = DUPLEX_HALF;
892 break;
893 case 1:
894 port->link_duplex = DUPLEX_FULL;
895 break;
896 default:
897 port->link_duplex = -1;
898 break;
900 if (adapter->phy_read
901 && adapter->
902 phy_read(adapter, port->portnum,
903 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
904 &autoneg) != 0)
905 port->link_autoneg = autoneg;
906 } else
907 goto link_down;
908 } else {
909 link_down:
910 port->link_speed = -1;
911 port->link_duplex = -1;
916 void netxen_nic_flash_print(struct netxen_adapter *adapter)
918 int valid = 1;
919 u32 fw_major = 0;
920 u32 fw_minor = 0;
921 u32 fw_build = 0;
922 char brd_name[NETXEN_MAX_SHORT_NAME];
923 struct netxen_new_user_info user_info;
924 int i, addr = USER_START;
925 u32 *ptr32;
927 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
928 if (board_info->magic != NETXEN_BDINFO_MAGIC) {
929 printk
930 ("NetXen Unknown board config, Read 0x%x expected as 0x%x\n",
931 board_info->magic, NETXEN_BDINFO_MAGIC);
932 valid = 0;
934 if (board_info->header_version != NETXEN_BDINFO_VERSION) {
935 printk("NetXen Unknown board config version."
936 " Read %x, expected %x\n",
937 board_info->header_version, NETXEN_BDINFO_VERSION);
938 valid = 0;
940 if (valid) {
941 ptr32 = (u32 *) & user_info;
942 for (i = 0;
943 i < sizeof(struct netxen_new_user_info) / sizeof(u32);
944 i++) {
945 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
946 printk("%s: ERROR reading %s board userarea.\n",
947 netxen_nic_driver_name,
948 netxen_nic_driver_name);
949 return;
951 ptr32++;
952 addr += sizeof(u32);
954 get_brd_name_by_type(board_info->board_type, brd_name);
956 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
957 brd_name, user_info.serial_num, board_info->chip_id);
959 printk("NetXen %s Board #%d, Chip id 0x%x\n",
960 board_info->board_type == 0x0b ? "XGB" : "GBE",
961 board_info->board_num, board_info->chip_id);
962 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
963 NETXEN_FW_VERSION_MAJOR));
964 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
965 NETXEN_FW_VERSION_MINOR));
966 fw_build =
967 readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
969 printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor,
970 fw_build);
972 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
973 printk(KERN_ERR "The mismatch in driver version and firmware "
974 "version major number\n"
975 "Driver version major number = %d \t"
976 "Firmware version major number = %d \n",
977 _NETXEN_NIC_LINUX_MAJOR, fw_major);
978 adapter->driver_mismatch = 1;
980 if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
981 fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
982 printk(KERN_ERR "The mismatch in driver version and firmware "
983 "version minor number\n"
984 "Driver version minor number = %d \t"
985 "Firmware version minor number = %d \n",
986 _NETXEN_NIC_LINUX_MINOR, fw_minor);
987 adapter->driver_mismatch = 1;
989 if (adapter->driver_mismatch)
990 printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n",
991 fw_major, fw_minor);