drivers/net/spider_net.h

   1 /*
   2  * Network device driver for Cell Processor-Based Blade
   3  *
   4  * (C) Copyright IBM Corp. 2005
   5  *
   6  * Authors : Utz Bacher <utz.bacher@de.ibm.com>
   7  *           Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2, or (at your option)
  12  * any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #ifndef _SPIDER_NET_H
  25 #define _SPIDER_NET_H
  26
  27 #define VERSION "1.6 A"
  28
  29 #include "sungem_phy.h"
  30
  31 extern int spider_net_stop(struct net_device *netdev);
  32 extern int spider_net_open(struct net_device *netdev);
  33
  34 extern const struct ethtool_ops spider_net_ethtool_ops;
  35
  36 extern char spider_net_driver_name[];
  37
  38 #define SPIDER_NET_MAX_FRAME                    2312
  39 #define SPIDER_NET_MAX_MTU                      2294
  40 #define SPIDER_NET_MIN_MTU                      64
  41
  42 #define SPIDER_NET_RXBUF_ALIGN                  128
  43
  44 #define SPIDER_NET_RX_DESCRIPTORS_DEFAULT       256
  45 #define SPIDER_NET_RX_DESCRIPTORS_MIN           16
  46 #define SPIDER_NET_RX_DESCRIPTORS_MAX           512
  47
  48 #define SPIDER_NET_TX_DESCRIPTORS_DEFAULT       256
  49 #define SPIDER_NET_TX_DESCRIPTORS_MIN           16
  50 #define SPIDER_NET_TX_DESCRIPTORS_MAX           512
  51
  52 #define SPIDER_NET_TX_TIMER                     (HZ/5)
  53
  54 #define SPIDER_NET_RX_CSUM_DEFAULT              1
  55
  56 #define SPIDER_NET_WATCHDOG_TIMEOUT             50*HZ
  57 #define SPIDER_NET_NAPI_WEIGHT                  64
  58
  59 #define SPIDER_NET_FIRMWARE_SEQS        6
  60 #define SPIDER_NET_FIRMWARE_SEQWORDS    1024
  61 #define SPIDER_NET_FIRMWARE_LEN         (SPIDER_NET_FIRMWARE_SEQS * \
  62                                          SPIDER_NET_FIRMWARE_SEQWORDS * \
  63                                          sizeof(u32))
  64 #define SPIDER_NET_FIRMWARE_NAME        "spider_fw.bin"
  65
  66 /** spider_net SMMIO registers */
  67 #define SPIDER_NET_GHIINT0STS           0x00000000
  68 #define SPIDER_NET_GHIINT1STS           0x00000004
  69 #define SPIDER_NET_GHIINT2STS           0x00000008
  70 #define SPIDER_NET_GHIINT0MSK           0x00000010
  71 #define SPIDER_NET_GHIINT1MSK           0x00000014
  72 #define SPIDER_NET_GHIINT2MSK           0x00000018
  73
  74 #define SPIDER_NET_GRESUMINTNUM         0x00000020
  75 #define SPIDER_NET_GREINTNUM            0x00000024
  76
  77 #define SPIDER_NET_GFFRMNUM             0x00000028
  78 #define SPIDER_NET_GFAFRMNUM            0x0000002c
  79 #define SPIDER_NET_GFBFRMNUM            0x00000030
  80 #define SPIDER_NET_GFCFRMNUM            0x00000034
  81 #define SPIDER_NET_GFDFRMNUM            0x00000038
  82
  83 /* clear them (don't use it) */
  84 #define SPIDER_NET_GFREECNNUM           0x0000003c
  85 #define SPIDER_NET_GONETIMENUM          0x00000040
  86
  87 #define SPIDER_NET_GTOUTFRMNUM          0x00000044
  88
  89 #define SPIDER_NET_GTXMDSET             0x00000050
  90 #define SPIDER_NET_GPCCTRL              0x00000054
  91 #define SPIDER_NET_GRXMDSET             0x00000058
  92 #define SPIDER_NET_GIPSECINIT           0x0000005c
  93 #define SPIDER_NET_GFTRESTRT            0x00000060
  94 #define SPIDER_NET_GRXDMAEN             0x00000064
  95 #define SPIDER_NET_GMRWOLCTRL           0x00000068
  96 #define SPIDER_NET_GPCWOPCMD            0x0000006c
  97 #define SPIDER_NET_GPCROPCMD            0x00000070
  98 #define SPIDER_NET_GTTFRMCNT            0x00000078
  99 #define SPIDER_NET_GTESTMD              0x0000007c
 100
 101 #define SPIDER_NET_GSINIT               0x00000080
 102 #define SPIDER_NET_GSnPRGADR            0x00000084
 103 #define SPIDER_NET_GSnPRGDAT            0x00000088
 104
 105 #define SPIDER_NET_GMACOPEMD            0x00000100
 106 #define SPIDER_NET_GMACLENLMT           0x00000108
 107 #define SPIDER_NET_GMACINTEN            0x00000118
 108 #define SPIDER_NET_GMACPHYCTRL          0x00000120
 109
 110 #define SPIDER_NET_GMACAPAUSE           0x00000154
 111 #define SPIDER_NET_GMACTXPAUSE          0x00000164
 112
 113 #define SPIDER_NET_GMACMODE             0x000001b0
 114 #define SPIDER_NET_GMACBSTLMT           0x000001b4
 115
 116 #define SPIDER_NET_GMACUNIMACU          0x000001c0
 117 #define SPIDER_NET_GMACUNIMACL          0x000001c8
 118
 119 #define SPIDER_NET_GMRMHFILnR           0x00000400
 120 #define SPIDER_NET_MULTICAST_HASHES     256
 121
 122 #define SPIDER_NET_GMRUAFILnR           0x00000500
 123 #define SPIDER_NET_GMRUA0FIL15R         0x00000578
 124
 125 #define SPIDER_NET_GTTQMSK              0x00000934
 126
 127 /* RX DMA controller registers, all 0x00000a.. are for DMA controller A,
 128  * 0x00000b.. for DMA controller B, etc. */
 129 #define SPIDER_NET_GDADCHA              0x00000a00
 130 #define SPIDER_NET_GDADMACCNTR          0x00000a04
 131 #define SPIDER_NET_GDACTDPA             0x00000a08
 132 #define SPIDER_NET_GDACTDCNT            0x00000a0c
 133 #define SPIDER_NET_GDACDBADDR           0x00000a20
 134 #define SPIDER_NET_GDACDBSIZE           0x00000a24
 135 #define SPIDER_NET_GDACNEXTDA           0x00000a28
 136 #define SPIDER_NET_GDACCOMST            0x00000a2c
 137 #define SPIDER_NET_GDAWBCOMST           0x00000a30
 138 #define SPIDER_NET_GDAWBRSIZE           0x00000a34
 139 #define SPIDER_NET_GDAWBVSIZE           0x00000a38
 140 #define SPIDER_NET_GDAWBTRST            0x00000a3c
 141 #define SPIDER_NET_GDAWBTRERR           0x00000a40
 142
 143 /* TX DMA controller registers */
 144 #define SPIDER_NET_GDTDCHA              0x00000e00
 145 #define SPIDER_NET_GDTDMACCNTR          0x00000e04
 146 #define SPIDER_NET_GDTCDPA              0x00000e08
 147 #define SPIDER_NET_GDTDMASEL            0x00000e14
 148
 149 #define SPIDER_NET_ECMODE               0x00000f00
 150 /* clock and reset control register */
 151 #define SPIDER_NET_CKRCTRL              0x00000ff0
 152
 153 /** SCONFIG registers */
 154 #define SPIDER_NET_SCONFIG_IOACTE       0x00002810
 155
 156 /** interrupt mask registers */
 157 #define SPIDER_NET_INT0_MASK_VALUE      0x3f7fe2c7
 158 #define SPIDER_NET_INT1_MASK_VALUE      0xffff7ff7
 159 /* no MAC aborts -> auto retransmission */
 160 #define SPIDER_NET_INT2_MASK_VALUE      0xffef7ff1
 161
 162 /* we rely on flagged descriptor interrupts */
 163 #define SPIDER_NET_FRAMENUM_VALUE       0x00000000
 164 /* set this first, then the FRAMENUM_VALUE */
 165 #define SPIDER_NET_GFXFRAMES_VALUE      0x00000000
 166
 167 #define SPIDER_NET_STOP_SEQ_VALUE       0x00000000
 168 #define SPIDER_NET_RUN_SEQ_VALUE        0x0000007e
 169
 170 #define SPIDER_NET_PHY_CTRL_VALUE       0x00040040
 171 /* #define SPIDER_NET_PHY_CTRL_VALUE    0x01070080*/
 172 #define SPIDER_NET_RXMODE_VALUE         0x00000011
 173 /* auto retransmission in case of MAC aborts */
 174 #define SPIDER_NET_TXMODE_VALUE         0x00010000
 175 #define SPIDER_NET_RESTART_VALUE        0x00000000
 176 #define SPIDER_NET_WOL_VALUE            0x00001111
 177 #if 0
 178 #define SPIDER_NET_WOL_VALUE            0x00000000
 179 #endif
 180 #define SPIDER_NET_IPSECINIT_VALUE      0x6f716f71
 181
 182 /* pause frames: automatic, no upper retransmission count */
 183 /* outside loopback mode: ETOMOD signal dont matter, not connected */
 184 #define SPIDER_NET_OPMODE_VALUE         0x00000063
 185 /*#define SPIDER_NET_OPMODE_VALUE               0x001b0062*/
 186 #define SPIDER_NET_LENLMT_VALUE         0x00000908
 187
 188 #define SPIDER_NET_MACAPAUSE_VALUE      0x00000800 /* about 1 ms */
 189 #define SPIDER_NET_TXPAUSE_VALUE        0x00000000
 190
 191 #define SPIDER_NET_MACMODE_VALUE        0x00000001
 192 #define SPIDER_NET_BURSTLMT_VALUE       0x00000200 /* about 16 us */
 193
 194 /* DMAC control register GDMACCNTR
 195  *
 196  * 1(0)                         enable r/tx dma
 197  *  0000000                             fixed to 0
 198  *
 199  *         000000                       fixed to 0
 200  *               0(1)                   en/disable descr writeback on force end
 201  *                0(1)                  force end
 202  *
 203  *                 000000               fixed to 0
 204  *                       00             burst alignment: 128 bytes
 205  *                       11             burst alignment: 1024 bytes
 206  *
 207  *                         00000        fixed to 0
 208  *                              0       descr writeback size 32 bytes
 209  *                               0(1)   descr chain end interrupt enable
 210  *                                0(1)  descr status writeback enable */
 211
 212 /* to set RX_DMA_EN */
 213 #define SPIDER_NET_DMA_RX_VALUE         0x80000000
 214 #define SPIDER_NET_DMA_RX_FEND_VALUE    0x00030003
 215 /* to set TX_DMA_EN */
 216 #define SPIDER_NET_TX_DMA_EN           0x80000000
 217 #define SPIDER_NET_GDTBSTA             0x00000300
 218 #define SPIDER_NET_GDTDCEIDIS          0x00000002
 219 #define SPIDER_NET_DMA_TX_VALUE        SPIDER_NET_TX_DMA_EN | \
 220                                        SPIDER_NET_GDTBSTA
 221
 222 #define SPIDER_NET_DMA_TX_FEND_VALUE    0x00030003
 223
 224 /* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
 225 #define SPIDER_NET_UA_DESCR_VALUE       0x00080000
 226 #define SPIDER_NET_PROMISC_VALUE        0x00080000
 227 #define SPIDER_NET_NONPROMISC_VALUE     0x00000000
 228
 229 #define SPIDER_NET_DMASEL_VALUE         0x00000001
 230
 231 #define SPIDER_NET_ECMODE_VALUE         0x00000000
 232
 233 #define SPIDER_NET_CKRCTRL_RUN_VALUE    0x1fff010f
 234 #define SPIDER_NET_CKRCTRL_STOP_VALUE   0x0000010f
 235
 236 #define SPIDER_NET_SBIMSTATE_VALUE      0x00000000
 237 #define SPIDER_NET_SBTMSTATE_VALUE      0x00000000
 238
 239 /* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used
 240  * with 1 << SPIDER_NET_... */
 241 enum spider_net_int0_status {
 242         SPIDER_NET_GPHYINT = 0,
 243         SPIDER_NET_GMAC2INT,
 244         SPIDER_NET_GMAC1INT,
 245         SPIDER_NET_GIPSINT,
 246         SPIDER_NET_GFIFOINT,
 247         SPIDER_NET_GDMACINT,
 248         SPIDER_NET_GSYSINT,
 249         SPIDER_NET_GPWOPCMPINT,
 250         SPIDER_NET_GPROPCMPINT,
 251         SPIDER_NET_GPWFFINT,
 252         SPIDER_NET_GRMDADRINT,
 253         SPIDER_NET_GRMARPINT,
 254         SPIDER_NET_GRMMPINT,
 255         SPIDER_NET_GDTDEN0INT,
 256         SPIDER_NET_GDDDEN0INT,
 257         SPIDER_NET_GDCDEN0INT,
 258         SPIDER_NET_GDBDEN0INT,
 259         SPIDER_NET_GDADEN0INT,
 260         SPIDER_NET_GDTFDCINT,
 261         SPIDER_NET_GDDFDCINT,
 262         SPIDER_NET_GDCFDCINT,
 263         SPIDER_NET_GDBFDCINT,
 264         SPIDER_NET_GDAFDCINT,
 265         SPIDER_NET_GTTEDINT,
 266         SPIDER_NET_GDTDCEINT,
 267         SPIDER_NET_GRFDNMINT,
 268         SPIDER_NET_GRFCNMINT,
 269         SPIDER_NET_GRFBNMINT,
 270         SPIDER_NET_GRFANMINT,
 271         SPIDER_NET_GRFNMINT,
 272         SPIDER_NET_G1TMCNTINT,
 273         SPIDER_NET_GFREECNTINT
 274 };
 275 /* GHIINT1STS bits */
 276 enum spider_net_int1_status {
 277         SPIDER_NET_GTMFLLINT = 0,
 278         SPIDER_NET_GRMFLLINT,
 279         SPIDER_NET_GTMSHTINT,
 280         SPIDER_NET_GDTINVDINT,
 281         SPIDER_NET_GRFDFLLINT,
 282         SPIDER_NET_GDDDCEINT,
 283         SPIDER_NET_GDDINVDINT,
 284         SPIDER_NET_GRFCFLLINT,
 285         SPIDER_NET_GDCDCEINT,
 286         SPIDER_NET_GDCINVDINT,
 287         SPIDER_NET_GRFBFLLINT,
 288         SPIDER_NET_GDBDCEINT,
 289         SPIDER_NET_GDBINVDINT,
 290         SPIDER_NET_GRFAFLLINT,
 291         SPIDER_NET_GDADCEINT,
 292         SPIDER_NET_GDAINVDINT,
 293         SPIDER_NET_GDTRSERINT,
 294         SPIDER_NET_GDDRSERINT,
 295         SPIDER_NET_GDCRSERINT,
 296         SPIDER_NET_GDBRSERINT,
 297         SPIDER_NET_GDARSERINT,
 298         SPIDER_NET_GDSERINT,
 299         SPIDER_NET_GDTPTERINT,
 300         SPIDER_NET_GDDPTERINT,
 301         SPIDER_NET_GDCPTERINT,
 302         SPIDER_NET_GDBPTERINT,
 303         SPIDER_NET_GDAPTERINT
 304 };
 305 /* GHIINT2STS bits */
 306 enum spider_net_int2_status {
 307         SPIDER_NET_GPROPERINT = 0,
 308         SPIDER_NET_GMCTCRSNGINT,
 309         SPIDER_NET_GMCTLCOLINT,
 310         SPIDER_NET_GMCTTMOTINT,
 311         SPIDER_NET_GMCRCAERINT,
 312         SPIDER_NET_GMCRCALERINT,
 313         SPIDER_NET_GMCRALNERINT,
 314         SPIDER_NET_GMCROVRINT,
 315         SPIDER_NET_GMCRRNTINT,
 316         SPIDER_NET_GMCRRXERINT,
 317         SPIDER_NET_GTITCSERINT,
 318         SPIDER_NET_GTIFMTERINT,
 319         SPIDER_NET_GTIPKTRVKINT,
 320         SPIDER_NET_GTISPINGINT,
 321         SPIDER_NET_GTISADNGINT,
 322         SPIDER_NET_GTISPDNGINT,
 323         SPIDER_NET_GRIFMTERINT,
 324         SPIDER_NET_GRIPKTRVKINT,
 325         SPIDER_NET_GRISPINGINT,
 326         SPIDER_NET_GRISADNGINT,
 327         SPIDER_NET_GRISPDNGINT
 328 };
 329
 330 #define SPIDER_NET_TXINT        ( (1 << SPIDER_NET_GDTFDCINT) | \
 331                              (1 << SPIDER_NET_GDTDCEINT) )
 332
 333 /* We rely on flagged descriptor interrupts */
 334 #define SPIDER_NET_RXINT        ( (1 << SPIDER_NET_GDAFDCINT) )
 335
 336 #define SPIDER_NET_ERRINT       ( 0xffffffff & \
 337                                   (~SPIDER_NET_TXINT) & \
 338                                   (~SPIDER_NET_RXINT) )
 339
 340 #define SPIDER_NET_GPREXEC                      0x80000000
 341 #define SPIDER_NET_GPRDAT_MASK                  0x0000ffff
 342
 343 #define SPIDER_NET_DMAC_NOINTR_COMPLETE         0x00800000
 344 #define SPIDER_NET_DMAC_NOCS                    0x00040000
 345 #define SPIDER_NET_DMAC_TCP                     0x00020000
 346 #define SPIDER_NET_DMAC_UDP                     0x00030000
 347 #define SPIDER_NET_TXDCEST                      0x08000000
 348
 349 #define SPIDER_NET_DESCR_IND_PROC_MASK          0xF0000000
 350 #define SPIDER_NET_DESCR_COMPLETE               0x00000000 /* used in rx and tx */
 351 #define SPIDER_NET_DESCR_RESPONSE_ERROR         0x10000000 /* used in rx and tx */
 352 #define SPIDER_NET_DESCR_PROTECTION_ERROR       0x20000000 /* used in rx and tx */
 353 #define SPIDER_NET_DESCR_FRAME_END              0x40000000 /* used in rx */
 354 #define SPIDER_NET_DESCR_FORCE_END              0x50000000 /* used in rx and tx */
 355 #define SPIDER_NET_DESCR_CARDOWNED              0xA0000000 /* used in rx and tx */
 356 #define SPIDER_NET_DESCR_NOT_IN_USE             0xF0000000
 357 #define SPIDER_NET_DESCR_TXDESFLG               0x00800000
 358
 359 struct spider_net_descr {
 360         /* as defined by the hardware */
 361         u32 buf_addr;
 362         u32 buf_size;
 363         u32 next_descr_addr;
 364         u32 dmac_cmd_status;
 365         u32 result_size;
 366         u32 valid_size; /* all zeroes for tx */
 367         u32 data_status;
 368         u32 data_error; /* all zeroes for tx */
 369
 370         /* used in the driver */
 371         struct sk_buff *skb;
 372         u32 bus_addr;
 373         struct spider_net_descr *next;
 374         struct spider_net_descr *prev;
 375 } __attribute__((aligned(32)));
 376
 377 struct spider_net_descr_chain {
 378         spinlock_t lock;
 379         struct spider_net_descr *head;
 380         struct spider_net_descr *tail;
 381 };
 382
 383 /* descriptor data_status bits */
 384 #define SPIDER_NET_RX_IPCHK             29
 385 #define SPIDER_NET_RX_TCPCHK            28
 386 #define SPIDER_NET_VLAN_PACKET          21
 387 #define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) | \
 388                                           (1 << SPIDER_NET_RX_TCPCHK) )
 389
 390 /* descriptor data_error bits */
 391 #define SPIDER_NET_RX_IPCHKERR          27
 392 #define SPIDER_NET_RX_RXTCPCHKERR       28
 393
 394 #define SPIDER_NET_DATA_ERR_CKSUM_MASK  (1 << SPIDER_NET_RX_IPCHKERR)
 395
 396 /* the cases we don't pass the packet to the stack.
 397  * 701b8000 would be correct, but every packets gets that flag */
 398 #define SPIDER_NET_DESTROY_RX_FLAGS     0x700b8000
 399
 400 #define SPIDER_NET_DESCR_SIZE           32
 401
 402 /* this will be bigger some time */
 403 struct spider_net_options {
 404         int rx_csum; /* for rx: if 0 ip_summed=NONE,
 405                         if 1 and hw has verified, ip_summed=UNNECESSARY */
 406 };
 407
 408 #define SPIDER_NET_DEFAULT_MSG          ( NETIF_MSG_DRV | \
 409                                           NETIF_MSG_PROBE | \
 410                                           NETIF_MSG_LINK | \
 411                                           NETIF_MSG_TIMER | \
 412                                           NETIF_MSG_IFDOWN | \
 413                                           NETIF_MSG_IFUP | \
 414                                           NETIF_MSG_RX_ERR | \
 415                                           NETIF_MSG_TX_ERR | \
 416                                           NETIF_MSG_TX_QUEUED | \
 417                                           NETIF_MSG_INTR | \
 418                                           NETIF_MSG_TX_DONE | \
 419                                           NETIF_MSG_RX_STATUS | \
 420                                           NETIF_MSG_PKTDATA | \
 421                                           NETIF_MSG_HW | \
 422                                           NETIF_MSG_WOL )
 423
 424 struct spider_net_extra_stats {
 425         unsigned long rx_desc_error;
 426         unsigned long tx_timeouts;
 427         unsigned long alloc_rx_skb_error;
 428         unsigned long rx_iommu_map_error;
 429         unsigned long tx_iommu_map_error;
 430         unsigned long rx_desc_unk_state;
 431 };
 432
 433 struct spider_net_card {
 434         struct net_device *netdev;
 435         struct pci_dev *pdev;
 436         struct mii_phy phy;
 437
 438         void __iomem *regs;
 439
 440         struct spider_net_descr_chain tx_chain;
 441         struct spider_net_descr_chain rx_chain;
 442         struct spider_net_descr *low_watermark;
 443
 444         struct net_device_stats netdev_stats;
 445
 446         struct spider_net_options options;
 447
 448         spinlock_t intmask_lock;
 449         struct tasklet_struct rxram_full_tl;
 450         struct timer_list tx_timer;
 451
 452         struct work_struct tx_timeout_task;
 453         atomic_t tx_timeout_task_counter;
 454         wait_queue_head_t waitq;
 455
 456         /* for ethtool */
 457         int msg_enable;
 458         int num_rx_desc;
 459         int num_tx_desc;
 460         struct spider_net_extra_stats spider_stats;
 461
 462         struct spider_net_descr descr[0];
 463 };
 464
 465 #define pr_err(fmt,arg...) \
 466         printk(KERN_ERR fmt ,##arg)
 467
 468 #endif