drivers/net/ucc_geth_phy.c

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
   3  *
   4  * Author: Shlomi Gridish <gridish@freescale.com>
   5  *
   6  * Description:
   7  * UCC GETH Driver -- PHY handling
   8  *
   9  * Changelog:
  10  * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
  11  * - Rearrange code and style fixes
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  *
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/sched.h>
  22 #include <linux/string.h>
  23 #include <linux/errno.h>
  24 #include <linux/slab.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/skbuff.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/version.h>
  35 #include <linux/crc32.h>
  36 #include <linux/mii.h>
  37 #include <linux/ethtool.h>
  38
  39 #include <asm/io.h>
  40 #include <asm/irq.h>
  41 #include <asm/uaccess.h>
  42
  43 #include "ucc_geth.h"
  44 #include "ucc_geth_phy.h"
  45
  46 #define ugphy_printk(level, format, arg...)  \
  47         printk(level format "\n", ## arg)
  48
  49 #define ugphy_dbg(format, arg...)            \
  50         ugphy_printk(KERN_DEBUG, format , ## arg)
  51 #define ugphy_err(format, arg...)            \
  52         ugphy_printk(KERN_ERR, format , ## arg)
  53 #define ugphy_info(format, arg...)           \
  54         ugphy_printk(KERN_INFO, format , ## arg)
  55 #define ugphy_warn(format, arg...)           \
  56         ugphy_printk(KERN_WARNING, format , ## arg)
  57
  58 #ifdef UGETH_VERBOSE_DEBUG
  59 #define ugphy_vdbg ugphy_dbg
  60 #else
  61 #define ugphy_vdbg(fmt, args...) do { } while (0)
  62 #endif                          /* UGETH_VERBOSE_DEBUG */
  63
  64 static void config_genmii_advert(struct ugeth_mii_info *mii_info);
  65 static void genmii_setup_forced(struct ugeth_mii_info *mii_info);
  66 static void genmii_restart_aneg(struct ugeth_mii_info *mii_info);
  67 static int gbit_config_aneg(struct ugeth_mii_info *mii_info);
  68 static int genmii_config_aneg(struct ugeth_mii_info *mii_info);
  69 static int genmii_update_link(struct ugeth_mii_info *mii_info);
  70 static int genmii_read_status(struct ugeth_mii_info *mii_info);
  71
  72 static u16 ucc_geth_phy_read(struct ugeth_mii_info *mii_info, u16 regnum)
  73 {
  74         u16 retval;
  75         unsigned long flags;
  76
  77         ugphy_vdbg("%s: IN", __FUNCTION__);
  78
  79         spin_lock_irqsave(&mii_info->mdio_lock, flags);
  80         retval = mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
  81         spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
  82
  83         return retval;
  84 }
  85
  86 static void ucc_geth_phy_write(struct ugeth_mii_info *mii_info, u16 regnum, u16 val)
  87 {
  88         unsigned long flags;
  89
  90         ugphy_vdbg("%s: IN", __FUNCTION__);
  91
  92         spin_lock_irqsave(&mii_info->mdio_lock, flags);
  93         mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val);
  94         spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
  95 }
  96
  97 /* Write value to the PHY for this device to the register at regnum, */
  98 /* waiting until the write is done before it returns.  All PHY */
  99 /* configuration has to be done through the TSEC1 MIIM regs */
 100 void write_phy_reg(struct net_device *dev, int mii_id, int regnum, int value)
 101 {
 102         struct ucc_geth_private *ugeth = netdev_priv(dev);
 103         struct ucc_mii_mng *mii_regs;
 104         enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg) regnum;
 105         u32 tmp_reg;
 106
 107         ugphy_vdbg("%s: IN", __FUNCTION__);
 108
 109         spin_lock_irq(&ugeth->lock);
 110
 111         mii_regs = ugeth->mii_info->mii_regs;
 112
 113         /* Set this UCC to be the master of the MII managment */
 114         ucc_set_qe_mux_mii_mng(ugeth->ug_info->uf_info.ucc_num);
 115
 116         /* Stop the MII management read cycle */
 117         out_be32(&mii_regs->miimcom, 0);
 118         /* Setting up the MII Mangement Address Register */
 119         tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
 120         out_be32(&mii_regs->miimadd, tmp_reg);
 121
 122         /* Setting up the MII Mangement Control Register with the value */
 123         out_be32(&mii_regs->miimcon, (u32) value);
 124
 125         /* Wait till MII management write is complete */
 126         while ((in_be32(&mii_regs->miimind)) & MIIMIND_BUSY)
 127                 cpu_relax();
 128
 129         spin_unlock_irq(&ugeth->lock);
 130
 131         udelay(10000);
 132 }
 133
 134 /* Reads from register regnum in the PHY for device dev, */
 135 /* returning the value.  Clears miimcom first.  All PHY */
 136 /* configuration has to be done through the TSEC1 MIIM regs */
 137 int read_phy_reg(struct net_device *dev, int mii_id, int regnum)
 138 {
 139         struct ucc_geth_private *ugeth = netdev_priv(dev);
 140         struct ucc_mii_mng *mii_regs;
 141         enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg) regnum;
 142         u32 tmp_reg;
 143         u16 value;
 144
 145         ugphy_vdbg("%s: IN", __FUNCTION__);
 146
 147         spin_lock_irq(&ugeth->lock);
 148
 149         mii_regs = ugeth->mii_info->mii_regs;
 150
 151         /* Setting up the MII Mangement Address Register */
 152         tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
 153         out_be32(&mii_regs->miimadd, tmp_reg);
 154
 155         /* Perform an MII management read cycle */
 156         out_be32(&mii_regs->miimcom, MIIMCOM_READ_CYCLE);
 157
 158         /* Wait till MII management write is complete */
 159         while ((in_be32(&mii_regs->miimind)) & MIIMIND_BUSY)
 160                 cpu_relax();
 161
 162         udelay(10000);
 163
 164         /* Read MII management status  */
 165         value = (u16) in_be32(&mii_regs->miimstat);
 166         out_be32(&mii_regs->miimcom, 0);
 167         if (value == 0xffff)
 168                 ugphy_warn("read wrong value : mii_id %d,mii_reg %d, base %08x",
 169                            mii_id, mii_reg, (u32) & (mii_regs->miimcfg));
 170
 171         spin_unlock_irq(&ugeth->lock);
 172
 173         return (value);
 174 }
 175
 176 void mii_clear_phy_interrupt(struct ugeth_mii_info *mii_info)
 177 {
 178         ugphy_vdbg("%s: IN", __FUNCTION__);
 179
 180         if (mii_info->phyinfo->ack_interrupt)
 181                 mii_info->phyinfo->ack_interrupt(mii_info);
 182 }
 183
 184 void mii_configure_phy_interrupt(struct ugeth_mii_info *mii_info,
 185                                  u32 interrupts)
 186 {
 187         ugphy_vdbg("%s: IN", __FUNCTION__);
 188
 189         mii_info->interrupts = interrupts;
 190         if (mii_info->phyinfo->config_intr)
 191                 mii_info->phyinfo->config_intr(mii_info);
 192 }
 193
 194 /* Writes MII_ADVERTISE with the appropriate values, after
 195  * sanitizing advertise to make sure only supported features
 196  * are advertised
 197  */
 198 static void config_genmii_advert(struct ugeth_mii_info *mii_info)
 199 {
 200         u32 advertise;
 201         u16 adv;
 202
 203         ugphy_vdbg("%s: IN", __FUNCTION__);
 204
 205         /* Only allow advertising what this PHY supports */
 206         mii_info->advertising &= mii_info->phyinfo->features;
 207         advertise = mii_info->advertising;
 208
 209         /* Setup standard advertisement */
 210         adv = ucc_geth_phy_read(mii_info, MII_ADVERTISE);
 211         adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
 212         if (advertise & ADVERTISED_10baseT_Half)
 213                 adv |= ADVERTISE_10HALF;
 214         if (advertise & ADVERTISED_10baseT_Full)
 215                 adv |= ADVERTISE_10FULL;
 216         if (advertise & ADVERTISED_100baseT_Half)
 217                 adv |= ADVERTISE_100HALF;
 218         if (advertise & ADVERTISED_100baseT_Full)
 219                 adv |= ADVERTISE_100FULL;
 220         ucc_geth_phy_write(mii_info, MII_ADVERTISE, adv);
 221 }
 222
 223 static void genmii_setup_forced(struct ugeth_mii_info *mii_info)
 224 {
 225         u16 ctrl;
 226         u32 features = mii_info->phyinfo->features;
 227
 228         ugphy_vdbg("%s: IN", __FUNCTION__);
 229
 230         ctrl = ucc_geth_phy_read(mii_info, MII_BMCR);
 231
 232         ctrl &=
 233             ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
 234         ctrl |= BMCR_RESET;
 235
 236         switch (mii_info->speed) {
 237         case SPEED_1000:
 238                 if (features & (SUPPORTED_1000baseT_Half
 239                                 | SUPPORTED_1000baseT_Full)) {
 240                         ctrl |= BMCR_SPEED1000;
 241                         break;
 242                 }
 243                 mii_info->speed = SPEED_100;
 244         case SPEED_100:
 245                 if (features & (SUPPORTED_100baseT_Half
 246                                 | SUPPORTED_100baseT_Full)) {
 247                         ctrl |= BMCR_SPEED100;
 248                         break;
 249                 }
 250                 mii_info->speed = SPEED_10;
 251         case SPEED_10:
 252                 if (features & (SUPPORTED_10baseT_Half
 253                                 | SUPPORTED_10baseT_Full))
 254                         break;
 255         default:                /* Unsupported speed! */
 256                 ugphy_err("%s: Bad speed!", mii_info->dev->name);
 257                 break;
 258         }
 259
 260         ucc_geth_phy_write(mii_info, MII_BMCR, ctrl);
 261 }
 262
 263 /* Enable and Restart Autonegotiation */
 264 static void genmii_restart_aneg(struct ugeth_mii_info *mii_info)
 265 {
 266         u16 ctl;
 267
 268         ugphy_vdbg("%s: IN", __FUNCTION__);
 269
 270         ctl = ucc_geth_phy_read(mii_info, MII_BMCR);
 271         ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
 272         ucc_geth_phy_write(mii_info, MII_BMCR, ctl);
 273 }
 274
 275 static int gbit_config_aneg(struct ugeth_mii_info *mii_info)
 276 {
 277         u16 adv;
 278         u32 advertise;
 279
 280         ugphy_vdbg("%s: IN", __FUNCTION__);
 281
 282         if (mii_info->autoneg) {
 283                 /* Configure the ADVERTISE register */
 284                 config_genmii_advert(mii_info);
 285                 advertise = mii_info->advertising;
 286
 287                 adv = ucc_geth_phy_read(mii_info, MII_1000BASETCONTROL);
 288                 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
 289                          MII_1000BASETCONTROL_HALFDUPLEXCAP);
 290                 if (advertise & SUPPORTED_1000baseT_Half)
 291                         adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
 292                 if (advertise & SUPPORTED_1000baseT_Full)
 293                         adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
 294                 ucc_geth_phy_write(mii_info, MII_1000BASETCONTROL, adv);
 295
 296                 /* Start/Restart aneg */
 297                 genmii_restart_aneg(mii_info);
 298         } else
 299                 genmii_setup_forced(mii_info);
 300
 301         return 0;
 302 }
 303
 304 static int genmii_config_aneg(struct ugeth_mii_info *mii_info)
 305 {
 306         ugphy_vdbg("%s: IN", __FUNCTION__);
 307
 308         if (mii_info->autoneg) {
 309                 config_genmii_advert(mii_info);
 310                 genmii_restart_aneg(mii_info);
 311         } else
 312                 genmii_setup_forced(mii_info);
 313
 314         return 0;
 315 }
 316
 317 static int genmii_update_link(struct ugeth_mii_info *mii_info)
 318 {
 319         u16 status;
 320
 321         ugphy_vdbg("%s: IN", __FUNCTION__);
 322
 323         /* Do a fake read */
 324         ucc_geth_phy_read(mii_info, MII_BMSR);
 325
 326         /* Read link and autonegotiation status */
 327         status = ucc_geth_phy_read(mii_info, MII_BMSR);
 328         if ((status & BMSR_LSTATUS) == 0)
 329                 mii_info->link = 0;
 330         else
 331                 mii_info->link = 1;
 332
 333         /* If we are autonegotiating, and not done,
 334          * return an error */
 335         if (mii_info->autoneg && !(status & BMSR_ANEGCOMPLETE))
 336                 return -EAGAIN;
 337
 338         return 0;
 339 }
 340
 341 static int genmii_read_status(struct ugeth_mii_info *mii_info)
 342 {
 343         u16 status;
 344         int err;
 345
 346         ugphy_vdbg("%s: IN", __FUNCTION__);
 347
 348         /* Update the link, but return if there
 349          * was an error */
 350         err = genmii_update_link(mii_info);
 351         if (err)
 352                 return err;
 353
 354         if (mii_info->autoneg) {
 355                 status = ucc_geth_phy_read(mii_info, MII_LPA);
 356
 357                 if (status & (LPA_10FULL | LPA_100FULL))
 358                         mii_info->duplex = DUPLEX_FULL;
 359                 else
 360                         mii_info->duplex = DUPLEX_HALF;
 361                 if (status & (LPA_100FULL | LPA_100HALF))
 362                         mii_info->speed = SPEED_100;
 363                 else
 364                         mii_info->speed = SPEED_10;
 365                 mii_info->pause = 0;
 366         }
 367         /* On non-aneg, we assume what we put in BMCR is the speed,
 368          * though magic-aneg shouldn't prevent this case from occurring
 369          */
 370
 371         return 0;
 372 }
 373
 374 static int marvell_init(struct ugeth_mii_info *mii_info)
 375 {
 376         ugphy_vdbg("%s: IN", __FUNCTION__);
 377
 378         ucc_geth_phy_write(mii_info, 0x14, 0x0cd2);
 379         ucc_geth_phy_write(mii_info, MII_BMCR,
 380                   ucc_geth_phy_read(mii_info, MII_BMCR) | BMCR_RESET);
 381         msleep(4000);
 382
 383         return 0;
 384 }
 385
 386 static int marvell_config_aneg(struct ugeth_mii_info *mii_info)
 387 {
 388         ugphy_vdbg("%s: IN", __FUNCTION__);
 389
 390         /* The Marvell PHY has an errata which requires
 391          * that certain registers get written in order
 392          * to restart autonegotiation */
 393         ucc_geth_phy_write(mii_info, MII_BMCR, BMCR_RESET);
 394
 395         ucc_geth_phy_write(mii_info, 0x1d, 0x1f);
 396         ucc_geth_phy_write(mii_info, 0x1e, 0x200c);
 397         ucc_geth_phy_write(mii_info, 0x1d, 0x5);
 398         ucc_geth_phy_write(mii_info, 0x1e, 0);
 399         ucc_geth_phy_write(mii_info, 0x1e, 0x100);
 400
 401         gbit_config_aneg(mii_info);
 402
 403         return 0;
 404 }
 405
 406 static int marvell_read_status(struct ugeth_mii_info *mii_info)
 407 {
 408         u16 status;
 409         int err;
 410
 411         ugphy_vdbg("%s: IN", __FUNCTION__);
 412
 413         /* Update the link, but return if there
 414          * was an error */
 415         err = genmii_update_link(mii_info);
 416         if (err)
 417                 return err;
 418
 419         /* If the link is up, read the speed and duplex */
 420         /* If we aren't autonegotiating, assume speeds
 421          * are as set */
 422         if (mii_info->autoneg && mii_info->link) {
 423                 int speed;
 424                 status = ucc_geth_phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
 425
 426                 /* Get the duplexity */
 427                 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
 428                         mii_info->duplex = DUPLEX_FULL;
 429                 else
 430                         mii_info->duplex = DUPLEX_HALF;
 431
 432                 /* Get the speed */
 433                 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
 434                 switch (speed) {
 435                 case MII_M1011_PHY_SPEC_STATUS_1000:
 436                         mii_info->speed = SPEED_1000;
 437                         break;
 438                 case MII_M1011_PHY_SPEC_STATUS_100:
 439                         mii_info->speed = SPEED_100;
 440                         break;
 441                 default:
 442                         mii_info->speed = SPEED_10;
 443                         break;
 444                 }
 445                 mii_info->pause = 0;
 446         }
 447
 448         return 0;
 449 }
 450
 451 static int marvell_ack_interrupt(struct ugeth_mii_info *mii_info)
 452 {
 453         ugphy_vdbg("%s: IN", __FUNCTION__);
 454
 455         /* Clear the interrupts by reading the reg */
 456         ucc_geth_phy_read(mii_info, MII_M1011_IEVENT);
 457
 458         return 0;
 459 }
 460
 461 static int marvell_config_intr(struct ugeth_mii_info *mii_info)
 462 {
 463         ugphy_vdbg("%s: IN", __FUNCTION__);
 464
 465         if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
 466                 ucc_geth_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
 467         else
 468                 ucc_geth_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
 469
 470         return 0;
 471 }
 472
 473 static int cis820x_init(struct ugeth_mii_info *mii_info)
 474 {
 475         ugphy_vdbg("%s: IN", __FUNCTION__);
 476
 477         ucc_geth_phy_write(mii_info, MII_CIS8201_AUX_CONSTAT,
 478                   MII_CIS8201_AUXCONSTAT_INIT);
 479         ucc_geth_phy_write(mii_info, MII_CIS8201_EXT_CON1, MII_CIS8201_EXTCON1_INIT);
 480
 481         return 0;
 482 }
 483
 484 static int cis820x_read_status(struct ugeth_mii_info *mii_info)
 485 {
 486         u16 status;
 487         int err;
 488
 489         ugphy_vdbg("%s: IN", __FUNCTION__);
 490
 491         /* Update the link, but return if there
 492          * was an error */
 493         err = genmii_update_link(mii_info);
 494         if (err)
 495                 return err;
 496
 497         /* If the link is up, read the speed and duplex */
 498         /* If we aren't autonegotiating, assume speeds
 499          * are as set */
 500         if (mii_info->autoneg && mii_info->link) {
 501                 int speed;
 502
 503                 status = ucc_geth_phy_read(mii_info, MII_CIS8201_AUX_CONSTAT);
 504                 if (status & MII_CIS8201_AUXCONSTAT_DUPLEX)
 505                         mii_info->duplex = DUPLEX_FULL;
 506                 else
 507                         mii_info->duplex = DUPLEX_HALF;
 508
 509                 speed = status & MII_CIS8201_AUXCONSTAT_SPEED;
 510
 511                 switch (speed) {
 512                 case MII_CIS8201_AUXCONSTAT_GBIT:
 513                         mii_info->speed = SPEED_1000;
 514                         break;
 515                 case MII_CIS8201_AUXCONSTAT_100:
 516                         mii_info->speed = SPEED_100;
 517                         break;
 518                 default:
 519                         mii_info->speed = SPEED_10;
 520                         break;
 521                 }
 522         }
 523
 524         return 0;
 525 }
 526
 527 static int cis820x_ack_interrupt(struct ugeth_mii_info *mii_info)
 528 {
 529         ugphy_vdbg("%s: IN", __FUNCTION__);
 530
 531         ucc_geth_phy_read(mii_info, MII_CIS8201_ISTAT);
 532
 533         return 0;
 534 }
 535
 536 static int cis820x_config_intr(struct ugeth_mii_info *mii_info)
 537 {
 538         ugphy_vdbg("%s: IN", __FUNCTION__);
 539
 540         if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
 541                 ucc_geth_phy_write(mii_info, MII_CIS8201_IMASK, MII_CIS8201_IMASK_MASK);
 542         else
 543                 ucc_geth_phy_write(mii_info, MII_CIS8201_IMASK, 0);
 544
 545         return 0;
 546 }
 547
 548 #define DM9161_DELAY 10
 549
 550 static int dm9161_read_status(struct ugeth_mii_info *mii_info)
 551 {
 552         u16 status;
 553         int err;
 554
 555         ugphy_vdbg("%s: IN", __FUNCTION__);
 556
 557         /* Update the link, but return if there
 558          * was an error */
 559         err = genmii_update_link(mii_info);
 560         if (err)
 561                 return err;
 562
 563         /* If the link is up, read the speed and duplex */
 564         /* If we aren't autonegotiating, assume speeds
 565          * are as set */
 566         if (mii_info->autoneg && mii_info->link) {
 567                 status = ucc_geth_phy_read(mii_info, MII_DM9161_SCSR);
 568                 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
 569                         mii_info->speed = SPEED_100;
 570                 else
 571                         mii_info->speed = SPEED_10;
 572
 573                 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
 574                         mii_info->duplex = DUPLEX_FULL;
 575                 else
 576                         mii_info->duplex = DUPLEX_HALF;
 577         }
 578
 579         return 0;
 580 }
 581
 582 static int dm9161_config_aneg(struct ugeth_mii_info *mii_info)
 583 {
 584         struct dm9161_private *priv = mii_info->priv;
 585
 586         ugphy_vdbg("%s: IN", __FUNCTION__);
 587
 588         if (0 == priv->resetdone)
 589                 return -EAGAIN;
 590
 591         return 0;
 592 }
 593
 594 static void dm9161_timer(unsigned long data)
 595 {
 596         struct ugeth_mii_info *mii_info = (struct ugeth_mii_info *)data;
 597         struct dm9161_private *priv = mii_info->priv;
 598         u16 status = ucc_geth_phy_read(mii_info, MII_BMSR);
 599
 600         ugphy_vdbg("%s: IN", __FUNCTION__);
 601
 602         if (status & BMSR_ANEGCOMPLETE) {
 603                 priv->resetdone = 1;
 604         } else
 605                 mod_timer(&priv->timer, jiffies + DM9161_DELAY * HZ);
 606 }
 607
 608 static int dm9161_init(struct ugeth_mii_info *mii_info)
 609 {
 610         struct dm9161_private *priv;
 611
 612         ugphy_vdbg("%s: IN", __FUNCTION__);
 613
 614         /* Allocate the private data structure */
 615         priv = kmalloc(sizeof(struct dm9161_private), GFP_KERNEL);
 616
 617         if (NULL == priv)
 618                 return -ENOMEM;
 619
 620         mii_info->priv = priv;
 621
 622         /* Reset is not done yet */
 623         priv->resetdone = 0;
 624
 625         ucc_geth_phy_write(mii_info, MII_BMCR,
 626                   ucc_geth_phy_read(mii_info, MII_BMCR) | BMCR_RESET);
 627
 628         ucc_geth_phy_write(mii_info, MII_BMCR,
 629                   ucc_geth_phy_read(mii_info, MII_BMCR) & ~BMCR_ISOLATE);
 630
 631         config_genmii_advert(mii_info);
 632         /* Start/Restart aneg */
 633         genmii_config_aneg(mii_info);
 634
 635         /* Start a timer for DM9161_DELAY seconds to wait
 636          * for the PHY to be ready */
 637         init_timer(&priv->timer);
 638         priv->timer.function = &dm9161_timer;
 639         priv->timer.data = (unsigned long)mii_info;
 640         mod_timer(&priv->timer, jiffies + DM9161_DELAY * HZ);
 641
 642         return 0;
 643 }
 644
 645 static void dm9161_close(struct ugeth_mii_info *mii_info)
 646 {
 647         struct dm9161_private *priv = mii_info->priv;
 648
 649         ugphy_vdbg("%s: IN", __FUNCTION__);
 650
 651         del_timer_sync(&priv->timer);
 652         kfree(priv);
 653 }
 654
 655 static int dm9161_ack_interrupt(struct ugeth_mii_info *mii_info)
 656 {
 657         ugphy_vdbg("%s: IN", __FUNCTION__);
 658
 659         /* Clear the interrupts by reading the reg */
 660         ucc_geth_phy_read(mii_info, MII_DM9161_INTR);
 661
 662
 663         return 0;
 664 }
 665
 666 static int dm9161_config_intr(struct ugeth_mii_info *mii_info)
 667 {
 668         ugphy_vdbg("%s: IN", __FUNCTION__);
 669
 670         if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
 671                 ucc_geth_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
 672         else
 673                 ucc_geth_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
 674
 675         return 0;
 676 }
 677
 678 /* Cicada 820x */
 679 static struct phy_info phy_info_cis820x = {
 680         .phy_id = 0x000fc440,
 681         .name = "Cicada Cis8204",
 682         .phy_id_mask = 0x000fffc0,
 683         .features = MII_GBIT_FEATURES,
 684         .init = &cis820x_init,
 685         .config_aneg = &gbit_config_aneg,
 686         .read_status = &cis820x_read_status,
 687         .ack_interrupt = &cis820x_ack_interrupt,
 688         .config_intr = &cis820x_config_intr,
 689 };
 690
 691 static struct phy_info phy_info_dm9161 = {
 692         .phy_id = 0x0181b880,
 693         .phy_id_mask = 0x0ffffff0,
 694         .name = "Davicom DM9161E",
 695         .init = dm9161_init,
 696         .config_aneg = dm9161_config_aneg,
 697         .read_status = dm9161_read_status,
 698         .close = dm9161_close,
 699 };
 700
 701 static struct phy_info phy_info_dm9161a = {
 702         .phy_id = 0x0181b8a0,
 703         .phy_id_mask = 0x0ffffff0,
 704         .name = "Davicom DM9161A",
 705         .features = MII_BASIC_FEATURES,
 706         .init = dm9161_init,
 707         .config_aneg = dm9161_config_aneg,
 708         .read_status = dm9161_read_status,
 709         .ack_interrupt = dm9161_ack_interrupt,
 710         .config_intr = dm9161_config_intr,
 711         .close = dm9161_close,
 712 };
 713
 714 static struct phy_info phy_info_marvell = {
 715         .phy_id = 0x01410c00,
 716         .phy_id_mask = 0xffffff00,
 717         .name = "Marvell 88E11x1",
 718         .features = MII_GBIT_FEATURES,
 719         .init = &marvell_init,
 720         .config_aneg = &marvell_config_aneg,
 721         .read_status = &marvell_read_status,
 722         .ack_interrupt = &marvell_ack_interrupt,
 723         .config_intr = &marvell_config_intr,
 724 };
 725
 726 static struct phy_info phy_info_genmii = {
 727         .phy_id = 0x00000000,
 728         .phy_id_mask = 0x00000000,
 729         .name = "Generic MII",
 730         .features = MII_BASIC_FEATURES,
 731         .config_aneg = genmii_config_aneg,
 732         .read_status = genmii_read_status,
 733 };
 734
 735 static struct phy_info *phy_info[] = {
 736         &phy_info_cis820x,
 737         &phy_info_marvell,
 738         &phy_info_dm9161,
 739         &phy_info_dm9161a,
 740         &phy_info_genmii,
 741         NULL
 742 };
 743
 744 /* Use the PHY ID registers to determine what type of PHY is attached
 745  * to device dev.  return a struct phy_info structure describing that PHY
 746  */
 747 struct phy_info *get_phy_info(struct ugeth_mii_info *mii_info)
 748 {
 749         u16 phy_reg;
 750         u32 phy_ID;
 751         int i;
 752         struct phy_info *theInfo = NULL;
 753         struct net_device *dev = mii_info->dev;
 754
 755         ugphy_vdbg("%s: IN", __FUNCTION__);
 756
 757         /* Grab the bits from PHYIR1, and put them in the upper half */
 758         phy_reg = ucc_geth_phy_read(mii_info, MII_PHYSID1);
 759         phy_ID = (phy_reg & 0xffff) << 16;
 760
 761         /* Grab the bits from PHYIR2, and put them in the lower half */
 762         phy_reg = ucc_geth_phy_read(mii_info, MII_PHYSID2);
 763         phy_ID |= (phy_reg & 0xffff);
 764
 765         /* loop through all the known PHY types, and find one that */
 766         /* matches the ID we read from the PHY. */
 767         for (i = 0; phy_info[i]; i++)
 768                 if (phy_info[i]->phy_id == (phy_ID & phy_info[i]->phy_id_mask)){
 769                         theInfo = phy_info[i];
 770                         break;
 771                 }
 772
 773         /* This shouldn't happen, as we have generic PHY support */
 774         if (theInfo == NULL) {
 775                 ugphy_info("%s: PHY id %x is not supported!", dev->name,
 776                            phy_ID);
 777                 return NULL;
 778         } else {
 779                 ugphy_info("%s: PHY is %s (%x)", dev->name, theInfo->name,
 780                            phy_ID);
 781         }
 782
 783         return theInfo;
 784 }