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Linux 2.6.20.7
[linux/fpc-iii.git] / drivers / net / wireless / zd1211rw / zd_chip.c
blob78ea72fb8f0ce9a3de74d6fd594442d90527ee4d
1 /* zd_chip.c
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16 */
17
18 /* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
25
26 #include "zd_def.h"
27 #include "zd_chip.h"
28 #include "zd_ieee80211.h"
29 #include "zd_mac.h"
30 #include "zd_rf.h"
31 #include "zd_util.h"
32
33 void zd_chip_init(struct zd_chip *chip,
34 struct net_device *netdev,
35 struct usb_interface *intf)
36 {
37 memset(chip, 0, sizeof(*chip));
38 mutex_init(&chip->mutex);
39 zd_usb_init(&chip->usb, netdev, intf);
40 zd_rf_init(&chip->rf);
41 }
42
43 void zd_chip_clear(struct zd_chip *chip)
44 {
45 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
46 zd_usb_clear(&chip->usb);
47 zd_rf_clear(&chip->rf);
48 mutex_destroy(&chip->mutex);
49 ZD_MEMCLEAR(chip, sizeof(*chip));
50 }
51
52 static int scnprint_mac_oui(const u8 *addr, char *buffer, size_t size)
53 {
54 return scnprintf(buffer, size, "%02x-%02x-%02x",
55 addr[0], addr[1], addr[2]);
56 }
57
58 /* Prints an identifier line, which will support debugging. */
59 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
60 {
61 int i = 0;
62
63 i = scnprintf(buffer, size, "zd1211%s chip ",
64 chip->is_zd1211b ? "b" : "");
65 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
66 i += scnprintf(buffer+i, size-i, " ");
67 i += scnprint_mac_oui(chip->e2p_mac, buffer+i, size-i);
68 i += scnprintf(buffer+i, size-i, " ");
69 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
70 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c", chip->pa_type,
71 chip->patch_cck_gain ? 'g' : '-',
72 chip->patch_cr157 ? '7' : '-',
73 chip->patch_6m_band_edge ? '6' : '-',
74 chip->new_phy_layout ? 'N' : '-');
75 return i;
76 }
77
78 static void print_id(struct zd_chip *chip)
79 {
80 char buffer[80];
81
82 scnprint_id(chip, buffer, sizeof(buffer));
83 buffer[sizeof(buffer)-1] = 0;
84 dev_info(zd_chip_dev(chip), "%s\n", buffer);
85 }
86
87 /* Read a variable number of 32-bit values. Parameter count is not allowed to
88 * exceed USB_MAX_IOREAD32_COUNT.
89 */
90 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
91 unsigned int count)
92 {
93 int r;
94 int i;
95 zd_addr_t *a16 = (zd_addr_t *)NULL;
96 u16 *v16;
97 unsigned int count16;
98
99 if (count > USB_MAX_IOREAD32_COUNT)
100 return -EINVAL;
101
102 /* Allocate a single memory block for values and addresses. */
103 count16 = 2*count;
104 a16 = kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
105 GFP_NOFS);
106 if (!a16) {
107 dev_dbg_f(zd_chip_dev(chip),
108 "error ENOMEM in allocation of a16\n");
109 r = -ENOMEM;
110 goto out;
111 }
112 v16 = (u16 *)(a16 + count16);
113
114 for (i = 0; i < count; i++) {
115 int j = 2*i;
116 /* We read the high word always first. */
117 a16[j] = zd_inc_word(addr[i]);
118 a16[j+1] = addr[i];
119 }
120
121 r = zd_ioread16v_locked(chip, v16, a16, count16);
122 if (r) {
123 dev_dbg_f(zd_chip_dev(chip),
124 "error: zd_ioread16v_locked. Error number %d\n", r);
125 goto out;
126 }
127
128 for (i = 0; i < count; i++) {
129 int j = 2*i;
130 values[i] = (v16[j] << 16) | v16[j+1];
131 }
132
133 out:
134 kfree((void *)a16);
135 return r;
136 }
137
138 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
139 unsigned int count)
140 {
141 int i, j, r;
142 struct zd_ioreq16 *ioreqs16;
143 unsigned int count16;
144
145 ZD_ASSERT(mutex_is_locked(&chip->mutex));
146
147 if (count == 0)
148 return 0;
149 if (count > USB_MAX_IOWRITE32_COUNT)
150 return -EINVAL;
151
152 /* Allocate a single memory block for values and addresses. */
153 count16 = 2*count;
154 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_NOFS);
155 if (!ioreqs16) {
156 r = -ENOMEM;
157 dev_dbg_f(zd_chip_dev(chip),
158 "error %d in ioreqs16 allocation\n", r);
159 goto out;
160 }
161
162 for (i = 0; i < count; i++) {
163 j = 2*i;
164 /* We write the high word always first. */
165 ioreqs16[j].value = ioreqs[i].value >> 16;
166 ioreqs16[j].addr = zd_inc_word(ioreqs[i].addr);
167 ioreqs16[j+1].value = ioreqs[i].value;
168 ioreqs16[j+1].addr = ioreqs[i].addr;
169 }
170
171 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
172 #ifdef DEBUG
173 if (r) {
174 dev_dbg_f(zd_chip_dev(chip),
175 "error %d in zd_usb_write16v\n", r);
176 }
177 #endif /* DEBUG */
178 out:
179 kfree(ioreqs16);
180 return r;
181 }
182
183 int zd_iowrite16a_locked(struct zd_chip *chip,
184 const struct zd_ioreq16 *ioreqs, unsigned int count)
185 {
186 int r;
187 unsigned int i, j, t, max;
188
189 ZD_ASSERT(mutex_is_locked(&chip->mutex));
190 for (i = 0; i < count; i += j + t) {
191 t = 0;
192 max = count-i;
193 if (max > USB_MAX_IOWRITE16_COUNT)
194 max = USB_MAX_IOWRITE16_COUNT;
195 for (j = 0; j < max; j++) {
196 if (!ioreqs[i+j].addr) {
197 t = 1;
198 break;
199 }
200 }
201
202 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
203 if (r) {
204 dev_dbg_f(zd_chip_dev(chip),
205 "error zd_usb_iowrite16v. Error number %d\n",
206 r);
207 return r;
208 }
209 }
210
211 return 0;
212 }
213
214 /* Writes a variable number of 32 bit registers. The functions will split
215 * that in several USB requests. A split can be forced by inserting an IO
216 * request with an zero address field.
217 */
218 int zd_iowrite32a_locked(struct zd_chip *chip,
219 const struct zd_ioreq32 *ioreqs, unsigned int count)
220 {
221 int r;
222 unsigned int i, j, t, max;
223
224 for (i = 0; i < count; i += j + t) {
225 t = 0;
226 max = count-i;
227 if (max > USB_MAX_IOWRITE32_COUNT)
228 max = USB_MAX_IOWRITE32_COUNT;
229 for (j = 0; j < max; j++) {
230 if (!ioreqs[i+j].addr) {
231 t = 1;
232 break;
233 }
234 }
235
236 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
237 if (r) {
238 dev_dbg_f(zd_chip_dev(chip),
239 "error _zd_iowrite32v_locked."
240 " Error number %d\n", r);
241 return r;
242 }
243 }
244
245 return 0;
246 }
247
248 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
249 {
250 int r;
251
252 mutex_lock(&chip->mutex);
253 r = zd_ioread16_locked(chip, value, addr);
254 mutex_unlock(&chip->mutex);
255 return r;
256 }
257
258 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
259 {
260 int r;
261
262 mutex_lock(&chip->mutex);
263 r = zd_ioread32_locked(chip, value, addr);
264 mutex_unlock(&chip->mutex);
265 return r;
266 }
267
268 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
269 {
270 int r;
271
272 mutex_lock(&chip->mutex);
273 r = zd_iowrite16_locked(chip, value, addr);
274 mutex_unlock(&chip->mutex);
275 return r;
276 }
277
278 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
279 {
280 int r;
281
282 mutex_lock(&chip->mutex);
283 r = zd_iowrite32_locked(chip, value, addr);
284 mutex_unlock(&chip->mutex);
285 return r;
286 }
287
288 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
289 u32 *values, unsigned int count)
290 {
291 int r;
292
293 mutex_lock(&chip->mutex);
294 r = zd_ioread32v_locked(chip, values, addresses, count);
295 mutex_unlock(&chip->mutex);
296 return r;
297 }
298
299 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
300 unsigned int count)
301 {
302 int r;
303
304 mutex_lock(&chip->mutex);
305 r = zd_iowrite32a_locked(chip, ioreqs, count);
306 mutex_unlock(&chip->mutex);
307 return r;
308 }
309
310 static int read_pod(struct zd_chip *chip, u8 *rf_type)
311 {
312 int r;
313 u32 value;
314
315 ZD_ASSERT(mutex_is_locked(&chip->mutex));
316 r = zd_ioread32_locked(chip, &value, E2P_POD);
317 if (r)
318 goto error;
319 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
320
321 /* FIXME: AL2230 handling (Bit 7 in POD) */
322 *rf_type = value & 0x0f;
323 chip->pa_type = (value >> 16) & 0x0f;
324 chip->patch_cck_gain = (value >> 8) & 0x1;
325 chip->patch_cr157 = (value >> 13) & 0x1;
326 chip->patch_6m_band_edge = (value >> 21) & 0x1;
327 chip->new_phy_layout = (value >> 31) & 0x1;
328 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
329 chip->supports_tx_led = 1;
330 if (value & (1 << 24)) { /* LED scenario */
331 if (value & (1 << 29))
332 chip->supports_tx_led = 0;
333 }
334
335 dev_dbg_f(zd_chip_dev(chip),
336 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
337 "patch 6M %d new PHY %d link LED%d tx led %d\n",
338 zd_rf_name(*rf_type), *rf_type,
339 chip->pa_type, chip->patch_cck_gain,
340 chip->patch_cr157, chip->patch_6m_band_edge,
341 chip->new_phy_layout,
342 chip->link_led == LED1 ? 1 : 2,
343 chip->supports_tx_led);
344 return 0;
345 error:
346 *rf_type = 0;
347 chip->pa_type = 0;
348 chip->patch_cck_gain = 0;
349 chip->patch_cr157 = 0;
350 chip->patch_6m_band_edge = 0;
351 chip->new_phy_layout = 0;
352 return r;
353 }
354
355 static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr,
356 const zd_addr_t *addr)
357 {
358 int r;
359 u32 parts[2];
360
361 r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2);
362 if (r) {
363 dev_dbg_f(zd_chip_dev(chip),
364 "error: couldn't read e2p macs. Error number %d\n", r);
365 return r;
366 }
367
368 mac_addr[0] = parts[0];
369 mac_addr[1] = parts[0] >> 8;
370 mac_addr[2] = parts[0] >> 16;
371 mac_addr[3] = parts[0] >> 24;
372 mac_addr[4] = parts[1];
373 mac_addr[5] = parts[1] >> 8;
374
375 return 0;
376 }
377
378 static int read_e2p_mac_addr(struct zd_chip *chip)
379 {
380 static const zd_addr_t addr[2] = { E2P_MAC_ADDR_P1, E2P_MAC_ADDR_P2 };
381
382 ZD_ASSERT(mutex_is_locked(&chip->mutex));
383 return _read_mac_addr(chip, chip->e2p_mac, (const zd_addr_t *)addr);
384 }
385
386 /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
387 * CR_MAC_ADDR_P2 must be overwritten
388 */
389 void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr)
390 {
391 mutex_lock(&chip->mutex);
392 memcpy(mac_addr, chip->e2p_mac, ETH_ALEN);
393 mutex_unlock(&chip->mutex);
394 }
395
396 static int read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
397 {
398 static const zd_addr_t addr[2] = { CR_MAC_ADDR_P1, CR_MAC_ADDR_P2 };
399 return _read_mac_addr(chip, mac_addr, (const zd_addr_t *)addr);
400 }
401
402 int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
403 {
404 int r;
405
406 dev_dbg_f(zd_chip_dev(chip), "\n");
407 mutex_lock(&chip->mutex);
408 r = read_mac_addr(chip, mac_addr);
409 mutex_unlock(&chip->mutex);
410 return r;
411 }
412
413 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
414 {
415 int r;
416 struct zd_ioreq32 reqs[2] = {
417 [0] = { .addr = CR_MAC_ADDR_P1 },
418 [1] = { .addr = CR_MAC_ADDR_P2 },
419 };
420
421 reqs[0].value = (mac_addr[3] << 24)
422 | (mac_addr[2] << 16)
423 | (mac_addr[1] << 8)
424 | mac_addr[0];
425 reqs[1].value = (mac_addr[5] << 8)
426 | mac_addr[4];
427
428 dev_dbg_f(zd_chip_dev(chip),
429 "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr));
430
431 mutex_lock(&chip->mutex);
432 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
433 #ifdef DEBUG
434 {
435 u8 tmp[ETH_ALEN];
436 read_mac_addr(chip, tmp);
437 }
438 #endif /* DEBUG */
439 mutex_unlock(&chip->mutex);
440 return r;
441 }
442
443 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
444 {
445 int r;
446 u32 value;
447
448 mutex_lock(&chip->mutex);
449 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
450 mutex_unlock(&chip->mutex);
451 if (r)
452 return r;
453
454 *regdomain = value >> 16;
455 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
456
457 return 0;
458 }
459
460 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
461 zd_addr_t e2p_addr, u32 guard)
462 {
463 int r;
464 int i;
465 u32 v;
466
467 ZD_ASSERT(mutex_is_locked(&chip->mutex));
468 for (i = 0;;) {
469 r = zd_ioread32_locked(chip, &v, e2p_addr+i/2);
470 if (r)
471 return r;
472 v -= guard;
473 if (i+4 < count) {
474 values[i++] = v;
475 values[i++] = v >> 8;
476 values[i++] = v >> 16;
477 values[i++] = v >> 24;
478 continue;
479 }
480 for (;i < count; i++)
481 values[i] = v >> (8*(i%3));
482 return 0;
483 }
484 }
485
486 static int read_pwr_cal_values(struct zd_chip *chip)
487 {
488 return read_values(chip, chip->pwr_cal_values,
489 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
490 0);
491 }
492
493 static int read_pwr_int_values(struct zd_chip *chip)
494 {
495 return read_values(chip, chip->pwr_int_values,
496 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
497 E2P_PWR_INT_GUARD);
498 }
499
500 static int read_ofdm_cal_values(struct zd_chip *chip)
501 {
502 int r;
503 int i;
504 static const zd_addr_t addresses[] = {
505 E2P_36M_CAL_VALUE1,
506 E2P_48M_CAL_VALUE1,
507 E2P_54M_CAL_VALUE1,
508 };
509
510 for (i = 0; i < 3; i++) {
511 r = read_values(chip, chip->ofdm_cal_values[i],
512 E2P_CHANNEL_COUNT, addresses[i], 0);
513 if (r)
514 return r;
515 }
516 return 0;
517 }
518
519 static int read_cal_int_tables(struct zd_chip *chip)
520 {
521 int r;
522
523 r = read_pwr_cal_values(chip);
524 if (r)
525 return r;
526 r = read_pwr_int_values(chip);
527 if (r)
528 return r;
529 r = read_ofdm_cal_values(chip);
530 if (r)
531 return r;
532 return 0;
533 }
534
535 /* phy means physical registers */
536 int zd_chip_lock_phy_regs(struct zd_chip *chip)
537 {
538 int r;
539 u32 tmp;
540
541 ZD_ASSERT(mutex_is_locked(&chip->mutex));
542 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
543 if (r) {
544 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
545 return r;
546 }
547
548 dev_dbg_f(zd_chip_dev(chip),
549 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS);
550 tmp &= ~UNLOCK_PHY_REGS;
551
552 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
553 if (r)
554 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
555 return r;
556 }
557
558 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
559 {
560 int r;
561 u32 tmp;
562
563 ZD_ASSERT(mutex_is_locked(&chip->mutex));
564 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
565 if (r) {
566 dev_err(zd_chip_dev(chip),
567 "error ioread32(CR_REG1): %d\n", r);
568 return r;
569 }
570
571 dev_dbg_f(zd_chip_dev(chip),
572 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS);
573 tmp |= UNLOCK_PHY_REGS;
574
575 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
576 if (r)
577 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
578 return r;
579 }
580
581 /* CR157 can be optionally patched by the EEPROM */
582 static int patch_cr157(struct zd_chip *chip)
583 {
584 int r;
585 u32 value;
586
587 if (!chip->patch_cr157)
588 return 0;
589
590 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
591 if (r)
592 return r;
593
594 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
595 return zd_iowrite32_locked(chip, value >> 8, CR157);
596 }
597
598 /*
599 * 6M band edge can be optionally overwritten for certain RF's
600 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
601 * bit (for AL2230, AL2230S)
602 */
603 static int patch_6m_band_edge(struct zd_chip *chip, int channel)
604 {
605 struct zd_ioreq16 ioreqs[] = {
606 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
607 { CR47, 0x1e },
608 };
609
610 if (!chip->patch_6m_band_edge || !chip->rf.patch_6m_band_edge)
611 return 0;
612
613 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
614 if (channel == 1 || channel == 11)
615 ioreqs[0].value = 0x12;
616
617 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
618 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
619 }
620
621 static int zd1211_hw_reset_phy(struct zd_chip *chip)
622 {
623 static const struct zd_ioreq16 ioreqs[] = {
624 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
625 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
626 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
627 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
628 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
629 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
630 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
631 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
632 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
633 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
634 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
635 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
636 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
637 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
638 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
639 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
640 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
641 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
642 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
643 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
644 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
645 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
646 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
647 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
648 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
649 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
650 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
651 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
652 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
653 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
654 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
655 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
656 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
657 { },
658 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
659 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
660 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
661 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
662 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
663 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
664 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
665 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
666 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
667 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
668 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
669 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
670 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
671 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
672 { CR123, 0x27 }, { CR125, 0xaa }, { CR127, 0x03 },
673 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
674 { CR131, 0x0C }, { CR136, 0xdf }, { CR137, 0x40 },
675 { CR138, 0xa0 }, { CR139, 0xb0 }, { CR140, 0x99 },
676 { CR141, 0x82 }, { CR142, 0x54 }, { CR143, 0x1c },
677 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x4c },
678 { CR149, 0x50 }, { CR150, 0x0e }, { CR151, 0x18 },
679 { CR160, 0xfe }, { CR161, 0xee }, { CR162, 0xaa },
680 { CR163, 0xfa }, { CR164, 0xfa }, { CR165, 0xea },
681 { CR166, 0xbe }, { CR167, 0xbe }, { CR168, 0x6a },
682 { CR169, 0xba }, { CR170, 0xba }, { CR171, 0xba },
683 /* Note: CR204 must lead the CR203 */
684 { CR204, 0x7d },
685 { },
686 { CR203, 0x30 },
687 };
688
689 int r, t;
690
691 dev_dbg_f(zd_chip_dev(chip), "\n");
692
693 r = zd_chip_lock_phy_regs(chip);
694 if (r)
695 goto out;
696
697 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
698 if (r)
699 goto unlock;
700
701 r = patch_cr157(chip);
702 unlock:
703 t = zd_chip_unlock_phy_regs(chip);
704 if (t && !r)
705 r = t;
706 out:
707 return r;
708 }
709
710 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
711 {
712 static const struct zd_ioreq16 ioreqs[] = {
713 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
714 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
715 { CR10, 0x81 },
716 /* power control { { CR11, 1 << 6 }, */
717 { CR11, 0x00 },
718 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
719 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
720 { CR18, 0x0a }, { CR19, 0x48 },
721 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
722 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
723 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
724 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
725 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
726 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
727 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
728 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
729 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
730 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
731 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
732 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
733 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
734 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
735 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
736 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
737 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
738 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
739 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
740 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
741 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
742 { CR94, 0x01 },
743 { CR95, 0x20 }, /* ZD1211B */
744 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
745 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
746 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
747 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
748 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
749 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
750 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
751 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
752 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
753 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
754 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
755 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
756 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
757 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
758 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
759 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
760 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
761 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
762 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
763 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
764 { CR170, 0xba }, { CR171, 0xba },
765 /* Note: CR204 must lead the CR203 */
766 { CR204, 0x7d },
767 {},
768 { CR203, 0x30 },
769 };
770
771 int r, t;
772
773 dev_dbg_f(zd_chip_dev(chip), "\n");
774
775 r = zd_chip_lock_phy_regs(chip);
776 if (r)
777 goto out;
778
779 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
780 if (r)
781 goto unlock;
782
783 r = patch_cr157(chip);
784 unlock:
785 t = zd_chip_unlock_phy_regs(chip);
786 if (t && !r)
787 r = t;
788 out:
789 return r;
790 }
791
792 static int hw_reset_phy(struct zd_chip *chip)
793 {
794 return chip->is_zd1211b ? zd1211b_hw_reset_phy(chip) :
795 zd1211_hw_reset_phy(chip);
796 }
797
798 static int zd1211_hw_init_hmac(struct zd_chip *chip)
799 {
800 static const struct zd_ioreq32 ioreqs[] = {
801 { CR_ACK_TIMEOUT_EXT, 0x20 },
802 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
803 { CR_ZD1211_RETRY_MAX, 0x2 },
804 { CR_SNIFFER_ON, 0 },
805 { CR_RX_FILTER, STA_RX_FILTER },
806 { CR_GROUP_HASH_P1, 0x00 },
807 { CR_GROUP_HASH_P2, 0x80000000 },
808 { CR_REG1, 0xa4 },
809 { CR_ADDA_PWR_DWN, 0x7f },
810 { CR_BCN_PLCP_CFG, 0x00f00401 },
811 { CR_PHY_DELAY, 0x00 },
812 { CR_ACK_TIMEOUT_EXT, 0x80 },
813 { CR_ADDA_PWR_DWN, 0x00 },
814 { CR_ACK_TIME_80211, 0x100 },
815 { CR_RX_PE_DELAY, 0x70 },
816 { CR_PS_CTRL, 0x10000000 },
817 { CR_RTS_CTS_RATE, 0x02030203 },
818 { CR_RX_THRESHOLD, 0x000c0640 },
819 { CR_AFTER_PNP, 0x1 },
820 { CR_WEP_PROTECT, 0x114 },
821 };
822
823 int r;
824
825 dev_dbg_f(zd_chip_dev(chip), "\n");
826 ZD_ASSERT(mutex_is_locked(&chip->mutex));
827 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
828 #ifdef DEBUG
829 if (r) {
830 dev_err(zd_chip_dev(chip),
831 "error in zd_iowrite32a_locked. Error number %d\n", r);
832 }
833 #endif /* DEBUG */
834 return r;
835 }
836
837 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
838 {
839 static const struct zd_ioreq32 ioreqs[] = {
840 { CR_ACK_TIMEOUT_EXT, 0x20 },
841 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
842 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
843 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
844 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
845 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
846 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
847 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
848 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
849 { CR_ZD1211B_TXOP, 0x01800824 },
850 { CR_SNIFFER_ON, 0 },
851 { CR_RX_FILTER, STA_RX_FILTER },
852 { CR_GROUP_HASH_P1, 0x00 },
853 { CR_GROUP_HASH_P2, 0x80000000 },
854 { CR_REG1, 0xa4 },
855 { CR_ADDA_PWR_DWN, 0x7f },
856 { CR_BCN_PLCP_CFG, 0x00f00401 },
857 { CR_PHY_DELAY, 0x00 },
858 { CR_ACK_TIMEOUT_EXT, 0x80 },
859 { CR_ADDA_PWR_DWN, 0x00 },
860 { CR_ACK_TIME_80211, 0x100 },
861 { CR_RX_PE_DELAY, 0x70 },
862 { CR_PS_CTRL, 0x10000000 },
863 { CR_RTS_CTS_RATE, 0x02030203 },
864 { CR_RX_THRESHOLD, 0x000c0eff, },
865 { CR_AFTER_PNP, 0x1 },
866 { CR_WEP_PROTECT, 0x114 },
867 };
868
869 int r;
870
871 dev_dbg_f(zd_chip_dev(chip), "\n");
872 ZD_ASSERT(mutex_is_locked(&chip->mutex));
873 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
874 if (r) {
875 dev_dbg_f(zd_chip_dev(chip),
876 "error in zd_iowrite32a_locked. Error number %d\n", r);
877 }
878 return r;
879 }
880
881 static int hw_init_hmac(struct zd_chip *chip)
882 {
883 return chip->is_zd1211b ?
884 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
885 }
886
887 struct aw_pt_bi {
888 u32 atim_wnd_period;
889 u32 pre_tbtt;
890 u32 beacon_interval;
891 };
892
893 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
894 {
895 int r;
896 static const zd_addr_t aw_pt_bi_addr[] =
897 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
898 u32 values[3];
899
900 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
901 ARRAY_SIZE(aw_pt_bi_addr));
902 if (r) {
903 memset(s, 0, sizeof(*s));
904 return r;
905 }
906
907 s->atim_wnd_period = values[0];
908 s->pre_tbtt = values[1];
909 s->beacon_interval = values[2];
910 dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n",
911 s->atim_wnd_period, s->pre_tbtt, s->beacon_interval);
912 return 0;
913 }
914
915 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
916 {
917 struct zd_ioreq32 reqs[3];
918
919 if (s->beacon_interval <= 5)
920 s->beacon_interval = 5;
921 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
922 s->pre_tbtt = s->beacon_interval - 1;
923 if (s->atim_wnd_period >= s->pre_tbtt)
924 s->atim_wnd_period = s->pre_tbtt - 1;
925
926 reqs[0].addr = CR_ATIM_WND_PERIOD;
927 reqs[0].value = s->atim_wnd_period;
928 reqs[1].addr = CR_PRE_TBTT;
929 reqs[1].value = s->pre_tbtt;
930 reqs[2].addr = CR_BCN_INTERVAL;
931 reqs[2].value = s->beacon_interval;
932
933 dev_dbg_f(zd_chip_dev(chip),
934 "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt,
935 s->beacon_interval);
936 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
937 }
938
939
940 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
941 {
942 int r;
943 struct aw_pt_bi s;
944
945 ZD_ASSERT(mutex_is_locked(&chip->mutex));
946 r = get_aw_pt_bi(chip, &s);
947 if (r)
948 return r;
949 s.beacon_interval = interval;
950 return set_aw_pt_bi(chip, &s);
951 }
952
953 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
954 {
955 int r;
956
957 mutex_lock(&chip->mutex);
958 r = set_beacon_interval(chip, interval);
959 mutex_unlock(&chip->mutex);
960 return r;
961 }
962
963 static int hw_init(struct zd_chip *chip)
964 {
965 int r;
966
967 dev_dbg_f(zd_chip_dev(chip), "\n");
968 ZD_ASSERT(mutex_is_locked(&chip->mutex));
969 r = hw_reset_phy(chip);
970 if (r)
971 return r;
972
973 r = hw_init_hmac(chip);
974 if (r)
975 return r;
976
977 /* Although the vendor driver defaults to a different value during
978 * init, it overwrites the IFS value with the following every time
979 * the channel changes. We should aim to be more intelligent... */
980 r = zd_iowrite32_locked(chip, IFS_VALUE_DEFAULT, CR_IFS_VALUE);
981 if (r)
982 return r;
983
984 return set_beacon_interval(chip, 100);
985 }
986
987 #ifdef DEBUG
988 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
989 const char *addr_string)
990 {
991 int r;
992 u32 value;
993
994 r = zd_ioread32_locked(chip, &value, addr);
995 if (r) {
996 dev_dbg_f(zd_chip_dev(chip),
997 "error reading %s. Error number %d\n", addr_string, r);
998 return r;
999 }
1000
1001 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
1002 addr_string, (unsigned int)value);
1003 return 0;
1004 }
1005
1006 static int test_init(struct zd_chip *chip)
1007 {
1008 int r;
1009
1010 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
1011 if (r)
1012 return r;
1013 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
1014 if (r)
1015 return r;
1016 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
1017 }
1018
1019 static void dump_fw_registers(struct zd_chip *chip)
1020 {
1021 static const zd_addr_t addr[4] = {
1022 FW_FIRMWARE_VER, FW_USB_SPEED, FW_FIX_TX_RATE,
1023 FW_LINK_STATUS
1024 };
1025
1026 int r;
1027 u16 values[4];
1028
1029 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
1030 ARRAY_SIZE(addr));
1031 if (r) {
1032 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
1033 r);
1034 return;
1035 }
1036
1037 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
1038 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
1039 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
1040 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
1041 }
1042 #endif /* DEBUG */
1043
1044 static int print_fw_version(struct zd_chip *chip)
1045 {
1046 int r;
1047 u16 version;
1048
1049 r = zd_ioread16_locked(chip, &version, FW_FIRMWARE_VER);
1050 if (r)
1051 return r;
1052
1053 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
1054 return 0;
1055 }
1056
1057 static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
1058 {
1059 u32 rates;
1060 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1061 /* This sets the mandatory rates, which only depend from the standard
1062 * that the device is supporting. Until further notice we should try
1063 * to support 802.11g also for full speed USB.
1064 */
1065 switch (std) {
1066 case IEEE80211B:
1067 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1068 break;
1069 case IEEE80211G:
1070 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1071 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1072 break;
1073 default:
1074 return -EINVAL;
1075 }
1076 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1077 }
1078
1079 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1080 u8 rts_rate, int preamble)
1081 {
1082 int rts_mod = ZD_RX_CCK;
1083 u32 value = 0;
1084
1085 /* Modulation bit */
1086 if (ZD_CS_TYPE(rts_rate) == ZD_CS_OFDM)
1087 rts_mod = ZD_RX_OFDM;
1088
1089 dev_dbg_f(zd_chip_dev(chip), "rts_rate=%x preamble=%x\n",
1090 rts_rate, preamble);
1091
1092 value |= rts_rate << RTSCTS_SH_RTS_RATE;
1093 value |= rts_mod << RTSCTS_SH_RTS_MOD_TYPE;
1094 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1095 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1096
1097 /* We always send 11M self-CTS messages, like the vendor driver. */
1098 value |= ZD_CCK_RATE_11M << RTSCTS_SH_CTS_RATE;
1099 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1100
1101 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1102 }
1103
1104 int zd_chip_enable_hwint(struct zd_chip *chip)
1105 {
1106 int r;
1107
1108 mutex_lock(&chip->mutex);
1109 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1110 mutex_unlock(&chip->mutex);
1111 return r;
1112 }
1113
1114 static int disable_hwint(struct zd_chip *chip)
1115 {
1116 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1117 }
1118
1119 int zd_chip_disable_hwint(struct zd_chip *chip)
1120 {
1121 int r;
1122
1123 mutex_lock(&chip->mutex);
1124 r = disable_hwint(chip);
1125 mutex_unlock(&chip->mutex);
1126 return r;
1127 }
1128
1129 int zd_chip_init_hw(struct zd_chip *chip, u8 device_type)
1130 {
1131 int r;
1132 u8 rf_type;
1133
1134 dev_dbg_f(zd_chip_dev(chip), "\n");
1135
1136 mutex_lock(&chip->mutex);
1137 chip->is_zd1211b = (device_type == DEVICE_ZD1211B) != 0;
1138
1139 #ifdef DEBUG
1140 r = test_init(chip);
1141 if (r)
1142 goto out;
1143 #endif
1144 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1145 if (r)
1146 goto out;
1147
1148 r = zd_usb_init_hw(&chip->usb);
1149 if (r)
1150 goto out;
1151
1152 /* GPI is always disabled, also in the other driver.
1153 */
1154 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1155 if (r)
1156 goto out;
1157 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1158 if (r)
1159 goto out;
1160 /* Currently we support IEEE 802.11g for full and high speed USB.
1161 * It might be discussed, whether we should suppport pure b mode for
1162 * full speed USB.
1163 */
1164 r = set_mandatory_rates(chip, IEEE80211G);
1165 if (r)
1166 goto out;
1167 /* Disabling interrupts is certainly a smart thing here.
1168 */
1169 r = disable_hwint(chip);
1170 if (r)
1171 goto out;
1172 r = read_pod(chip, &rf_type);
1173 if (r)
1174 goto out;
1175 r = hw_init(chip);
1176 if (r)
1177 goto out;
1178 r = zd_rf_init_hw(&chip->rf, rf_type);
1179 if (r)
1180 goto out;
1181
1182 r = print_fw_version(chip);
1183 if (r)
1184 goto out;
1185
1186 #ifdef DEBUG
1187 dump_fw_registers(chip);
1188 r = test_init(chip);
1189 if (r)
1190 goto out;
1191 #endif /* DEBUG */
1192
1193 r = read_e2p_mac_addr(chip);
1194 if (r)
1195 goto out;
1196
1197 r = read_cal_int_tables(chip);
1198 if (r)
1199 goto out;
1200
1201 print_id(chip);
1202 out:
1203 mutex_unlock(&chip->mutex);
1204 return r;
1205 }
1206
1207 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1208 {
1209 u8 value = chip->pwr_int_values[channel - 1];
1210 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n",
1211 channel, value);
1212 return zd_iowrite16_locked(chip, value, CR31);
1213 }
1214
1215 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1216 {
1217 u8 value = chip->pwr_cal_values[channel-1];
1218 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n",
1219 channel, value);
1220 return zd_iowrite16_locked(chip, value, CR68);
1221 }
1222
1223 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1224 {
1225 struct zd_ioreq16 ioreqs[3];
1226
1227 ioreqs[0].addr = CR67;
1228 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1229 ioreqs[1].addr = CR66;
1230 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1231 ioreqs[2].addr = CR65;
1232 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1233
1234 dev_dbg_f(zd_chip_dev(chip),
1235 "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n",
1236 channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value);
1237 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1238 }
1239
1240 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1241 u8 channel)
1242 {
1243 int r;
1244
1245 r = update_pwr_int(chip, channel);
1246 if (r)
1247 return r;
1248 if (chip->is_zd1211b) {
1249 static const struct zd_ioreq16 ioreqs[] = {
1250 { CR69, 0x28 },
1251 {},
1252 { CR69, 0x2a },
1253 };
1254
1255 r = update_ofdm_cal(chip, channel);
1256 if (r)
1257 return r;
1258 r = update_pwr_cal(chip, channel);
1259 if (r)
1260 return r;
1261 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1262 if (r)
1263 return r;
1264 }
1265
1266 return 0;
1267 }
1268
1269 /* The CCK baseband gain can be optionally patched by the EEPROM */
1270 static int patch_cck_gain(struct zd_chip *chip)
1271 {
1272 int r;
1273 u32 value;
1274
1275 if (!chip->patch_cck_gain)
1276 return 0;
1277
1278 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1279 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1280 if (r)
1281 return r;
1282 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1283 return zd_iowrite16_locked(chip, value & 0xff, CR47);
1284 }
1285
1286 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1287 {
1288 int r, t;
1289
1290 mutex_lock(&chip->mutex);
1291 r = zd_chip_lock_phy_regs(chip);
1292 if (r)
1293 goto out;
1294 r = zd_rf_set_channel(&chip->rf, channel);
1295 if (r)
1296 goto unlock;
1297 r = update_channel_integration_and_calibration(chip, channel);
1298 if (r)
1299 goto unlock;
1300 r = patch_cck_gain(chip);
1301 if (r)
1302 goto unlock;
1303 r = patch_6m_band_edge(chip, channel);
1304 if (r)
1305 goto unlock;
1306 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1307 unlock:
1308 t = zd_chip_unlock_phy_regs(chip);
1309 if (t && !r)
1310 r = t;
1311 out:
1312 mutex_unlock(&chip->mutex);
1313 return r;
1314 }
1315
1316 u8 zd_chip_get_channel(struct zd_chip *chip)
1317 {
1318 u8 channel;
1319
1320 mutex_lock(&chip->mutex);
1321 channel = chip->rf.channel;
1322 mutex_unlock(&chip->mutex);
1323 return channel;
1324 }
1325
1326 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1327 {
1328 static const zd_addr_t a[] = {
1329 FW_LINK_STATUS,
1330 CR_LED,
1331 };
1332
1333 int r;
1334 u16 v[ARRAY_SIZE(a)];
1335 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1336 [0] = { FW_LINK_STATUS },
1337 [1] = { CR_LED },
1338 };
1339 u16 other_led;
1340
1341 mutex_lock(&chip->mutex);
1342 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
1343 if (r)
1344 goto out;
1345
1346 other_led = chip->link_led == LED1 ? LED2 : LED1;
1347
1348 switch (status) {
1349 case LED_OFF:
1350 ioreqs[0].value = FW_LINK_OFF;
1351 ioreqs[1].value = v[1] & ~(LED1|LED2);
1352 break;
1353 case LED_SCANNING:
1354 ioreqs[0].value = FW_LINK_OFF;
1355 ioreqs[1].value = v[1] & ~other_led;
1356 if (get_seconds() % 3 == 0) {
1357 ioreqs[1].value &= ~chip->link_led;
1358 } else {
1359 ioreqs[1].value |= chip->link_led;
1360 }
1361 break;
1362 case LED_ASSOCIATED:
1363 ioreqs[0].value = FW_LINK_TX;
1364 ioreqs[1].value = v[1] & ~other_led;
1365 ioreqs[1].value |= chip->link_led;
1366 break;
1367 default:
1368 r = -EINVAL;
1369 goto out;
1370 }
1371
1372 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1373 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1374 if (r)
1375 goto out;
1376 }
1377 r = 0;
1378 out:
1379 mutex_unlock(&chip->mutex);
1380 return r;
1381 }
1382
1383 int zd_chip_set_basic_rates_locked(struct zd_chip *chip, u16 cr_rates)
1384 {
1385 ZD_ASSERT((cr_rates & ~(CR_RATES_80211B | CR_RATES_80211G)) == 0);
1386 dev_dbg_f(zd_chip_dev(chip), "%x\n", cr_rates);
1387
1388 return zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1389 }
1390
1391 static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size)
1392 {
1393 static const u16 constants[] = {
1394 715, 655, 585, 540, 470, 410, 360, 315,
1395 270, 235, 205, 175, 150, 125, 105, 85,
1396 65, 50, 40, 25, 15
1397 };
1398
1399 int i;
1400 u32 x;
1401
1402 /* It seems that their quality parameter is somehow per signal
1403 * and is now transferred per bit.
1404 */
1405 switch (rate) {
1406 case ZD_OFDM_RATE_6M:
1407 case ZD_OFDM_RATE_12M:
1408 case ZD_OFDM_RATE_24M:
1409 size *= 2;
1410 break;
1411 case ZD_OFDM_RATE_9M:
1412 case ZD_OFDM_RATE_18M:
1413 case ZD_OFDM_RATE_36M:
1414 case ZD_OFDM_RATE_54M:
1415 size *= 4;
1416 size /= 3;
1417 break;
1418 case ZD_OFDM_RATE_48M:
1419 size *= 3;
1420 size /= 2;
1421 break;
1422 default:
1423 return -EINVAL;
1424 }
1425
1426 x = (10000 * status_quality)/size;
1427 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1428 if (x > constants[i])
1429 break;
1430 }
1431
1432 switch (rate) {
1433 case ZD_OFDM_RATE_6M:
1434 case ZD_OFDM_RATE_9M:
1435 i += 3;
1436 break;
1437 case ZD_OFDM_RATE_12M:
1438 case ZD_OFDM_RATE_18M:
1439 i += 5;
1440 break;
1441 case ZD_OFDM_RATE_24M:
1442 case ZD_OFDM_RATE_36M:
1443 i += 9;
1444 break;
1445 case ZD_OFDM_RATE_48M:
1446 case ZD_OFDM_RATE_54M:
1447 i += 15;
1448 break;
1449 default:
1450 return -EINVAL;
1451 }
1452
1453 return i;
1454 }
1455
1456 static int ofdm_qual_percent(u8 status_quality, u8 rate, unsigned int size)
1457 {
1458 int r;
1459
1460 r = ofdm_qual_db(status_quality, rate, size);
1461 ZD_ASSERT(r >= 0);
1462 if (r < 0)
1463 r = 0;
1464
1465 r = (r * 100)/29;
1466 return r <= 100 ? r : 100;
1467 }
1468
1469 static unsigned int log10times100(unsigned int x)
1470 {
1471 static const u8 log10[] = {
1472 0,
1473 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1474 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1475 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1476 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1477 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1478 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1479 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1480 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1481 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1482 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1483 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1484 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1485 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1486 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1487 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1488 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1489 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1490 223, 223, 223, 224, 224, 224, 224,
1491 };
1492
1493 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1494 }
1495
1496 enum {
1497 MAX_CCK_EVM_DB = 45,
1498 };
1499
1500 static int cck_evm_db(u8 status_quality)
1501 {
1502 return (20 * log10times100(status_quality)) / 100;
1503 }
1504
1505 static int cck_snr_db(u8 status_quality)
1506 {
1507 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1508 ZD_ASSERT(r >= 0);
1509 return r;
1510 }
1511
1512 static int cck_qual_percent(u8 status_quality)
1513 {
1514 int r;
1515
1516 r = cck_snr_db(status_quality);
1517 r = (100*r)/17;
1518 return r <= 100 ? r : 100;
1519 }
1520
1521 u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1522 const struct rx_status *status)
1523 {
1524 return (status->frame_status&ZD_RX_OFDM) ?
1525 ofdm_qual_percent(status->signal_quality_ofdm,
1526 zd_ofdm_plcp_header_rate(rx_frame),
1527 size) :
1528 cck_qual_percent(status->signal_quality_cck);
1529 }
1530
1531 u8 zd_rx_strength_percent(u8 rssi)
1532 {
1533 int r = (rssi*100) / 41;
1534 if (r > 100)
1535 r = 100;
1536 return (u8) r;
1537 }
1538
1539 u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1540 {
1541 static const u16 ofdm_rates[] = {
1542 [ZD_OFDM_RATE_6M] = 60,
1543 [ZD_OFDM_RATE_9M] = 90,
1544 [ZD_OFDM_RATE_12M] = 120,
1545 [ZD_OFDM_RATE_18M] = 180,
1546 [ZD_OFDM_RATE_24M] = 240,
1547 [ZD_OFDM_RATE_36M] = 360,
1548 [ZD_OFDM_RATE_48M] = 480,
1549 [ZD_OFDM_RATE_54M] = 540,
1550 };
1551 u16 rate;
1552 if (status->frame_status & ZD_RX_OFDM) {
1553 u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame);
1554 rate = ofdm_rates[ofdm_rate & 0xf];
1555 } else {
1556 u8 cck_rate = zd_cck_plcp_header_rate(rx_frame);
1557 switch (cck_rate) {
1558 case ZD_CCK_SIGNAL_1M:
1559 rate = 10;
1560 break;
1561 case ZD_CCK_SIGNAL_2M:
1562 rate = 20;
1563 break;
1564 case ZD_CCK_SIGNAL_5M5:
1565 rate = 55;
1566 break;
1567 case ZD_CCK_SIGNAL_11M:
1568 rate = 110;
1569 break;
1570 default:
1571 rate = 0;
1572 }
1573 }
1574
1575 return rate;
1576 }
1577
1578 int zd_chip_switch_radio_on(struct zd_chip *chip)
1579 {
1580 int r;
1581
1582 mutex_lock(&chip->mutex);
1583 r = zd_switch_radio_on(&chip->rf);
1584 mutex_unlock(&chip->mutex);
1585 return r;
1586 }
1587
1588 int zd_chip_switch_radio_off(struct zd_chip *chip)
1589 {
1590 int r;
1591
1592 mutex_lock(&chip->mutex);
1593 r = zd_switch_radio_off(&chip->rf);
1594 mutex_unlock(&chip->mutex);
1595 return r;
1596 }
1597
1598 int zd_chip_enable_int(struct zd_chip *chip)
1599 {
1600 int r;
1601
1602 mutex_lock(&chip->mutex);
1603 r = zd_usb_enable_int(&chip->usb);
1604 mutex_unlock(&chip->mutex);
1605 return r;
1606 }
1607
1608 void zd_chip_disable_int(struct zd_chip *chip)
1609 {
1610 mutex_lock(&chip->mutex);
1611 zd_usb_disable_int(&chip->usb);
1612 mutex_unlock(&chip->mutex);
1613 }
1614
1615 int zd_chip_enable_rx(struct zd_chip *chip)
1616 {
1617 int r;
1618
1619 mutex_lock(&chip->mutex);
1620 r = zd_usb_enable_rx(&chip->usb);
1621 mutex_unlock(&chip->mutex);
1622 return r;
1623 }
1624
1625 void zd_chip_disable_rx(struct zd_chip *chip)
1626 {
1627 mutex_lock(&chip->mutex);
1628 zd_usb_disable_rx(&chip->usb);
1629 mutex_unlock(&chip->mutex);
1630 }
1631
1632 int zd_rfwritev_locked(struct zd_chip *chip,
1633 const u32* values, unsigned int count, u8 bits)
1634 {
1635 int r;
1636 unsigned int i;
1637
1638 for (i = 0; i < count; i++) {
1639 r = zd_rfwrite_locked(chip, values[i], bits);
1640 if (r)
1641 return r;
1642 }
1643
1644 return 0;
1645 }
1646
1647 /*
1648 * We can optionally program the RF directly through CR regs, if supported by
1649 * the hardware. This is much faster than the older method.
1650 */
1651 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1652 {
1653 struct zd_ioreq16 ioreqs[] = {
1654 { CR244, (value >> 16) & 0xff },
1655 { CR243, (value >> 8) & 0xff },
1656 { CR242, value & 0xff },
1657 };
1658 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1659 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1660 }
1661
1662 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1663 const u32 *values, unsigned int count)
1664 {
1665 int r;
1666 unsigned int i;
1667
1668 for (i = 0; i < count; i++) {
1669 r = zd_rfwrite_cr_locked(chip, values[i]);
1670 if (r)
1671 return r;
1672 }
1673
1674 return 0;
1675 }
1676
1677 int zd_chip_set_multicast_hash(struct zd_chip *chip,
1678 struct zd_mc_hash *hash)
1679 {
1680 struct zd_ioreq32 ioreqs[] = {
1681 { CR_GROUP_HASH_P1, hash->low },
1682 { CR_GROUP_HASH_P2, hash->high },
1683 };
1684
1685 dev_dbg_f(zd_chip_dev(chip), "hash l 0x%08x h 0x%08x\n",
1686 ioreqs[0].value, ioreqs[1].value);
1687 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1688 }
Linux with added FPC-III support