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Linux 2.6.20.7
[linux/fpc-iii.git] / drivers / sbus / char / bpp.c
blobac7d1258efee13610244b8e7a81feaf4a0348c7f
1 /*
2 * drivers/sbus/char/bpp.c
3 *
4 * Copyright (c) 1995 Picture Elements
5 * Stephen Williams (steve@icarus.com)
6 * Gus Baldauf (gbaldauf@ix.netcom.com)
7 *
8 * Linux/SPARC port by Peter Zaitcev.
9 * Integration into SPARC tree by Tom Dyas.
10 */
11
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/fs.h>
16 #include <linux/errno.h>
17 #include <linux/sched.h>
18 #include <linux/smp_lock.h>
19 #include <linux/spinlock.h>
20 #include <linux/timer.h>
21 #include <linux/ioport.h>
22 #include <linux/major.h>
23
24 #include <asm/uaccess.h>
25 #include <asm/io.h>
26
27 #if defined(__i386__)
28 # include <asm/system.h>
29 #endif
30
31 #if defined(__sparc__)
32 # include <linux/init.h>
33 # include <linux/delay.h> /* udelay() */
34
35 # include <asm/oplib.h> /* OpenProm Library */
36 # include <asm/sbus.h>
37 #endif
38
39 #include <asm/bpp.h>
40
41 #define BPP_PROBE_CODE 0x55
42 #define BPP_DELAY 100
43
44 static const unsigned BPP_MAJOR = LP_MAJOR;
45 static const char* dev_name = "bpp";
46
47 /* When switching from compatibility to a mode where I can read, try
48 the following mode first. */
49
50 /* const unsigned char DEFAULT_ECP = 0x10; */
51 static const unsigned char DEFAULT_ECP = 0x30;
52 static const unsigned char DEFAULT_NIBBLE = 0x00;
53
54 /*
55 * These are 1284 time constraints, in units of jiffies.
56 */
57
58 static const unsigned long TIME_PSetup = 1;
59 static const unsigned long TIME_PResponse = 6;
60 static const unsigned long TIME_IDLE_LIMIT = 2000;
61
62 /*
63 * One instance per supported subdevice...
64 */
65 # define BPP_NO 3
66
67 enum IEEE_Mode { COMPATIBILITY, NIBBLE, ECP, ECP_RLE, EPP };
68
69 struct inst {
70 unsigned present : 1; /* True if the hardware exists */
71 unsigned enhanced : 1; /* True if the hardware in "enhanced" */
72 unsigned opened : 1; /* True if the device is opened already */
73 unsigned run_flag : 1; /* True if waiting for a repeate byte */
74
75 unsigned char direction; /* 0 --> out, 0x20 --> IN */
76 unsigned char pp_state; /* State of host controlled pins. */
77 enum IEEE_Mode mode;
78
79 unsigned char run_length;
80 unsigned char repeat_byte;
81 };
82
83 static struct inst instances[BPP_NO];
84
85 #if defined(__i386__)
86
87 static const unsigned short base_addrs[BPP_NO] = { 0x278, 0x378, 0x3bc };
88
89 /*
90 * These are for data access.
91 * Control lines accesses are hidden in set_bits() and get_bits().
92 * The exception is the probe procedure, which is system-dependent.
93 */
94 #define bpp_outb_p(data, base) outb_p((data), (base))
95 #define bpp_inb(base) inb(base)
96 #define bpp_inb_p(base) inb_p(base)
97
98 /*
99 * This method takes the pin values mask and sets the hardware pins to
100 * the requested value: 1 == high voltage, 0 == low voltage. This
101 * burries the annoying PC bit inversion and preserves the direction
102 * flag.
103 */
104 static void set_pins(unsigned short pins, unsigned minor)
105 {
106 unsigned char bits = instances[minor].direction; /* == 0x20 */
107
108 if (! (pins & BPP_PP_nStrobe)) bits |= 1;
109 if (! (pins & BPP_PP_nAutoFd)) bits |= 2;
110 if ( pins & BPP_PP_nInit) bits |= 4;
111 if (! (pins & BPP_PP_nSelectIn)) bits |= 8;
112
113 instances[minor].pp_state = bits;
114
115 outb_p(bits, base_addrs[minor]+2);
116 }
117
118 static unsigned short get_pins(unsigned minor)
119 {
120 unsigned short bits = 0;
121
122 unsigned value = instances[minor].pp_state;
123 if (! (value & 0x01)) bits |= BPP_PP_nStrobe;
124 if (! (value & 0x02)) bits |= BPP_PP_nAutoFd;
125 if (value & 0x04) bits |= BPP_PP_nInit;
126 if (! (value & 0x08)) bits |= BPP_PP_nSelectIn;
127
128 value = inb_p(base_addrs[minor]+1);
129 if (value & 0x08) bits |= BPP_GP_nFault;
130 if (value & 0x10) bits |= BPP_GP_Select;
131 if (value & 0x20) bits |= BPP_GP_PError;
132 if (value & 0x40) bits |= BPP_GP_nAck;
133 if (! (value & 0x80)) bits |= BPP_GP_Busy;
134
135 return bits;
136 }
137
138 #endif /* __i386__ */
139
140 #if defined(__sparc__)
141
142 /*
143 * Register block
144 */
145 /* DMA registers */
146 #define BPP_CSR 0x00
147 #define BPP_ADDR 0x04
148 #define BPP_BCNT 0x08
149 #define BPP_TST_CSR 0x0C
150 /* Parallel Port registers */
151 #define BPP_HCR 0x10
152 #define BPP_OCR 0x12
153 #define BPP_DR 0x14
154 #define BPP_TCR 0x15
155 #define BPP_OR 0x16
156 #define BPP_IR 0x17
157 #define BPP_ICR 0x18
158 #define BPP_SIZE 0x1A
159
160 /* BPP_CSR. Bits of type RW1 are cleared with writting '1'. */
161 #define P_DEV_ID_MASK 0xf0000000 /* R */
162 #define P_DEV_ID_ZEBRA 0x40000000
163 #define P_DEV_ID_L64854 0xa0000000 /* == NCR 89C100+89C105. Pity. */
164 #define P_NA_LOADED 0x08000000 /* R NA wirtten but was not used */
165 #define P_A_LOADED 0x04000000 /* R */
166 #define P_DMA_ON 0x02000000 /* R DMA is not disabled */
167 #define P_EN_NEXT 0x01000000 /* RW */
168 #define P_TCI_DIS 0x00800000 /* RW TCI forbidden from interrupts */
169 #define P_DIAG 0x00100000 /* RW Disables draining and resetting
170 of P-FIFO on loading of P_ADDR*/
171 #define P_BURST_SIZE 0x000c0000 /* RW SBus burst size */
172 #define P_BURST_8 0x00000000
173 #define P_BURST_4 0x00040000
174 #define P_BURST_1 0x00080000 /* "No burst" write */
175 #define P_TC 0x00004000 /* RW1 Term Count, can be cleared when
176 P_EN_NEXT=1 */
177 #define P_EN_CNT 0x00002000 /* RW */
178 #define P_EN_DMA 0x00000200 /* RW */
179 #define P_WRITE 0x00000100 /* R DMA dir, 1=to ram, 0=to port */
180 #define P_RESET 0x00000080 /* RW */
181 #define P_SLAVE_ERR 0x00000040 /* RW1 Access size error */
182 #define P_INVALIDATE 0x00000020 /* W Drop P-FIFO */
183 #define P_INT_EN 0x00000010 /* RW OK to P_INT_PEND||P_ERR_PEND */
184 #define P_DRAINING 0x0000000c /* R P-FIFO is draining to memory */
185 #define P_ERR_PEND 0x00000002 /* R */
186 #define P_INT_PEND 0x00000001 /* R */
187
188 /* BPP_HCR. Time is in increments of SBus clock. */
189 #define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
190 #define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
191 #define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
192
193 /* BPP_OCR. */
194 #define P_OCR_MEM_CLR 0x8000
195 #define P_OCR_DATA_SRC 0x4000 /* ) */
196 #define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
197 #define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
198 #define P_OCR_ACK_DSEL 0x0800 /* ) */
199 #define P_OCR_EN_DIAG 0x0400
200 #define P_OCR_BUSY_OP 0x0200 /* Busy operation */
201 #define P_OCR_ACK_OP 0x0100 /* Ack operation */
202 #define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
203 #define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */
204 #define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
205 #define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
206
207 /* BPP_TCR */
208 #define P_TCR_DIR 0x08
209 #define P_TCR_BUSY 0x04
210 #define P_TCR_ACK 0x02
211 #define P_TCR_DS 0x01 /* Strobe */
212
213 /* BPP_OR */
214 #define P_OR_V3 0x20 /* ) */
215 #define P_OR_V2 0x10 /* ) on Zebra only */
216 #define P_OR_V1 0x08 /* ) */
217 #define P_OR_INIT 0x04
218 #define P_OR_AFXN 0x02 /* Auto Feed */
219 #define P_OR_SLCT_IN 0x01
220
221 /* BPP_IR */
222 #define P_IR_PE 0x04
223 #define P_IR_SLCT 0x02
224 #define P_IR_ERR 0x01
225
226 /* BPP_ICR */
227 #define P_DS_IRQ 0x8000 /* RW1 */
228 #define P_ACK_IRQ 0x4000 /* RW1 */
229 #define P_BUSY_IRQ 0x2000 /* RW1 */
230 #define P_PE_IRQ 0x1000 /* RW1 */
231 #define P_SLCT_IRQ 0x0800 /* RW1 */
232 #define P_ERR_IRQ 0x0400 /* RW1 */
233 #define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */
234 #define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */
235 #define P_BUSY_IRP 0x0080 /* RW 1= rising edge */
236 #define P_BUSY_IRQ_EN 0x0040 /* RW */
237 #define P_PE_IRP 0x0020 /* RW 1= rising edge */
238 #define P_PE_IRQ_EN 0x0010 /* RW */
239 #define P_SLCT_IRP 0x0008 /* RW 1= rising edge */
240 #define P_SLCT_IRQ_EN 0x0004 /* RW */
241 #define P_ERR_IRP 0x0002 /* RW1 1= rising edge */
242 #define P_ERR_IRQ_EN 0x0001 /* RW */
243
244 static void __iomem *base_addrs[BPP_NO];
245
246 #define bpp_outb_p(data, base) sbus_writeb(data, (base) + BPP_DR)
247 #define bpp_inb_p(base) sbus_readb((base) + BPP_DR)
248 #define bpp_inb(base) sbus_readb((base) + BPP_DR)
249
250 static void set_pins(unsigned short pins, unsigned minor)
251 {
252 void __iomem *base = base_addrs[minor];
253 unsigned char bits_tcr = 0, bits_or = 0;
254
255 if (instances[minor].direction & 0x20) bits_tcr |= P_TCR_DIR;
256 if ( pins & BPP_PP_nStrobe) bits_tcr |= P_TCR_DS;
257
258 if ( pins & BPP_PP_nAutoFd) bits_or |= P_OR_AFXN;
259 if (! (pins & BPP_PP_nInit)) bits_or |= P_OR_INIT;
260 if (! (pins & BPP_PP_nSelectIn)) bits_or |= P_OR_SLCT_IN;
261
262 sbus_writeb(bits_or, base + BPP_OR);
263 sbus_writeb(bits_tcr, base + BPP_TCR);
264 }
265
266 /*
267 * i386 people read output pins from a software image.
268 * We may get them back from hardware.
269 * Again, inversion of pins must he buried here.
270 */
271 static unsigned short get_pins(unsigned minor)
272 {
273 void __iomem *base = base_addrs[minor];
274 unsigned short bits = 0;
275 unsigned value_tcr = sbus_readb(base + BPP_TCR);
276 unsigned value_ir = sbus_readb(base + BPP_IR);
277 unsigned value_or = sbus_readb(base + BPP_OR);
278
279 if (value_tcr & P_TCR_DS) bits |= BPP_PP_nStrobe;
280 if (value_or & P_OR_AFXN) bits |= BPP_PP_nAutoFd;
281 if (! (value_or & P_OR_INIT)) bits |= BPP_PP_nInit;
282 if (! (value_or & P_OR_SLCT_IN)) bits |= BPP_PP_nSelectIn;
283
284 if (value_ir & P_IR_ERR) bits |= BPP_GP_nFault;
285 if (! (value_ir & P_IR_SLCT)) bits |= BPP_GP_Select;
286 if (! (value_ir & P_IR_PE)) bits |= BPP_GP_PError;
287 if (! (value_tcr & P_TCR_ACK)) bits |= BPP_GP_nAck;
288 if (value_tcr & P_TCR_BUSY) bits |= BPP_GP_Busy;
289
290 return bits;
291 }
292
293 #endif /* __sparc__ */
294
295 static void snooze(unsigned long snooze_time, unsigned minor)
296 {
297 schedule_timeout_uninterruptible(snooze_time + 1);
298 }
299
300 static int wait_for(unsigned short set, unsigned short clr,
301 unsigned long delay, unsigned minor)
302 {
303 unsigned short pins = get_pins(minor);
304
305 unsigned long extime = 0;
306
307 /*
308 * Try a real fast scan for the first jiffy, in case the device
309 * responds real good. The first while loop guesses an expire
310 * time accounting for possible wraparound of jiffies.
311 */
312 while (time_after_eq(jiffies, extime)) extime = jiffies + 1;
313 while ( (time_before(jiffies, extime))
314 && (((pins & set) != set) || ((pins & clr) != 0)) ) {
315 pins = get_pins(minor);
316 }
317
318 delay -= 1;
319
320 /*
321 * If my delay expired or the pins are still not where I want
322 * them, then resort to using the timer and greatly reduce my
323 * sample rate. If the peripheral is going to be slow, this will
324 * give the CPU up to some more worthy process.
325 */
326 while ( delay && (((pins & set) != set) || ((pins & clr) != 0)) ) {
327
328 snooze(1, minor);
329 pins = get_pins(minor);
330 delay -= 1;
331 }
332
333 if (delay == 0) return -1;
334 else return pins;
335 }
336
337 /*
338 * Return ZERO(0) If the negotiation succeeds, an errno otherwise. An
339 * errno means something broke, and I do not yet know how to fix it.
340 */
341 static int negotiate(unsigned char mode, unsigned minor)
342 {
343 int rc;
344 unsigned short pins = get_pins(minor);
345 if (pins & BPP_PP_nSelectIn) return -EIO;
346
347
348 /* Event 0: Write the mode to the data lines */
349 bpp_outb_p(mode, base_addrs[minor]);
350
351 snooze(TIME_PSetup, minor);
352
353 /* Event 1: Strobe the mode code into the peripheral */
354 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nInit, minor);
355
356 /* Wait for Event 2: Peripheral responds as a 1284 device. */
357 rc = wait_for(BPP_GP_PError|BPP_GP_Select|BPP_GP_nFault,
358 BPP_GP_nAck,
359 TIME_PResponse,
360 minor);
361
362 if (rc == -1) return -ETIMEDOUT;
363
364 /* Event 3: latch extensibility request */
365 set_pins(BPP_PP_nSelectIn|BPP_PP_nInit, minor);
366
367 /* ... quick nap while peripheral ponders the byte i'm sending...*/
368 snooze(1, minor);
369
370 /* Event 4: restore strobe, to ACK peripheral's response. */
371 set_pins(BPP_PP_nSelectIn|BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
372
373 /* Wait for Event 6: Peripheral latches response bits */
374 rc = wait_for(BPP_GP_nAck, 0, TIME_PSetup+TIME_PResponse, minor);
375 if (rc == -1) return -EIO;
376
377 /* A 1284 device cannot refuse nibble mode */
378 if (mode == DEFAULT_NIBBLE) return 0;
379
380 if (pins & BPP_GP_Select) return 0;
381
382 return -EPROTONOSUPPORT;
383 }
384
385 static int terminate(unsigned minor)
386 {
387 int rc;
388
389 /* Event 22: Request termination of 1284 mode */
390 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
391
392 /* Wait for Events 23 and 24: ACK termination request. */
393 rc = wait_for(BPP_GP_Busy|BPP_GP_nFault,
394 BPP_GP_nAck,
395 TIME_PSetup+TIME_PResponse,
396 minor);
397
398 instances[minor].direction = 0;
399 instances[minor].mode = COMPATIBILITY;
400
401 if (rc == -1) {
402 return -EIO;
403 }
404
405 /* Event 25: Handshake by lowering nAutoFd */
406 set_pins(BPP_PP_nStrobe|BPP_PP_nInit, minor);
407
408 /* Event 26: Peripheral wiggles lines... */
409
410 /* Event 27: Peripheral sets nAck HIGH to ack handshake */
411 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
412 if (rc == -1) {
413 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
414 return -EIO;
415 }
416
417 /* Event 28: Finish phase by raising nAutoFd */
418 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
419
420 return 0;
421 }
422
423 static DEFINE_SPINLOCK(bpp_open_lock);
424
425 /*
426 * Allow only one process to open the device at a time.
427 */
428 static int bpp_open(struct inode *inode, struct file *f)
429 {
430 unsigned minor = iminor(inode);
431 int ret;
432
433 spin_lock(&bpp_open_lock);
434 ret = 0;
435 if (minor >= BPP_NO) {
436 ret = -ENODEV;
437 } else {
438 if (! instances[minor].present) {
439 ret = -ENODEV;
440 } else {
441 if (instances[minor].opened)
442 ret = -EBUSY;
443 else
444 instances[minor].opened = 1;
445 }
446 }
447 spin_unlock(&bpp_open_lock);
448
449 return ret;
450 }
451
452 /*
453 * When the process closes the device, this method is called to clean
454 * up and reset the hardware. Always leave the device in compatibility
455 * mode as this is a reasonable place to clean up from messes made by
456 * ioctls, or other mayhem.
457 */
458 static int bpp_release(struct inode *inode, struct file *f)
459 {
460 unsigned minor = iminor(inode);
461
462 spin_lock(&bpp_open_lock);
463 instances[minor].opened = 0;
464
465 if (instances[minor].mode != COMPATIBILITY)
466 terminate(minor);
467
468 spin_unlock(&bpp_open_lock);
469
470 return 0;
471 }
472
473 static long read_nibble(unsigned minor, char __user *c, unsigned long cnt)
474 {
475 unsigned long remaining = cnt;
476 long rc;
477
478 while (remaining > 0) {
479 unsigned char byte = 0;
480 int pins;
481
482 /* Event 7: request nibble */
483 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
484
485 /* Wait for event 9: Peripher strobes first nibble */
486 pins = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
487 if (pins == -1) return -ETIMEDOUT;
488
489 /* Event 10: I handshake nibble */
490 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
491 if (pins & BPP_GP_nFault) byte |= 0x01;
492 if (pins & BPP_GP_Select) byte |= 0x02;
493 if (pins & BPP_GP_PError) byte |= 0x04;
494 if (pins & BPP_GP_Busy) byte |= 0x08;
495
496 /* Wait for event 11: Peripheral handshakes nibble */
497 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
498
499 /* Event 7: request nibble */
500 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
501
502 /* Wait for event 9: Peripher strobes first nibble */
503 pins = wait_for(0, BPP_GP_nAck, TIME_PResponse, minor);
504 if (rc == -1) return -ETIMEDOUT;
505
506 /* Event 10: I handshake nibble */
507 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
508 if (pins & BPP_GP_nFault) byte |= 0x10;
509 if (pins & BPP_GP_Select) byte |= 0x20;
510 if (pins & BPP_GP_PError) byte |= 0x40;
511 if (pins & BPP_GP_Busy) byte |= 0x80;
512
513 if (put_user(byte, c))
514 return -EFAULT;
515 c += 1;
516 remaining -= 1;
517
518 /* Wait for event 11: Peripheral handshakes nibble */
519 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
520 if (rc == -1) return -EIO;
521 }
522
523 return cnt - remaining;
524 }
525
526 static long read_ecp(unsigned minor, char __user *c, unsigned long cnt)
527 {
528 unsigned long remaining;
529 long rc;
530
531 /* Turn ECP mode from forward to reverse if needed. */
532 if (! instances[minor].direction) {
533 unsigned short pins = get_pins(minor);
534
535 /* Event 38: Turn the bus around */
536 instances[minor].direction = 0x20;
537 pins &= ~BPP_PP_nAutoFd;
538 set_pins(pins, minor);
539
540 /* Event 39: Set pins for reverse mode. */
541 snooze(TIME_PSetup, minor);
542 set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
543
544 /* Wait for event 40: Peripheral ready to be strobed */
545 rc = wait_for(0, BPP_GP_PError, TIME_PResponse, minor);
546 if (rc == -1) return -ETIMEDOUT;
547 }
548
549 remaining = cnt;
550
551 while (remaining > 0) {
552
553 /* If there is a run length for a repeated byte, repeat */
554 /* that byte a few times. */
555 if (instances[minor].run_length && !instances[minor].run_flag) {
556
557 char buffer[128];
558 unsigned idx;
559 unsigned repeat = remaining < instances[minor].run_length
560 ? remaining
561 : instances[minor].run_length;
562
563 for (idx = 0 ; idx < repeat ; idx += 1)
564 buffer[idx] = instances[minor].repeat_byte;
565
566 if (copy_to_user(c, buffer, repeat))
567 return -EFAULT;
568 remaining -= repeat;
569 c += repeat;
570 instances[minor].run_length -= repeat;
571 }
572
573 if (remaining == 0) break;
574
575
576 /* Wait for Event 43: Data active on the bus. */
577 rc = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
578 if (rc == -1) break;
579
580 if (rc & BPP_GP_Busy) {
581 /* OK, this is data. read it in. */
582 unsigned char byte = bpp_inb(base_addrs[minor]);
583 if (put_user(byte, c))
584 return -EFAULT;
585 c += 1;
586 remaining -= 1;
587
588 if (instances[minor].run_flag) {
589 instances[minor].repeat_byte = byte;
590 instances[minor].run_flag = 0;
591 }
592
593 } else {
594 unsigned char byte = bpp_inb(base_addrs[minor]);
595 if (byte & 0x80) {
596 printk("bpp%d: "
597 "Ignoring ECP channel %u from device.\n",
598 minor, byte & 0x7f);
599 } else {
600 instances[minor].run_length = byte;
601 instances[minor].run_flag = 1;
602 }
603 }
604
605 /* Event 44: I got it. */
606 set_pins(BPP_PP_nStrobe|BPP_PP_nAutoFd|BPP_PP_nSelectIn, minor);
607
608 /* Wait for event 45: peripheral handshake */
609 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
610 if (rc == -1) return -ETIMEDOUT;
611
612 /* Event 46: Finish handshake */
613 set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
614
615 }
616
617
618 return cnt - remaining;
619 }
620
621 static ssize_t bpp_read(struct file *f, char __user *c, size_t cnt, loff_t * ppos)
622 {
623 long rc;
624 unsigned minor = iminor(f->f_path.dentry->d_inode);
625 if (minor >= BPP_NO) return -ENODEV;
626 if (!instances[minor].present) return -ENODEV;
627
628 switch (instances[minor].mode) {
629
630 default:
631 if (instances[minor].mode != COMPATIBILITY)
632 terminate(minor);
633
634 if (instances[minor].enhanced) {
635 /* For now, do all reads with ECP-RLE mode */
636 unsigned short pins;
637
638 rc = negotiate(DEFAULT_ECP, minor);
639 if (rc < 0) break;
640
641 instances[minor].mode = ECP_RLE;
642
643 /* Event 30: set nAutoFd low to setup for ECP mode */
644 pins = get_pins(minor);
645 pins &= ~BPP_PP_nAutoFd;
646 set_pins(pins, minor);
647
648 /* Wait for Event 31: peripheral ready */
649 rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
650 if (rc == -1) return -ETIMEDOUT;
651
652 rc = read_ecp(minor, c, cnt);
653
654 } else {
655 rc = negotiate(DEFAULT_NIBBLE, minor);
656 if (rc < 0) break;
657
658 instances[minor].mode = NIBBLE;
659
660 rc = read_nibble(minor, c, cnt);
661 }
662 break;
663
664 case NIBBLE:
665 rc = read_nibble(minor, c, cnt);
666 break;
667
668 case ECP:
669 case ECP_RLE:
670 rc = read_ecp(minor, c, cnt);
671 break;
672
673 }
674
675
676 return rc;
677 }
678
679 /*
680 * Compatibility mode handshaking is a matter of writing data,
681 * strobing it, and waiting for the printer to stop being busy.
682 */
683 static long write_compat(unsigned minor, const char __user *c, unsigned long cnt)
684 {
685 long rc;
686 unsigned short pins = get_pins(minor);
687
688 unsigned long remaining = cnt;
689
690
691 while (remaining > 0) {
692 unsigned char byte;
693
694 if (get_user(byte, c))
695 return -EFAULT;
696 c += 1;
697
698 rc = wait_for(BPP_GP_nAck, BPP_GP_Busy, TIME_IDLE_LIMIT, minor);
699 if (rc == -1) return -ETIMEDOUT;
700
701 bpp_outb_p(byte, base_addrs[minor]);
702 remaining -= 1;
703 /* snooze(1, minor); */
704
705 pins &= ~BPP_PP_nStrobe;
706 set_pins(pins, minor);
707
708 rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
709
710 pins |= BPP_PP_nStrobe;
711 set_pins(pins, minor);
712 }
713
714 return cnt - remaining;
715 }
716
717 /*
718 * Write data using ECP mode. Watch out that the port may be set up
719 * for reading. If so, turn the port around.
720 */
721 static long write_ecp(unsigned minor, const char __user *c, unsigned long cnt)
722 {
723 unsigned short pins = get_pins(minor);
724 unsigned long remaining = cnt;
725
726 if (instances[minor].direction) {
727 int rc;
728
729 /* Event 47 Request bus be turned around */
730 pins |= BPP_PP_nInit;
731 set_pins(pins, minor);
732
733 /* Wait for Event 49: Peripheral relinquished bus */
734 rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
735
736 pins |= BPP_PP_nAutoFd;
737 instances[minor].direction = 0;
738 set_pins(pins, minor);
739 }
740
741 while (remaining > 0) {
742 unsigned char byte;
743 int rc;
744
745 if (get_user(byte, c))
746 return -EFAULT;
747
748 rc = wait_for(0, BPP_GP_Busy, TIME_PResponse, minor);
749 if (rc == -1) return -ETIMEDOUT;
750
751 c += 1;
752
753 bpp_outb_p(byte, base_addrs[minor]);
754
755 pins &= ~BPP_PP_nStrobe;
756 set_pins(pins, minor);
757
758 pins |= BPP_PP_nStrobe;
759 rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
760 if (rc == -1) return -EIO;
761
762 set_pins(pins, minor);
763 }
764
765 return cnt - remaining;
766 }
767
768 /*
769 * Write to the peripheral. Be sensitive of the current mode. If I'm
770 * in a mode that can be turned around (ECP) then just do
771 * that. Otherwise, terminate and do my writing in compat mode. This
772 * is the safest course as any device can handle it.
773 */
774 static ssize_t bpp_write(struct file *f, const char __user *c, size_t cnt, loff_t * ppos)
775 {
776 long errno = 0;
777 unsigned minor = iminor(f->f_path.dentry->d_inode);
778 if (minor >= BPP_NO) return -ENODEV;
779 if (!instances[minor].present) return -ENODEV;
780
781 switch (instances[minor].mode) {
782
783 case ECP:
784 case ECP_RLE:
785 errno = write_ecp(minor, c, cnt);
786 break;
787 case COMPATIBILITY:
788 errno = write_compat(minor, c, cnt);
789 break;
790 default:
791 terminate(minor);
792 errno = write_compat(minor, c, cnt);
793 }
794
795 return errno;
796 }
797
798 static int bpp_ioctl(struct inode *inode, struct file *f, unsigned int cmd,
799 unsigned long arg)
800 {
801 int errno = 0;
802
803 unsigned minor = iminor(inode);
804 if (minor >= BPP_NO) return -ENODEV;
805 if (!instances[minor].present) return -ENODEV;
806
807
808 switch (cmd) {
809
810 case BPP_PUT_PINS:
811 set_pins(arg, minor);
812 break;
813
814 case BPP_GET_PINS:
815 errno = get_pins(minor);
816 break;
817
818 case BPP_PUT_DATA:
819 bpp_outb_p(arg, base_addrs[minor]);
820 break;
821
822 case BPP_GET_DATA:
823 errno = bpp_inb_p(base_addrs[minor]);
824 break;
825
826 case BPP_SET_INPUT:
827 if (arg)
828 if (instances[minor].enhanced) {
829 unsigned short bits = get_pins(minor);
830 instances[minor].direction = 0x20;
831 set_pins(bits, minor);
832 } else {
833 errno = -ENOTTY;
834 }
835 else {
836 unsigned short bits = get_pins(minor);
837 instances[minor].direction = 0x00;
838 set_pins(bits, minor);
839 }
840 break;
841
842 default:
843 errno = -EINVAL;
844 }
845
846 return errno;
847 }
848
849 static struct file_operations bpp_fops = {
850 .owner = THIS_MODULE,
851 .read = bpp_read,
852 .write = bpp_write,
853 .ioctl = bpp_ioctl,
854 .open = bpp_open,
855 .release = bpp_release,
856 };
857
858 #if defined(__i386__)
859
860 #define collectLptPorts() {}
861
862 static void probeLptPort(unsigned idx)
863 {
864 unsigned int testvalue;
865 const unsigned short lpAddr = base_addrs[idx];
866
867 instances[idx].present = 0;
868 instances[idx].enhanced = 0;
869 instances[idx].direction = 0;
870 instances[idx].mode = COMPATIBILITY;
871 instances[idx].run_length = 0;
872 instances[idx].run_flag = 0;
873 if (!request_region(lpAddr,3, dev_name)) return;
874
875 /*
876 * First, make sure the instance exists. Do this by writing to
877 * the data latch and reading the value back. If the port *is*
878 * present, test to see if it supports extended-mode
879 * operation. This will be required for IEEE1284 reverse
880 * transfers.
881 */
882
883 outb_p(BPP_PROBE_CODE, lpAddr);
884 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
885 ;
886 testvalue = inb_p(lpAddr);
887 if (testvalue == BPP_PROBE_CODE) {
888 unsigned save;
889 instances[idx].present = 1;
890
891 save = inb_p(lpAddr+2);
892 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
893 ;
894 outb_p(save|0x20, lpAddr+2);
895 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
896 ;
897 outb_p(~BPP_PROBE_CODE, lpAddr);
898 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
899 ;
900 testvalue = inb_p(lpAddr);
901 if ((testvalue&0xff) == (0xff&~BPP_PROBE_CODE))
902 instances[idx].enhanced = 0;
903 else
904 instances[idx].enhanced = 1;
905 outb_p(save, lpAddr+2);
906 }
907 else {
908 release_region(lpAddr,3);
909 }
910 /*
911 * Leave the port in compat idle mode.
912 */
913 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
914
915 printk("bpp%d: Port at 0x%03x: Enhanced mode %s\n", idx, base_addrs[idx],
916 instances[idx].enhanced? "SUPPORTED" : "UNAVAILABLE");
917 }
918
919 static inline void freeLptPort(int idx)
920 {
921 release_region(base_addrs[idx], 3);
922 }
923
924 #endif
925
926 #if defined(__sparc__)
927
928 static void __iomem *map_bpp(struct sbus_dev *dev, int idx)
929 {
930 return sbus_ioremap(&dev->resource[0], 0, BPP_SIZE, "bpp");
931 }
932
933 static int collectLptPorts(void)
934 {
935 struct sbus_bus *bus;
936 struct sbus_dev *dev;
937 int count;
938
939 count = 0;
940 for_all_sbusdev(dev, bus) {
941 if (strcmp(dev->prom_name, "SUNW,bpp") == 0) {
942 if (count >= BPP_NO) {
943 printk(KERN_NOTICE
944 "bpp: More than %d bpp ports,"
945 " rest is ignored\n", BPP_NO);
946 return count;
947 }
948 base_addrs[count] = map_bpp(dev, count);
949 count++;
950 }
951 }
952 return count;
953 }
954
955 static void probeLptPort(unsigned idx)
956 {
957 void __iomem *rp = base_addrs[idx];
958 __u32 csr;
959 char *brand;
960
961 instances[idx].present = 0;
962 instances[idx].enhanced = 0;
963 instances[idx].direction = 0;
964 instances[idx].mode = COMPATIBILITY;
965 instances[idx].run_length = 0;
966 instances[idx].run_flag = 0;
967
968 if (!rp) return;
969
970 instances[idx].present = 1;
971 instances[idx].enhanced = 1; /* Sure */
972
973 csr = sbus_readl(rp + BPP_CSR);
974 if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
975 udelay(20);
976 csr = sbus_readl(rp + BPP_CSR);
977 if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
978 printk("bpp%d: DRAINING still active (0x%08x)\n", idx, csr);
979 }
980 }
981 printk("bpp%d: reset with 0x%08x ..", idx, csr);
982 sbus_writel((csr | P_RESET) & ~P_INT_EN, rp + BPP_CSR);
983 udelay(500);
984 sbus_writel(sbus_readl(rp + BPP_CSR) & ~P_RESET, rp + BPP_CSR);
985 csr = sbus_readl(rp + BPP_CSR);
986 printk(" done with csr=0x%08x ocr=0x%04x\n",
987 csr, sbus_readw(rp + BPP_OCR));
988
989 switch (csr & P_DEV_ID_MASK) {
990 case P_DEV_ID_ZEBRA:
991 brand = "Zebra";
992 break;
993 case P_DEV_ID_L64854:
994 brand = "DMA2";
995 break;
996 default:
997 brand = "Unknown";
998 }
999 printk("bpp%d: %s at %p\n", idx, brand, rp);
1000
1001 /*
1002 * Leave the port in compat idle mode.
1003 */
1004 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
1005
1006 return;
1007 }
1008
1009 static inline void freeLptPort(int idx)
1010 {
1011 sbus_iounmap(base_addrs[idx], BPP_SIZE);
1012 }
1013
1014 #endif
1015
1016 static int __init bpp_init(void)
1017 {
1018 int rc;
1019 unsigned idx;
1020
1021 rc = collectLptPorts();
1022 if (rc == 0)
1023 return -ENODEV;
1024
1025 rc = register_chrdev(BPP_MAJOR, dev_name, &bpp_fops);
1026 if (rc < 0)
1027 return rc;
1028
1029 for (idx = 0; idx < BPP_NO; idx++) {
1030 instances[idx].opened = 0;
1031 probeLptPort(idx);
1032 }
1033
1034 return 0;
1035 }
1036
1037 static void __exit bpp_cleanup(void)
1038 {
1039 unsigned idx;
1040
1041 unregister_chrdev(BPP_MAJOR, dev_name);
1042
1043 for (idx = 0; idx < BPP_NO; idx++) {
1044 if (instances[idx].present)
1045 freeLptPort(idx);
1046 }
1047 }
1048
1049 module_init(bpp_init);
1050 module_exit(bpp_cleanup);
1051
1052 MODULE_LICENSE("GPL");
1053
Linux with added FPC-III support