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Linux 2.6.20.7
[linux/fpc-iii.git] / drivers / serial / 8250_pci.c
blob52e2e64c6649dc25379994f6b1b119bc2d3b768f
1 /*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/tty.h>
25 #include <linux/serial_core.h>
26 #include <linux/8250_pci.h>
27 #include <linux/bitops.h>
28
29 #include <asm/byteorder.h>
30 #include <asm/io.h>
31
32 #include "8250.h"
33
34 #undef SERIAL_DEBUG_PCI
35
36 /*
37 * init function returns:
38 * > 0 - number of ports
39 * = 0 - use board->num_ports
40 * < 0 - error
41 */
42 struct pci_serial_quirk {
43 u32 vendor;
44 u32 device;
45 u32 subvendor;
46 u32 subdevice;
47 int (*init)(struct pci_dev *dev);
48 int (*setup)(struct serial_private *, struct pciserial_board *,
49 struct uart_port *, int);
50 void (*exit)(struct pci_dev *dev);
51 };
52
53 #define PCI_NUM_BAR_RESOURCES 6
54
55 struct serial_private {
56 struct pci_dev *dev;
57 unsigned int nr;
58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
59 struct pci_serial_quirk *quirk;
60 int line[0];
61 };
62
63 static void moan_device(const char *str, struct pci_dev *dev)
64 {
65 printk(KERN_WARNING "%s: %s\n"
66 KERN_WARNING "Please send the output of lspci -vv, this\n"
67 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 KERN_WARNING "manufacturer and name of serial board or\n"
69 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
72 }
73
74 static int
75 setup_port(struct serial_private *priv, struct uart_port *port,
76 int bar, int offset, int regshift)
77 {
78 struct pci_dev *dev = priv->dev;
79 unsigned long base, len;
80
81 if (bar >= PCI_NUM_BAR_RESOURCES)
82 return -EINVAL;
83
84 base = pci_resource_start(dev, bar);
85
86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
87 len = pci_resource_len(dev, bar);
88
89 if (!priv->remapped_bar[bar])
90 priv->remapped_bar[bar] = ioremap(base, len);
91 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
94 port->iotype = UPIO_MEM;
95 port->iobase = 0;
96 port->mapbase = base + offset;
97 port->membase = priv->remapped_bar[bar] + offset;
98 port->regshift = regshift;
99 } else {
100 port->iotype = UPIO_PORT;
101 port->iobase = base + offset;
102 port->mapbase = 0;
103 port->membase = NULL;
104 port->regshift = 0;
105 }
106 return 0;
107 }
108
109 /*
110 * AFAVLAB uses a different mixture of BARs and offsets
111 * Not that ugly ;) -- HW
112 */
113 static int
114 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
115 struct uart_port *port, int idx)
116 {
117 unsigned int bar, offset = board->first_offset;
118
119 bar = FL_GET_BASE(board->flags);
120 if (idx < 4)
121 bar += idx;
122 else {
123 bar = 4;
124 offset += (idx - 4) * board->uart_offset;
125 }
126
127 return setup_port(priv, port, bar, offset, board->reg_shift);
128 }
129
130 /*
131 * HP's Remote Management Console. The Diva chip came in several
132 * different versions. N-class, L2000 and A500 have two Diva chips, each
133 * with 3 UARTs (the third UART on the second chip is unused). Superdome
134 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
135 * one Diva chip, but it has been expanded to 5 UARTs.
136 */
137 static int pci_hp_diva_init(struct pci_dev *dev)
138 {
139 int rc = 0;
140
141 switch (dev->subsystem_device) {
142 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
143 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
144 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
145 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
146 rc = 3;
147 break;
148 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
149 rc = 2;
150 break;
151 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
152 rc = 4;
153 break;
154 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
155 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
156 rc = 1;
157 break;
158 }
159
160 return rc;
161 }
162
163 /*
164 * HP's Diva chip puts the 4th/5th serial port further out, and
165 * some serial ports are supposed to be hidden on certain models.
166 */
167 static int
168 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
169 struct uart_port *port, int idx)
170 {
171 unsigned int offset = board->first_offset;
172 unsigned int bar = FL_GET_BASE(board->flags);
173
174 switch (priv->dev->subsystem_device) {
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
176 if (idx == 3)
177 idx++;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
180 if (idx > 0)
181 idx++;
182 if (idx > 2)
183 idx++;
184 break;
185 }
186 if (idx > 2)
187 offset = 0x18;
188
189 offset += idx * board->uart_offset;
190
191 return setup_port(priv, port, bar, offset, board->reg_shift);
192 }
193
194 /*
195 * Added for EKF Intel i960 serial boards
196 */
197 static int pci_inteli960ni_init(struct pci_dev *dev)
198 {
199 unsigned long oldval;
200
201 if (!(dev->subsystem_device & 0x1000))
202 return -ENODEV;
203
204 /* is firmware started? */
205 pci_read_config_dword(dev, 0x44, (void*) &oldval);
206 if (oldval == 0x00001000L) { /* RESET value */
207 printk(KERN_DEBUG "Local i960 firmware missing");
208 return -ENODEV;
209 }
210 return 0;
211 }
212
213 /*
214 * Some PCI serial cards using the PLX 9050 PCI interface chip require
215 * that the card interrupt be explicitly enabled or disabled. This
216 * seems to be mainly needed on card using the PLX which also use I/O
217 * mapped memory.
218 */
219 static int pci_plx9050_init(struct pci_dev *dev)
220 {
221 u8 irq_config;
222 void __iomem *p;
223
224 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
225 moan_device("no memory in bar 0", dev);
226 return 0;
227 }
228
229 irq_config = 0x41;
230 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
231 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
232 irq_config = 0x43;
233 }
234 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
235 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
236 /*
237 * As the megawolf cards have the int pins active
238 * high, and have 2 UART chips, both ints must be
239 * enabled on the 9050. Also, the UARTS are set in
240 * 16450 mode by default, so we have to enable the
241 * 16C950 'enhanced' mode so that we can use the
242 * deep FIFOs
243 */
244 irq_config = 0x5b;
245 }
246
247 /*
248 * enable/disable interrupts
249 */
250 p = ioremap(pci_resource_start(dev, 0), 0x80);
251 if (p == NULL)
252 return -ENOMEM;
253 writel(irq_config, p + 0x4c);
254
255 /*
256 * Read the register back to ensure that it took effect.
257 */
258 readl(p + 0x4c);
259 iounmap(p);
260
261 return 0;
262 }
263
264 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
265 {
266 u8 __iomem *p;
267
268 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
269 return;
270
271 /*
272 * disable interrupts
273 */
274 p = ioremap(pci_resource_start(dev, 0), 0x80);
275 if (p != NULL) {
276 writel(0, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283 }
284 }
285
286 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
287 static int
288 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
289 struct uart_port *port, int idx)
290 {
291 unsigned int bar, offset = board->first_offset;
292
293 bar = 0;
294
295 if (idx < 4) {
296 /* first four channels map to 0, 0x100, 0x200, 0x300 */
297 offset += idx * board->uart_offset;
298 } else if (idx < 8) {
299 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
300 offset += idx * board->uart_offset + 0xC00;
301 } else /* we have only 8 ports on PMC-OCTALPRO */
302 return 1;
303
304 return setup_port(priv, port, bar, offset, board->reg_shift);
305 }
306
307 /*
308 * This does initialization for PMC OCTALPRO cards:
309 * maps the device memory, resets the UARTs (needed, bc
310 * if the module is removed and inserted again, the card
311 * is in the sleep mode) and enables global interrupt.
312 */
313
314 /* global control register offset for SBS PMC-OctalPro */
315 #define OCT_REG_CR_OFF 0x500
316
317 static int sbs_init(struct pci_dev *dev)
318 {
319 u8 __iomem *p;
320
321 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
322
323 if (p == NULL)
324 return -ENOMEM;
325 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
326 writeb(0x10,p + OCT_REG_CR_OFF);
327 udelay(50);
328 writeb(0x0,p + OCT_REG_CR_OFF);
329
330 /* Set bit-2 (INTENABLE) of Control Register */
331 writeb(0x4, p + OCT_REG_CR_OFF);
332 iounmap(p);
333
334 return 0;
335 }
336
337 /*
338 * Disables the global interrupt of PMC-OctalPro
339 */
340
341 static void __devexit sbs_exit(struct pci_dev *dev)
342 {
343 u8 __iomem *p;
344
345 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
346 if (p != NULL) {
347 writeb(0, p + OCT_REG_CR_OFF);
348 }
349 iounmap(p);
350 }
351
352 /*
353 * SIIG serial cards have an PCI interface chip which also controls
354 * the UART clocking frequency. Each UART can be clocked independently
355 * (except cards equiped with 4 UARTs) and initial clocking settings
356 * are stored in the EEPROM chip. It can cause problems because this
357 * version of serial driver doesn't support differently clocked UART's
358 * on single PCI card. To prevent this, initialization functions set
359 * high frequency clocking for all UART's on given card. It is safe (I
360 * hope) because it doesn't touch EEPROM settings to prevent conflicts
361 * with other OSes (like M$ DOS).
362 *
363 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
364 *
365 * There is two family of SIIG serial cards with different PCI
366 * interface chip and different configuration methods:
367 * - 10x cards have control registers in IO and/or memory space;
368 * - 20x cards have control registers in standard PCI configuration space.
369 *
370 * Note: all 10x cards have PCI device ids 0x10..
371 * all 20x cards have PCI device ids 0x20..
372 *
373 * There are also Quartet Serial cards which use Oxford Semiconductor
374 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
375 *
376 * Note: some SIIG cards are probed by the parport_serial object.
377 */
378
379 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
380 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
381
382 static int pci_siig10x_init(struct pci_dev *dev)
383 {
384 u16 data;
385 void __iomem *p;
386
387 switch (dev->device & 0xfff8) {
388 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
389 data = 0xffdf;
390 break;
391 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
392 data = 0xf7ff;
393 break;
394 default: /* 1S1P, 4S */
395 data = 0xfffb;
396 break;
397 }
398
399 p = ioremap(pci_resource_start(dev, 0), 0x80);
400 if (p == NULL)
401 return -ENOMEM;
402
403 writew(readw(p + 0x28) & data, p + 0x28);
404 readw(p + 0x28);
405 iounmap(p);
406 return 0;
407 }
408
409 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
410 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
411
412 static int pci_siig20x_init(struct pci_dev *dev)
413 {
414 u8 data;
415
416 /* Change clock frequency for the first UART. */
417 pci_read_config_byte(dev, 0x6f, &data);
418 pci_write_config_byte(dev, 0x6f, data & 0xef);
419
420 /* If this card has 2 UART, we have to do the same with second UART. */
421 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
422 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
423 pci_read_config_byte(dev, 0x73, &data);
424 pci_write_config_byte(dev, 0x73, data & 0xef);
425 }
426 return 0;
427 }
428
429 static int pci_siig_init(struct pci_dev *dev)
430 {
431 unsigned int type = dev->device & 0xff00;
432
433 if (type == 0x1000)
434 return pci_siig10x_init(dev);
435 else if (type == 0x2000)
436 return pci_siig20x_init(dev);
437
438 moan_device("Unknown SIIG card", dev);
439 return -ENODEV;
440 }
441
442 static int pci_siig_setup(struct serial_private *priv,
443 struct pciserial_board *board,
444 struct uart_port *port, int idx)
445 {
446 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
447
448 if (idx > 3) {
449 bar = 4;
450 offset = (idx - 4) * 8;
451 }
452
453 return setup_port(priv, port, bar, offset, 0);
454 }
455
456 /*
457 * Timedia has an explosion of boards, and to avoid the PCI table from
458 * growing *huge*, we use this function to collapse some 70 entries
459 * in the PCI table into one, for sanity's and compactness's sake.
460 */
461 static const unsigned short timedia_single_port[] = {
462 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
463 };
464
465 static const unsigned short timedia_dual_port[] = {
466 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
467 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
468 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
469 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
470 0xD079, 0
471 };
472
473 static const unsigned short timedia_quad_port[] = {
474 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
475 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
476 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
477 0xB157, 0
478 };
479
480 static const unsigned short timedia_eight_port[] = {
481 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
482 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
483 };
484
485 static const struct timedia_struct {
486 int num;
487 const unsigned short *ids;
488 } timedia_data[] = {
489 { 1, timedia_single_port },
490 { 2, timedia_dual_port },
491 { 4, timedia_quad_port },
492 { 8, timedia_eight_port }
493 };
494
495 static int pci_timedia_init(struct pci_dev *dev)
496 {
497 const unsigned short *ids;
498 int i, j;
499
500 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
501 ids = timedia_data[i].ids;
502 for (j = 0; ids[j]; j++)
503 if (dev->subsystem_device == ids[j])
504 return timedia_data[i].num;
505 }
506 return 0;
507 }
508
509 /*
510 * Timedia/SUNIX uses a mixture of BARs and offsets
511 * Ugh, this is ugly as all hell --- TYT
512 */
513 static int
514 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
515 struct uart_port *port, int idx)
516 {
517 unsigned int bar = 0, offset = board->first_offset;
518
519 switch (idx) {
520 case 0:
521 bar = 0;
522 break;
523 case 1:
524 offset = board->uart_offset;
525 bar = 0;
526 break;
527 case 2:
528 bar = 1;
529 break;
530 case 3:
531 offset = board->uart_offset;
532 /* FALLTHROUGH */
533 case 4: /* BAR 2 */
534 case 5: /* BAR 3 */
535 case 6: /* BAR 4 */
536 case 7: /* BAR 5 */
537 bar = idx - 2;
538 }
539
540 return setup_port(priv, port, bar, offset, board->reg_shift);
541 }
542
543 /*
544 * Some Titan cards are also a little weird
545 */
546 static int
547 titan_400l_800l_setup(struct serial_private *priv,
548 struct pciserial_board *board,
549 struct uart_port *port, int idx)
550 {
551 unsigned int bar, offset = board->first_offset;
552
553 switch (idx) {
554 case 0:
555 bar = 1;
556 break;
557 case 1:
558 bar = 2;
559 break;
560 default:
561 bar = 4;
562 offset = (idx - 2) * board->uart_offset;
563 }
564
565 return setup_port(priv, port, bar, offset, board->reg_shift);
566 }
567
568 static int pci_xircom_init(struct pci_dev *dev)
569 {
570 msleep(100);
571 return 0;
572 }
573
574 static int pci_netmos_init(struct pci_dev *dev)
575 {
576 /* subdevice 0x00PS means <P> parallel, <S> serial */
577 unsigned int num_serial = dev->subsystem_device & 0xf;
578
579 if (num_serial == 0)
580 return -ENODEV;
581 return num_serial;
582 }
583
584 static int
585 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
586 struct uart_port *port, int idx)
587 {
588 unsigned int bar, offset = board->first_offset, maxnr;
589
590 bar = FL_GET_BASE(board->flags);
591 if (board->flags & FL_BASE_BARS)
592 bar += idx;
593 else
594 offset += idx * board->uart_offset;
595
596 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
597 (board->reg_shift + 3);
598
599 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
600 return 1;
601
602 return setup_port(priv, port, bar, offset, board->reg_shift);
603 }
604
605 /* This should be in linux/pci_ids.h */
606 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
607 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
608 #define PCI_DEVICE_ID_OCTPRO 0x0001
609 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
610 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
611 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
612 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
613
614 /*
615 * Master list of serial port init/setup/exit quirks.
616 * This does not describe the general nature of the port.
617 * (ie, baud base, number and location of ports, etc)
618 *
619 * This list is ordered alphabetically by vendor then device.
620 * Specific entries must come before more generic entries.
621 */
622 static struct pci_serial_quirk pci_serial_quirks[] = {
623 /*
624 * AFAVLAB cards - these may be called via parport_serial
625 * It is not clear whether this applies to all products.
626 */
627 {
628 .vendor = PCI_VENDOR_ID_AFAVLAB,
629 .device = PCI_ANY_ID,
630 .subvendor = PCI_ANY_ID,
631 .subdevice = PCI_ANY_ID,
632 .setup = afavlab_setup,
633 },
634 /*
635 * HP Diva
636 */
637 {
638 .vendor = PCI_VENDOR_ID_HP,
639 .device = PCI_DEVICE_ID_HP_DIVA,
640 .subvendor = PCI_ANY_ID,
641 .subdevice = PCI_ANY_ID,
642 .init = pci_hp_diva_init,
643 .setup = pci_hp_diva_setup,
644 },
645 /*
646 * Intel
647 */
648 {
649 .vendor = PCI_VENDOR_ID_INTEL,
650 .device = PCI_DEVICE_ID_INTEL_80960_RP,
651 .subvendor = 0xe4bf,
652 .subdevice = PCI_ANY_ID,
653 .init = pci_inteli960ni_init,
654 .setup = pci_default_setup,
655 },
656 /*
657 * Panacom
658 */
659 {
660 .vendor = PCI_VENDOR_ID_PANACOM,
661 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
662 .subvendor = PCI_ANY_ID,
663 .subdevice = PCI_ANY_ID,
664 .init = pci_plx9050_init,
665 .setup = pci_default_setup,
666 .exit = __devexit_p(pci_plx9050_exit),
667 },
668 {
669 .vendor = PCI_VENDOR_ID_PANACOM,
670 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
671 .subvendor = PCI_ANY_ID,
672 .subdevice = PCI_ANY_ID,
673 .init = pci_plx9050_init,
674 .setup = pci_default_setup,
675 .exit = __devexit_p(pci_plx9050_exit),
676 },
677 /*
678 * PLX
679 */
680 {
681 .vendor = PCI_VENDOR_ID_PLX,
682 .device = PCI_DEVICE_ID_PLX_9050,
683 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
684 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
685 .init = pci_plx9050_init,
686 .setup = pci_default_setup,
687 .exit = __devexit_p(pci_plx9050_exit),
688 },
689 {
690 .vendor = PCI_VENDOR_ID_PLX,
691 .device = PCI_DEVICE_ID_PLX_9050,
692 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
693 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
694 .init = pci_plx9050_init,
695 .setup = pci_default_setup,
696 .exit = __devexit_p(pci_plx9050_exit),
697 },
698 {
699 .vendor = PCI_VENDOR_ID_PLX,
700 .device = PCI_DEVICE_ID_PLX_ROMULUS,
701 .subvendor = PCI_VENDOR_ID_PLX,
702 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
703 .init = pci_plx9050_init,
704 .setup = pci_default_setup,
705 .exit = __devexit_p(pci_plx9050_exit),
706 },
707 /*
708 * SBS Technologies, Inc., PMC-OCTALPRO 232
709 */
710 {
711 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
712 .device = PCI_DEVICE_ID_OCTPRO,
713 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
714 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
715 .init = sbs_init,
716 .setup = sbs_setup,
717 .exit = __devexit_p(sbs_exit),
718 },
719 /*
720 * SBS Technologies, Inc., PMC-OCTALPRO 422
721 */
722 {
723 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
724 .device = PCI_DEVICE_ID_OCTPRO,
725 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
726 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
727 .init = sbs_init,
728 .setup = sbs_setup,
729 .exit = __devexit_p(sbs_exit),
730 },
731 /*
732 * SBS Technologies, Inc., P-Octal 232
733 */
734 {
735 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
736 .device = PCI_DEVICE_ID_OCTPRO,
737 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
738 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
739 .init = sbs_init,
740 .setup = sbs_setup,
741 .exit = __devexit_p(sbs_exit),
742 },
743 /*
744 * SBS Technologies, Inc., P-Octal 422
745 */
746 {
747 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
748 .device = PCI_DEVICE_ID_OCTPRO,
749 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
750 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
751 .init = sbs_init,
752 .setup = sbs_setup,
753 .exit = __devexit_p(sbs_exit),
754 },
755 /*
756 * SIIG cards - these may be called via parport_serial
757 */
758 {
759 .vendor = PCI_VENDOR_ID_SIIG,
760 .device = PCI_ANY_ID,
761 .subvendor = PCI_ANY_ID,
762 .subdevice = PCI_ANY_ID,
763 .init = pci_siig_init,
764 .setup = pci_siig_setup,
765 },
766 /*
767 * Titan cards
768 */
769 {
770 .vendor = PCI_VENDOR_ID_TITAN,
771 .device = PCI_DEVICE_ID_TITAN_400L,
772 .subvendor = PCI_ANY_ID,
773 .subdevice = PCI_ANY_ID,
774 .setup = titan_400l_800l_setup,
775 },
776 {
777 .vendor = PCI_VENDOR_ID_TITAN,
778 .device = PCI_DEVICE_ID_TITAN_800L,
779 .subvendor = PCI_ANY_ID,
780 .subdevice = PCI_ANY_ID,
781 .setup = titan_400l_800l_setup,
782 },
783 /*
784 * Timedia cards
785 */
786 {
787 .vendor = PCI_VENDOR_ID_TIMEDIA,
788 .device = PCI_DEVICE_ID_TIMEDIA_1889,
789 .subvendor = PCI_VENDOR_ID_TIMEDIA,
790 .subdevice = PCI_ANY_ID,
791 .init = pci_timedia_init,
792 .setup = pci_timedia_setup,
793 },
794 {
795 .vendor = PCI_VENDOR_ID_TIMEDIA,
796 .device = PCI_ANY_ID,
797 .subvendor = PCI_ANY_ID,
798 .subdevice = PCI_ANY_ID,
799 .setup = pci_timedia_setup,
800 },
801 /*
802 * Xircom cards
803 */
804 {
805 .vendor = PCI_VENDOR_ID_XIRCOM,
806 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
807 .subvendor = PCI_ANY_ID,
808 .subdevice = PCI_ANY_ID,
809 .init = pci_xircom_init,
810 .setup = pci_default_setup,
811 },
812 /*
813 * Netmos cards - these may be called via parport_serial
814 */
815 {
816 .vendor = PCI_VENDOR_ID_NETMOS,
817 .device = PCI_ANY_ID,
818 .subvendor = PCI_ANY_ID,
819 .subdevice = PCI_ANY_ID,
820 .init = pci_netmos_init,
821 .setup = pci_default_setup,
822 },
823 /*
824 * Default "match everything" terminator entry
825 */
826 {
827 .vendor = PCI_ANY_ID,
828 .device = PCI_ANY_ID,
829 .subvendor = PCI_ANY_ID,
830 .subdevice = PCI_ANY_ID,
831 .setup = pci_default_setup,
832 }
833 };
834
835 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
836 {
837 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
838 }
839
840 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
841 {
842 struct pci_serial_quirk *quirk;
843
844 for (quirk = pci_serial_quirks; ; quirk++)
845 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
846 quirk_id_matches(quirk->device, dev->device) &&
847 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
848 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
849 break;
850 return quirk;
851 }
852
853 static inline int get_pci_irq(struct pci_dev *dev,
854 struct pciserial_board *board)
855 {
856 if (board->flags & FL_NOIRQ)
857 return 0;
858 else
859 return dev->irq;
860 }
861
862 /*
863 * This is the configuration table for all of the PCI serial boards
864 * which we support. It is directly indexed by the pci_board_num_t enum
865 * value, which is encoded in the pci_device_id PCI probe table's
866 * driver_data member.
867 *
868 * The makeup of these names are:
869 * pbn_bn{_bt}_n_baud{_offsetinhex}
870 *
871 * bn = PCI BAR number
872 * bt = Index using PCI BARs
873 * n = number of serial ports
874 * baud = baud rate
875 * offsetinhex = offset for each sequential port (in hex)
876 *
877 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
878 *
879 * Please note: in theory if n = 1, _bt infix should make no difference.
880 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
881 */
882 enum pci_board_num_t {
883 pbn_default = 0,
884
885 pbn_b0_1_115200,
886 pbn_b0_2_115200,
887 pbn_b0_4_115200,
888 pbn_b0_5_115200,
889
890 pbn_b0_1_921600,
891 pbn_b0_2_921600,
892 pbn_b0_4_921600,
893
894 pbn_b0_2_1130000,
895
896 pbn_b0_4_1152000,
897
898 pbn_b0_2_1843200,
899 pbn_b0_4_1843200,
900
901 pbn_b0_2_1843200_200,
902 pbn_b0_4_1843200_200,
903 pbn_b0_8_1843200_200,
904
905 pbn_b0_bt_1_115200,
906 pbn_b0_bt_2_115200,
907 pbn_b0_bt_8_115200,
908
909 pbn_b0_bt_1_460800,
910 pbn_b0_bt_2_460800,
911 pbn_b0_bt_4_460800,
912
913 pbn_b0_bt_1_921600,
914 pbn_b0_bt_2_921600,
915 pbn_b0_bt_4_921600,
916 pbn_b0_bt_8_921600,
917
918 pbn_b1_1_115200,
919 pbn_b1_2_115200,
920 pbn_b1_4_115200,
921 pbn_b1_8_115200,
922
923 pbn_b1_1_921600,
924 pbn_b1_2_921600,
925 pbn_b1_4_921600,
926 pbn_b1_8_921600,
927
928 pbn_b1_2_1250000,
929
930 pbn_b1_bt_2_921600,
931
932 pbn_b1_1_1382400,
933 pbn_b1_2_1382400,
934 pbn_b1_4_1382400,
935 pbn_b1_8_1382400,
936
937 pbn_b2_1_115200,
938 pbn_b2_2_115200,
939 pbn_b2_8_115200,
940
941 pbn_b2_1_460800,
942 pbn_b2_4_460800,
943 pbn_b2_8_460800,
944 pbn_b2_16_460800,
945
946 pbn_b2_1_921600,
947 pbn_b2_4_921600,
948 pbn_b2_8_921600,
949
950 pbn_b2_bt_1_115200,
951 pbn_b2_bt_2_115200,
952 pbn_b2_bt_4_115200,
953
954 pbn_b2_bt_2_921600,
955 pbn_b2_bt_4_921600,
956
957 pbn_b3_2_115200,
958 pbn_b3_4_115200,
959 pbn_b3_8_115200,
960
961 /*
962 * Board-specific versions.
963 */
964 pbn_panacom,
965 pbn_panacom2,
966 pbn_panacom4,
967 pbn_exsys_4055,
968 pbn_plx_romulus,
969 pbn_oxsemi,
970 pbn_intel_i960,
971 pbn_sgi_ioc3,
972 pbn_nec_nile4,
973 pbn_computone_4,
974 pbn_computone_6,
975 pbn_computone_8,
976 pbn_sbsxrsio,
977 pbn_exar_XR17C152,
978 pbn_exar_XR17C154,
979 pbn_exar_XR17C158,
980 };
981
982 /*
983 * uart_offset - the space between channels
984 * reg_shift - describes how the UART registers are mapped
985 * to PCI memory by the card.
986 * For example IER register on SBS, Inc. PMC-OctPro is located at
987 * offset 0x10 from the UART base, while UART_IER is defined as 1
988 * in include/linux/serial_reg.h,
989 * see first lines of serial_in() and serial_out() in 8250.c
990 */
991
992 static struct pciserial_board pci_boards[] __devinitdata = {
993 [pbn_default] = {
994 .flags = FL_BASE0,
995 .num_ports = 1,
996 .base_baud = 115200,
997 .uart_offset = 8,
998 },
999 [pbn_b0_1_115200] = {
1000 .flags = FL_BASE0,
1001 .num_ports = 1,
1002 .base_baud = 115200,
1003 .uart_offset = 8,
1004 },
1005 [pbn_b0_2_115200] = {
1006 .flags = FL_BASE0,
1007 .num_ports = 2,
1008 .base_baud = 115200,
1009 .uart_offset = 8,
1010 },
1011 [pbn_b0_4_115200] = {
1012 .flags = FL_BASE0,
1013 .num_ports = 4,
1014 .base_baud = 115200,
1015 .uart_offset = 8,
1016 },
1017 [pbn_b0_5_115200] = {
1018 .flags = FL_BASE0,
1019 .num_ports = 5,
1020 .base_baud = 115200,
1021 .uart_offset = 8,
1022 },
1023
1024 [pbn_b0_1_921600] = {
1025 .flags = FL_BASE0,
1026 .num_ports = 1,
1027 .base_baud = 921600,
1028 .uart_offset = 8,
1029 },
1030 [pbn_b0_2_921600] = {
1031 .flags = FL_BASE0,
1032 .num_ports = 2,
1033 .base_baud = 921600,
1034 .uart_offset = 8,
1035 },
1036 [pbn_b0_4_921600] = {
1037 .flags = FL_BASE0,
1038 .num_ports = 4,
1039 .base_baud = 921600,
1040 .uart_offset = 8,
1041 },
1042
1043 [pbn_b0_2_1130000] = {
1044 .flags = FL_BASE0,
1045 .num_ports = 2,
1046 .base_baud = 1130000,
1047 .uart_offset = 8,
1048 },
1049
1050 [pbn_b0_4_1152000] = {
1051 .flags = FL_BASE0,
1052 .num_ports = 4,
1053 .base_baud = 1152000,
1054 .uart_offset = 8,
1055 },
1056
1057 [pbn_b0_2_1843200] = {
1058 .flags = FL_BASE0,
1059 .num_ports = 2,
1060 .base_baud = 1843200,
1061 .uart_offset = 8,
1062 },
1063 [pbn_b0_4_1843200] = {
1064 .flags = FL_BASE0,
1065 .num_ports = 4,
1066 .base_baud = 1843200,
1067 .uart_offset = 8,
1068 },
1069
1070 [pbn_b0_2_1843200_200] = {
1071 .flags = FL_BASE0,
1072 .num_ports = 2,
1073 .base_baud = 1843200,
1074 .uart_offset = 0x200,
1075 },
1076 [pbn_b0_4_1843200_200] = {
1077 .flags = FL_BASE0,
1078 .num_ports = 4,
1079 .base_baud = 1843200,
1080 .uart_offset = 0x200,
1081 },
1082 [pbn_b0_8_1843200_200] = {
1083 .flags = FL_BASE0,
1084 .num_ports = 8,
1085 .base_baud = 1843200,
1086 .uart_offset = 0x200,
1087 },
1088
1089 [pbn_b0_bt_1_115200] = {
1090 .flags = FL_BASE0|FL_BASE_BARS,
1091 .num_ports = 1,
1092 .base_baud = 115200,
1093 .uart_offset = 8,
1094 },
1095 [pbn_b0_bt_2_115200] = {
1096 .flags = FL_BASE0|FL_BASE_BARS,
1097 .num_ports = 2,
1098 .base_baud = 115200,
1099 .uart_offset = 8,
1100 },
1101 [pbn_b0_bt_8_115200] = {
1102 .flags = FL_BASE0|FL_BASE_BARS,
1103 .num_ports = 8,
1104 .base_baud = 115200,
1105 .uart_offset = 8,
1106 },
1107
1108 [pbn_b0_bt_1_460800] = {
1109 .flags = FL_BASE0|FL_BASE_BARS,
1110 .num_ports = 1,
1111 .base_baud = 460800,
1112 .uart_offset = 8,
1113 },
1114 [pbn_b0_bt_2_460800] = {
1115 .flags = FL_BASE0|FL_BASE_BARS,
1116 .num_ports = 2,
1117 .base_baud = 460800,
1118 .uart_offset = 8,
1119 },
1120 [pbn_b0_bt_4_460800] = {
1121 .flags = FL_BASE0|FL_BASE_BARS,
1122 .num_ports = 4,
1123 .base_baud = 460800,
1124 .uart_offset = 8,
1125 },
1126
1127 [pbn_b0_bt_1_921600] = {
1128 .flags = FL_BASE0|FL_BASE_BARS,
1129 .num_ports = 1,
1130 .base_baud = 921600,
1131 .uart_offset = 8,
1132 },
1133 [pbn_b0_bt_2_921600] = {
1134 .flags = FL_BASE0|FL_BASE_BARS,
1135 .num_ports = 2,
1136 .base_baud = 921600,
1137 .uart_offset = 8,
1138 },
1139 [pbn_b0_bt_4_921600] = {
1140 .flags = FL_BASE0|FL_BASE_BARS,
1141 .num_ports = 4,
1142 .base_baud = 921600,
1143 .uart_offset = 8,
1144 },
1145 [pbn_b0_bt_8_921600] = {
1146 .flags = FL_BASE0|FL_BASE_BARS,
1147 .num_ports = 8,
1148 .base_baud = 921600,
1149 .uart_offset = 8,
1150 },
1151
1152 [pbn_b1_1_115200] = {
1153 .flags = FL_BASE1,
1154 .num_ports = 1,
1155 .base_baud = 115200,
1156 .uart_offset = 8,
1157 },
1158 [pbn_b1_2_115200] = {
1159 .flags = FL_BASE1,
1160 .num_ports = 2,
1161 .base_baud = 115200,
1162 .uart_offset = 8,
1163 },
1164 [pbn_b1_4_115200] = {
1165 .flags = FL_BASE1,
1166 .num_ports = 4,
1167 .base_baud = 115200,
1168 .uart_offset = 8,
1169 },
1170 [pbn_b1_8_115200] = {
1171 .flags = FL_BASE1,
1172 .num_ports = 8,
1173 .base_baud = 115200,
1174 .uart_offset = 8,
1175 },
1176
1177 [pbn_b1_1_921600] = {
1178 .flags = FL_BASE1,
1179 .num_ports = 1,
1180 .base_baud = 921600,
1181 .uart_offset = 8,
1182 },
1183 [pbn_b1_2_921600] = {
1184 .flags = FL_BASE1,
1185 .num_ports = 2,
1186 .base_baud = 921600,
1187 .uart_offset = 8,
1188 },
1189 [pbn_b1_4_921600] = {
1190 .flags = FL_BASE1,
1191 .num_ports = 4,
1192 .base_baud = 921600,
1193 .uart_offset = 8,
1194 },
1195 [pbn_b1_8_921600] = {
1196 .flags = FL_BASE1,
1197 .num_ports = 8,
1198 .base_baud = 921600,
1199 .uart_offset = 8,
1200 },
1201 [pbn_b1_2_1250000] = {
1202 .flags = FL_BASE1,
1203 .num_ports = 2,
1204 .base_baud = 1250000,
1205 .uart_offset = 8,
1206 },
1207
1208 [pbn_b1_bt_2_921600] = {
1209 .flags = FL_BASE1|FL_BASE_BARS,
1210 .num_ports = 2,
1211 .base_baud = 921600,
1212 .uart_offset = 8,
1213 },
1214
1215 [pbn_b1_1_1382400] = {
1216 .flags = FL_BASE1,
1217 .num_ports = 1,
1218 .base_baud = 1382400,
1219 .uart_offset = 8,
1220 },
1221 [pbn_b1_2_1382400] = {
1222 .flags = FL_BASE1,
1223 .num_ports = 2,
1224 .base_baud = 1382400,
1225 .uart_offset = 8,
1226 },
1227 [pbn_b1_4_1382400] = {
1228 .flags = FL_BASE1,
1229 .num_ports = 4,
1230 .base_baud = 1382400,
1231 .uart_offset = 8,
1232 },
1233 [pbn_b1_8_1382400] = {
1234 .flags = FL_BASE1,
1235 .num_ports = 8,
1236 .base_baud = 1382400,
1237 .uart_offset = 8,
1238 },
1239
1240 [pbn_b2_1_115200] = {
1241 .flags = FL_BASE2,
1242 .num_ports = 1,
1243 .base_baud = 115200,
1244 .uart_offset = 8,
1245 },
1246 [pbn_b2_2_115200] = {
1247 .flags = FL_BASE2,
1248 .num_ports = 2,
1249 .base_baud = 115200,
1250 .uart_offset = 8,
1251 },
1252 [pbn_b2_8_115200] = {
1253 .flags = FL_BASE2,
1254 .num_ports = 8,
1255 .base_baud = 115200,
1256 .uart_offset = 8,
1257 },
1258
1259 [pbn_b2_1_460800] = {
1260 .flags = FL_BASE2,
1261 .num_ports = 1,
1262 .base_baud = 460800,
1263 .uart_offset = 8,
1264 },
1265 [pbn_b2_4_460800] = {
1266 .flags = FL_BASE2,
1267 .num_ports = 4,
1268 .base_baud = 460800,
1269 .uart_offset = 8,
1270 },
1271 [pbn_b2_8_460800] = {
1272 .flags = FL_BASE2,
1273 .num_ports = 8,
1274 .base_baud = 460800,
1275 .uart_offset = 8,
1276 },
1277 [pbn_b2_16_460800] = {
1278 .flags = FL_BASE2,
1279 .num_ports = 16,
1280 .base_baud = 460800,
1281 .uart_offset = 8,
1282 },
1283
1284 [pbn_b2_1_921600] = {
1285 .flags = FL_BASE2,
1286 .num_ports = 1,
1287 .base_baud = 921600,
1288 .uart_offset = 8,
1289 },
1290 [pbn_b2_4_921600] = {
1291 .flags = FL_BASE2,
1292 .num_ports = 4,
1293 .base_baud = 921600,
1294 .uart_offset = 8,
1295 },
1296 [pbn_b2_8_921600] = {
1297 .flags = FL_BASE2,
1298 .num_ports = 8,
1299 .base_baud = 921600,
1300 .uart_offset = 8,
1301 },
1302
1303 [pbn_b2_bt_1_115200] = {
1304 .flags = FL_BASE2|FL_BASE_BARS,
1305 .num_ports = 1,
1306 .base_baud = 115200,
1307 .uart_offset = 8,
1308 },
1309 [pbn_b2_bt_2_115200] = {
1310 .flags = FL_BASE2|FL_BASE_BARS,
1311 .num_ports = 2,
1312 .base_baud = 115200,
1313 .uart_offset = 8,
1314 },
1315 [pbn_b2_bt_4_115200] = {
1316 .flags = FL_BASE2|FL_BASE_BARS,
1317 .num_ports = 4,
1318 .base_baud = 115200,
1319 .uart_offset = 8,
1320 },
1321
1322 [pbn_b2_bt_2_921600] = {
1323 .flags = FL_BASE2|FL_BASE_BARS,
1324 .num_ports = 2,
1325 .base_baud = 921600,
1326 .uart_offset = 8,
1327 },
1328 [pbn_b2_bt_4_921600] = {
1329 .flags = FL_BASE2|FL_BASE_BARS,
1330 .num_ports = 4,
1331 .base_baud = 921600,
1332 .uart_offset = 8,
1333 },
1334
1335 [pbn_b3_2_115200] = {
1336 .flags = FL_BASE3,
1337 .num_ports = 2,
1338 .base_baud = 115200,
1339 .uart_offset = 8,
1340 },
1341 [pbn_b3_4_115200] = {
1342 .flags = FL_BASE3,
1343 .num_ports = 4,
1344 .base_baud = 115200,
1345 .uart_offset = 8,
1346 },
1347 [pbn_b3_8_115200] = {
1348 .flags = FL_BASE3,
1349 .num_ports = 8,
1350 .base_baud = 115200,
1351 .uart_offset = 8,
1352 },
1353
1354 /*
1355 * Entries following this are board-specific.
1356 */
1357
1358 /*
1359 * Panacom - IOMEM
1360 */
1361 [pbn_panacom] = {
1362 .flags = FL_BASE2,
1363 .num_ports = 2,
1364 .base_baud = 921600,
1365 .uart_offset = 0x400,
1366 .reg_shift = 7,
1367 },
1368 [pbn_panacom2] = {
1369 .flags = FL_BASE2|FL_BASE_BARS,
1370 .num_ports = 2,
1371 .base_baud = 921600,
1372 .uart_offset = 0x400,
1373 .reg_shift = 7,
1374 },
1375 [pbn_panacom4] = {
1376 .flags = FL_BASE2|FL_BASE_BARS,
1377 .num_ports = 4,
1378 .base_baud = 921600,
1379 .uart_offset = 0x400,
1380 .reg_shift = 7,
1381 },
1382
1383 [pbn_exsys_4055] = {
1384 .flags = FL_BASE2,
1385 .num_ports = 4,
1386 .base_baud = 115200,
1387 .uart_offset = 8,
1388 },
1389
1390 /* I think this entry is broken - the first_offset looks wrong --rmk */
1391 [pbn_plx_romulus] = {
1392 .flags = FL_BASE2,
1393 .num_ports = 4,
1394 .base_baud = 921600,
1395 .uart_offset = 8 << 2,
1396 .reg_shift = 2,
1397 .first_offset = 0x03,
1398 },
1399
1400 /*
1401 * This board uses the size of PCI Base region 0 to
1402 * signal now many ports are available
1403 */
1404 [pbn_oxsemi] = {
1405 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1406 .num_ports = 32,
1407 .base_baud = 115200,
1408 .uart_offset = 8,
1409 },
1410
1411 /*
1412 * EKF addition for i960 Boards form EKF with serial port.
1413 * Max 256 ports.
1414 */
1415 [pbn_intel_i960] = {
1416 .flags = FL_BASE0,
1417 .num_ports = 32,
1418 .base_baud = 921600,
1419 .uart_offset = 8 << 2,
1420 .reg_shift = 2,
1421 .first_offset = 0x10000,
1422 },
1423 [pbn_sgi_ioc3] = {
1424 .flags = FL_BASE0|FL_NOIRQ,
1425 .num_ports = 1,
1426 .base_baud = 458333,
1427 .uart_offset = 8,
1428 .reg_shift = 0,
1429 .first_offset = 0x20178,
1430 },
1431
1432 /*
1433 * NEC Vrc-5074 (Nile 4) builtin UART.
1434 */
1435 [pbn_nec_nile4] = {
1436 .flags = FL_BASE0,
1437 .num_ports = 1,
1438 .base_baud = 520833,
1439 .uart_offset = 8 << 3,
1440 .reg_shift = 3,
1441 .first_offset = 0x300,
1442 },
1443
1444 /*
1445 * Computone - uses IOMEM.
1446 */
1447 [pbn_computone_4] = {
1448 .flags = FL_BASE0,
1449 .num_ports = 4,
1450 .base_baud = 921600,
1451 .uart_offset = 0x40,
1452 .reg_shift = 2,
1453 .first_offset = 0x200,
1454 },
1455 [pbn_computone_6] = {
1456 .flags = FL_BASE0,
1457 .num_ports = 6,
1458 .base_baud = 921600,
1459 .uart_offset = 0x40,
1460 .reg_shift = 2,
1461 .first_offset = 0x200,
1462 },
1463 [pbn_computone_8] = {
1464 .flags = FL_BASE0,
1465 .num_ports = 8,
1466 .base_baud = 921600,
1467 .uart_offset = 0x40,
1468 .reg_shift = 2,
1469 .first_offset = 0x200,
1470 },
1471 [pbn_sbsxrsio] = {
1472 .flags = FL_BASE0,
1473 .num_ports = 8,
1474 .base_baud = 460800,
1475 .uart_offset = 256,
1476 .reg_shift = 4,
1477 },
1478 /*
1479 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1480 * Only basic 16550A support.
1481 * XR17C15[24] are not tested, but they should work.
1482 */
1483 [pbn_exar_XR17C152] = {
1484 .flags = FL_BASE0,
1485 .num_ports = 2,
1486 .base_baud = 921600,
1487 .uart_offset = 0x200,
1488 },
1489 [pbn_exar_XR17C154] = {
1490 .flags = FL_BASE0,
1491 .num_ports = 4,
1492 .base_baud = 921600,
1493 .uart_offset = 0x200,
1494 },
1495 [pbn_exar_XR17C158] = {
1496 .flags = FL_BASE0,
1497 .num_ports = 8,
1498 .base_baud = 921600,
1499 .uart_offset = 0x200,
1500 },
1501 };
1502
1503 /*
1504 * Given a complete unknown PCI device, try to use some heuristics to
1505 * guess what the configuration might be, based on the pitiful PCI
1506 * serial specs. Returns 0 on success, 1 on failure.
1507 */
1508 static int __devinit
1509 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1510 {
1511 int num_iomem, num_port, first_port = -1, i;
1512
1513 /*
1514 * If it is not a communications device or the programming
1515 * interface is greater than 6, give up.
1516 *
1517 * (Should we try to make guesses for multiport serial devices
1518 * later?)
1519 */
1520 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1521 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1522 (dev->class & 0xff) > 6)
1523 return -ENODEV;
1524
1525 num_iomem = num_port = 0;
1526 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1527 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1528 num_port++;
1529 if (first_port == -1)
1530 first_port = i;
1531 }
1532 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1533 num_iomem++;
1534 }
1535
1536 /*
1537 * If there is 1 or 0 iomem regions, and exactly one port,
1538 * use it. We guess the number of ports based on the IO
1539 * region size.
1540 */
1541 if (num_iomem <= 1 && num_port == 1) {
1542 board->flags = first_port;
1543 board->num_ports = pci_resource_len(dev, first_port) / 8;
1544 return 0;
1545 }
1546
1547 /*
1548 * Now guess if we've got a board which indexes by BARs.
1549 * Each IO BAR should be 8 bytes, and they should follow
1550 * consecutively.
1551 */
1552 first_port = -1;
1553 num_port = 0;
1554 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1555 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1556 pci_resource_len(dev, i) == 8 &&
1557 (first_port == -1 || (first_port + num_port) == i)) {
1558 num_port++;
1559 if (first_port == -1)
1560 first_port = i;
1561 }
1562 }
1563
1564 if (num_port > 1) {
1565 board->flags = first_port | FL_BASE_BARS;
1566 board->num_ports = num_port;
1567 return 0;
1568 }
1569
1570 return -ENODEV;
1571 }
1572
1573 static inline int
1574 serial_pci_matches(struct pciserial_board *board,
1575 struct pciserial_board *guessed)
1576 {
1577 return
1578 board->num_ports == guessed->num_ports &&
1579 board->base_baud == guessed->base_baud &&
1580 board->uart_offset == guessed->uart_offset &&
1581 board->reg_shift == guessed->reg_shift &&
1582 board->first_offset == guessed->first_offset;
1583 }
1584
1585 struct serial_private *
1586 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1587 {
1588 struct uart_port serial_port;
1589 struct serial_private *priv;
1590 struct pci_serial_quirk *quirk;
1591 int rc, nr_ports, i;
1592
1593 nr_ports = board->num_ports;
1594
1595 /*
1596 * Find an init and setup quirks.
1597 */
1598 quirk = find_quirk(dev);
1599
1600 /*
1601 * Run the new-style initialization function.
1602 * The initialization function returns:
1603 * <0 - error
1604 * 0 - use board->num_ports
1605 * >0 - number of ports
1606 */
1607 if (quirk->init) {
1608 rc = quirk->init(dev);
1609 if (rc < 0) {
1610 priv = ERR_PTR(rc);
1611 goto err_out;
1612 }
1613 if (rc)
1614 nr_ports = rc;
1615 }
1616
1617 priv = kmalloc(sizeof(struct serial_private) +
1618 sizeof(unsigned int) * nr_ports,
1619 GFP_KERNEL);
1620 if (!priv) {
1621 priv = ERR_PTR(-ENOMEM);
1622 goto err_deinit;
1623 }
1624
1625 memset(priv, 0, sizeof(struct serial_private) +
1626 sizeof(unsigned int) * nr_ports);
1627
1628 priv->dev = dev;
1629 priv->quirk = quirk;
1630
1631 memset(&serial_port, 0, sizeof(struct uart_port));
1632 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1633 serial_port.uartclk = board->base_baud * 16;
1634 serial_port.irq = get_pci_irq(dev, board);
1635 serial_port.dev = &dev->dev;
1636
1637 for (i = 0; i < nr_ports; i++) {
1638 if (quirk->setup(priv, board, &serial_port, i))
1639 break;
1640
1641 #ifdef SERIAL_DEBUG_PCI
1642 printk("Setup PCI port: port %x, irq %d, type %d\n",
1643 serial_port.iobase, serial_port.irq, serial_port.iotype);
1644 #endif
1645
1646 priv->line[i] = serial8250_register_port(&serial_port);
1647 if (priv->line[i] < 0) {
1648 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1649 break;
1650 }
1651 }
1652
1653 priv->nr = i;
1654
1655 return priv;
1656
1657 err_deinit:
1658 if (quirk->exit)
1659 quirk->exit(dev);
1660 err_out:
1661 return priv;
1662 }
1663 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1664
1665 void pciserial_remove_ports(struct serial_private *priv)
1666 {
1667 struct pci_serial_quirk *quirk;
1668 int i;
1669
1670 for (i = 0; i < priv->nr; i++)
1671 serial8250_unregister_port(priv->line[i]);
1672
1673 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1674 if (priv->remapped_bar[i])
1675 iounmap(priv->remapped_bar[i]);
1676 priv->remapped_bar[i] = NULL;
1677 }
1678
1679 /*
1680 * Find the exit quirks.
1681 */
1682 quirk = find_quirk(priv->dev);
1683 if (quirk->exit)
1684 quirk->exit(priv->dev);
1685
1686 kfree(priv);
1687 }
1688 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1689
1690 void pciserial_suspend_ports(struct serial_private *priv)
1691 {
1692 int i;
1693
1694 for (i = 0; i < priv->nr; i++)
1695 if (priv->line[i] >= 0)
1696 serial8250_suspend_port(priv->line[i]);
1697 }
1698 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1699
1700 void pciserial_resume_ports(struct serial_private *priv)
1701 {
1702 int i;
1703
1704 /*
1705 * Ensure that the board is correctly configured.
1706 */
1707 if (priv->quirk->init)
1708 priv->quirk->init(priv->dev);
1709
1710 for (i = 0; i < priv->nr; i++)
1711 if (priv->line[i] >= 0)
1712 serial8250_resume_port(priv->line[i]);
1713 }
1714 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1715
1716 /*
1717 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1718 * to the arrangement of serial ports on a PCI card.
1719 */
1720 static int __devinit
1721 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1722 {
1723 struct serial_private *priv;
1724 struct pciserial_board *board, tmp;
1725 int rc;
1726
1727 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1728 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1729 ent->driver_data);
1730 return -EINVAL;
1731 }
1732
1733 board = &pci_boards[ent->driver_data];
1734
1735 rc = pci_enable_device(dev);
1736 if (rc)
1737 return rc;
1738
1739 if (ent->driver_data == pbn_default) {
1740 /*
1741 * Use a copy of the pci_board entry for this;
1742 * avoid changing entries in the table.
1743 */
1744 memcpy(&tmp, board, sizeof(struct pciserial_board));
1745 board = &tmp;
1746
1747 /*
1748 * We matched one of our class entries. Try to
1749 * determine the parameters of this board.
1750 */
1751 rc = serial_pci_guess_board(dev, board);
1752 if (rc)
1753 goto disable;
1754 } else {
1755 /*
1756 * We matched an explicit entry. If we are able to
1757 * detect this boards settings with our heuristic,
1758 * then we no longer need this entry.
1759 */
1760 memcpy(&tmp, &pci_boards[pbn_default],
1761 sizeof(struct pciserial_board));
1762 rc = serial_pci_guess_board(dev, &tmp);
1763 if (rc == 0 && serial_pci_matches(board, &tmp))
1764 moan_device("Redundant entry in serial pci_table.",
1765 dev);
1766 }
1767
1768 priv = pciserial_init_ports(dev, board);
1769 if (!IS_ERR(priv)) {
1770 pci_set_drvdata(dev, priv);
1771 return 0;
1772 }
1773
1774 rc = PTR_ERR(priv);
1775
1776 disable:
1777 pci_disable_device(dev);
1778 return rc;
1779 }
1780
1781 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1782 {
1783 struct serial_private *priv = pci_get_drvdata(dev);
1784
1785 pci_set_drvdata(dev, NULL);
1786
1787 pciserial_remove_ports(priv);
1788
1789 pci_disable_device(dev);
1790 }
1791
1792 #ifdef CONFIG_PM
1793 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1794 {
1795 struct serial_private *priv = pci_get_drvdata(dev);
1796
1797 if (priv)
1798 pciserial_suspend_ports(priv);
1799
1800 pci_save_state(dev);
1801 pci_set_power_state(dev, pci_choose_state(dev, state));
1802 return 0;
1803 }
1804
1805 static int pciserial_resume_one(struct pci_dev *dev)
1806 {
1807 struct serial_private *priv = pci_get_drvdata(dev);
1808
1809 pci_set_power_state(dev, PCI_D0);
1810 pci_restore_state(dev);
1811
1812 if (priv) {
1813 /*
1814 * The device may have been disabled. Re-enable it.
1815 */
1816 pci_enable_device(dev);
1817
1818 pciserial_resume_ports(priv);
1819 }
1820 return 0;
1821 }
1822 #endif
1823
1824 static struct pci_device_id serial_pci_tbl[] = {
1825 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1826 PCI_SUBVENDOR_ID_CONNECT_TECH,
1827 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1828 pbn_b1_8_1382400 },
1829 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1830 PCI_SUBVENDOR_ID_CONNECT_TECH,
1831 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1832 pbn_b1_4_1382400 },
1833 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1834 PCI_SUBVENDOR_ID_CONNECT_TECH,
1835 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1836 pbn_b1_2_1382400 },
1837 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1838 PCI_SUBVENDOR_ID_CONNECT_TECH,
1839 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1840 pbn_b1_8_1382400 },
1841 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1842 PCI_SUBVENDOR_ID_CONNECT_TECH,
1843 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1844 pbn_b1_4_1382400 },
1845 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1846 PCI_SUBVENDOR_ID_CONNECT_TECH,
1847 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1848 pbn_b1_2_1382400 },
1849 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1850 PCI_SUBVENDOR_ID_CONNECT_TECH,
1851 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1852 pbn_b1_8_921600 },
1853 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1854 PCI_SUBVENDOR_ID_CONNECT_TECH,
1855 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1856 pbn_b1_8_921600 },
1857 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1858 PCI_SUBVENDOR_ID_CONNECT_TECH,
1859 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1860 pbn_b1_4_921600 },
1861 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1862 PCI_SUBVENDOR_ID_CONNECT_TECH,
1863 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1864 pbn_b1_4_921600 },
1865 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1866 PCI_SUBVENDOR_ID_CONNECT_TECH,
1867 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1868 pbn_b1_2_921600 },
1869 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1870 PCI_SUBVENDOR_ID_CONNECT_TECH,
1871 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1872 pbn_b1_8_921600 },
1873 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1874 PCI_SUBVENDOR_ID_CONNECT_TECH,
1875 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1876 pbn_b1_8_921600 },
1877 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1878 PCI_SUBVENDOR_ID_CONNECT_TECH,
1879 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1880 pbn_b1_4_921600 },
1881 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1882 PCI_SUBVENDOR_ID_CONNECT_TECH,
1883 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
1884 pbn_b1_2_1250000 },
1885 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1886 PCI_SUBVENDOR_ID_CONNECT_TECH,
1887 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
1888 pbn_b0_2_1843200 },
1889 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1890 PCI_SUBVENDOR_ID_CONNECT_TECH,
1891 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
1892 pbn_b0_4_1843200 },
1893 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1894 PCI_VENDOR_ID_AFAVLAB,
1895 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
1896 pbn_b0_4_1152000 },
1897 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1898 PCI_SUBVENDOR_ID_CONNECT_TECH,
1899 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
1900 pbn_b0_2_1843200_200 },
1901 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1902 PCI_SUBVENDOR_ID_CONNECT_TECH,
1903 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
1904 pbn_b0_4_1843200_200 },
1905 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1906 PCI_SUBVENDOR_ID_CONNECT_TECH,
1907 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
1908 pbn_b0_8_1843200_200 },
1909 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1910 PCI_SUBVENDOR_ID_CONNECT_TECH,
1911 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
1912 pbn_b0_2_1843200_200 },
1913 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1914 PCI_SUBVENDOR_ID_CONNECT_TECH,
1915 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
1916 pbn_b0_4_1843200_200 },
1917 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1918 PCI_SUBVENDOR_ID_CONNECT_TECH,
1919 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
1920 pbn_b0_8_1843200_200 },
1921 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1922 PCI_SUBVENDOR_ID_CONNECT_TECH,
1923 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
1924 pbn_b0_2_1843200_200 },
1925 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1926 PCI_SUBVENDOR_ID_CONNECT_TECH,
1927 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
1928 pbn_b0_4_1843200_200 },
1929 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1930 PCI_SUBVENDOR_ID_CONNECT_TECH,
1931 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
1932 pbn_b0_8_1843200_200 },
1933 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1934 PCI_SUBVENDOR_ID_CONNECT_TECH,
1935 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
1936 pbn_b0_2_1843200_200 },
1937 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1938 PCI_SUBVENDOR_ID_CONNECT_TECH,
1939 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
1940 pbn_b0_4_1843200_200 },
1941 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1942 PCI_SUBVENDOR_ID_CONNECT_TECH,
1943 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
1944 pbn_b0_8_1843200_200 },
1945
1946 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1948 pbn_b2_bt_1_115200 },
1949 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1951 pbn_b2_bt_2_115200 },
1952 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1954 pbn_b2_bt_4_115200 },
1955 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1957 pbn_b2_bt_2_115200 },
1958 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1960 pbn_b2_bt_4_115200 },
1961 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1963 pbn_b2_8_115200 },
1964 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1966 pbn_b2_8_115200 },
1967
1968 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1970 pbn_b2_bt_2_115200 },
1971 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1973 pbn_b2_bt_2_921600 },
1974 /*
1975 * VScom SPCOM800, from sl@s.pl
1976 */
1977 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1979 pbn_b2_8_921600 },
1980 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1982 pbn_b2_4_921600 },
1983 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1984 PCI_SUBVENDOR_ID_KEYSPAN,
1985 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1986 pbn_panacom },
1987 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1989 pbn_panacom4 },
1990 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1992 pbn_panacom2 },
1993 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1994 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1995 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1996 pbn_b2_4_460800 },
1997 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1998 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1999 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2000 pbn_b2_8_460800 },
2001 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2002 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2003 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2004 pbn_b2_16_460800 },
2005 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2006 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2007 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2008 pbn_b2_16_460800 },
2009 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2010 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2011 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2012 pbn_b2_4_460800 },
2013 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2014 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2015 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2016 pbn_b2_8_460800 },
2017 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2018 PCI_SUBVENDOR_ID_EXSYS,
2019 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2020 pbn_exsys_4055 },
2021 /*
2022 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2023 * (Exoray@isys.ca)
2024 */
2025 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2026 0x10b5, 0x106a, 0, 0,
2027 pbn_plx_romulus },
2028 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2029 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2030 pbn_b1_4_115200 },
2031 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2032 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2033 pbn_b1_2_115200 },
2034 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2035 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2036 pbn_b1_8_115200 },
2037 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2038 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2039 pbn_b1_8_115200 },
2040 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2041 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2042 pbn_b0_4_921600 },
2043 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2044 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2045 pbn_b0_4_1152000 },
2046
2047 /*
2048 * The below card is a little controversial since it is the
2049 * subject of a PCI vendor/device ID clash. (See
2050 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2051 * For now just used the hex ID 0x950a.
2052 */
2053 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2055 pbn_b0_2_1130000 },
2056 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2058 pbn_b0_4_115200 },
2059 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2061 pbn_b0_bt_2_921600 },
2062
2063 /*
2064 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2065 * from skokodyn@yahoo.com
2066 */
2067 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2068 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2069 pbn_sbsxrsio },
2070 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2071 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2072 pbn_sbsxrsio },
2073 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2074 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2075 pbn_sbsxrsio },
2076 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2077 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2078 pbn_sbsxrsio },
2079
2080 /*
2081 * Digitan DS560-558, from jimd@esoft.com
2082 */
2083 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2085 pbn_b1_1_115200 },
2086
2087 /*
2088 * Titan Electronic cards
2089 * The 400L and 800L have a custom setup quirk.
2090 */
2091 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2093 pbn_b0_1_921600 },
2094 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2096 pbn_b0_2_921600 },
2097 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2099 pbn_b0_4_921600 },
2100 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2102 pbn_b0_4_921600 },
2103 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2105 pbn_b1_1_921600 },
2106 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2108 pbn_b1_bt_2_921600 },
2109 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2111 pbn_b0_bt_4_921600 },
2112 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2114 pbn_b0_bt_8_921600 },
2115
2116 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2118 pbn_b2_1_460800 },
2119 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2121 pbn_b2_1_460800 },
2122 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2124 pbn_b2_1_460800 },
2125 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2127 pbn_b2_bt_2_921600 },
2128 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2130 pbn_b2_bt_2_921600 },
2131 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2133 pbn_b2_bt_2_921600 },
2134 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2136 pbn_b2_bt_4_921600 },
2137 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2139 pbn_b2_bt_4_921600 },
2140 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2142 pbn_b2_bt_4_921600 },
2143 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2145 pbn_b0_1_921600 },
2146 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2148 pbn_b0_1_921600 },
2149 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2151 pbn_b0_1_921600 },
2152 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2154 pbn_b0_bt_2_921600 },
2155 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2157 pbn_b0_bt_2_921600 },
2158 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2160 pbn_b0_bt_2_921600 },
2161 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2163 pbn_b0_bt_4_921600 },
2164 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2166 pbn_b0_bt_4_921600 },
2167 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2169 pbn_b0_bt_4_921600 },
2170 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2172 pbn_b0_bt_8_921600 },
2173 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2175 pbn_b0_bt_8_921600 },
2176 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2178 pbn_b0_bt_8_921600 },
2179
2180 /*
2181 * Computone devices submitted by Doug McNash dmcnash@computone.com
2182 */
2183 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2184 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2185 0, 0, pbn_computone_4 },
2186 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2187 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2188 0, 0, pbn_computone_8 },
2189 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2190 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2191 0, 0, pbn_computone_6 },
2192
2193 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2195 pbn_oxsemi },
2196 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2197 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2198 pbn_b0_bt_1_921600 },
2199
2200 /*
2201 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2202 */
2203 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2205 pbn_b0_bt_8_115200 },
2206 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2208 pbn_b0_bt_8_115200 },
2209
2210 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2212 pbn_b0_bt_2_115200 },
2213 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2215 pbn_b0_bt_2_115200 },
2216 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2218 pbn_b0_bt_2_115200 },
2219 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2221 pbn_b0_bt_4_460800 },
2222 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2224 pbn_b0_bt_4_460800 },
2225 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2227 pbn_b0_bt_2_460800 },
2228 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2230 pbn_b0_bt_2_460800 },
2231 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2233 pbn_b0_bt_2_460800 },
2234 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2236 pbn_b0_bt_1_115200 },
2237 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2239 pbn_b0_bt_1_460800 },
2240
2241 /*
2242 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2243 * Cards are identified by their subsystem vendor IDs, which
2244 * (in hex) match the model number.
2245 *
2246 * Note that JC140x are RS422/485 cards which require ox950
2247 * ACR = 0x10, and as such are not currently fully supported.
2248 */
2249 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2250 0x1204, 0x0004, 0, 0,
2251 pbn_b0_4_921600 },
2252 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2253 0x1208, 0x0004, 0, 0,
2254 pbn_b0_4_921600 },
2255 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2256 0x1402, 0x0002, 0, 0,
2257 pbn_b0_2_921600 }, */
2258 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2259 0x1404, 0x0004, 0, 0,
2260 pbn_b0_4_921600 }, */
2261 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2262 0x1208, 0x0004, 0, 0,
2263 pbn_b0_4_921600 },
2264
2265 /*
2266 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2267 */
2268 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2270 pbn_b1_1_1382400 },
2271
2272 /*
2273 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2274 */
2275 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2277 pbn_b1_1_1382400 },
2278
2279 /*
2280 * RAStel 2 port modem, gerg@moreton.com.au
2281 */
2282 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2284 pbn_b2_bt_2_115200 },
2285
2286 /*
2287 * EKF addition for i960 Boards form EKF with serial port
2288 */
2289 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2290 0xE4BF, PCI_ANY_ID, 0, 0,
2291 pbn_intel_i960 },
2292
2293 /*
2294 * Xircom Cardbus/Ethernet combos
2295 */
2296 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2298 pbn_b0_1_115200 },
2299 /*
2300 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2301 */
2302 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2304 pbn_b0_1_115200 },
2305
2306 /*
2307 * Untested PCI modems, sent in from various folks...
2308 */
2309
2310 /*
2311 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2312 */
2313 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2314 0x1048, 0x1500, 0, 0,
2315 pbn_b1_1_115200 },
2316
2317 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2318 0xFF00, 0, 0, 0,
2319 pbn_sgi_ioc3 },
2320
2321 /*
2322 * HP Diva card
2323 */
2324 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2325 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2326 pbn_b1_1_115200 },
2327 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2329 pbn_b0_5_115200 },
2330 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2332 pbn_b2_1_115200 },
2333
2334 /*
2335 * NEC Vrc-5074 (Nile 4) builtin UART.
2336 */
2337 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2339 pbn_nec_nile4 },
2340
2341 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2343 pbn_b3_2_115200 },
2344 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2346 pbn_b3_4_115200 },
2347 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2348 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2349 pbn_b3_8_115200 },
2350
2351 /*
2352 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2353 */
2354 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2355 PCI_ANY_ID, PCI_ANY_ID,
2356 0,
2357 0, pbn_exar_XR17C152 },
2358 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2359 PCI_ANY_ID, PCI_ANY_ID,
2360 0,
2361 0, pbn_exar_XR17C154 },
2362 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2363 PCI_ANY_ID, PCI_ANY_ID,
2364 0,
2365 0, pbn_exar_XR17C158 },
2366
2367 /*
2368 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2369 */
2370 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2372 pbn_b0_1_115200 },
2373
2374 /*
2375 * IntaShield IS-200
2376 */
2377 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
2379 pbn_b2_2_115200 },
2380
2381 /*
2382 * These entries match devices with class COMMUNICATION_SERIAL,
2383 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2384 */
2385 { PCI_ANY_ID, PCI_ANY_ID,
2386 PCI_ANY_ID, PCI_ANY_ID,
2387 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2388 0xffff00, pbn_default },
2389 { PCI_ANY_ID, PCI_ANY_ID,
2390 PCI_ANY_ID, PCI_ANY_ID,
2391 PCI_CLASS_COMMUNICATION_MODEM << 8,
2392 0xffff00, pbn_default },
2393 { PCI_ANY_ID, PCI_ANY_ID,
2394 PCI_ANY_ID, PCI_ANY_ID,
2395 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2396 0xffff00, pbn_default },
2397 { 0, }
2398 };
2399
2400 static struct pci_driver serial_pci_driver = {
2401 .name = "serial",
2402 .probe = pciserial_init_one,
2403 .remove = __devexit_p(pciserial_remove_one),
2404 #ifdef CONFIG_PM
2405 .suspend = pciserial_suspend_one,
2406 .resume = pciserial_resume_one,
2407 #endif
2408 .id_table = serial_pci_tbl,
2409 };
2410
2411 static int __init serial8250_pci_init(void)
2412 {
2413 return pci_register_driver(&serial_pci_driver);
2414 }
2415
2416 static void __exit serial8250_pci_exit(void)
2417 {
2418 pci_unregister_driver(&serial_pci_driver);
2419 }
2420
2421 module_init(serial8250_pci_init);
2422 module_exit(serial8250_pci_exit);
2423
2424 MODULE_LICENSE("GPL");
2425 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2426 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux with added FPC-III support