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Linux 2.6.20.7
[linux/fpc-iii.git] / drivers / serial / amba-pl011.c
blob44639e71372a7eb08c209562e95374fe5d0fb22e
1 /*
2 * linux/drivers/char/amba.c
3 *
4 * Driver for AMBA serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
26 *
27 * This is a generic driver for ARM AMBA-type serial ports. They
28 * have a lot of 16550-like features, but are not register compatible.
29 * Note that although they do have CTS, DCD and DSR inputs, they do
30 * not have an RI input, nor do they have DTR or RTS outputs. If
31 * required, these have to be supplied via some other means (eg, GPIO)
32 * and hooked into this driver.
33 */
34
35 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
36 #define SUPPORT_SYSRQ
37 #endif
38
39 #include <linux/module.h>
40 #include <linux/ioport.h>
41 #include <linux/init.h>
42 #include <linux/console.h>
43 #include <linux/sysrq.h>
44 #include <linux/device.h>
45 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
47 #include <linux/serial_core.h>
48 #include <linux/serial.h>
49 #include <linux/amba/bus.h>
50 #include <linux/amba/serial.h>
51 #include <linux/clk.h>
52
53 #include <asm/io.h>
54 #include <asm/sizes.h>
55
56 #define UART_NR 14
57
58 #define SERIAL_AMBA_MAJOR 204
59 #define SERIAL_AMBA_MINOR 64
60 #define SERIAL_AMBA_NR UART_NR
61
62 #define AMBA_ISR_PASS_LIMIT 256
63
64 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
65 #define UART_DUMMY_DR_RX (1 << 16)
66
67 /*
68 * We wrap our port structure around the generic uart_port.
69 */
70 struct uart_amba_port {
71 struct uart_port port;
72 struct clk *clk;
73 unsigned int im; /* interrupt mask */
74 unsigned int old_status;
75 };
76
77 static void pl011_stop_tx(struct uart_port *port)
78 {
79 struct uart_amba_port *uap = (struct uart_amba_port *)port;
80
81 uap->im &= ~UART011_TXIM;
82 writew(uap->im, uap->port.membase + UART011_IMSC);
83 }
84
85 static void pl011_start_tx(struct uart_port *port)
86 {
87 struct uart_amba_port *uap = (struct uart_amba_port *)port;
88
89 uap->im |= UART011_TXIM;
90 writew(uap->im, uap->port.membase + UART011_IMSC);
91 }
92
93 static void pl011_stop_rx(struct uart_port *port)
94 {
95 struct uart_amba_port *uap = (struct uart_amba_port *)port;
96
97 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
98 UART011_PEIM|UART011_BEIM|UART011_OEIM);
99 writew(uap->im, uap->port.membase + UART011_IMSC);
100 }
101
102 static void pl011_enable_ms(struct uart_port *port)
103 {
104 struct uart_amba_port *uap = (struct uart_amba_port *)port;
105
106 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
107 writew(uap->im, uap->port.membase + UART011_IMSC);
108 }
109
110 static void pl011_rx_chars(struct uart_amba_port *uap)
111 {
112 struct tty_struct *tty = uap->port.info->tty;
113 unsigned int status, ch, flag, max_count = 256;
114
115 status = readw(uap->port.membase + UART01x_FR);
116 while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
117 ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX;
118 flag = TTY_NORMAL;
119 uap->port.icount.rx++;
120
121 /*
122 * Note that the error handling code is
123 * out of the main execution path
124 */
125 if (unlikely(ch & UART_DR_ERROR)) {
126 if (ch & UART011_DR_BE) {
127 ch &= ~(UART011_DR_FE | UART011_DR_PE);
128 uap->port.icount.brk++;
129 if (uart_handle_break(&uap->port))
130 goto ignore_char;
131 } else if (ch & UART011_DR_PE)
132 uap->port.icount.parity++;
133 else if (ch & UART011_DR_FE)
134 uap->port.icount.frame++;
135 if (ch & UART011_DR_OE)
136 uap->port.icount.overrun++;
137
138 ch &= uap->port.read_status_mask;
139
140 if (ch & UART011_DR_BE)
141 flag = TTY_BREAK;
142 else if (ch & UART011_DR_PE)
143 flag = TTY_PARITY;
144 else if (ch & UART011_DR_FE)
145 flag = TTY_FRAME;
146 }
147
148 if (uart_handle_sysrq_char(&uap->port, ch & 255))
149 goto ignore_char;
150
151 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
152
153 ignore_char:
154 status = readw(uap->port.membase + UART01x_FR);
155 }
156 tty_flip_buffer_push(tty);
157 return;
158 }
159
160 static void pl011_tx_chars(struct uart_amba_port *uap)
161 {
162 struct circ_buf *xmit = &uap->port.info->xmit;
163 int count;
164
165 if (uap->port.x_char) {
166 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
167 uap->port.icount.tx++;
168 uap->port.x_char = 0;
169 return;
170 }
171 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
172 pl011_stop_tx(&uap->port);
173 return;
174 }
175
176 count = uap->port.fifosize >> 1;
177 do {
178 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
179 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
180 uap->port.icount.tx++;
181 if (uart_circ_empty(xmit))
182 break;
183 } while (--count > 0);
184
185 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
186 uart_write_wakeup(&uap->port);
187
188 if (uart_circ_empty(xmit))
189 pl011_stop_tx(&uap->port);
190 }
191
192 static void pl011_modem_status(struct uart_amba_port *uap)
193 {
194 unsigned int status, delta;
195
196 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
197
198 delta = status ^ uap->old_status;
199 uap->old_status = status;
200
201 if (!delta)
202 return;
203
204 if (delta & UART01x_FR_DCD)
205 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
206
207 if (delta & UART01x_FR_DSR)
208 uap->port.icount.dsr++;
209
210 if (delta & UART01x_FR_CTS)
211 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
212
213 wake_up_interruptible(&uap->port.info->delta_msr_wait);
214 }
215
216 static irqreturn_t pl011_int(int irq, void *dev_id)
217 {
218 struct uart_amba_port *uap = dev_id;
219 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
220 int handled = 0;
221
222 spin_lock(&uap->port.lock);
223
224 status = readw(uap->port.membase + UART011_MIS);
225 if (status) {
226 do {
227 writew(status & ~(UART011_TXIS|UART011_RTIS|
228 UART011_RXIS),
229 uap->port.membase + UART011_ICR);
230
231 if (status & (UART011_RTIS|UART011_RXIS))
232 pl011_rx_chars(uap);
233 if (status & (UART011_DSRMIS|UART011_DCDMIS|
234 UART011_CTSMIS|UART011_RIMIS))
235 pl011_modem_status(uap);
236 if (status & UART011_TXIS)
237 pl011_tx_chars(uap);
238
239 if (pass_counter-- == 0)
240 break;
241
242 status = readw(uap->port.membase + UART011_MIS);
243 } while (status != 0);
244 handled = 1;
245 }
246
247 spin_unlock(&uap->port.lock);
248
249 return IRQ_RETVAL(handled);
250 }
251
252 static unsigned int pl01x_tx_empty(struct uart_port *port)
253 {
254 struct uart_amba_port *uap = (struct uart_amba_port *)port;
255 unsigned int status = readw(uap->port.membase + UART01x_FR);
256 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
257 }
258
259 static unsigned int pl01x_get_mctrl(struct uart_port *port)
260 {
261 struct uart_amba_port *uap = (struct uart_amba_port *)port;
262 unsigned int result = 0;
263 unsigned int status = readw(uap->port.membase + UART01x_FR);
264
265 #define BIT(uartbit, tiocmbit) \
266 if (status & uartbit) \
267 result |= tiocmbit
268
269 BIT(UART01x_FR_DCD, TIOCM_CAR);
270 BIT(UART01x_FR_DSR, TIOCM_DSR);
271 BIT(UART01x_FR_CTS, TIOCM_CTS);
272 BIT(UART011_FR_RI, TIOCM_RNG);
273 #undef BIT
274 return result;
275 }
276
277 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
278 {
279 struct uart_amba_port *uap = (struct uart_amba_port *)port;
280 unsigned int cr;
281
282 cr = readw(uap->port.membase + UART011_CR);
283
284 #define BIT(tiocmbit, uartbit) \
285 if (mctrl & tiocmbit) \
286 cr |= uartbit; \
287 else \
288 cr &= ~uartbit
289
290 BIT(TIOCM_RTS, UART011_CR_RTS);
291 BIT(TIOCM_DTR, UART011_CR_DTR);
292 BIT(TIOCM_OUT1, UART011_CR_OUT1);
293 BIT(TIOCM_OUT2, UART011_CR_OUT2);
294 BIT(TIOCM_LOOP, UART011_CR_LBE);
295 #undef BIT
296
297 writew(cr, uap->port.membase + UART011_CR);
298 }
299
300 static void pl011_break_ctl(struct uart_port *port, int break_state)
301 {
302 struct uart_amba_port *uap = (struct uart_amba_port *)port;
303 unsigned long flags;
304 unsigned int lcr_h;
305
306 spin_lock_irqsave(&uap->port.lock, flags);
307 lcr_h = readw(uap->port.membase + UART011_LCRH);
308 if (break_state == -1)
309 lcr_h |= UART01x_LCRH_BRK;
310 else
311 lcr_h &= ~UART01x_LCRH_BRK;
312 writew(lcr_h, uap->port.membase + UART011_LCRH);
313 spin_unlock_irqrestore(&uap->port.lock, flags);
314 }
315
316 static int pl011_startup(struct uart_port *port)
317 {
318 struct uart_amba_port *uap = (struct uart_amba_port *)port;
319 unsigned int cr;
320 int retval;
321
322 /*
323 * Try to enable the clock producer.
324 */
325 retval = clk_enable(uap->clk);
326 if (retval)
327 goto out;
328
329 uap->port.uartclk = clk_get_rate(uap->clk);
330
331 /*
332 * Allocate the IRQ
333 */
334 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
335 if (retval)
336 goto clk_dis;
337
338 writew(UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
339 uap->port.membase + UART011_IFLS);
340
341 /*
342 * Provoke TX FIFO interrupt into asserting.
343 */
344 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
345 writew(cr, uap->port.membase + UART011_CR);
346 writew(0, uap->port.membase + UART011_FBRD);
347 writew(1, uap->port.membase + UART011_IBRD);
348 writew(0, uap->port.membase + UART011_LCRH);
349 writew(0, uap->port.membase + UART01x_DR);
350 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
351 barrier();
352
353 cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
354 writew(cr, uap->port.membase + UART011_CR);
355
356 /*
357 * initialise the old status of the modem signals
358 */
359 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
360
361 /*
362 * Finally, enable interrupts
363 */
364 spin_lock_irq(&uap->port.lock);
365 uap->im = UART011_RXIM | UART011_RTIM;
366 writew(uap->im, uap->port.membase + UART011_IMSC);
367 spin_unlock_irq(&uap->port.lock);
368
369 return 0;
370
371 clk_dis:
372 clk_disable(uap->clk);
373 out:
374 return retval;
375 }
376
377 static void pl011_shutdown(struct uart_port *port)
378 {
379 struct uart_amba_port *uap = (struct uart_amba_port *)port;
380 unsigned long val;
381
382 /*
383 * disable all interrupts
384 */
385 spin_lock_irq(&uap->port.lock);
386 uap->im = 0;
387 writew(uap->im, uap->port.membase + UART011_IMSC);
388 writew(0xffff, uap->port.membase + UART011_ICR);
389 spin_unlock_irq(&uap->port.lock);
390
391 /*
392 * Free the interrupt
393 */
394 free_irq(uap->port.irq, uap);
395
396 /*
397 * disable the port
398 */
399 writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
400
401 /*
402 * disable break condition and fifos
403 */
404 val = readw(uap->port.membase + UART011_LCRH);
405 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
406 writew(val, uap->port.membase + UART011_LCRH);
407
408 /*
409 * Shut down the clock producer
410 */
411 clk_disable(uap->clk);
412 }
413
414 static void
415 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
416 struct ktermios *old)
417 {
418 unsigned int lcr_h, old_cr;
419 unsigned long flags;
420 unsigned int baud, quot;
421
422 /*
423 * Ask the core to calculate the divisor for us.
424 */
425 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
426 quot = port->uartclk * 4 / baud;
427
428 switch (termios->c_cflag & CSIZE) {
429 case CS5:
430 lcr_h = UART01x_LCRH_WLEN_5;
431 break;
432 case CS6:
433 lcr_h = UART01x_LCRH_WLEN_6;
434 break;
435 case CS7:
436 lcr_h = UART01x_LCRH_WLEN_7;
437 break;
438 default: // CS8
439 lcr_h = UART01x_LCRH_WLEN_8;
440 break;
441 }
442 if (termios->c_cflag & CSTOPB)
443 lcr_h |= UART01x_LCRH_STP2;
444 if (termios->c_cflag & PARENB) {
445 lcr_h |= UART01x_LCRH_PEN;
446 if (!(termios->c_cflag & PARODD))
447 lcr_h |= UART01x_LCRH_EPS;
448 }
449 if (port->fifosize > 1)
450 lcr_h |= UART01x_LCRH_FEN;
451
452 spin_lock_irqsave(&port->lock, flags);
453
454 /*
455 * Update the per-port timeout.
456 */
457 uart_update_timeout(port, termios->c_cflag, baud);
458
459 port->read_status_mask = UART011_DR_OE | 255;
460 if (termios->c_iflag & INPCK)
461 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
462 if (termios->c_iflag & (BRKINT | PARMRK))
463 port->read_status_mask |= UART011_DR_BE;
464
465 /*
466 * Characters to ignore
467 */
468 port->ignore_status_mask = 0;
469 if (termios->c_iflag & IGNPAR)
470 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
471 if (termios->c_iflag & IGNBRK) {
472 port->ignore_status_mask |= UART011_DR_BE;
473 /*
474 * If we're ignoring parity and break indicators,
475 * ignore overruns too (for real raw support).
476 */
477 if (termios->c_iflag & IGNPAR)
478 port->ignore_status_mask |= UART011_DR_OE;
479 }
480
481 /*
482 * Ignore all characters if CREAD is not set.
483 */
484 if ((termios->c_cflag & CREAD) == 0)
485 port->ignore_status_mask |= UART_DUMMY_DR_RX;
486
487 if (UART_ENABLE_MS(port, termios->c_cflag))
488 pl011_enable_ms(port);
489
490 /* first, disable everything */
491 old_cr = readw(port->membase + UART011_CR);
492 writew(0, port->membase + UART011_CR);
493
494 /* Set baud rate */
495 writew(quot & 0x3f, port->membase + UART011_FBRD);
496 writew(quot >> 6, port->membase + UART011_IBRD);
497
498 /*
499 * ----------v----------v----------v----------v-----
500 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
501 * ----------^----------^----------^----------^-----
502 */
503 writew(lcr_h, port->membase + UART011_LCRH);
504 writew(old_cr, port->membase + UART011_CR);
505
506 spin_unlock_irqrestore(&port->lock, flags);
507 }
508
509 static const char *pl011_type(struct uart_port *port)
510 {
511 return port->type == PORT_AMBA ? "AMBA/PL011" : NULL;
512 }
513
514 /*
515 * Release the memory region(s) being used by 'port'
516 */
517 static void pl010_release_port(struct uart_port *port)
518 {
519 release_mem_region(port->mapbase, SZ_4K);
520 }
521
522 /*
523 * Request the memory region(s) being used by 'port'
524 */
525 static int pl010_request_port(struct uart_port *port)
526 {
527 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
528 != NULL ? 0 : -EBUSY;
529 }
530
531 /*
532 * Configure/autoconfigure the port.
533 */
534 static void pl010_config_port(struct uart_port *port, int flags)
535 {
536 if (flags & UART_CONFIG_TYPE) {
537 port->type = PORT_AMBA;
538 pl010_request_port(port);
539 }
540 }
541
542 /*
543 * verify the new serial_struct (for TIOCSSERIAL).
544 */
545 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
546 {
547 int ret = 0;
548 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
549 ret = -EINVAL;
550 if (ser->irq < 0 || ser->irq >= NR_IRQS)
551 ret = -EINVAL;
552 if (ser->baud_base < 9600)
553 ret = -EINVAL;
554 return ret;
555 }
556
557 static struct uart_ops amba_pl011_pops = {
558 .tx_empty = pl01x_tx_empty,
559 .set_mctrl = pl011_set_mctrl,
560 .get_mctrl = pl01x_get_mctrl,
561 .stop_tx = pl011_stop_tx,
562 .start_tx = pl011_start_tx,
563 .stop_rx = pl011_stop_rx,
564 .enable_ms = pl011_enable_ms,
565 .break_ctl = pl011_break_ctl,
566 .startup = pl011_startup,
567 .shutdown = pl011_shutdown,
568 .set_termios = pl011_set_termios,
569 .type = pl011_type,
570 .release_port = pl010_release_port,
571 .request_port = pl010_request_port,
572 .config_port = pl010_config_port,
573 .verify_port = pl010_verify_port,
574 };
575
576 static struct uart_amba_port *amba_ports[UART_NR];
577
578 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
579
580 static void pl011_console_putchar(struct uart_port *port, int ch)
581 {
582 struct uart_amba_port *uap = (struct uart_amba_port *)port;
583
584 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
585 barrier();
586 writew(ch, uap->port.membase + UART01x_DR);
587 }
588
589 static void
590 pl011_console_write(struct console *co, const char *s, unsigned int count)
591 {
592 struct uart_amba_port *uap = amba_ports[co->index];
593 unsigned int status, old_cr, new_cr;
594
595 clk_enable(uap->clk);
596
597 /*
598 * First save the CR then disable the interrupts
599 */
600 old_cr = readw(uap->port.membase + UART011_CR);
601 new_cr = old_cr & ~UART011_CR_CTSEN;
602 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
603 writew(new_cr, uap->port.membase + UART011_CR);
604
605 uart_console_write(&uap->port, s, count, pl011_console_putchar);
606
607 /*
608 * Finally, wait for transmitter to become empty
609 * and restore the TCR
610 */
611 do {
612 status = readw(uap->port.membase + UART01x_FR);
613 } while (status & UART01x_FR_BUSY);
614 writew(old_cr, uap->port.membase + UART011_CR);
615
616 clk_disable(uap->clk);
617 }
618
619 static void __init
620 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
621 int *parity, int *bits)
622 {
623 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
624 unsigned int lcr_h, ibrd, fbrd;
625
626 lcr_h = readw(uap->port.membase + UART011_LCRH);
627
628 *parity = 'n';
629 if (lcr_h & UART01x_LCRH_PEN) {
630 if (lcr_h & UART01x_LCRH_EPS)
631 *parity = 'e';
632 else
633 *parity = 'o';
634 }
635
636 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
637 *bits = 7;
638 else
639 *bits = 8;
640
641 ibrd = readw(uap->port.membase + UART011_IBRD);
642 fbrd = readw(uap->port.membase + UART011_FBRD);
643
644 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
645 }
646 }
647
648 static int __init pl011_console_setup(struct console *co, char *options)
649 {
650 struct uart_amba_port *uap;
651 int baud = 38400;
652 int bits = 8;
653 int parity = 'n';
654 int flow = 'n';
655
656 /*
657 * Check whether an invalid uart number has been specified, and
658 * if so, search for the first available port that does have
659 * console support.
660 */
661 if (co->index >= UART_NR)
662 co->index = 0;
663 uap = amba_ports[co->index];
664 if (!uap)
665 return -ENODEV;
666
667 uap->port.uartclk = clk_get_rate(uap->clk);
668
669 if (options)
670 uart_parse_options(options, &baud, &parity, &bits, &flow);
671 else
672 pl011_console_get_options(uap, &baud, &parity, &bits);
673
674 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
675 }
676
677 static struct uart_driver amba_reg;
678 static struct console amba_console = {
679 .name = "ttyAMA",
680 .write = pl011_console_write,
681 .device = uart_console_device,
682 .setup = pl011_console_setup,
683 .flags = CON_PRINTBUFFER,
684 .index = -1,
685 .data = &amba_reg,
686 };
687
688 #define AMBA_CONSOLE (&amba_console)
689 #else
690 #define AMBA_CONSOLE NULL
691 #endif
692
693 static struct uart_driver amba_reg = {
694 .owner = THIS_MODULE,
695 .driver_name = "ttyAMA",
696 .dev_name = "ttyAMA",
697 .major = SERIAL_AMBA_MAJOR,
698 .minor = SERIAL_AMBA_MINOR,
699 .nr = UART_NR,
700 .cons = AMBA_CONSOLE,
701 };
702
703 static int pl011_probe(struct amba_device *dev, void *id)
704 {
705 struct uart_amba_port *uap;
706 void __iomem *base;
707 int i, ret;
708
709 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
710 if (amba_ports[i] == NULL)
711 break;
712
713 if (i == ARRAY_SIZE(amba_ports)) {
714 ret = -EBUSY;
715 goto out;
716 }
717
718 uap = kmalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
719 if (uap == NULL) {
720 ret = -ENOMEM;
721 goto out;
722 }
723
724 base = ioremap(dev->res.start, PAGE_SIZE);
725 if (!base) {
726 ret = -ENOMEM;
727 goto free;
728 }
729
730 memset(uap, 0, sizeof(struct uart_amba_port));
731 uap->clk = clk_get(&dev->dev, "UARTCLK");
732 if (IS_ERR(uap->clk)) {
733 ret = PTR_ERR(uap->clk);
734 goto unmap;
735 }
736
737 uap->port.dev = &dev->dev;
738 uap->port.mapbase = dev->res.start;
739 uap->port.membase = base;
740 uap->port.iotype = UPIO_MEM;
741 uap->port.irq = dev->irq[0];
742 uap->port.fifosize = 16;
743 uap->port.ops = &amba_pl011_pops;
744 uap->port.flags = UPF_BOOT_AUTOCONF;
745 uap->port.line = i;
746
747 amba_ports[i] = uap;
748
749 amba_set_drvdata(dev, uap);
750 ret = uart_add_one_port(&amba_reg, &uap->port);
751 if (ret) {
752 amba_set_drvdata(dev, NULL);
753 amba_ports[i] = NULL;
754 clk_put(uap->clk);
755 unmap:
756 iounmap(base);
757 free:
758 kfree(uap);
759 }
760 out:
761 return ret;
762 }
763
764 static int pl011_remove(struct amba_device *dev)
765 {
766 struct uart_amba_port *uap = amba_get_drvdata(dev);
767 int i;
768
769 amba_set_drvdata(dev, NULL);
770
771 uart_remove_one_port(&amba_reg, &uap->port);
772
773 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
774 if (amba_ports[i] == uap)
775 amba_ports[i] = NULL;
776
777 iounmap(uap->port.membase);
778 clk_put(uap->clk);
779 kfree(uap);
780 return 0;
781 }
782
783 static struct amba_id pl011_ids[] __initdata = {
784 {
785 .id = 0x00041011,
786 .mask = 0x000fffff,
787 },
788 { 0, 0 },
789 };
790
791 static struct amba_driver pl011_driver = {
792 .drv = {
793 .name = "uart-pl011",
794 },
795 .id_table = pl011_ids,
796 .probe = pl011_probe,
797 .remove = pl011_remove,
798 };
799
800 static int __init pl011_init(void)
801 {
802 int ret;
803 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
804
805 ret = uart_register_driver(&amba_reg);
806 if (ret == 0) {
807 ret = amba_driver_register(&pl011_driver);
808 if (ret)
809 uart_unregister_driver(&amba_reg);
810 }
811 return ret;
812 }
813
814 static void __exit pl011_exit(void)
815 {
816 amba_driver_unregister(&pl011_driver);
817 uart_unregister_driver(&amba_reg);
818 }
819
820 module_init(pl011_init);
821 module_exit(pl011_exit);
822
823 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
824 MODULE_DESCRIPTION("ARM AMBA serial port driver");
825 MODULE_LICENSE("GPL");
Linux with added FPC-III support