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Linux 2.6.20.7
[linux/fpc-iii.git] / drivers / serial / ioc4_serial.c
blobc862f67c985af312b15f11d68cb29390688bfacb
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9
10 /*
11 * This file contains a module version of the ioc4 serial driver. This
12 * includes all the support functions needed (support functions, etc.)
13 * and the serial driver itself.
14 */
15 #include <linux/errno.h>
16 #include <linux/tty.h>
17 #include <linux/serial.h>
18 #include <linux/serialP.h>
19 #include <linux/circ_buf.h>
20 #include <linux/serial_reg.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/ioc4.h>
24 #include <linux/serial_core.h>
25
26 /*
27 * interesting things about the ioc4
28 */
29
30 #define IOC4_NUM_SERIAL_PORTS 4 /* max ports per card */
31 #define IOC4_NUM_CARDS 8 /* max cards per partition */
32
33 #define GET_SIO_IR(_n) (_n == 0) ? (IOC4_SIO_IR_S0) : \
34 (_n == 1) ? (IOC4_SIO_IR_S1) : \
35 (_n == 2) ? (IOC4_SIO_IR_S2) : \
36 (IOC4_SIO_IR_S3)
37
38 #define GET_OTHER_IR(_n) (_n == 0) ? (IOC4_OTHER_IR_S0_MEMERR) : \
39 (_n == 1) ? (IOC4_OTHER_IR_S1_MEMERR) : \
40 (_n == 2) ? (IOC4_OTHER_IR_S2_MEMERR) : \
41 (IOC4_OTHER_IR_S3_MEMERR)
42
43
44 /*
45 * All IOC4 registers are 32 bits wide.
46 */
47
48 /*
49 * PCI Memory Space Map
50 */
51 #define IOC4_PCI_ERR_ADDR_L 0x000 /* Low Error Address */
52 #define IOC4_PCI_ERR_ADDR_VLD (0x1 << 0)
53 #define IOC4_PCI_ERR_ADDR_MST_ID_MSK (0xf << 1)
54 #define IOC4_PCI_ERR_ADDR_MST_NUM_MSK (0xe << 1)
55 #define IOC4_PCI_ERR_ADDR_MST_TYP_MSK (0x1 << 1)
56 #define IOC4_PCI_ERR_ADDR_MUL_ERR (0x1 << 5)
57 #define IOC4_PCI_ERR_ADDR_ADDR_MSK (0x3ffffff << 6)
58
59 /* Interrupt types */
60 #define IOC4_SIO_INTR_TYPE 0
61 #define IOC4_OTHER_INTR_TYPE 1
62 #define IOC4_NUM_INTR_TYPES 2
63
64 /* Bitmasks for IOC4_SIO_IR, IOC4_SIO_IEC, and IOC4_SIO_IES */
65 #define IOC4_SIO_IR_S0_TX_MT 0x00000001 /* Serial port 0 TX empty */
66 #define IOC4_SIO_IR_S0_RX_FULL 0x00000002 /* Port 0 RX buf full */
67 #define IOC4_SIO_IR_S0_RX_HIGH 0x00000004 /* Port 0 RX hiwat */
68 #define IOC4_SIO_IR_S0_RX_TIMER 0x00000008 /* Port 0 RX timeout */
69 #define IOC4_SIO_IR_S0_DELTA_DCD 0x00000010 /* Port 0 delta DCD */
70 #define IOC4_SIO_IR_S0_DELTA_CTS 0x00000020 /* Port 0 delta CTS */
71 #define IOC4_SIO_IR_S0_INT 0x00000040 /* Port 0 pass-thru intr */
72 #define IOC4_SIO_IR_S0_TX_EXPLICIT 0x00000080 /* Port 0 explicit TX thru */
73 #define IOC4_SIO_IR_S1_TX_MT 0x00000100 /* Serial port 1 */
74 #define IOC4_SIO_IR_S1_RX_FULL 0x00000200 /* */
75 #define IOC4_SIO_IR_S1_RX_HIGH 0x00000400 /* */
76 #define IOC4_SIO_IR_S1_RX_TIMER 0x00000800 /* */
77 #define IOC4_SIO_IR_S1_DELTA_DCD 0x00001000 /* */
78 #define IOC4_SIO_IR_S1_DELTA_CTS 0x00002000 /* */
79 #define IOC4_SIO_IR_S1_INT 0x00004000 /* */
80 #define IOC4_SIO_IR_S1_TX_EXPLICIT 0x00008000 /* */
81 #define IOC4_SIO_IR_S2_TX_MT 0x00010000 /* Serial port 2 */
82 #define IOC4_SIO_IR_S2_RX_FULL 0x00020000 /* */
83 #define IOC4_SIO_IR_S2_RX_HIGH 0x00040000 /* */
84 #define IOC4_SIO_IR_S2_RX_TIMER 0x00080000 /* */
85 #define IOC4_SIO_IR_S2_DELTA_DCD 0x00100000 /* */
86 #define IOC4_SIO_IR_S2_DELTA_CTS 0x00200000 /* */
87 #define IOC4_SIO_IR_S2_INT 0x00400000 /* */
88 #define IOC4_SIO_IR_S2_TX_EXPLICIT 0x00800000 /* */
89 #define IOC4_SIO_IR_S3_TX_MT 0x01000000 /* Serial port 3 */
90 #define IOC4_SIO_IR_S3_RX_FULL 0x02000000 /* */
91 #define IOC4_SIO_IR_S3_RX_HIGH 0x04000000 /* */
92 #define IOC4_SIO_IR_S3_RX_TIMER 0x08000000 /* */
93 #define IOC4_SIO_IR_S3_DELTA_DCD 0x10000000 /* */
94 #define IOC4_SIO_IR_S3_DELTA_CTS 0x20000000 /* */
95 #define IOC4_SIO_IR_S3_INT 0x40000000 /* */
96 #define IOC4_SIO_IR_S3_TX_EXPLICIT 0x80000000 /* */
97
98 /* Per device interrupt masks */
99 #define IOC4_SIO_IR_S0 (IOC4_SIO_IR_S0_TX_MT | \
100 IOC4_SIO_IR_S0_RX_FULL | \
101 IOC4_SIO_IR_S0_RX_HIGH | \
102 IOC4_SIO_IR_S0_RX_TIMER | \
103 IOC4_SIO_IR_S0_DELTA_DCD | \
104 IOC4_SIO_IR_S0_DELTA_CTS | \
105 IOC4_SIO_IR_S0_INT | \
106 IOC4_SIO_IR_S0_TX_EXPLICIT)
107 #define IOC4_SIO_IR_S1 (IOC4_SIO_IR_S1_TX_MT | \
108 IOC4_SIO_IR_S1_RX_FULL | \
109 IOC4_SIO_IR_S1_RX_HIGH | \
110 IOC4_SIO_IR_S1_RX_TIMER | \
111 IOC4_SIO_IR_S1_DELTA_DCD | \
112 IOC4_SIO_IR_S1_DELTA_CTS | \
113 IOC4_SIO_IR_S1_INT | \
114 IOC4_SIO_IR_S1_TX_EXPLICIT)
115 #define IOC4_SIO_IR_S2 (IOC4_SIO_IR_S2_TX_MT | \
116 IOC4_SIO_IR_S2_RX_FULL | \
117 IOC4_SIO_IR_S2_RX_HIGH | \
118 IOC4_SIO_IR_S2_RX_TIMER | \
119 IOC4_SIO_IR_S2_DELTA_DCD | \
120 IOC4_SIO_IR_S2_DELTA_CTS | \
121 IOC4_SIO_IR_S2_INT | \
122 IOC4_SIO_IR_S2_TX_EXPLICIT)
123 #define IOC4_SIO_IR_S3 (IOC4_SIO_IR_S3_TX_MT | \
124 IOC4_SIO_IR_S3_RX_FULL | \
125 IOC4_SIO_IR_S3_RX_HIGH | \
126 IOC4_SIO_IR_S3_RX_TIMER | \
127 IOC4_SIO_IR_S3_DELTA_DCD | \
128 IOC4_SIO_IR_S3_DELTA_CTS | \
129 IOC4_SIO_IR_S3_INT | \
130 IOC4_SIO_IR_S3_TX_EXPLICIT)
131
132 /* Bitmasks for IOC4_OTHER_IR, IOC4_OTHER_IEC, and IOC4_OTHER_IES */
133 #define IOC4_OTHER_IR_ATA_INT 0x00000001 /* ATAPI intr pass-thru */
134 #define IOC4_OTHER_IR_ATA_MEMERR 0x00000002 /* ATAPI DMA PCI error */
135 #define IOC4_OTHER_IR_S0_MEMERR 0x00000004 /* Port 0 PCI error */
136 #define IOC4_OTHER_IR_S1_MEMERR 0x00000008 /* Port 1 PCI error */
137 #define IOC4_OTHER_IR_S2_MEMERR 0x00000010 /* Port 2 PCI error */
138 #define IOC4_OTHER_IR_S3_MEMERR 0x00000020 /* Port 3 PCI error */
139 #define IOC4_OTHER_IR_KBD_INT 0x00000040 /* Keyboard/mouse */
140 #define IOC4_OTHER_IR_RESERVED 0x007fff80 /* Reserved */
141 #define IOC4_OTHER_IR_RT_INT 0x00800000 /* INT_OUT section output */
142 #define IOC4_OTHER_IR_GEN_INT 0xff000000 /* Generic pins */
143
144 #define IOC4_OTHER_IR_SER_MEMERR (IOC4_OTHER_IR_S0_MEMERR | IOC4_OTHER_IR_S1_MEMERR | \
145 IOC4_OTHER_IR_S2_MEMERR | IOC4_OTHER_IR_S3_MEMERR)
146
147 /* Bitmasks for IOC4_SIO_CR */
148 #define IOC4_SIO_CR_CMD_PULSE_SHIFT 0 /* byte bus strobe shift */
149 #define IOC4_SIO_CR_ARB_DIAG_TX0 0x00000000
150 #define IOC4_SIO_CR_ARB_DIAG_RX0 0x00000010
151 #define IOC4_SIO_CR_ARB_DIAG_TX1 0x00000020
152 #define IOC4_SIO_CR_ARB_DIAG_RX1 0x00000030
153 #define IOC4_SIO_CR_ARB_DIAG_TX2 0x00000040
154 #define IOC4_SIO_CR_ARB_DIAG_RX2 0x00000050
155 #define IOC4_SIO_CR_ARB_DIAG_TX3 0x00000060
156 #define IOC4_SIO_CR_ARB_DIAG_RX3 0x00000070
157 #define IOC4_SIO_CR_SIO_DIAG_IDLE 0x00000080 /* 0 -> active request among
158 serial ports (ro) */
159 /* Defs for some of the generic I/O pins */
160 #define IOC4_GPCR_UART0_MODESEL 0x10 /* Pin is output to port 0
161 mode sel */
162 #define IOC4_GPCR_UART1_MODESEL 0x20 /* Pin is output to port 1
163 mode sel */
164 #define IOC4_GPCR_UART2_MODESEL 0x40 /* Pin is output to port 2
165 mode sel */
166 #define IOC4_GPCR_UART3_MODESEL 0x80 /* Pin is output to port 3
167 mode sel */
168
169 #define IOC4_GPPR_UART0_MODESEL_PIN 4 /* GIO pin controlling
170 uart 0 mode select */
171 #define IOC4_GPPR_UART1_MODESEL_PIN 5 /* GIO pin controlling
172 uart 1 mode select */
173 #define IOC4_GPPR_UART2_MODESEL_PIN 6 /* GIO pin controlling
174 uart 2 mode select */
175 #define IOC4_GPPR_UART3_MODESEL_PIN 7 /* GIO pin controlling
176 uart 3 mode select */
177
178 /* Bitmasks for serial RX status byte */
179 #define IOC4_RXSB_OVERRUN 0x01 /* Char(s) lost */
180 #define IOC4_RXSB_PAR_ERR 0x02 /* Parity error */
181 #define IOC4_RXSB_FRAME_ERR 0x04 /* Framing error */
182 #define IOC4_RXSB_BREAK 0x08 /* Break character */
183 #define IOC4_RXSB_CTS 0x10 /* State of CTS */
184 #define IOC4_RXSB_DCD 0x20 /* State of DCD */
185 #define IOC4_RXSB_MODEM_VALID 0x40 /* DCD, CTS, and OVERRUN are valid */
186 #define IOC4_RXSB_DATA_VALID 0x80 /* Data byte, FRAME_ERR PAR_ERR
187 * & BREAK valid */
188
189 /* Bitmasks for serial TX control byte */
190 #define IOC4_TXCB_INT_WHEN_DONE 0x20 /* Interrupt after this byte is sent */
191 #define IOC4_TXCB_INVALID 0x00 /* Byte is invalid */
192 #define IOC4_TXCB_VALID 0x40 /* Byte is valid */
193 #define IOC4_TXCB_MCR 0x80 /* Data<7:0> to modem control reg */
194 #define IOC4_TXCB_DELAY 0xc0 /* Delay data<7:0> mSec */
195
196 /* Bitmasks for IOC4_SBBR_L */
197 #define IOC4_SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */
198
199 /* Bitmasks for IOC4_SSCR_<3:0> */
200 #define IOC4_SSCR_RX_THRESHOLD 0x000001ff /* Hiwater mark */
201 #define IOC4_SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
202 #define IOC4_SSCR_HFC_EN 0x00020000 /* Hardware flow control enabled */
203 #define IOC4_SSCR_RX_RING_DCD 0x00040000 /* Post RX record on delta-DCD */
204 #define IOC4_SSCR_RX_RING_CTS 0x00080000 /* Post RX record on delta-CTS */
205 #define IOC4_SSCR_DIAG 0x00200000 /* Bypass clock divider for sim */
206 #define IOC4_SSCR_RX_DRAIN 0x08000000 /* Drain RX buffer to memory */
207 #define IOC4_SSCR_DMA_EN 0x10000000 /* Enable ring buffer DMA */
208 #define IOC4_SSCR_DMA_PAUSE 0x20000000 /* Pause DMA */
209 #define IOC4_SSCR_PAUSE_STATE 0x40000000 /* Sets when PAUSE takes effect */
210 #define IOC4_SSCR_RESET 0x80000000 /* Reset DMA channels */
211
212 /* All producer/comsumer pointers are the same bitfield */
213 #define IOC4_PROD_CONS_PTR_4K 0x00000ff8 /* For 4K buffers */
214 #define IOC4_PROD_CONS_PTR_1K 0x000003f8 /* For 1K buffers */
215 #define IOC4_PROD_CONS_PTR_OFF 3
216
217 /* Bitmasks for IOC4_SRCIR_<3:0> */
218 #define IOC4_SRCIR_ARM 0x80000000 /* Arm RX timer */
219
220 /* Bitmasks for IOC4_SHADOW_<3:0> */
221 #define IOC4_SHADOW_DR 0x00000001 /* Data ready */
222 #define IOC4_SHADOW_OE 0x00000002 /* Overrun error */
223 #define IOC4_SHADOW_PE 0x00000004 /* Parity error */
224 #define IOC4_SHADOW_FE 0x00000008 /* Framing error */
225 #define IOC4_SHADOW_BI 0x00000010 /* Break interrupt */
226 #define IOC4_SHADOW_THRE 0x00000020 /* Xmit holding register empty */
227 #define IOC4_SHADOW_TEMT 0x00000040 /* Xmit shift register empty */
228 #define IOC4_SHADOW_RFCE 0x00000080 /* Char in RX fifo has an error */
229 #define IOC4_SHADOW_DCTS 0x00010000 /* Delta clear to send */
230 #define IOC4_SHADOW_DDCD 0x00080000 /* Delta data carrier detect */
231 #define IOC4_SHADOW_CTS 0x00100000 /* Clear to send */
232 #define IOC4_SHADOW_DCD 0x00800000 /* Data carrier detect */
233 #define IOC4_SHADOW_DTR 0x01000000 /* Data terminal ready */
234 #define IOC4_SHADOW_RTS 0x02000000 /* Request to send */
235 #define IOC4_SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
236 #define IOC4_SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
237 #define IOC4_SHADOW_LOOP 0x10000000 /* Loopback enabled */
238
239 /* Bitmasks for IOC4_SRTR_<3:0> */
240 #define IOC4_SRTR_CNT 0x00000fff /* Reload value for RX timer */
241 #define IOC4_SRTR_CNT_VAL 0x0fff0000 /* Current value of RX timer */
242 #define IOC4_SRTR_CNT_VAL_SHIFT 16
243 #define IOC4_SRTR_HZ 16000 /* SRTR clock frequency */
244
245 /* Serial port register map used for DMA and PIO serial I/O */
246 struct ioc4_serialregs {
247 uint32_t sscr;
248 uint32_t stpir;
249 uint32_t stcir;
250 uint32_t srpir;
251 uint32_t srcir;
252 uint32_t srtr;
253 uint32_t shadow;
254 };
255
256 /* IOC4 UART register map */
257 struct ioc4_uartregs {
258 char i4u_lcr;
259 union {
260 char iir; /* read only */
261 char fcr; /* write only */
262 } u3;
263 union {
264 char ier; /* DLAB == 0 */
265 char dlm; /* DLAB == 1 */
266 } u2;
267 union {
268 char rbr; /* read only, DLAB == 0 */
269 char thr; /* write only, DLAB == 0 */
270 char dll; /* DLAB == 1 */
271 } u1;
272 char i4u_scr;
273 char i4u_msr;
274 char i4u_lsr;
275 char i4u_mcr;
276 };
277
278 /* short names */
279 #define i4u_dll u1.dll
280 #define i4u_ier u2.ier
281 #define i4u_dlm u2.dlm
282 #define i4u_fcr u3.fcr
283
284 /* Serial port registers used for DMA serial I/O */
285 struct ioc4_serial {
286 uint32_t sbbr01_l;
287 uint32_t sbbr01_h;
288 uint32_t sbbr23_l;
289 uint32_t sbbr23_h;
290
291 struct ioc4_serialregs port_0;
292 struct ioc4_serialregs port_1;
293 struct ioc4_serialregs port_2;
294 struct ioc4_serialregs port_3;
295 struct ioc4_uartregs uart_0;
296 struct ioc4_uartregs uart_1;
297 struct ioc4_uartregs uart_2;
298 struct ioc4_uartregs uart_3;
299 } ioc4_serial;
300
301 /* UART clock speed */
302 #define IOC4_SER_XIN_CLK_66 66666667
303 #define IOC4_SER_XIN_CLK_33 33333333
304
305 #define IOC4_W_IES 0
306 #define IOC4_W_IEC 1
307
308 typedef void ioc4_intr_func_f(void *, uint32_t);
309 typedef ioc4_intr_func_f *ioc4_intr_func_t;
310
311 static unsigned int Num_of_ioc4_cards;
312
313 /* defining this will get you LOTS of great debug info */
314 //#define DEBUG_INTERRUPTS
315 #define DPRINT_CONFIG(_x...) ;
316 //#define DPRINT_CONFIG(_x...) printk _x
317
318 /* number of characters left in xmit buffer before we ask for more */
319 #define WAKEUP_CHARS 256
320
321 /* number of characters we want to transmit to the lower level at a time */
322 #define IOC4_MAX_CHARS 256
323 #define IOC4_FIFO_CHARS 255
324
325 /* Device name we're using */
326 #define DEVICE_NAME_RS232 "ttyIOC"
327 #define DEVICE_NAME_RS422 "ttyAIOC"
328 #define DEVICE_MAJOR 204
329 #define DEVICE_MINOR_RS232 50
330 #define DEVICE_MINOR_RS422 84
331
332
333 /* register offsets */
334 #define IOC4_SERIAL_OFFSET 0x300
335
336 /* flags for next_char_state */
337 #define NCS_BREAK 0x1
338 #define NCS_PARITY 0x2
339 #define NCS_FRAMING 0x4
340 #define NCS_OVERRUN 0x8
341
342 /* cause we need SOME parameters ... */
343 #define MIN_BAUD_SUPPORTED 1200
344 #define MAX_BAUD_SUPPORTED 115200
345
346 /* protocol types supported */
347 #define PROTO_RS232 3
348 #define PROTO_RS422 7
349
350 /* Notification types */
351 #define N_DATA_READY 0x01
352 #define N_OUTPUT_LOWAT 0x02
353 #define N_BREAK 0x04
354 #define N_PARITY_ERROR 0x08
355 #define N_FRAMING_ERROR 0x10
356 #define N_OVERRUN_ERROR 0x20
357 #define N_DDCD 0x40
358 #define N_DCTS 0x80
359
360 #define N_ALL_INPUT (N_DATA_READY | N_BREAK | \
361 N_PARITY_ERROR | N_FRAMING_ERROR | \
362 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
363
364 #define N_ALL_OUTPUT N_OUTPUT_LOWAT
365
366 #define N_ALL_ERRORS (N_PARITY_ERROR | N_FRAMING_ERROR | N_OVERRUN_ERROR)
367
368 #define N_ALL (N_DATA_READY | N_OUTPUT_LOWAT | N_BREAK | \
369 N_PARITY_ERROR | N_FRAMING_ERROR | \
370 N_OVERRUN_ERROR | N_DDCD | N_DCTS)
371
372 #define SER_DIVISOR(_x, clk) (((clk) + (_x) * 8) / ((_x) * 16))
373 #define DIVISOR_TO_BAUD(div, clk) ((clk) / 16 / (div))
374
375 /* Some masks */
376 #define LCR_MASK_BITS_CHAR (UART_LCR_WLEN5 | UART_LCR_WLEN6 \
377 | UART_LCR_WLEN7 | UART_LCR_WLEN8)
378 #define LCR_MASK_STOP_BITS (UART_LCR_STOP)
379
380 #define PENDING(_p) (readl(&(_p)->ip_mem->sio_ir.raw) & _p->ip_ienb)
381 #define READ_SIO_IR(_p) readl(&(_p)->ip_mem->sio_ir.raw)
382
383 /* Default to 4k buffers */
384 #ifdef IOC4_1K_BUFFERS
385 #define RING_BUF_SIZE 1024
386 #define IOC4_BUF_SIZE_BIT 0
387 #define PROD_CONS_MASK IOC4_PROD_CONS_PTR_1K
388 #else
389 #define RING_BUF_SIZE 4096
390 #define IOC4_BUF_SIZE_BIT IOC4_SBBR_L_SIZE
391 #define PROD_CONS_MASK IOC4_PROD_CONS_PTR_4K
392 #endif
393
394 #define TOTAL_RING_BUF_SIZE (RING_BUF_SIZE * 4)
395
396 /*
397 * This is the entry saved by the driver - one per card
398 */
399
400 #define UART_PORT_MIN 0
401 #define UART_PORT_RS232 UART_PORT_MIN
402 #define UART_PORT_RS422 1
403 #define UART_PORT_COUNT 2 /* one for each mode */
404
405 struct ioc4_control {
406 int ic_irq;
407 struct {
408 /* uart ports are allocated here - 1 for rs232, 1 for rs422 */
409 struct uart_port icp_uart_port[UART_PORT_COUNT];
410 /* Handy reference material */
411 struct ioc4_port *icp_port;
412 } ic_port[IOC4_NUM_SERIAL_PORTS];
413 struct ioc4_soft *ic_soft;
414 };
415
416 /*
417 * per-IOC4 data structure
418 */
419 #define MAX_IOC4_INTR_ENTS (8 * sizeof(uint32_t))
420 struct ioc4_soft {
421 struct ioc4_misc_regs __iomem *is_ioc4_misc_addr;
422 struct ioc4_serial __iomem *is_ioc4_serial_addr;
423
424 /* Each interrupt type has an entry in the array */
425 struct ioc4_intr_type {
426
427 /*
428 * Each in-use entry in this array contains at least
429 * one nonzero bit in sd_bits; no two entries in this
430 * array have overlapping sd_bits values.
431 */
432 struct ioc4_intr_info {
433 uint32_t sd_bits;
434 ioc4_intr_func_f *sd_intr;
435 void *sd_info;
436 } is_intr_info[MAX_IOC4_INTR_ENTS];
437
438 /* Number of entries active in the above array */
439 atomic_t is_num_intrs;
440 } is_intr_type[IOC4_NUM_INTR_TYPES];
441
442 /* is_ir_lock must be held while
443 * modifying sio_ie values, so
444 * we can be sure that sio_ie is
445 * not changing when we read it
446 * along with sio_ir.
447 */
448 spinlock_t is_ir_lock; /* SIO_IE[SC] mod lock */
449 };
450
451 /* Local port info for each IOC4 serial ports */
452 struct ioc4_port {
453 struct uart_port *ip_port; /* current active port ptr */
454 /* Ptrs for all ports */
455 struct uart_port *ip_all_ports[UART_PORT_COUNT];
456 /* Back ptrs for this port */
457 struct ioc4_control *ip_control;
458 struct pci_dev *ip_pdev;
459 struct ioc4_soft *ip_ioc4_soft;
460
461 /* pci mem addresses */
462 struct ioc4_misc_regs __iomem *ip_mem;
463 struct ioc4_serial __iomem *ip_serial;
464 struct ioc4_serialregs __iomem *ip_serial_regs;
465 struct ioc4_uartregs __iomem *ip_uart_regs;
466
467 /* Ring buffer page for this port */
468 dma_addr_t ip_dma_ringbuf;
469 /* vaddr of ring buffer */
470 struct ring_buffer *ip_cpu_ringbuf;
471
472 /* Rings for this port */
473 struct ring *ip_inring;
474 struct ring *ip_outring;
475
476 /* Hook to port specific values */
477 struct hooks *ip_hooks;
478
479 spinlock_t ip_lock;
480
481 /* Various rx/tx parameters */
482 int ip_baud;
483 int ip_tx_lowat;
484 int ip_rx_timeout;
485
486 /* Copy of notification bits */
487 int ip_notify;
488
489 /* Shadow copies of various registers so we don't need to PIO
490 * read them constantly
491 */
492 uint32_t ip_ienb; /* Enabled interrupts */
493 uint32_t ip_sscr;
494 uint32_t ip_tx_prod;
495 uint32_t ip_rx_cons;
496 int ip_pci_bus_speed;
497 unsigned char ip_flags;
498 };
499
500 /* tx low water mark. We need to notify the driver whenever tx is getting
501 * close to empty so it can refill the tx buffer and keep things going.
502 * Let's assume that if we interrupt 1 ms before the tx goes idle, we'll
503 * have no trouble getting in more chars in time (I certainly hope so).
504 */
505 #define TX_LOWAT_LATENCY 1000
506 #define TX_LOWAT_HZ (1000000 / TX_LOWAT_LATENCY)
507 #define TX_LOWAT_CHARS(baud) (baud / 10 / TX_LOWAT_HZ)
508
509 /* Flags per port */
510 #define INPUT_HIGH 0x01
511 #define DCD_ON 0x02
512 #define LOWAT_WRITTEN 0x04
513 #define READ_ABORTED 0x08
514 #define PORT_ACTIVE 0x10
515 #define PORT_INACTIVE 0 /* This is the value when "off" */
516
517
518 /* Since each port has different register offsets and bitmasks
519 * for everything, we'll store those that we need in tables so we
520 * don't have to be constantly checking the port we are dealing with.
521 */
522 struct hooks {
523 uint32_t intr_delta_dcd;
524 uint32_t intr_delta_cts;
525 uint32_t intr_tx_mt;
526 uint32_t intr_rx_timer;
527 uint32_t intr_rx_high;
528 uint32_t intr_tx_explicit;
529 uint32_t intr_dma_error;
530 uint32_t intr_clear;
531 uint32_t intr_all;
532 int rs422_select_pin;
533 };
534
535 static struct hooks hooks_array[IOC4_NUM_SERIAL_PORTS] = {
536 /* Values for port 0 */
537 {
538 IOC4_SIO_IR_S0_DELTA_DCD, IOC4_SIO_IR_S0_DELTA_CTS,
539 IOC4_SIO_IR_S0_TX_MT, IOC4_SIO_IR_S0_RX_TIMER,
540 IOC4_SIO_IR_S0_RX_HIGH, IOC4_SIO_IR_S0_TX_EXPLICIT,
541 IOC4_OTHER_IR_S0_MEMERR,
542 (IOC4_SIO_IR_S0_TX_MT | IOC4_SIO_IR_S0_RX_FULL |
543 IOC4_SIO_IR_S0_RX_HIGH | IOC4_SIO_IR_S0_RX_TIMER |
544 IOC4_SIO_IR_S0_DELTA_DCD | IOC4_SIO_IR_S0_DELTA_CTS |
545 IOC4_SIO_IR_S0_INT | IOC4_SIO_IR_S0_TX_EXPLICIT),
546 IOC4_SIO_IR_S0, IOC4_GPPR_UART0_MODESEL_PIN,
547 },
548
549 /* Values for port 1 */
550 {
551 IOC4_SIO_IR_S1_DELTA_DCD, IOC4_SIO_IR_S1_DELTA_CTS,
552 IOC4_SIO_IR_S1_TX_MT, IOC4_SIO_IR_S1_RX_TIMER,
553 IOC4_SIO_IR_S1_RX_HIGH, IOC4_SIO_IR_S1_TX_EXPLICIT,
554 IOC4_OTHER_IR_S1_MEMERR,
555 (IOC4_SIO_IR_S1_TX_MT | IOC4_SIO_IR_S1_RX_FULL |
556 IOC4_SIO_IR_S1_RX_HIGH | IOC4_SIO_IR_S1_RX_TIMER |
557 IOC4_SIO_IR_S1_DELTA_DCD | IOC4_SIO_IR_S1_DELTA_CTS |
558 IOC4_SIO_IR_S1_INT | IOC4_SIO_IR_S1_TX_EXPLICIT),
559 IOC4_SIO_IR_S1, IOC4_GPPR_UART1_MODESEL_PIN,
560 },
561
562 /* Values for port 2 */
563 {
564 IOC4_SIO_IR_S2_DELTA_DCD, IOC4_SIO_IR_S2_DELTA_CTS,
565 IOC4_SIO_IR_S2_TX_MT, IOC4_SIO_IR_S2_RX_TIMER,
566 IOC4_SIO_IR_S2_RX_HIGH, IOC4_SIO_IR_S2_TX_EXPLICIT,
567 IOC4_OTHER_IR_S2_MEMERR,
568 (IOC4_SIO_IR_S2_TX_MT | IOC4_SIO_IR_S2_RX_FULL |
569 IOC4_SIO_IR_S2_RX_HIGH | IOC4_SIO_IR_S2_RX_TIMER |
570 IOC4_SIO_IR_S2_DELTA_DCD | IOC4_SIO_IR_S2_DELTA_CTS |
571 IOC4_SIO_IR_S2_INT | IOC4_SIO_IR_S2_TX_EXPLICIT),
572 IOC4_SIO_IR_S2, IOC4_GPPR_UART2_MODESEL_PIN,
573 },
574
575 /* Values for port 3 */
576 {
577 IOC4_SIO_IR_S3_DELTA_DCD, IOC4_SIO_IR_S3_DELTA_CTS,
578 IOC4_SIO_IR_S3_TX_MT, IOC4_SIO_IR_S3_RX_TIMER,
579 IOC4_SIO_IR_S3_RX_HIGH, IOC4_SIO_IR_S3_TX_EXPLICIT,
580 IOC4_OTHER_IR_S3_MEMERR,
581 (IOC4_SIO_IR_S3_TX_MT | IOC4_SIO_IR_S3_RX_FULL |
582 IOC4_SIO_IR_S3_RX_HIGH | IOC4_SIO_IR_S3_RX_TIMER |
583 IOC4_SIO_IR_S3_DELTA_DCD | IOC4_SIO_IR_S3_DELTA_CTS |
584 IOC4_SIO_IR_S3_INT | IOC4_SIO_IR_S3_TX_EXPLICIT),
585 IOC4_SIO_IR_S3, IOC4_GPPR_UART3_MODESEL_PIN,
586 }
587 };
588
589 /* A ring buffer entry */
590 struct ring_entry {
591 union {
592 struct {
593 uint32_t alldata;
594 uint32_t allsc;
595 } all;
596 struct {
597 char data[4]; /* data bytes */
598 char sc[4]; /* status/control */
599 } s;
600 } u;
601 };
602
603 /* Test the valid bits in any of the 4 sc chars using "allsc" member */
604 #define RING_ANY_VALID \
605 ((uint32_t)(IOC4_RXSB_MODEM_VALID | IOC4_RXSB_DATA_VALID) * 0x01010101)
606
607 #define ring_sc u.s.sc
608 #define ring_data u.s.data
609 #define ring_allsc u.all.allsc
610
611 /* Number of entries per ring buffer. */
612 #define ENTRIES_PER_RING (RING_BUF_SIZE / (int) sizeof(struct ring_entry))
613
614 /* An individual ring */
615 struct ring {
616 struct ring_entry entries[ENTRIES_PER_RING];
617 };
618
619 /* The whole enchilada */
620 struct ring_buffer {
621 struct ring TX_0_OR_2;
622 struct ring RX_0_OR_2;
623 struct ring TX_1_OR_3;
624 struct ring RX_1_OR_3;
625 };
626
627 /* Get a ring from a port struct */
628 #define RING(_p, _wh) &(((struct ring_buffer *)((_p)->ip_cpu_ringbuf))->_wh)
629
630 /* Infinite loop detection.
631 */
632 #define MAXITER 10000000
633
634 /* Prototypes */
635 static void receive_chars(struct uart_port *);
636 static void handle_intr(void *arg, uint32_t sio_ir);
637
638 /*
639 * port_is_active - determines if this port is currently active
640 * @port: ptr to soft struct for this port
641 * @uart_port: uart port to test for
642 */
643 static inline int port_is_active(struct ioc4_port *port,
644 struct uart_port *uart_port)
645 {
646 if (port) {
647 if ((port->ip_flags & PORT_ACTIVE)
648 && (port->ip_port == uart_port))
649 return 1;
650 }
651 return 0;
652 }
653
654
655 /**
656 * write_ireg - write the interrupt regs
657 * @ioc4_soft: ptr to soft struct for this port
658 * @val: value to write
659 * @which: which register
660 * @type: which ireg set
661 */
662 static inline void
663 write_ireg(struct ioc4_soft *ioc4_soft, uint32_t val, int which, int type)
664 {
665 struct ioc4_misc_regs __iomem *mem = ioc4_soft->is_ioc4_misc_addr;
666 unsigned long flags;
667
668 spin_lock_irqsave(&ioc4_soft->is_ir_lock, flags);
669
670 switch (type) {
671 case IOC4_SIO_INTR_TYPE:
672 switch (which) {
673 case IOC4_W_IES:
674 writel(val, &mem->sio_ies.raw);
675 break;
676
677 case IOC4_W_IEC:
678 writel(val, &mem->sio_iec.raw);
679 break;
680 }
681 break;
682
683 case IOC4_OTHER_INTR_TYPE:
684 switch (which) {
685 case IOC4_W_IES:
686 writel(val, &mem->other_ies.raw);
687 break;
688
689 case IOC4_W_IEC:
690 writel(val, &mem->other_iec.raw);
691 break;
692 }
693 break;
694
695 default:
696 break;
697 }
698 spin_unlock_irqrestore(&ioc4_soft->is_ir_lock, flags);
699 }
700
701 /**
702 * set_baud - Baud rate setting code
703 * @port: port to set
704 * @baud: baud rate to use
705 */
706 static int set_baud(struct ioc4_port *port, int baud)
707 {
708 int actual_baud;
709 int diff;
710 int lcr;
711 unsigned short divisor;
712 struct ioc4_uartregs __iomem *uart;
713
714 divisor = SER_DIVISOR(baud, port->ip_pci_bus_speed);
715 if (!divisor)
716 return 1;
717 actual_baud = DIVISOR_TO_BAUD(divisor, port->ip_pci_bus_speed);
718
719 diff = actual_baud - baud;
720 if (diff < 0)
721 diff = -diff;
722
723 /* If we're within 1%, we've found a match */
724 if (diff * 100 > actual_baud)
725 return 1;
726
727 uart = port->ip_uart_regs;
728 lcr = readb(&uart->i4u_lcr);
729 writeb(lcr | UART_LCR_DLAB, &uart->i4u_lcr);
730 writeb((unsigned char)divisor, &uart->i4u_dll);
731 writeb((unsigned char)(divisor >> 8), &uart->i4u_dlm);
732 writeb(lcr, &uart->i4u_lcr);
733 return 0;
734 }
735
736
737 /**
738 * get_ioc4_port - given a uart port, return the control structure
739 * @port: uart port
740 * @set: set this port as current
741 */
742 static struct ioc4_port *get_ioc4_port(struct uart_port *the_port, int set)
743 {
744 struct ioc4_driver_data *idd = dev_get_drvdata(the_port->dev);
745 struct ioc4_control *control = idd->idd_serial_data;
746 struct ioc4_port *port;
747 int port_num, port_type;
748
749 if (control) {
750 for ( port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS;
751 port_num++ ) {
752 port = control->ic_port[port_num].icp_port;
753 if (!port)
754 continue;
755 for (port_type = UART_PORT_MIN;
756 port_type < UART_PORT_COUNT;
757 port_type++) {
758 if (the_port == port->ip_all_ports
759 [port_type]) {
760 /* set local copy */
761 if (set) {
762 port->ip_port = the_port;
763 }
764 return port;
765 }
766 }
767 }
768 }
769 return NULL;
770 }
771
772 /* The IOC4 hardware provides no atomic way to determine if interrupts
773 * are pending since two reads are required to do so. The handler must
774 * read the SIO_IR and the SIO_IES, and take the logical and of the
775 * two. When this value is zero, all interrupts have been serviced and
776 * the handler may return.
777 *
778 * This has the unfortunate "hole" that, if some other CPU or
779 * some other thread or some higher level interrupt manages to
780 * modify SIO_IE between our reads of SIO_IR and SIO_IE, we may
781 * think we have observed SIO_IR&SIO_IE==0 when in fact this
782 * condition never really occurred.
783 *
784 * To solve this, we use a simple spinlock that must be held
785 * whenever modifying SIO_IE; holding this lock while observing
786 * both SIO_IR and SIO_IE guarantees that we do not falsely
787 * conclude that no enabled interrupts are pending.
788 */
789
790 static inline uint32_t
791 pending_intrs(struct ioc4_soft *soft, int type)
792 {
793 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
794 unsigned long flag;
795 uint32_t intrs = 0;
796
797 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
798 || (type == IOC4_OTHER_INTR_TYPE)));
799
800 spin_lock_irqsave(&soft->is_ir_lock, flag);
801
802 switch (type) {
803 case IOC4_SIO_INTR_TYPE:
804 intrs = readl(&mem->sio_ir.raw) & readl(&mem->sio_ies.raw);
805 break;
806
807 case IOC4_OTHER_INTR_TYPE:
808 intrs = readl(&mem->other_ir.raw) & readl(&mem->other_ies.raw);
809
810 /* Don't process any ATA interrupte */
811 intrs &= ~(IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
812 break;
813
814 default:
815 break;
816 }
817 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
818 return intrs;
819 }
820
821 /**
822 * port_init - Initialize the sio and ioc4 hardware for a given port
823 * called per port from attach...
824 * @port: port to initialize
825 */
826 static int inline port_init(struct ioc4_port *port)
827 {
828 uint32_t sio_cr;
829 struct hooks *hooks = port->ip_hooks;
830 struct ioc4_uartregs __iomem *uart;
831
832 /* Idle the IOC4 serial interface */
833 writel(IOC4_SSCR_RESET, &port->ip_serial_regs->sscr);
834
835 /* Wait until any pending bus activity for this port has ceased */
836 do
837 sio_cr = readl(&port->ip_mem->sio_cr.raw);
838 while (!(sio_cr & IOC4_SIO_CR_SIO_DIAG_IDLE));
839
840 /* Finish reset sequence */
841 writel(0, &port->ip_serial_regs->sscr);
842
843 /* Once RESET is done, reload cached tx_prod and rx_cons values
844 * and set rings to empty by making prod == cons
845 */
846 port->ip_tx_prod = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
847 writel(port->ip_tx_prod, &port->ip_serial_regs->stpir);
848 port->ip_rx_cons = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
849 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
850
851 /* Disable interrupts for this 16550 */
852 uart = port->ip_uart_regs;
853 writeb(0, &uart->i4u_lcr);
854 writeb(0, &uart->i4u_ier);
855
856 /* Set the default baud */
857 set_baud(port, port->ip_baud);
858
859 /* Set line control to 8 bits no parity */
860 writeb(UART_LCR_WLEN8 | 0, &uart->i4u_lcr);
861 /* UART_LCR_STOP == 1 stop */
862
863 /* Enable the FIFOs */
864 writeb(UART_FCR_ENABLE_FIFO, &uart->i4u_fcr);
865 /* then reset 16550 FIFOs */
866 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
867 &uart->i4u_fcr);
868
869 /* Clear modem control register */
870 writeb(0, &uart->i4u_mcr);
871
872 /* Clear deltas in modem status register */
873 readb(&uart->i4u_msr);
874
875 /* Only do this once per port pair */
876 if (port->ip_hooks == &hooks_array[0]
877 || port->ip_hooks == &hooks_array[2]) {
878 unsigned long ring_pci_addr;
879 uint32_t __iomem *sbbr_l;
880 uint32_t __iomem *sbbr_h;
881
882 if (port->ip_hooks == &hooks_array[0]) {
883 sbbr_l = &port->ip_serial->sbbr01_l;
884 sbbr_h = &port->ip_serial->sbbr01_h;
885 } else {
886 sbbr_l = &port->ip_serial->sbbr23_l;
887 sbbr_h = &port->ip_serial->sbbr23_h;
888 }
889
890 ring_pci_addr = (unsigned long __iomem)port->ip_dma_ringbuf;
891 DPRINT_CONFIG(("%s: ring_pci_addr 0x%lx\n",
892 __FUNCTION__, ring_pci_addr));
893
894 writel((unsigned int)((uint64_t)ring_pci_addr >> 32), sbbr_h);
895 writel((unsigned int)ring_pci_addr | IOC4_BUF_SIZE_BIT, sbbr_l);
896 }
897
898 /* Set the receive timeout value to 10 msec */
899 writel(IOC4_SRTR_HZ / 100, &port->ip_serial_regs->srtr);
900
901 /* Set rx threshold, enable DMA */
902 /* Set high water mark at 3/4 of full ring */
903 port->ip_sscr = (ENTRIES_PER_RING * 3 / 4);
904 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
905
906 /* Disable and clear all serial related interrupt bits */
907 write_ireg(port->ip_ioc4_soft, hooks->intr_clear,
908 IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
909 port->ip_ienb &= ~hooks->intr_clear;
910 writel(hooks->intr_clear, &port->ip_mem->sio_ir.raw);
911 return 0;
912 }
913
914 /**
915 * handle_dma_error_intr - service any pending DMA error interrupts for the
916 * given port - 2nd level called via sd_intr
917 * @arg: handler arg
918 * @other_ir: ioc4regs
919 */
920 static void handle_dma_error_intr(void *arg, uint32_t other_ir)
921 {
922 struct ioc4_port *port = (struct ioc4_port *)arg;
923 struct hooks *hooks = port->ip_hooks;
924 unsigned long flags;
925
926 spin_lock_irqsave(&port->ip_lock, flags);
927
928 /* ACK the interrupt */
929 writel(hooks->intr_dma_error, &port->ip_mem->other_ir.raw);
930
931 if (readl(&port->ip_mem->pci_err_addr_l.raw) & IOC4_PCI_ERR_ADDR_VLD) {
932 printk(KERN_ERR
933 "PCI error address is 0x%lx, "
934 "master is serial port %c %s\n",
935 (((uint64_t)readl(&port->ip_mem->pci_err_addr_h)
936 << 32)
937 | readl(&port->ip_mem->pci_err_addr_l.raw))
938 & IOC4_PCI_ERR_ADDR_ADDR_MSK, '1' +
939 ((char)(readl(&port->ip_mem->pci_err_addr_l.raw) &
940 IOC4_PCI_ERR_ADDR_MST_NUM_MSK) >> 1),
941 (readl(&port->ip_mem->pci_err_addr_l.raw)
942 & IOC4_PCI_ERR_ADDR_MST_TYP_MSK)
943 ? "RX" : "TX");
944
945 if (readl(&port->ip_mem->pci_err_addr_l.raw)
946 & IOC4_PCI_ERR_ADDR_MUL_ERR) {
947 printk(KERN_ERR
948 "Multiple errors occurred\n");
949 }
950 }
951 spin_unlock_irqrestore(&port->ip_lock, flags);
952
953 /* Re-enable DMA error interrupts */
954 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error, IOC4_W_IES,
955 IOC4_OTHER_INTR_TYPE);
956 }
957
958 /**
959 * intr_connect - interrupt connect function
960 * @soft: soft struct for this card
961 * @type: interrupt type
962 * @intrbits: bit pattern to set
963 * @intr: handler function
964 * @info: handler arg
965 */
966 static void
967 intr_connect(struct ioc4_soft *soft, int type,
968 uint32_t intrbits, ioc4_intr_func_f * intr, void *info)
969 {
970 int i;
971 struct ioc4_intr_info *intr_ptr;
972
973 BUG_ON(!((type == IOC4_SIO_INTR_TYPE)
974 || (type == IOC4_OTHER_INTR_TYPE)));
975
976 i = atomic_inc(&soft-> is_intr_type[type].is_num_intrs) - 1;
977 BUG_ON(!(i < MAX_IOC4_INTR_ENTS || (printk("i %d\n", i), 0)));
978
979 /* Save off the lower level interrupt handler */
980 intr_ptr = &soft->is_intr_type[type].is_intr_info[i];
981 intr_ptr->sd_bits = intrbits;
982 intr_ptr->sd_intr = intr;
983 intr_ptr->sd_info = info;
984 }
985
986 /**
987 * ioc4_intr - Top level IOC4 interrupt handler.
988 * @irq: irq value
989 * @arg: handler arg
990 */
991
992 static irqreturn_t ioc4_intr(int irq, void *arg)
993 {
994 struct ioc4_soft *soft;
995 uint32_t this_ir, this_mir;
996 int xx, num_intrs = 0;
997 int intr_type;
998 int handled = 0;
999 struct ioc4_intr_info *intr_info;
1000
1001 soft = arg;
1002 for (intr_type = 0; intr_type < IOC4_NUM_INTR_TYPES; intr_type++) {
1003 num_intrs = (int)atomic_read(
1004 &soft->is_intr_type[intr_type].is_num_intrs);
1005
1006 this_mir = this_ir = pending_intrs(soft, intr_type);
1007
1008 /* Farm out the interrupt to the various drivers depending on
1009 * which interrupt bits are set.
1010 */
1011 for (xx = 0; xx < num_intrs; xx++) {
1012 intr_info = &soft->is_intr_type[intr_type].is_intr_info[xx];
1013 if ((this_mir = this_ir & intr_info->sd_bits)) {
1014 /* Disable owned interrupts, call handler */
1015 handled++;
1016 write_ireg(soft, intr_info->sd_bits, IOC4_W_IEC,
1017 intr_type);
1018 intr_info->sd_intr(intr_info->sd_info, this_mir);
1019 this_ir &= ~this_mir;
1020 }
1021 }
1022 }
1023 #ifdef DEBUG_INTERRUPTS
1024 {
1025 struct ioc4_misc_regs __iomem *mem = soft->is_ioc4_misc_addr;
1026 unsigned long flag;
1027
1028 spin_lock_irqsave(&soft->is_ir_lock, flag);
1029 printk ("%s : %d : mem 0x%p sio_ir 0x%x sio_ies 0x%x "
1030 "other_ir 0x%x other_ies 0x%x mask 0x%x\n",
1031 __FUNCTION__, __LINE__,
1032 (void *)mem, readl(&mem->sio_ir.raw),
1033 readl(&mem->sio_ies.raw),
1034 readl(&mem->other_ir.raw),
1035 readl(&mem->other_ies.raw),
1036 IOC4_OTHER_IR_ATA_INT | IOC4_OTHER_IR_ATA_MEMERR);
1037 spin_unlock_irqrestore(&soft->is_ir_lock, flag);
1038 }
1039 #endif
1040 return handled ? IRQ_HANDLED : IRQ_NONE;
1041 }
1042
1043 /**
1044 * ioc4_attach_local - Device initialization.
1045 * Called at *_attach() time for each
1046 * IOC4 with serial ports in the system.
1047 * @idd: Master module data for this IOC4
1048 */
1049 static int inline ioc4_attach_local(struct ioc4_driver_data *idd)
1050 {
1051 struct ioc4_port *port;
1052 struct ioc4_port *ports[IOC4_NUM_SERIAL_PORTS];
1053 int port_number;
1054 uint16_t ioc4_revid_min = 62;
1055 uint16_t ioc4_revid;
1056 struct pci_dev *pdev = idd->idd_pdev;
1057 struct ioc4_control* control = idd->idd_serial_data;
1058 struct ioc4_soft *soft = control->ic_soft;
1059 void __iomem *ioc4_misc = idd->idd_misc_regs;
1060 void __iomem *ioc4_serial = soft->is_ioc4_serial_addr;
1061
1062 /* IOC4 firmware must be at least rev 62 */
1063 pci_read_config_word(pdev, PCI_COMMAND_SPECIAL, &ioc4_revid);
1064
1065 printk(KERN_INFO "IOC4 firmware revision %d\n", ioc4_revid);
1066 if (ioc4_revid < ioc4_revid_min) {
1067 printk(KERN_WARNING
1068 "IOC4 serial not supported on firmware rev %d, "
1069 "please upgrade to rev %d or higher\n",
1070 ioc4_revid, ioc4_revid_min);
1071 return -EPERM;
1072 }
1073 BUG_ON(ioc4_misc == NULL);
1074 BUG_ON(ioc4_serial == NULL);
1075
1076 /* Create port structures for each port */
1077 for (port_number = 0; port_number < IOC4_NUM_SERIAL_PORTS;
1078 port_number++) {
1079 port = kmalloc(sizeof(struct ioc4_port), GFP_KERNEL);
1080 if (!port) {
1081 printk(KERN_WARNING
1082 "IOC4 serial memory not available for port\n");
1083 return -ENOMEM;
1084 }
1085 memset(port, 0, sizeof(struct ioc4_port));
1086 spin_lock_init(&port->ip_lock);
1087
1088 /* we need to remember the previous ones, to point back to
1089 * them farther down - setting up the ring buffers.
1090 */
1091 ports[port_number] = port;
1092
1093 /* Allocate buffers and jumpstart the hardware. */
1094 control->ic_port[port_number].icp_port = port;
1095 port->ip_ioc4_soft = soft;
1096 port->ip_pdev = pdev;
1097 port->ip_ienb = 0;
1098 /* Use baud rate calculations based on detected PCI
1099 * bus speed. Simply test whether the PCI clock is
1100 * running closer to 66MHz or 33MHz.
1101 */
1102 if (idd->count_period/IOC4_EXTINT_COUNT_DIVISOR < 20) {
1103 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_66;
1104 } else {
1105 port->ip_pci_bus_speed = IOC4_SER_XIN_CLK_33;
1106 }
1107 port->ip_baud = 9600;
1108 port->ip_control = control;
1109 port->ip_mem = ioc4_misc;
1110 port->ip_serial = ioc4_serial;
1111
1112 /* point to the right hook */
1113 port->ip_hooks = &hooks_array[port_number];
1114
1115 /* Get direct hooks to the serial regs and uart regs
1116 * for this port
1117 */
1118 switch (port_number) {
1119 case 0:
1120 port->ip_serial_regs = &(port->ip_serial->port_0);
1121 port->ip_uart_regs = &(port->ip_serial->uart_0);
1122 break;
1123 case 1:
1124 port->ip_serial_regs = &(port->ip_serial->port_1);
1125 port->ip_uart_regs = &(port->ip_serial->uart_1);
1126 break;
1127 case 2:
1128 port->ip_serial_regs = &(port->ip_serial->port_2);
1129 port->ip_uart_regs = &(port->ip_serial->uart_2);
1130 break;
1131 default:
1132 case 3:
1133 port->ip_serial_regs = &(port->ip_serial->port_3);
1134 port->ip_uart_regs = &(port->ip_serial->uart_3);
1135 break;
1136 }
1137
1138 /* ring buffers are 1 to a pair of ports */
1139 if (port_number && (port_number & 1)) {
1140 /* odd use the evens buffer */
1141 port->ip_dma_ringbuf =
1142 ports[port_number - 1]->ip_dma_ringbuf;
1143 port->ip_cpu_ringbuf =
1144 ports[port_number - 1]->ip_cpu_ringbuf;
1145 port->ip_inring = RING(port, RX_1_OR_3);
1146 port->ip_outring = RING(port, TX_1_OR_3);
1147
1148 } else {
1149 if (port->ip_dma_ringbuf == 0) {
1150 port->ip_cpu_ringbuf = pci_alloc_consistent
1151 (pdev, TOTAL_RING_BUF_SIZE,
1152 &port->ip_dma_ringbuf);
1153
1154 }
1155 BUG_ON(!((((int64_t)port->ip_dma_ringbuf) &
1156 (TOTAL_RING_BUF_SIZE - 1)) == 0));
1157 DPRINT_CONFIG(("%s : ip_cpu_ringbuf 0x%p "
1158 "ip_dma_ringbuf 0x%p\n",
1159 __FUNCTION__,
1160 (void *)port->ip_cpu_ringbuf,
1161 (void *)port->ip_dma_ringbuf));
1162 port->ip_inring = RING(port, RX_0_OR_2);
1163 port->ip_outring = RING(port, TX_0_OR_2);
1164 }
1165 DPRINT_CONFIG(("%s : port %d [addr 0x%p] control 0x%p",
1166 __FUNCTION__,
1167 port_number, (void *)port, (void *)control));
1168 DPRINT_CONFIG((" ip_serial_regs 0x%p ip_uart_regs 0x%p\n",
1169 (void *)port->ip_serial_regs,
1170 (void *)port->ip_uart_regs));
1171
1172 /* Initialize the hardware for IOC4 */
1173 port_init(port);
1174
1175 DPRINT_CONFIG(("%s: port_number %d port 0x%p inring 0x%p "
1176 "outring 0x%p\n",
1177 __FUNCTION__,
1178 port_number, (void *)port,
1179 (void *)port->ip_inring,
1180 (void *)port->ip_outring));
1181
1182 /* Attach interrupt handlers */
1183 intr_connect(soft, IOC4_SIO_INTR_TYPE,
1184 GET_SIO_IR(port_number),
1185 handle_intr, port);
1186
1187 intr_connect(soft, IOC4_OTHER_INTR_TYPE,
1188 GET_OTHER_IR(port_number),
1189 handle_dma_error_intr, port);
1190 }
1191 return 0;
1192 }
1193
1194 /**
1195 * enable_intrs - enable interrupts
1196 * @port: port to enable
1197 * @mask: mask to use
1198 */
1199 static void enable_intrs(struct ioc4_port *port, uint32_t mask)
1200 {
1201 struct hooks *hooks = port->ip_hooks;
1202
1203 if ((port->ip_ienb & mask) != mask) {
1204 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IES,
1205 IOC4_SIO_INTR_TYPE);
1206 port->ip_ienb |= mask;
1207 }
1208
1209 if (port->ip_ienb)
1210 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1211 IOC4_W_IES, IOC4_OTHER_INTR_TYPE);
1212 }
1213
1214 /**
1215 * local_open - local open a port
1216 * @port: port to open
1217 */
1218 static inline int local_open(struct ioc4_port *port)
1219 {
1220 int spiniter = 0;
1221
1222 port->ip_flags = PORT_ACTIVE;
1223
1224 /* Pause the DMA interface if necessary */
1225 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1226 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1227 &port->ip_serial_regs->sscr);
1228 while((readl(&port->ip_serial_regs-> sscr)
1229 & IOC4_SSCR_PAUSE_STATE) == 0) {
1230 spiniter++;
1231 if (spiniter > MAXITER) {
1232 port->ip_flags = PORT_INACTIVE;
1233 return -1;
1234 }
1235 }
1236 }
1237
1238 /* Reset the input fifo. If the uart received chars while the port
1239 * was closed and DMA is not enabled, the uart may have a bunch of
1240 * chars hanging around in its rx fifo which will not be discarded
1241 * by rclr in the upper layer. We must get rid of them here.
1242 */
1243 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1244 &port->ip_uart_regs->i4u_fcr);
1245
1246 writeb(UART_LCR_WLEN8, &port->ip_uart_regs->i4u_lcr);
1247 /* UART_LCR_STOP == 1 stop */
1248
1249 /* Re-enable DMA, set default threshold to intr whenever there is
1250 * data available.
1251 */
1252 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1253 port->ip_sscr |= 1; /* default threshold */
1254
1255 /* Plug in the new sscr. This implicitly clears the DMA_PAUSE
1256 * flag if it was set above
1257 */
1258 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1259 port->ip_tx_lowat = 1;
1260 return 0;
1261 }
1262
1263 /**
1264 * set_rx_timeout - Set rx timeout and threshold values.
1265 * @port: port to use
1266 * @timeout: timeout value in ticks
1267 */
1268 static inline int set_rx_timeout(struct ioc4_port *port, int timeout)
1269 {
1270 int threshold;
1271
1272 port->ip_rx_timeout = timeout;
1273
1274 /* Timeout is in ticks. Let's figure out how many chars we
1275 * can receive at the current baud rate in that interval
1276 * and set the rx threshold to that amount. There are 4 chars
1277 * per ring entry, so we'll divide the number of chars that will
1278 * arrive in timeout by 4.
1279 * So .... timeout * baud / 10 / HZ / 4, with HZ = 100.
1280 */
1281 threshold = timeout * port->ip_baud / 4000;
1282 if (threshold == 0)
1283 threshold = 1; /* otherwise we'll intr all the time! */
1284
1285 if ((unsigned)threshold > (unsigned)IOC4_SSCR_RX_THRESHOLD)
1286 return 1;
1287
1288 port->ip_sscr &= ~IOC4_SSCR_RX_THRESHOLD;
1289 port->ip_sscr |= threshold;
1290
1291 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1292
1293 /* Now set the rx timeout to the given value
1294 * again timeout * IOC4_SRTR_HZ / HZ
1295 */
1296 timeout = timeout * IOC4_SRTR_HZ / 100;
1297 if (timeout > IOC4_SRTR_CNT)
1298 timeout = IOC4_SRTR_CNT;
1299
1300 writel(timeout, &port->ip_serial_regs->srtr);
1301 return 0;
1302 }
1303
1304 /**
1305 * config_port - config the hardware
1306 * @port: port to config
1307 * @baud: baud rate for the port
1308 * @byte_size: data size
1309 * @stop_bits: number of stop bits
1310 * @parenb: parity enable ?
1311 * @parodd: odd parity ?
1312 */
1313 static inline int
1314 config_port(struct ioc4_port *port,
1315 int baud, int byte_size, int stop_bits, int parenb, int parodd)
1316 {
1317 char lcr, sizebits;
1318 int spiniter = 0;
1319
1320 DPRINT_CONFIG(("%s: baud %d byte_size %d stop %d parenb %d parodd %d\n",
1321 __FUNCTION__, baud, byte_size, stop_bits, parenb, parodd));
1322
1323 if (set_baud(port, baud))
1324 return 1;
1325
1326 switch (byte_size) {
1327 case 5:
1328 sizebits = UART_LCR_WLEN5;
1329 break;
1330 case 6:
1331 sizebits = UART_LCR_WLEN6;
1332 break;
1333 case 7:
1334 sizebits = UART_LCR_WLEN7;
1335 break;
1336 case 8:
1337 sizebits = UART_LCR_WLEN8;
1338 break;
1339 default:
1340 return 1;
1341 }
1342
1343 /* Pause the DMA interface if necessary */
1344 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1345 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1346 &port->ip_serial_regs->sscr);
1347 while((readl(&port->ip_serial_regs->sscr)
1348 & IOC4_SSCR_PAUSE_STATE) == 0) {
1349 spiniter++;
1350 if (spiniter > MAXITER)
1351 return -1;
1352 }
1353 }
1354
1355 /* Clear relevant fields in lcr */
1356 lcr = readb(&port->ip_uart_regs->i4u_lcr);
1357 lcr &= ~(LCR_MASK_BITS_CHAR | UART_LCR_EPAR |
1358 UART_LCR_PARITY | LCR_MASK_STOP_BITS);
1359
1360 /* Set byte size in lcr */
1361 lcr |= sizebits;
1362
1363 /* Set parity */
1364 if (parenb) {
1365 lcr |= UART_LCR_PARITY;
1366 if (!parodd)
1367 lcr |= UART_LCR_EPAR;
1368 }
1369
1370 /* Set stop bits */
1371 if (stop_bits)
1372 lcr |= UART_LCR_STOP /* 2 stop bits */ ;
1373
1374 writeb(lcr, &port->ip_uart_regs->i4u_lcr);
1375
1376 /* Re-enable the DMA interface if necessary */
1377 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1378 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1379 }
1380 port->ip_baud = baud;
1381
1382 /* When we get within this number of ring entries of filling the
1383 * entire ring on tx, place an EXPLICIT intr to generate a lowat
1384 * notification when output has drained.
1385 */
1386 port->ip_tx_lowat = (TX_LOWAT_CHARS(baud) + 3) / 4;
1387 if (port->ip_tx_lowat == 0)
1388 port->ip_tx_lowat = 1;
1389
1390 set_rx_timeout(port, 2);
1391
1392 return 0;
1393 }
1394
1395 /**
1396 * do_write - Write bytes to the port. Returns the number of bytes
1397 * actually written. Called from transmit_chars
1398 * @port: port to use
1399 * @buf: the stuff to write
1400 * @len: how many bytes in 'buf'
1401 */
1402 static inline int do_write(struct ioc4_port *port, char *buf, int len)
1403 {
1404 int prod_ptr, cons_ptr, total = 0;
1405 struct ring *outring;
1406 struct ring_entry *entry;
1407 struct hooks *hooks = port->ip_hooks;
1408
1409 BUG_ON(!(len >= 0));
1410
1411 prod_ptr = port->ip_tx_prod;
1412 cons_ptr = readl(&port->ip_serial_regs->stcir) & PROD_CONS_MASK;
1413 outring = port->ip_outring;
1414
1415 /* Maintain a 1-entry red-zone. The ring buffer is full when
1416 * (cons - prod) % ring_size is 1. Rather than do this subtraction
1417 * in the body of the loop, I'll do it now.
1418 */
1419 cons_ptr = (cons_ptr - (int)sizeof(struct ring_entry)) & PROD_CONS_MASK;
1420
1421 /* Stuff the bytes into the output */
1422 while ((prod_ptr != cons_ptr) && (len > 0)) {
1423 int xx;
1424
1425 /* Get 4 bytes (one ring entry) at a time */
1426 entry = (struct ring_entry *)((caddr_t) outring + prod_ptr);
1427
1428 /* Invalidate all entries */
1429 entry->ring_allsc = 0;
1430
1431 /* Copy in some bytes */
1432 for (xx = 0; (xx < 4) && (len > 0); xx++) {
1433 entry->ring_data[xx] = *buf++;
1434 entry->ring_sc[xx] = IOC4_TXCB_VALID;
1435 len--;
1436 total++;
1437 }
1438
1439 /* If we are within some small threshold of filling up the
1440 * entire ring buffer, we must place an EXPLICIT intr here
1441 * to generate a lowat interrupt in case we subsequently
1442 * really do fill up the ring and the caller goes to sleep.
1443 * No need to place more than one though.
1444 */
1445 if (!(port->ip_flags & LOWAT_WRITTEN) &&
1446 ((cons_ptr - prod_ptr) & PROD_CONS_MASK)
1447 <= port->ip_tx_lowat
1448 * (int)sizeof(struct ring_entry)) {
1449 port->ip_flags |= LOWAT_WRITTEN;
1450 entry->ring_sc[0] |= IOC4_TXCB_INT_WHEN_DONE;
1451 }
1452
1453 /* Go on to next entry */
1454 prod_ptr += sizeof(struct ring_entry);
1455 prod_ptr &= PROD_CONS_MASK;
1456 }
1457
1458 /* If we sent something, start DMA if necessary */
1459 if (total > 0 && !(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
1460 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1461 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1462 }
1463
1464 /* Store the new producer pointer. If tx is disabled, we stuff the
1465 * data into the ring buffer, but we don't actually start tx.
1466 */
1467 if (!uart_tx_stopped(port->ip_port)) {
1468 writel(prod_ptr, &port->ip_serial_regs->stpir);
1469
1470 /* If we are now transmitting, enable tx_mt interrupt so we
1471 * can disable DMA if necessary when the tx finishes.
1472 */
1473 if (total > 0)
1474 enable_intrs(port, hooks->intr_tx_mt);
1475 }
1476 port->ip_tx_prod = prod_ptr;
1477 return total;
1478 }
1479
1480 /**
1481 * disable_intrs - disable interrupts
1482 * @port: port to enable
1483 * @mask: mask to use
1484 */
1485 static void disable_intrs(struct ioc4_port *port, uint32_t mask)
1486 {
1487 struct hooks *hooks = port->ip_hooks;
1488
1489 if (port->ip_ienb & mask) {
1490 write_ireg(port->ip_ioc4_soft, mask, IOC4_W_IEC,
1491 IOC4_SIO_INTR_TYPE);
1492 port->ip_ienb &= ~mask;
1493 }
1494
1495 if (!port->ip_ienb)
1496 write_ireg(port->ip_ioc4_soft, hooks->intr_dma_error,
1497 IOC4_W_IEC, IOC4_OTHER_INTR_TYPE);
1498 }
1499
1500 /**
1501 * set_notification - Modify event notification
1502 * @port: port to use
1503 * @mask: events mask
1504 * @set_on: set ?
1505 */
1506 static int set_notification(struct ioc4_port *port, int mask, int set_on)
1507 {
1508 struct hooks *hooks = port->ip_hooks;
1509 uint32_t intrbits, sscrbits;
1510
1511 BUG_ON(!mask);
1512
1513 intrbits = sscrbits = 0;
1514
1515 if (mask & N_DATA_READY)
1516 intrbits |= (hooks->intr_rx_timer | hooks->intr_rx_high);
1517 if (mask & N_OUTPUT_LOWAT)
1518 intrbits |= hooks->intr_tx_explicit;
1519 if (mask & N_DDCD) {
1520 intrbits |= hooks->intr_delta_dcd;
1521 sscrbits |= IOC4_SSCR_RX_RING_DCD;
1522 }
1523 if (mask & N_DCTS)
1524 intrbits |= hooks->intr_delta_cts;
1525
1526 if (set_on) {
1527 enable_intrs(port, intrbits);
1528 port->ip_notify |= mask;
1529 port->ip_sscr |= sscrbits;
1530 } else {
1531 disable_intrs(port, intrbits);
1532 port->ip_notify &= ~mask;
1533 port->ip_sscr &= ~sscrbits;
1534 }
1535
1536 /* We require DMA if either DATA_READY or DDCD notification is
1537 * currently requested. If neither of these is requested and
1538 * there is currently no tx in progress, DMA may be disabled.
1539 */
1540 if (port->ip_notify & (N_DATA_READY | N_DDCD))
1541 port->ip_sscr |= IOC4_SSCR_DMA_EN;
1542 else if (!(port->ip_ienb & hooks->intr_tx_mt))
1543 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
1544
1545 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1546 return 0;
1547 }
1548
1549 /**
1550 * set_mcr - set the master control reg
1551 * @the_port: port to use
1552 * @mask1: mcr mask
1553 * @mask2: shadow mask
1554 */
1555 static inline int set_mcr(struct uart_port *the_port,
1556 int mask1, int mask2)
1557 {
1558 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1559 uint32_t shadow;
1560 int spiniter = 0;
1561 char mcr;
1562
1563 if (!port)
1564 return -1;
1565
1566 /* Pause the DMA interface if necessary */
1567 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1568 writel(port->ip_sscr | IOC4_SSCR_DMA_PAUSE,
1569 &port->ip_serial_regs->sscr);
1570 while ((readl(&port->ip_serial_regs->sscr)
1571 & IOC4_SSCR_PAUSE_STATE) == 0) {
1572 spiniter++;
1573 if (spiniter > MAXITER)
1574 return -1;
1575 }
1576 }
1577 shadow = readl(&port->ip_serial_regs->shadow);
1578 mcr = (shadow & 0xff000000) >> 24;
1579
1580 /* Set new value */
1581 mcr |= mask1;
1582 shadow |= mask2;
1583
1584 writeb(mcr, &port->ip_uart_regs->i4u_mcr);
1585 writel(shadow, &port->ip_serial_regs->shadow);
1586
1587 /* Re-enable the DMA interface if necessary */
1588 if (port->ip_sscr & IOC4_SSCR_DMA_EN) {
1589 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1590 }
1591 return 0;
1592 }
1593
1594 /**
1595 * ioc4_set_proto - set the protocol for the port
1596 * @port: port to use
1597 * @proto: protocol to use
1598 */
1599 static int ioc4_set_proto(struct ioc4_port *port, int proto)
1600 {
1601 struct hooks *hooks = port->ip_hooks;
1602
1603 switch (proto) {
1604 case PROTO_RS232:
1605 /* Clear the appropriate GIO pin */
1606 writel(0, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1607 break;
1608
1609 case PROTO_RS422:
1610 /* Set the appropriate GIO pin */
1611 writel(1, (&port->ip_mem->gppr[hooks->rs422_select_pin].raw));
1612 break;
1613
1614 default:
1615 return 1;
1616 }
1617 return 0;
1618 }
1619
1620 /**
1621 * transmit_chars - upper level write, called with ip_lock
1622 * @the_port: port to write
1623 */
1624 static void transmit_chars(struct uart_port *the_port)
1625 {
1626 int xmit_count, tail, head;
1627 int result;
1628 char *start;
1629 struct tty_struct *tty;
1630 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1631 struct uart_info *info;
1632
1633 if (!the_port)
1634 return;
1635 if (!port)
1636 return;
1637
1638 info = the_port->info;
1639 tty = info->tty;
1640
1641 if (uart_circ_empty(&info->xmit) || uart_tx_stopped(the_port)) {
1642 /* Nothing to do or hw stopped */
1643 set_notification(port, N_ALL_OUTPUT, 0);
1644 return;
1645 }
1646
1647 head = info->xmit.head;
1648 tail = info->xmit.tail;
1649 start = (char *)&info->xmit.buf[tail];
1650
1651 /* write out all the data or until the end of the buffer */
1652 xmit_count = (head < tail) ? (UART_XMIT_SIZE - tail) : (head - tail);
1653 if (xmit_count > 0) {
1654 result = do_write(port, start, xmit_count);
1655 if (result > 0) {
1656 /* booking */
1657 xmit_count -= result;
1658 the_port->icount.tx += result;
1659 /* advance the pointers */
1660 tail += result;
1661 tail &= UART_XMIT_SIZE - 1;
1662 info->xmit.tail = tail;
1663 start = (char *)&info->xmit.buf[tail];
1664 }
1665 }
1666 if (uart_circ_chars_pending(&info->xmit) < WAKEUP_CHARS)
1667 uart_write_wakeup(the_port);
1668
1669 if (uart_circ_empty(&info->xmit)) {
1670 set_notification(port, N_OUTPUT_LOWAT, 0);
1671 } else {
1672 set_notification(port, N_OUTPUT_LOWAT, 1);
1673 }
1674 }
1675
1676 /**
1677 * ioc4_change_speed - change the speed of the port
1678 * @the_port: port to change
1679 * @new_termios: new termios settings
1680 * @old_termios: old termios settings
1681 */
1682 static void
1683 ioc4_change_speed(struct uart_port *the_port,
1684 struct ktermios *new_termios, struct ktermios *old_termios)
1685 {
1686 struct ioc4_port *port = get_ioc4_port(the_port, 0);
1687 int baud, bits;
1688 unsigned cflag;
1689 int new_parity = 0, new_parity_enable = 0, new_stop = 0, new_data = 8;
1690 struct uart_info *info = the_port->info;
1691
1692 cflag = new_termios->c_cflag;
1693
1694 switch (cflag & CSIZE) {
1695 case CS5:
1696 new_data = 5;
1697 bits = 7;
1698 break;
1699 case CS6:
1700 new_data = 6;
1701 bits = 8;
1702 break;
1703 case CS7:
1704 new_data = 7;
1705 bits = 9;
1706 break;
1707 case CS8:
1708 new_data = 8;
1709 bits = 10;
1710 break;
1711 default:
1712 /* cuz we always need a default ... */
1713 new_data = 5;
1714 bits = 7;
1715 break;
1716 }
1717 if (cflag & CSTOPB) {
1718 bits++;
1719 new_stop = 1;
1720 }
1721 if (cflag & PARENB) {
1722 bits++;
1723 new_parity_enable = 1;
1724 if (cflag & PARODD)
1725 new_parity = 1;
1726 }
1727 baud = uart_get_baud_rate(the_port, new_termios, old_termios,
1728 MIN_BAUD_SUPPORTED, MAX_BAUD_SUPPORTED);
1729 DPRINT_CONFIG(("%s: returned baud %d\n", __FUNCTION__, baud));
1730
1731 /* default is 9600 */
1732 if (!baud)
1733 baud = 9600;
1734
1735 if (!the_port->fifosize)
1736 the_port->fifosize = IOC4_FIFO_CHARS;
1737 the_port->timeout = ((the_port->fifosize * HZ * bits) / (baud / 10));
1738 the_port->timeout += HZ / 50; /* Add .02 seconds of slop */
1739
1740 the_port->ignore_status_mask = N_ALL_INPUT;
1741
1742 info->tty->low_latency = 1;
1743
1744 if (I_IGNPAR(info->tty))
1745 the_port->ignore_status_mask &= ~(N_PARITY_ERROR
1746 | N_FRAMING_ERROR);
1747 if (I_IGNBRK(info->tty)) {
1748 the_port->ignore_status_mask &= ~N_BREAK;
1749 if (I_IGNPAR(info->tty))
1750 the_port->ignore_status_mask &= ~N_OVERRUN_ERROR;
1751 }
1752 if (!(cflag & CREAD)) {
1753 /* ignore everything */
1754 the_port->ignore_status_mask &= ~N_DATA_READY;
1755 }
1756
1757 if (cflag & CRTSCTS) {
1758 port->ip_sscr |= IOC4_SSCR_HFC_EN;
1759 }
1760 else {
1761 port->ip_sscr &= ~IOC4_SSCR_HFC_EN;
1762 }
1763 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
1764
1765 /* Set the configuration and proper notification call */
1766 DPRINT_CONFIG(("%s : port 0x%p cflag 0%o "
1767 "config_port(baud %d data %d stop %d p enable %d parity %d),"
1768 " notification 0x%x\n",
1769 __FUNCTION__, (void *)port, cflag, baud, new_data, new_stop,
1770 new_parity_enable, new_parity, the_port->ignore_status_mask));
1771
1772 if ((config_port(port, baud, /* baud */
1773 new_data, /* byte size */
1774 new_stop, /* stop bits */
1775 new_parity_enable, /* set parity */
1776 new_parity)) >= 0) { /* parity 1==odd */
1777 set_notification(port, the_port->ignore_status_mask, 1);
1778 }
1779 }
1780
1781 /**
1782 * ic4_startup_local - Start up the serial port - returns >= 0 if no errors
1783 * @the_port: Port to operate on
1784 */
1785 static inline int ic4_startup_local(struct uart_port *the_port)
1786 {
1787 struct ioc4_port *port;
1788 struct uart_info *info;
1789
1790 if (!the_port)
1791 return -1;
1792
1793 port = get_ioc4_port(the_port, 0);
1794 if (!port)
1795 return -1;
1796
1797 info = the_port->info;
1798
1799 local_open(port);
1800
1801 /* set the protocol - mapbase has the port type */
1802 ioc4_set_proto(port, the_port->mapbase);
1803
1804 /* set the speed of the serial port */
1805 ioc4_change_speed(the_port, info->tty->termios, (struct ktermios *)0);
1806
1807 return 0;
1808 }
1809
1810 /*
1811 * ioc4_cb_output_lowat - called when the output low water mark is hit
1812 * @the_port: port to output
1813 */
1814 static void ioc4_cb_output_lowat(struct uart_port *the_port)
1815 {
1816 unsigned long pflags;
1817
1818 /* ip_lock is set on the call here */
1819 if (the_port) {
1820 spin_lock_irqsave(&the_port->lock, pflags);
1821 transmit_chars(the_port);
1822 spin_unlock_irqrestore(&the_port->lock, pflags);
1823 }
1824 }
1825
1826 /**
1827 * handle_intr - service any interrupts for the given port - 2nd level
1828 * called via sd_intr
1829 * @arg: handler arg
1830 * @sio_ir: ioc4regs
1831 */
1832 static void handle_intr(void *arg, uint32_t sio_ir)
1833 {
1834 struct ioc4_port *port = (struct ioc4_port *)arg;
1835 struct hooks *hooks = port->ip_hooks;
1836 unsigned int rx_high_rd_aborted = 0;
1837 unsigned long flags;
1838 struct uart_port *the_port;
1839 int loop_counter;
1840
1841 /* Possible race condition here: The tx_mt interrupt bit may be
1842 * cleared without the intervention of the interrupt handler,
1843 * e.g. by a write. If the top level interrupt handler reads a
1844 * tx_mt, then some other processor does a write, starting up
1845 * output, then we come in here, see the tx_mt and stop DMA, the
1846 * output started by the other processor will hang. Thus we can
1847 * only rely on tx_mt being legitimate if it is read while the
1848 * port lock is held. Therefore this bit must be ignored in the
1849 * passed in interrupt mask which was read by the top level
1850 * interrupt handler since the port lock was not held at the time
1851 * it was read. We can only rely on this bit being accurate if it
1852 * is read while the port lock is held. So we'll clear it for now,
1853 * and reload it later once we have the port lock.
1854 */
1855 sio_ir &= ~(hooks->intr_tx_mt);
1856
1857 spin_lock_irqsave(&port->ip_lock, flags);
1858
1859 loop_counter = MAXITER; /* to avoid hangs */
1860
1861 do {
1862 uint32_t shadow;
1863
1864 if ( loop_counter-- <= 0 ) {
1865 printk(KERN_WARNING "IOC4 serial: "
1866 "possible hang condition/"
1867 "port stuck on interrupt.\n");
1868 break;
1869 }
1870
1871 /* Handle a DCD change */
1872 if (sio_ir & hooks->intr_delta_dcd) {
1873 /* ACK the interrupt */
1874 writel(hooks->intr_delta_dcd,
1875 &port->ip_mem->sio_ir.raw);
1876
1877 shadow = readl(&port->ip_serial_regs->shadow);
1878
1879 if ((port->ip_notify & N_DDCD)
1880 && (shadow & IOC4_SHADOW_DCD)
1881 && (port->ip_port)) {
1882 the_port = port->ip_port;
1883 the_port->icount.dcd = 1;
1884 wake_up_interruptible
1885 (&the_port-> info->delta_msr_wait);
1886 } else if ((port->ip_notify & N_DDCD)
1887 && !(shadow & IOC4_SHADOW_DCD)) {
1888 /* Flag delta DCD/no DCD */
1889 port->ip_flags |= DCD_ON;
1890 }
1891 }
1892
1893 /* Handle a CTS change */
1894 if (sio_ir & hooks->intr_delta_cts) {
1895 /* ACK the interrupt */
1896 writel(hooks->intr_delta_cts,
1897 &port->ip_mem->sio_ir.raw);
1898
1899 shadow = readl(&port->ip_serial_regs->shadow);
1900
1901 if ((port->ip_notify & N_DCTS)
1902 && (port->ip_port)) {
1903 the_port = port->ip_port;
1904 the_port->icount.cts =
1905 (shadow & IOC4_SHADOW_CTS) ? 1 : 0;
1906 wake_up_interruptible
1907 (&the_port->info->delta_msr_wait);
1908 }
1909 }
1910
1911 /* rx timeout interrupt. Must be some data available. Put this
1912 * before the check for rx_high since servicing this condition
1913 * may cause that condition to clear.
1914 */
1915 if (sio_ir & hooks->intr_rx_timer) {
1916 /* ACK the interrupt */
1917 writel(hooks->intr_rx_timer,
1918 &port->ip_mem->sio_ir.raw);
1919
1920 if ((port->ip_notify & N_DATA_READY)
1921 && (port->ip_port)) {
1922 /* ip_lock is set on call here */
1923 receive_chars(port->ip_port);
1924 }
1925 }
1926
1927 /* rx high interrupt. Must be after rx_timer. */
1928 else if (sio_ir & hooks->intr_rx_high) {
1929 /* Data available, notify upper layer */
1930 if ((port->ip_notify & N_DATA_READY)
1931 && port->ip_port) {
1932 /* ip_lock is set on call here */
1933 receive_chars(port->ip_port);
1934 }
1935
1936 /* We can't ACK this interrupt. If receive_chars didn't
1937 * cause the condition to clear, we'll have to disable
1938 * the interrupt until the data is drained.
1939 * If the read was aborted, don't disable the interrupt
1940 * as this may cause us to hang indefinitely. An
1941 * aborted read generally means that this interrupt
1942 * hasn't been delivered to the cpu yet anyway, even
1943 * though we see it as asserted when we read the sio_ir.
1944 */
1945 if ((sio_ir = PENDING(port)) & hooks->intr_rx_high) {
1946 if ((port->ip_flags & READ_ABORTED) == 0) {
1947 port->ip_ienb &= ~hooks->intr_rx_high;
1948 port->ip_flags |= INPUT_HIGH;
1949 } else {
1950 rx_high_rd_aborted++;
1951 }
1952 }
1953 }
1954
1955 /* We got a low water interrupt: notify upper layer to
1956 * send more data. Must come before tx_mt since servicing
1957 * this condition may cause that condition to clear.
1958 */
1959 if (sio_ir & hooks->intr_tx_explicit) {
1960 port->ip_flags &= ~LOWAT_WRITTEN;
1961
1962 /* ACK the interrupt */
1963 writel(hooks->intr_tx_explicit,
1964 &port->ip_mem->sio_ir.raw);
1965
1966 if (port->ip_notify & N_OUTPUT_LOWAT)
1967 ioc4_cb_output_lowat(port->ip_port);
1968 }
1969
1970 /* Handle tx_mt. Must come after tx_explicit. */
1971 else if (sio_ir & hooks->intr_tx_mt) {
1972 /* If we are expecting a lowat notification
1973 * and we get to this point it probably means that for
1974 * some reason the tx_explicit didn't work as expected
1975 * (that can legitimately happen if the output buffer is
1976 * filled up in just the right way).
1977 * So send the notification now.
1978 */
1979 if (port->ip_notify & N_OUTPUT_LOWAT) {
1980 ioc4_cb_output_lowat(port->ip_port);
1981
1982 /* We need to reload the sio_ir since the lowat
1983 * call may have caused another write to occur,
1984 * clearing the tx_mt condition.
1985 */
1986 sio_ir = PENDING(port);
1987 }
1988
1989 /* If the tx_mt condition still persists even after the
1990 * lowat call, we've got some work to do.
1991 */
1992 if (sio_ir & hooks->intr_tx_mt) {
1993
1994 /* If we are not currently expecting DMA input,
1995 * and the transmitter has just gone idle,
1996 * there is no longer any reason for DMA, so
1997 * disable it.
1998 */
1999 if (!(port->ip_notify
2000 & (N_DATA_READY | N_DDCD))) {
2001 BUG_ON(!(port->ip_sscr
2002 & IOC4_SSCR_DMA_EN));
2003 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2004 writel(port->ip_sscr,
2005 &port->ip_serial_regs->sscr);
2006 }
2007
2008 /* Prevent infinite tx_mt interrupt */
2009 port->ip_ienb &= ~hooks->intr_tx_mt;
2010 }
2011 }
2012 sio_ir = PENDING(port);
2013
2014 /* if the read was aborted and only hooks->intr_rx_high,
2015 * clear hooks->intr_rx_high, so we do not loop forever.
2016 */
2017
2018 if (rx_high_rd_aborted && (sio_ir == hooks->intr_rx_high)) {
2019 sio_ir &= ~hooks->intr_rx_high;
2020 }
2021 } while (sio_ir & hooks->intr_all);
2022
2023 spin_unlock_irqrestore(&port->ip_lock, flags);
2024
2025 /* Re-enable interrupts before returning from interrupt handler.
2026 * Getting interrupted here is okay. It'll just v() our semaphore, and
2027 * we'll come through the loop again.
2028 */
2029
2030 write_ireg(port->ip_ioc4_soft, port->ip_ienb, IOC4_W_IES,
2031 IOC4_SIO_INTR_TYPE);
2032 }
2033
2034 /*
2035 * ioc4_cb_post_ncs - called for some basic errors
2036 * @port: port to use
2037 * @ncs: event
2038 */
2039 static void ioc4_cb_post_ncs(struct uart_port *the_port, int ncs)
2040 {
2041 struct uart_icount *icount;
2042
2043 icount = &the_port->icount;
2044
2045 if (ncs & NCS_BREAK)
2046 icount->brk++;
2047 if (ncs & NCS_FRAMING)
2048 icount->frame++;
2049 if (ncs & NCS_OVERRUN)
2050 icount->overrun++;
2051 if (ncs & NCS_PARITY)
2052 icount->parity++;
2053 }
2054
2055 /**
2056 * do_read - Read in bytes from the port. Return the number of bytes
2057 * actually read.
2058 * @the_port: port to use
2059 * @buf: place to put the stuff we read
2060 * @len: how big 'buf' is
2061 */
2062
2063 static inline int do_read(struct uart_port *the_port, unsigned char *buf,
2064 int len)
2065 {
2066 int prod_ptr, cons_ptr, total;
2067 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2068 struct ring *inring;
2069 struct ring_entry *entry;
2070 struct hooks *hooks = port->ip_hooks;
2071 int byte_num;
2072 char *sc;
2073 int loop_counter;
2074
2075 BUG_ON(!(len >= 0));
2076 BUG_ON(!port);
2077
2078 /* There is a nasty timing issue in the IOC4. When the rx_timer
2079 * expires or the rx_high condition arises, we take an interrupt.
2080 * At some point while servicing the interrupt, we read bytes from
2081 * the ring buffer and re-arm the rx_timer. However the rx_timer is
2082 * not started until the first byte is received *after* it is armed,
2083 * and any bytes pending in the rx construction buffers are not drained
2084 * to memory until either there are 4 bytes available or the rx_timer
2085 * expires. This leads to a potential situation where data is left
2086 * in the construction buffers forever - 1 to 3 bytes were received
2087 * after the interrupt was generated but before the rx_timer was
2088 * re-armed. At that point as long as no subsequent bytes are received
2089 * the timer will never be started and the bytes will remain in the
2090 * construction buffer forever. The solution is to execute a DRAIN
2091 * command after rearming the timer. This way any bytes received before
2092 * the DRAIN will be drained to memory, and any bytes received after
2093 * the DRAIN will start the TIMER and be drained when it expires.
2094 * Luckily, this only needs to be done when the DMA buffer is empty
2095 * since there is no requirement that this function return all
2096 * available data as long as it returns some.
2097 */
2098 /* Re-arm the timer */
2099 writel(port->ip_rx_cons | IOC4_SRCIR_ARM, &port->ip_serial_regs->srcir);
2100
2101 prod_ptr = readl(&port->ip_serial_regs->srpir) & PROD_CONS_MASK;
2102 cons_ptr = port->ip_rx_cons;
2103
2104 if (prod_ptr == cons_ptr) {
2105 int reset_dma = 0;
2106
2107 /* Input buffer appears empty, do a flush. */
2108
2109 /* DMA must be enabled for this to work. */
2110 if (!(port->ip_sscr & IOC4_SSCR_DMA_EN)) {
2111 port->ip_sscr |= IOC4_SSCR_DMA_EN;
2112 reset_dma = 1;
2113 }
2114
2115 /* Potential race condition: we must reload the srpir after
2116 * issuing the drain command, otherwise we could think the rx
2117 * buffer is empty, then take a very long interrupt, and when
2118 * we come back it's full and we wait forever for the drain to
2119 * complete.
2120 */
2121 writel(port->ip_sscr | IOC4_SSCR_RX_DRAIN,
2122 &port->ip_serial_regs->sscr);
2123 prod_ptr = readl(&port->ip_serial_regs->srpir)
2124 & PROD_CONS_MASK;
2125
2126 /* We must not wait for the DRAIN to complete unless there are
2127 * at least 8 bytes (2 ring entries) available to receive the
2128 * data otherwise the DRAIN will never complete and we'll
2129 * deadlock here.
2130 * In fact, to make things easier, I'll just ignore the flush if
2131 * there is any data at all now available.
2132 */
2133 if (prod_ptr == cons_ptr) {
2134 loop_counter = 0;
2135 while (readl(&port->ip_serial_regs->sscr) &
2136 IOC4_SSCR_RX_DRAIN) {
2137 loop_counter++;
2138 if (loop_counter > MAXITER)
2139 return -1;
2140 }
2141
2142 /* SIGH. We have to reload the prod_ptr *again* since
2143 * the drain may have caused it to change
2144 */
2145 prod_ptr = readl(&port->ip_serial_regs->srpir)
2146 & PROD_CONS_MASK;
2147 }
2148 if (reset_dma) {
2149 port->ip_sscr &= ~IOC4_SSCR_DMA_EN;
2150 writel(port->ip_sscr, &port->ip_serial_regs->sscr);
2151 }
2152 }
2153 inring = port->ip_inring;
2154 port->ip_flags &= ~READ_ABORTED;
2155
2156 total = 0;
2157 loop_counter = 0xfffff; /* to avoid hangs */
2158
2159 /* Grab bytes from the hardware */
2160 while ((prod_ptr != cons_ptr) && (len > 0)) {
2161 entry = (struct ring_entry *)((caddr_t)inring + cons_ptr);
2162
2163 if ( loop_counter-- <= 0 ) {
2164 printk(KERN_WARNING "IOC4 serial: "
2165 "possible hang condition/"
2166 "port stuck on read.\n");
2167 break;
2168 }
2169
2170 /* According to the producer pointer, this ring entry
2171 * must contain some data. But if the PIO happened faster
2172 * than the DMA, the data may not be available yet, so let's
2173 * wait until it arrives.
2174 */
2175 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2176 /* Indicate the read is aborted so we don't disable
2177 * the interrupt thinking that the consumer is
2178 * congested.
2179 */
2180 port->ip_flags |= READ_ABORTED;
2181 len = 0;
2182 break;
2183 }
2184
2185 /* Load the bytes/status out of the ring entry */
2186 for (byte_num = 0; byte_num < 4 && len > 0; byte_num++) {
2187 sc = &(entry->ring_sc[byte_num]);
2188
2189 /* Check for change in modem state or overrun */
2190 if ((*sc & IOC4_RXSB_MODEM_VALID)
2191 && (port->ip_notify & N_DDCD)) {
2192 /* Notify upper layer if DCD dropped */
2193
2194 if ((port->ip_flags & DCD_ON)
2195 && !(*sc & IOC4_RXSB_DCD)) {
2196
2197 /* If we have already copied some data,
2198 * return it. We'll pick up the carrier
2199 * drop on the next pass. That way we
2200 * don't throw away the data that has
2201 * already been copied back to
2202 * the caller's buffer.
2203 */
2204 if (total > 0) {
2205 len = 0;
2206 break;
2207 }
2208 port->ip_flags &= ~DCD_ON;
2209
2210 /* Turn off this notification so the
2211 * carrier drop protocol won't see it
2212 * again when it does a read.
2213 */
2214 *sc &= ~IOC4_RXSB_MODEM_VALID;
2215
2216 /* To keep things consistent, we need
2217 * to update the consumer pointer so
2218 * the next reader won't come in and
2219 * try to read the same ring entries
2220 * again. This must be done here before
2221 * the dcd change.
2222 */
2223
2224 if ((entry->ring_allsc & RING_ANY_VALID)
2225 == 0) {
2226 cons_ptr += (int)sizeof
2227 (struct ring_entry);
2228 cons_ptr &= PROD_CONS_MASK;
2229 }
2230 writel(cons_ptr,
2231 &port->ip_serial_regs->srcir);
2232 port->ip_rx_cons = cons_ptr;
2233
2234 /* Notify upper layer of carrier drop */
2235 if ((port->ip_notify & N_DDCD)
2236 && port->ip_port) {
2237 the_port->icount.dcd = 0;
2238 wake_up_interruptible
2239 (&the_port->info->
2240 delta_msr_wait);
2241 }
2242
2243 /* If we had any data to return, we
2244 * would have returned it above.
2245 */
2246 return 0;
2247 }
2248 }
2249 if (*sc & IOC4_RXSB_MODEM_VALID) {
2250 /* Notify that an input overrun occurred */
2251 if ((*sc & IOC4_RXSB_OVERRUN)
2252 && (port->ip_notify & N_OVERRUN_ERROR)) {
2253 ioc4_cb_post_ncs(the_port, NCS_OVERRUN);
2254 }
2255 /* Don't look at this byte again */
2256 *sc &= ~IOC4_RXSB_MODEM_VALID;
2257 }
2258
2259 /* Check for valid data or RX errors */
2260 if ((*sc & IOC4_RXSB_DATA_VALID) &&
2261 ((*sc & (IOC4_RXSB_PAR_ERR
2262 | IOC4_RXSB_FRAME_ERR
2263 | IOC4_RXSB_BREAK))
2264 && (port->ip_notify & (N_PARITY_ERROR
2265 | N_FRAMING_ERROR
2266 | N_BREAK)))) {
2267 /* There is an error condition on the next byte.
2268 * If we have already transferred some bytes,
2269 * we'll stop here. Otherwise if this is the
2270 * first byte to be read, we'll just transfer
2271 * it alone after notifying the
2272 * upper layer of its status.
2273 */
2274 if (total > 0) {
2275 len = 0;
2276 break;
2277 } else {
2278 if ((*sc & IOC4_RXSB_PAR_ERR) &&
2279 (port->ip_notify & N_PARITY_ERROR)) {
2280 ioc4_cb_post_ncs(the_port,
2281 NCS_PARITY);
2282 }
2283 if ((*sc & IOC4_RXSB_FRAME_ERR) &&
2284 (port->ip_notify & N_FRAMING_ERROR)){
2285 ioc4_cb_post_ncs(the_port,
2286 NCS_FRAMING);
2287 }
2288 if ((*sc & IOC4_RXSB_BREAK)
2289 && (port->ip_notify & N_BREAK)) {
2290 ioc4_cb_post_ncs
2291 (the_port,
2292 NCS_BREAK);
2293 }
2294 len = 1;
2295 }
2296 }
2297 if (*sc & IOC4_RXSB_DATA_VALID) {
2298 *sc &= ~IOC4_RXSB_DATA_VALID;
2299 *buf = entry->ring_data[byte_num];
2300 buf++;
2301 len--;
2302 total++;
2303 }
2304 }
2305
2306 /* If we used up this entry entirely, go on to the next one,
2307 * otherwise we must have run out of buffer space, so
2308 * leave the consumer pointer here for the next read in case
2309 * there are still unread bytes in this entry.
2310 */
2311 if ((entry->ring_allsc & RING_ANY_VALID) == 0) {
2312 cons_ptr += (int)sizeof(struct ring_entry);
2313 cons_ptr &= PROD_CONS_MASK;
2314 }
2315 }
2316
2317 /* Update consumer pointer and re-arm rx timer interrupt */
2318 writel(cons_ptr, &port->ip_serial_regs->srcir);
2319 port->ip_rx_cons = cons_ptr;
2320
2321 /* If we have now dipped below the rx high water mark and we have
2322 * rx_high interrupt turned off, we can now turn it back on again.
2323 */
2324 if ((port->ip_flags & INPUT_HIGH) && (((prod_ptr - cons_ptr)
2325 & PROD_CONS_MASK) < ((port->ip_sscr &
2326 IOC4_SSCR_RX_THRESHOLD)
2327 << IOC4_PROD_CONS_PTR_OFF))) {
2328 port->ip_flags &= ~INPUT_HIGH;
2329 enable_intrs(port, hooks->intr_rx_high);
2330 }
2331 return total;
2332 }
2333
2334 /**
2335 * receive_chars - upper level read. Called with ip_lock.
2336 * @the_port: port to read from
2337 */
2338 static void receive_chars(struct uart_port *the_port)
2339 {
2340 struct tty_struct *tty;
2341 unsigned char ch[IOC4_MAX_CHARS];
2342 int read_count, request_count = IOC4_MAX_CHARS;
2343 struct uart_icount *icount;
2344 struct uart_info *info = the_port->info;
2345 unsigned long pflags;
2346
2347 /* Make sure all the pointers are "good" ones */
2348 if (!info)
2349 return;
2350 if (!info->tty)
2351 return;
2352
2353 spin_lock_irqsave(&the_port->lock, pflags);
2354 tty = info->tty;
2355
2356 request_count = tty_buffer_request_room(tty, IOC4_MAX_CHARS);
2357
2358 if (request_count > 0) {
2359 icount = &the_port->icount;
2360 read_count = do_read(the_port, ch, request_count);
2361 if (read_count > 0) {
2362 tty_insert_flip_string(tty, ch, read_count);
2363 icount->rx += read_count;
2364 }
2365 }
2366
2367 spin_unlock_irqrestore(&the_port->lock, pflags);
2368
2369 tty_flip_buffer_push(tty);
2370 }
2371
2372 /**
2373 * ic4_type - What type of console are we?
2374 * @port: Port to operate with (we ignore since we only have one port)
2375 *
2376 */
2377 static const char *ic4_type(struct uart_port *the_port)
2378 {
2379 if (the_port->mapbase == PROTO_RS232)
2380 return "SGI IOC4 Serial [rs232]";
2381 else
2382 return "SGI IOC4 Serial [rs422]";
2383 }
2384
2385 /**
2386 * ic4_tx_empty - Is the transmitter empty?
2387 * @port: Port to operate on
2388 *
2389 */
2390 static unsigned int ic4_tx_empty(struct uart_port *the_port)
2391 {
2392 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2393 unsigned int ret = 0;
2394
2395 if (port_is_active(port, the_port)) {
2396 if (readl(&port->ip_serial_regs->shadow) & IOC4_SHADOW_TEMT)
2397 ret = TIOCSER_TEMT;
2398 }
2399 return ret;
2400 }
2401
2402 /**
2403 * ic4_stop_tx - stop the transmitter
2404 * @port: Port to operate on
2405 *
2406 */
2407 static void ic4_stop_tx(struct uart_port *the_port)
2408 {
2409 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2410
2411 if (port_is_active(port, the_port))
2412 set_notification(port, N_OUTPUT_LOWAT, 0);
2413 }
2414
2415 /**
2416 * null_void_function -
2417 * @port: Port to operate on
2418 *
2419 */
2420 static void null_void_function(struct uart_port *the_port)
2421 {
2422 }
2423
2424 /**
2425 * ic4_shutdown - shut down the port - free irq and disable
2426 * @port: Port to shut down
2427 *
2428 */
2429 static void ic4_shutdown(struct uart_port *the_port)
2430 {
2431 unsigned long port_flags;
2432 struct ioc4_port *port;
2433 struct uart_info *info;
2434
2435 port = get_ioc4_port(the_port, 0);
2436 if (!port)
2437 return;
2438
2439 info = the_port->info;
2440 port->ip_port = NULL;
2441
2442 wake_up_interruptible(&info->delta_msr_wait);
2443
2444 if (info->tty)
2445 set_bit(TTY_IO_ERROR, &info->tty->flags);
2446
2447 spin_lock_irqsave(&the_port->lock, port_flags);
2448 set_notification(port, N_ALL, 0);
2449 port->ip_flags = PORT_INACTIVE;
2450 spin_unlock_irqrestore(&the_port->lock, port_flags);
2451 }
2452
2453 /**
2454 * ic4_set_mctrl - set control lines (dtr, rts, etc)
2455 * @port: Port to operate on
2456 * @mctrl: Lines to set/unset
2457 *
2458 */
2459 static void ic4_set_mctrl(struct uart_port *the_port, unsigned int mctrl)
2460 {
2461 unsigned char mcr = 0;
2462 struct ioc4_port *port;
2463
2464 port = get_ioc4_port(the_port, 0);
2465 if (!port_is_active(port, the_port))
2466 return;
2467
2468 if (mctrl & TIOCM_RTS)
2469 mcr |= UART_MCR_RTS;
2470 if (mctrl & TIOCM_DTR)
2471 mcr |= UART_MCR_DTR;
2472 if (mctrl & TIOCM_OUT1)
2473 mcr |= UART_MCR_OUT1;
2474 if (mctrl & TIOCM_OUT2)
2475 mcr |= UART_MCR_OUT2;
2476 if (mctrl & TIOCM_LOOP)
2477 mcr |= UART_MCR_LOOP;
2478
2479 set_mcr(the_port, mcr, IOC4_SHADOW_DTR);
2480 }
2481
2482 /**
2483 * ic4_get_mctrl - get control line info
2484 * @port: port to operate on
2485 *
2486 */
2487 static unsigned int ic4_get_mctrl(struct uart_port *the_port)
2488 {
2489 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2490 uint32_t shadow;
2491 unsigned int ret = 0;
2492
2493 if (!port_is_active(port, the_port))
2494 return 0;
2495
2496 shadow = readl(&port->ip_serial_regs->shadow);
2497 if (shadow & IOC4_SHADOW_DCD)
2498 ret |= TIOCM_CAR;
2499 if (shadow & IOC4_SHADOW_DR)
2500 ret |= TIOCM_DSR;
2501 if (shadow & IOC4_SHADOW_CTS)
2502 ret |= TIOCM_CTS;
2503 return ret;
2504 }
2505
2506 /**
2507 * ic4_start_tx - Start transmitter, flush any output
2508 * @port: Port to operate on
2509 *
2510 */
2511 static void ic4_start_tx(struct uart_port *the_port)
2512 {
2513 struct ioc4_port *port = get_ioc4_port(the_port, 0);
2514
2515 if (port_is_active(port, the_port)) {
2516 set_notification(port, N_OUTPUT_LOWAT, 1);
2517 enable_intrs(port, port->ip_hooks->intr_tx_mt);
2518 }
2519 }
2520
2521 /**
2522 * ic4_break_ctl - handle breaks
2523 * @port: Port to operate on
2524 * @break_state: Break state
2525 *
2526 */
2527 static void ic4_break_ctl(struct uart_port *the_port, int break_state)
2528 {
2529 }
2530
2531 /**
2532 * ic4_startup - Start up the serial port
2533 * @port: Port to operate on
2534 *
2535 */
2536 static int ic4_startup(struct uart_port *the_port)
2537 {
2538 int retval;
2539 struct ioc4_port *port;
2540 struct ioc4_control *control;
2541 struct uart_info *info;
2542 unsigned long port_flags;
2543
2544 if (!the_port)
2545 return -ENODEV;
2546 port = get_ioc4_port(the_port, 1);
2547 if (!port)
2548 return -ENODEV;
2549 info = the_port->info;
2550
2551 control = port->ip_control;
2552 if (!control) {
2553 port->ip_port = NULL;
2554 return -ENODEV;
2555 }
2556
2557 /* Start up the serial port */
2558 spin_lock_irqsave(&the_port->lock, port_flags);
2559 retval = ic4_startup_local(the_port);
2560 spin_unlock_irqrestore(&the_port->lock, port_flags);
2561 return retval;
2562 }
2563
2564 /**
2565 * ic4_set_termios - set termios stuff
2566 * @port: port to operate on
2567 * @termios: New settings
2568 * @termios: Old
2569 *
2570 */
2571 static void
2572 ic4_set_termios(struct uart_port *the_port,
2573 struct ktermios *termios, struct ktermios *old_termios)
2574 {
2575 unsigned long port_flags;
2576
2577 spin_lock_irqsave(&the_port->lock, port_flags);
2578 ioc4_change_speed(the_port, termios, old_termios);
2579 spin_unlock_irqrestore(&the_port->lock, port_flags);
2580 }
2581
2582 /**
2583 * ic4_request_port - allocate resources for port - no op....
2584 * @port: port to operate on
2585 *
2586 */
2587 static int ic4_request_port(struct uart_port *port)
2588 {
2589 return 0;
2590 }
2591
2592 /* Associate the uart functions above - given to serial core */
2593
2594 static struct uart_ops ioc4_ops = {
2595 .tx_empty = ic4_tx_empty,
2596 .set_mctrl = ic4_set_mctrl,
2597 .get_mctrl = ic4_get_mctrl,
2598 .stop_tx = ic4_stop_tx,
2599 .start_tx = ic4_start_tx,
2600 .stop_rx = null_void_function,
2601 .enable_ms = null_void_function,
2602 .break_ctl = ic4_break_ctl,
2603 .startup = ic4_startup,
2604 .shutdown = ic4_shutdown,
2605 .set_termios = ic4_set_termios,
2606 .type = ic4_type,
2607 .release_port = null_void_function,
2608 .request_port = ic4_request_port,
2609 };
2610
2611 /*
2612 * Boot-time initialization code
2613 */
2614
2615 static struct uart_driver ioc4_uart_rs232 = {
2616 .owner = THIS_MODULE,
2617 .driver_name = "ioc4_serial_rs232",
2618 .dev_name = DEVICE_NAME_RS232,
2619 .major = DEVICE_MAJOR,
2620 .minor = DEVICE_MINOR_RS232,
2621 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2622 };
2623
2624 static struct uart_driver ioc4_uart_rs422 = {
2625 .owner = THIS_MODULE,
2626 .driver_name = "ioc4_serial_rs422",
2627 .dev_name = DEVICE_NAME_RS422,
2628 .major = DEVICE_MAJOR,
2629 .minor = DEVICE_MINOR_RS422,
2630 .nr = IOC4_NUM_CARDS * IOC4_NUM_SERIAL_PORTS,
2631 };
2632
2633
2634 /**
2635 * ioc4_serial_remove_one - detach function
2636 *
2637 * @idd: IOC4 master module data for this IOC4
2638 */
2639
2640 static int ioc4_serial_remove_one(struct ioc4_driver_data *idd)
2641 {
2642 int port_num, port_type;
2643 struct ioc4_control *control;
2644 struct uart_port *the_port;
2645 struct ioc4_port *port;
2646 struct ioc4_soft *soft;
2647
2648 /* If serial driver did not attach, don't try to detach */
2649 control = idd->idd_serial_data;
2650 if (!control)
2651 return 0;
2652
2653 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2654 for (port_type = UART_PORT_MIN;
2655 port_type < UART_PORT_COUNT;
2656 port_type++) {
2657 the_port = &control->ic_port[port_num].icp_uart_port
2658 [port_type];
2659 if (the_port) {
2660 switch (port_type) {
2661 case UART_PORT_RS422:
2662 uart_remove_one_port(&ioc4_uart_rs422,
2663 the_port);
2664 break;
2665 default:
2666 case UART_PORT_RS232:
2667 uart_remove_one_port(&ioc4_uart_rs232,
2668 the_port);
2669 break;
2670 }
2671 }
2672 }
2673 port = control->ic_port[port_num].icp_port;
2674 /* we allocate in pairs */
2675 if (!(port_num & 1) && port) {
2676 pci_free_consistent(port->ip_pdev,
2677 TOTAL_RING_BUF_SIZE,
2678 port->ip_cpu_ringbuf,
2679 port->ip_dma_ringbuf);
2680 kfree(port);
2681 }
2682 }
2683 soft = control->ic_soft;
2684 if (soft) {
2685 free_irq(control->ic_irq, soft);
2686 if (soft->is_ioc4_serial_addr) {
2687 iounmap(soft->is_ioc4_serial_addr);
2688 release_region((unsigned long)
2689 soft->is_ioc4_serial_addr,
2690 sizeof(struct ioc4_serial));
2691 }
2692 kfree(soft);
2693 }
2694 kfree(control);
2695 idd->idd_serial_data = NULL;
2696
2697 return 0;
2698 }
2699
2700
2701 /**
2702 * ioc4_serial_core_attach_rs232 - register with serial core
2703 * This is done during pci probing
2704 * @pdev: handle for this card
2705 */
2706 static inline int
2707 ioc4_serial_core_attach(struct pci_dev *pdev, int port_type)
2708 {
2709 struct ioc4_port *port;
2710 struct uart_port *the_port;
2711 struct ioc4_driver_data *idd = pci_get_drvdata(pdev);
2712 struct ioc4_control *control = idd->idd_serial_data;
2713 int port_num;
2714 int port_type_idx;
2715 struct uart_driver *u_driver;
2716
2717
2718 DPRINT_CONFIG(("%s: attach pdev 0x%p - control 0x%p\n",
2719 __FUNCTION__, pdev, (void *)control));
2720
2721 if (!control)
2722 return -ENODEV;
2723
2724 port_type_idx = (port_type == PROTO_RS232) ? UART_PORT_RS232
2725 : UART_PORT_RS422;
2726
2727 u_driver = (port_type == PROTO_RS232) ? &ioc4_uart_rs232
2728 : &ioc4_uart_rs422;
2729
2730 /* once around for each port on this card */
2731 for (port_num = 0; port_num < IOC4_NUM_SERIAL_PORTS; port_num++) {
2732 the_port = &control->ic_port[port_num].icp_uart_port
2733 [port_type_idx];
2734 port = control->ic_port[port_num].icp_port;
2735 port->ip_all_ports[port_type_idx] = the_port;
2736
2737 DPRINT_CONFIG(("%s: attach the_port 0x%p / port 0x%p : type %s\n",
2738 __FUNCTION__, (void *)the_port,
2739 (void *)port,
2740 port_type == PROTO_RS232 ? "rs232" : "rs422"));
2741
2742 /* membase, iobase and mapbase just need to be non-0 */
2743 the_port->membase = (unsigned char __iomem *)1;
2744 the_port->iobase = (pdev->bus->number << 16) | port_num;
2745 the_port->line = (Num_of_ioc4_cards << 2) | port_num;
2746 the_port->mapbase = port_type;
2747 the_port->type = PORT_16550A;
2748 the_port->fifosize = IOC4_FIFO_CHARS;
2749 the_port->ops = &ioc4_ops;
2750 the_port->irq = control->ic_irq;
2751 the_port->dev = &pdev->dev;
2752 spin_lock_init(&the_port->lock);
2753 if (uart_add_one_port(u_driver, the_port) < 0) {
2754 printk(KERN_WARNING
2755 "%s: unable to add port %d bus %d\n",
2756 __FUNCTION__, the_port->line, pdev->bus->number);
2757 } else {
2758 DPRINT_CONFIG(
2759 ("IOC4 serial port %d irq = %d, bus %d\n",
2760 the_port->line, the_port->irq, pdev->bus->number));
2761 }
2762 }
2763 return 0;
2764 }
2765
2766 /**
2767 * ioc4_serial_attach_one - register attach function
2768 * called per card found from IOC4 master module.
2769 * @idd: Master module data for this IOC4
2770 */
2771 int
2772 ioc4_serial_attach_one(struct ioc4_driver_data *idd)
2773 {
2774 unsigned long tmp_addr1;
2775 struct ioc4_serial __iomem *serial;
2776 struct ioc4_soft *soft;
2777 struct ioc4_control *control;
2778 int ret = 0;
2779
2780
2781 DPRINT_CONFIG(("%s (0x%p, 0x%p)\n", __FUNCTION__, idd->idd_pdev,
2782 idd->idd_pci_id));
2783
2784 /* PCI-RT does not bring out serial connections.
2785 * Do not attach to this particular IOC4.
2786 */
2787 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
2788 return 0;
2789
2790 /* request serial registers */
2791 tmp_addr1 = idd->idd_bar0 + IOC4_SERIAL_OFFSET;
2792
2793 if (!request_region(tmp_addr1, sizeof(struct ioc4_serial),
2794 "sioc4_uart")) {
2795 printk(KERN_WARNING
2796 "ioc4 (%p): unable to get request region for "
2797 "uart space\n", (void *)idd->idd_pdev);
2798 ret = -ENODEV;
2799 goto out1;
2800 }
2801 serial = ioremap(tmp_addr1, sizeof(struct ioc4_serial));
2802 if (!serial) {
2803 printk(KERN_WARNING
2804 "ioc4 (%p) : unable to remap ioc4 serial register\n",
2805 (void *)idd->idd_pdev);
2806 ret = -ENODEV;
2807 goto out2;
2808 }
2809 DPRINT_CONFIG(("%s : mem 0x%p, serial 0x%p\n",
2810 __FUNCTION__, (void *)idd->idd_misc_regs,
2811 (void *)serial));
2812
2813 /* Get memory for the new card */
2814 control = kmalloc(sizeof(struct ioc4_control), GFP_KERNEL);
2815
2816 if (!control) {
2817 printk(KERN_WARNING "ioc4_attach_one"
2818 ": unable to get memory for the IOC4\n");
2819 ret = -ENOMEM;
2820 goto out2;
2821 }
2822 memset(control, 0, sizeof(struct ioc4_control));
2823 idd->idd_serial_data = control;
2824
2825 /* Allocate the soft structure */
2826 soft = kmalloc(sizeof(struct ioc4_soft), GFP_KERNEL);
2827 if (!soft) {
2828 printk(KERN_WARNING
2829 "ioc4 (%p): unable to get memory for the soft struct\n",
2830 (void *)idd->idd_pdev);
2831 ret = -ENOMEM;
2832 goto out3;
2833 }
2834 memset(soft, 0, sizeof(struct ioc4_soft));
2835
2836 spin_lock_init(&soft->is_ir_lock);
2837 soft->is_ioc4_misc_addr = idd->idd_misc_regs;
2838 soft->is_ioc4_serial_addr = serial;
2839
2840 /* Init the IOC4 */
2841 writel(0xf << IOC4_SIO_CR_CMD_PULSE_SHIFT,
2842 &idd->idd_misc_regs->sio_cr.raw);
2843
2844 /* Enable serial port mode select generic PIO pins as outputs */
2845 writel(IOC4_GPCR_UART0_MODESEL | IOC4_GPCR_UART1_MODESEL
2846 | IOC4_GPCR_UART2_MODESEL | IOC4_GPCR_UART3_MODESEL,
2847 &idd->idd_misc_regs->gpcr_s.raw);
2848
2849 /* Clear and disable all serial interrupts */
2850 write_ireg(soft, ~0, IOC4_W_IEC, IOC4_SIO_INTR_TYPE);
2851 writel(~0, &idd->idd_misc_regs->sio_ir.raw);
2852 write_ireg(soft, IOC4_OTHER_IR_SER_MEMERR, IOC4_W_IEC,
2853 IOC4_OTHER_INTR_TYPE);
2854 writel(IOC4_OTHER_IR_SER_MEMERR, &idd->idd_misc_regs->other_ir.raw);
2855 control->ic_soft = soft;
2856
2857 /* Hook up interrupt handler */
2858 if (!request_irq(idd->idd_pdev->irq, ioc4_intr, IRQF_SHARED,
2859 "sgi-ioc4serial", soft)) {
2860 control->ic_irq = idd->idd_pdev->irq;
2861 } else {
2862 printk(KERN_WARNING
2863 "%s : request_irq fails for IRQ 0x%x\n ",
2864 __FUNCTION__, idd->idd_pdev->irq);
2865 }
2866 ret = ioc4_attach_local(idd);
2867 if (ret)
2868 goto out4;
2869
2870 /* register port with the serial core - 1 rs232, 1 rs422 */
2871
2872 if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS232)))
2873 goto out4;
2874
2875 if ((ret = ioc4_serial_core_attach(idd->idd_pdev, PROTO_RS422)))
2876 goto out5;
2877
2878 Num_of_ioc4_cards++;
2879
2880 return ret;
2881
2882 /* error exits that give back resources */
2883 out5:
2884 ioc4_serial_remove_one(idd);
2885 out4:
2886 kfree(soft);
2887 out3:
2888 kfree(control);
2889 out2:
2890 if (serial)
2891 iounmap(serial);
2892 release_region(tmp_addr1, sizeof(struct ioc4_serial));
2893 out1:
2894
2895 return ret;
2896 }
2897
2898
2899 static struct ioc4_submodule ioc4_serial_submodule = {
2900 .is_name = "IOC4_serial",
2901 .is_owner = THIS_MODULE,
2902 .is_probe = ioc4_serial_attach_one,
2903 .is_remove = ioc4_serial_remove_one,
2904 };
2905
2906 /**
2907 * ioc4_serial_init - module init
2908 */
2909 int ioc4_serial_init(void)
2910 {
2911 int ret;
2912
2913 /* register with serial core */
2914 if ((ret = uart_register_driver(&ioc4_uart_rs232)) < 0) {
2915 printk(KERN_WARNING
2916 "%s: Couldn't register rs232 IOC4 serial driver\n",
2917 __FUNCTION__);
2918 return ret;
2919 }
2920 if ((ret = uart_register_driver(&ioc4_uart_rs422)) < 0) {
2921 printk(KERN_WARNING
2922 "%s: Couldn't register rs422 IOC4 serial driver\n",
2923 __FUNCTION__);
2924 return ret;
2925 }
2926
2927 /* register with IOC4 main module */
2928 return ioc4_register_submodule(&ioc4_serial_submodule);
2929 }
2930
2931 static void __devexit ioc4_serial_exit(void)
2932 {
2933 ioc4_unregister_submodule(&ioc4_serial_submodule);
2934 uart_unregister_driver(&ioc4_uart_rs232);
2935 uart_unregister_driver(&ioc4_uart_rs422);
2936 }
2937
2938 late_initcall(ioc4_serial_init); /* Call only after tty init is done */
2939 module_exit(ioc4_serial_exit);
2940
2941 MODULE_AUTHOR("Pat Gefre - Silicon Graphics Inc. (SGI) <pfg@sgi.com>");
2942 MODULE_DESCRIPTION("Serial PCI driver module for SGI IOC4 Base-IO Card");
2943 MODULE_LICENSE("GPL");
Linux with added FPC-III support