include/asm-mips/i8259.h

   1 /*
   2  *      include/asm-mips/i8259.h
   3  *
   4  *      i8259A interrupt definitions.
   5  *
   6  *      Copyright (C) 2003  Maciej W. Rozycki
   7  *      Copyright (C) 2003  Ralf Baechle <ralf@linux-mips.org>
   8  *
   9  *      This program is free software; you can redistribute it and/or
  10  *      modify it under the terms of the GNU General Public License
  11  *      as published by the Free Software Foundation; either version
  12  *      2 of the License, or (at your option) any later version.
  13  */
  14 #ifndef _ASM_I8259_H
  15 #define _ASM_I8259_H
  16
  17 #include <linux/compiler.h>
  18 #include <linux/spinlock.h>
  19
  20 #include <asm/io.h>
  21
  22 /* i8259A PIC registers */
  23 #define PIC_MASTER_CMD          0x20
  24 #define PIC_MASTER_IMR          0x21
  25 #define PIC_MASTER_ISR          PIC_MASTER_CMD
  26 #define PIC_MASTER_POLL         PIC_MASTER_ISR
  27 #define PIC_MASTER_OCW3         PIC_MASTER_ISR
  28 #define PIC_SLAVE_CMD           0xa0
  29 #define PIC_SLAVE_IMR           0xa1
  30
  31 /* i8259A PIC related value */
  32 #define PIC_CASCADE_IR          2
  33 #define MASTER_ICW4_DEFAULT     0x01
  34 #define SLAVE_ICW4_DEFAULT      0x01
  35 #define PIC_ICW4_AEOI           2
  36
  37 extern spinlock_t i8259A_lock;
  38
  39 extern void init_8259A(int auto_eoi);
  40 extern void enable_8259A_irq(unsigned int irq);
  41 extern void disable_8259A_irq(unsigned int irq);
  42
  43 extern void init_i8259_irqs(void);
  44
  45 #define I8259A_IRQ_BASE 0
  46
  47 /*
  48  * Do the traditional i8259 interrupt polling thing.  This is for the few
  49  * cases where no better interrupt acknowledge method is available and we
  50  * absolutely must touch the i8259.
  51  */
  52 static inline int i8259_irq(void)
  53 {
  54         int irq;
  55
  56         spin_lock(&i8259A_lock);
  57
  58         /* Perform an interrupt acknowledge cycle on controller 1. */
  59         outb(0x0C, PIC_MASTER_CMD);             /* prepare for poll */
  60         irq = inb(PIC_MASTER_CMD) & 7;
  61         if (irq == PIC_CASCADE_IR) {
  62                 /*
  63                  * Interrupt is cascaded so perform interrupt
  64                  * acknowledge on controller 2.
  65                  */
  66                 outb(0x0C, PIC_SLAVE_CMD);              /* prepare for poll */
  67                 irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
  68         }
  69
  70         if (unlikely(irq == 7)) {
  71                 /*
  72                  * This may be a spurious interrupt.
  73                  *
  74                  * Read the interrupt status register (ISR). If the most
  75                  * significant bit is not set then there is no valid
  76                  * interrupt.
  77                  */
  78                 outb(0x0B, PIC_MASTER_ISR);             /* ISR register */
  79                 if(~inb(PIC_MASTER_ISR) & 0x80)
  80                         irq = -1;
  81         }
  82
  83         spin_unlock(&i8259A_lock);
  84
  85         return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
  86 }
  87
  88 #endif /* _ASM_I8259_H */