include/asm-powerpc/mpic.h

   1 #ifndef _ASM_POWERPC_MPIC_H
   2 #define _ASM_POWERPC_MPIC_H
   3 #ifdef __KERNEL__
   4
   5 #include <linux/irq.h>
   6 #include <asm/dcr.h>
   7
   8 /*
   9  * Global registers
  10  */
  11
  12 #define MPIC_GREG_BASE                  0x01000
  13
  14 #define MPIC_GREG_FEATURE_0             0x00000
  15 #define         MPIC_GREG_FEATURE_LAST_SRC_MASK         0x07ff0000
  16 #define         MPIC_GREG_FEATURE_LAST_SRC_SHIFT        16
  17 #define         MPIC_GREG_FEATURE_LAST_CPU_MASK         0x00001f00
  18 #define         MPIC_GREG_FEATURE_LAST_CPU_SHIFT        8
  19 #define         MPIC_GREG_FEATURE_VERSION_MASK          0xff
  20 #define MPIC_GREG_FEATURE_1             0x00010
  21 #define MPIC_GREG_GLOBAL_CONF_0         0x00020
  22 #define         MPIC_GREG_GCONF_RESET                   0x80000000
  23 #define         MPIC_GREG_GCONF_8259_PTHROU_DIS         0x20000000
  24 #define         MPIC_GREG_GCONF_BASE_MASK               0x000fffff
  25 #define MPIC_GREG_GLOBAL_CONF_1         0x00030
  26 #define         MPIC_GREG_GLOBAL_CONF_1_SIE             0x08000000
  27 #define         MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK  0x70000000
  28 #define         MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r)    \
  29                         (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
  30 #define MPIC_GREG_VENDOR_0              0x00040
  31 #define MPIC_GREG_VENDOR_1              0x00050
  32 #define MPIC_GREG_VENDOR_2              0x00060
  33 #define MPIC_GREG_VENDOR_3              0x00070
  34 #define MPIC_GREG_VENDOR_ID             0x00080
  35 #define         MPIC_GREG_VENDOR_ID_STEPPING_MASK       0x00ff0000
  36 #define         MPIC_GREG_VENDOR_ID_STEPPING_SHIFT      16
  37 #define         MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK      0x0000ff00
  38 #define         MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT     8
  39 #define         MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK      0x000000ff
  40 #define MPIC_GREG_PROCESSOR_INIT        0x00090
  41 #define MPIC_GREG_IPI_VECTOR_PRI_0      0x000a0
  42 #define MPIC_GREG_IPI_VECTOR_PRI_1      0x000b0
  43 #define MPIC_GREG_IPI_VECTOR_PRI_2      0x000c0
  44 #define MPIC_GREG_IPI_VECTOR_PRI_3      0x000d0
  45 #define MPIC_GREG_IPI_STRIDE            0x10
  46 #define MPIC_GREG_SPURIOUS              0x000e0
  47 #define MPIC_GREG_TIMER_FREQ            0x000f0
  48
  49 /*
  50  *
  51  * Timer registers
  52  */
  53 #define MPIC_TIMER_BASE                 0x01100
  54 #define MPIC_TIMER_STRIDE               0x40
  55
  56 #define MPIC_TIMER_CURRENT_CNT          0x00000
  57 #define MPIC_TIMER_BASE_CNT             0x00010
  58 #define MPIC_TIMER_VECTOR_PRI           0x00020
  59 #define MPIC_TIMER_DESTINATION          0x00030
  60
  61 /*
  62  * Per-Processor registers
  63  */
  64
  65 #define MPIC_CPU_THISBASE               0x00000
  66 #define MPIC_CPU_BASE                   0x20000
  67 #define MPIC_CPU_STRIDE                 0x01000
  68
  69 #define MPIC_CPU_IPI_DISPATCH_0         0x00040
  70 #define MPIC_CPU_IPI_DISPATCH_1         0x00050
  71 #define MPIC_CPU_IPI_DISPATCH_2         0x00060
  72 #define MPIC_CPU_IPI_DISPATCH_3         0x00070
  73 #define MPIC_CPU_IPI_DISPATCH_STRIDE    0x00010
  74 #define MPIC_CPU_CURRENT_TASK_PRI       0x00080
  75 #define         MPIC_CPU_TASKPRI_MASK                   0x0000000f
  76 #define MPIC_CPU_WHOAMI                 0x00090
  77 #define         MPIC_CPU_WHOAMI_MASK                    0x0000001f
  78 #define MPIC_CPU_INTACK                 0x000a0
  79 #define MPIC_CPU_EOI                    0x000b0
  80
  81 /*
  82  * Per-source registers
  83  */
  84
  85 #define MPIC_IRQ_BASE                   0x10000
  86 #define MPIC_IRQ_STRIDE                 0x00020
  87 #define MPIC_IRQ_VECTOR_PRI             0x00000
  88 #define         MPIC_VECPRI_MASK                        0x80000000
  89 #define         MPIC_VECPRI_ACTIVITY                    0x40000000      /* Read Only */
  90 #define         MPIC_VECPRI_PRIORITY_MASK               0x000f0000
  91 #define         MPIC_VECPRI_PRIORITY_SHIFT              16
  92 #define         MPIC_VECPRI_VECTOR_MASK                 0x000007ff
  93 #define         MPIC_VECPRI_POLARITY_POSITIVE           0x00800000
  94 #define         MPIC_VECPRI_POLARITY_NEGATIVE           0x00000000
  95 #define         MPIC_VECPRI_POLARITY_MASK               0x00800000
  96 #define         MPIC_VECPRI_SENSE_LEVEL                 0x00400000
  97 #define         MPIC_VECPRI_SENSE_EDGE                  0x00000000
  98 #define         MPIC_VECPRI_SENSE_MASK                  0x00400000
  99 #define MPIC_IRQ_DESTINATION            0x00010
 100
 101 #define MPIC_MAX_IRQ_SOURCES    2048
 102 #define MPIC_MAX_CPUS           32
 103 #define MPIC_MAX_ISU            32
 104
 105 /*
 106  * Special vector numbers (internal use only)
 107  */
 108 #define MPIC_VEC_SPURRIOUS      255
 109 #define MPIC_VEC_IPI_3          254
 110 #define MPIC_VEC_IPI_2          253
 111 #define MPIC_VEC_IPI_1          252
 112 #define MPIC_VEC_IPI_0          251
 113
 114 /* unused */
 115 #define MPIC_VEC_TIMER_3        250
 116 #define MPIC_VEC_TIMER_2        249
 117 #define MPIC_VEC_TIMER_1        248
 118 #define MPIC_VEC_TIMER_0        247
 119
 120 /*
 121  * Tsi108 implementation of MPIC has many differences from the original one
 122  */
 123
 124 /*
 125  * Global registers
 126  */
 127
 128 #define TSI108_GREG_BASE                0x00000
 129 #define TSI108_GREG_FEATURE_0           0x00000
 130 #define TSI108_GREG_GLOBAL_CONF_0       0x00004
 131 #define TSI108_GREG_VENDOR_ID           0x0000c
 132 #define TSI108_GREG_IPI_VECTOR_PRI_0    0x00204         /* Doorbell 0 */
 133 #define TSI108_GREG_IPI_STRIDE          0x0c
 134 #define TSI108_GREG_SPURIOUS            0x00010
 135 #define TSI108_GREG_TIMER_FREQ          0x00014
 136
 137 /*
 138  * Timer registers
 139  */
 140 #define TSI108_TIMER_BASE               0x0030
 141 #define TSI108_TIMER_STRIDE             0x10
 142 #define TSI108_TIMER_CURRENT_CNT        0x00000
 143 #define TSI108_TIMER_BASE_CNT           0x00004
 144 #define TSI108_TIMER_VECTOR_PRI         0x00008
 145 #define TSI108_TIMER_DESTINATION        0x0000c
 146
 147 /*
 148  * Per-Processor registers
 149  */
 150 #define TSI108_CPU_BASE                 0x00300
 151 #define TSI108_CPU_STRIDE               0x00040
 152 #define TSI108_CPU_IPI_DISPATCH_0       0x00200
 153 #define TSI108_CPU_IPI_DISPATCH_STRIDE  0x00000
 154 #define TSI108_CPU_CURRENT_TASK_PRI     0x00000
 155 #define TSI108_CPU_WHOAMI               0xffffffff
 156 #define TSI108_CPU_INTACK               0x00004
 157 #define TSI108_CPU_EOI                  0x00008
 158
 159 /*
 160  * Per-source registers
 161  */
 162 #define TSI108_IRQ_BASE                 0x00100
 163 #define TSI108_IRQ_STRIDE               0x00008
 164 #define TSI108_IRQ_VECTOR_PRI           0x00000
 165 #define TSI108_VECPRI_VECTOR_MASK       0x000000ff
 166 #define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
 167 #define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
 168 #define TSI108_VECPRI_SENSE_LEVEL       0x02000000
 169 #define TSI108_VECPRI_SENSE_EDGE        0x00000000
 170 #define TSI108_VECPRI_POLARITY_MASK     0x01000000
 171 #define TSI108_VECPRI_SENSE_MASK        0x02000000
 172 #define TSI108_IRQ_DESTINATION          0x00004
 173
 174 /* weird mpic register indices and mask bits in the HW info array */
 175 enum {
 176         MPIC_IDX_GREG_BASE = 0,
 177         MPIC_IDX_GREG_FEATURE_0,
 178         MPIC_IDX_GREG_GLOBAL_CONF_0,
 179         MPIC_IDX_GREG_VENDOR_ID,
 180         MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
 181         MPIC_IDX_GREG_IPI_STRIDE,
 182         MPIC_IDX_GREG_SPURIOUS,
 183         MPIC_IDX_GREG_TIMER_FREQ,
 184
 185         MPIC_IDX_TIMER_BASE,
 186         MPIC_IDX_TIMER_STRIDE,
 187         MPIC_IDX_TIMER_CURRENT_CNT,
 188         MPIC_IDX_TIMER_BASE_CNT,
 189         MPIC_IDX_TIMER_VECTOR_PRI,
 190         MPIC_IDX_TIMER_DESTINATION,
 191
 192         MPIC_IDX_CPU_BASE,
 193         MPIC_IDX_CPU_STRIDE,
 194         MPIC_IDX_CPU_IPI_DISPATCH_0,
 195         MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
 196         MPIC_IDX_CPU_CURRENT_TASK_PRI,
 197         MPIC_IDX_CPU_WHOAMI,
 198         MPIC_IDX_CPU_INTACK,
 199         MPIC_IDX_CPU_EOI,
 200
 201         MPIC_IDX_IRQ_BASE,
 202         MPIC_IDX_IRQ_STRIDE,
 203         MPIC_IDX_IRQ_VECTOR_PRI,
 204
 205         MPIC_IDX_VECPRI_VECTOR_MASK,
 206         MPIC_IDX_VECPRI_POLARITY_POSITIVE,
 207         MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
 208         MPIC_IDX_VECPRI_SENSE_LEVEL,
 209         MPIC_IDX_VECPRI_SENSE_EDGE,
 210         MPIC_IDX_VECPRI_POLARITY_MASK,
 211         MPIC_IDX_VECPRI_SENSE_MASK,
 212         MPIC_IDX_IRQ_DESTINATION,
 213         MPIC_IDX_END
 214 };
 215
 216
 217 #ifdef CONFIG_MPIC_BROKEN_U3
 218 /* Fixup table entry */
 219 struct mpic_irq_fixup
 220 {
 221         u8 __iomem      *base;
 222         u8 __iomem      *applebase;
 223         u32             data;
 224         unsigned int    index;
 225 };
 226 #endif /* CONFIG_MPIC_BROKEN_U3 */
 227
 228
 229 enum mpic_reg_type {
 230         mpic_access_mmio_le,
 231         mpic_access_mmio_be,
 232 #ifdef CONFIG_PPC_DCR
 233         mpic_access_dcr
 234 #endif
 235 };
 236
 237 struct mpic_reg_bank {
 238         u32 __iomem     *base;
 239 #ifdef CONFIG_PPC_DCR
 240         dcr_host_t      dhost;
 241         unsigned int    dbase;
 242         unsigned int    doff;
 243 #endif /* CONFIG_PPC_DCR */
 244 };
 245
 246 /* The instance data of a given MPIC */
 247 struct mpic
 248 {
 249         /* The device node of the interrupt controller */
 250         struct device_node      *of_node;
 251
 252         /* The remapper for this MPIC */
 253         struct irq_host         *irqhost;
 254
 255         /* The "linux" controller struct */
 256         struct irq_chip         hc_irq;
 257 #ifdef CONFIG_MPIC_BROKEN_U3
 258         struct irq_chip         hc_ht_irq;
 259 #endif
 260 #ifdef CONFIG_SMP
 261         struct irq_chip         hc_ipi;
 262 #endif
 263         const char              *name;
 264         /* Flags */
 265         unsigned int            flags;
 266         /* How many irq sources in a given ISU */
 267         unsigned int            isu_size;
 268         unsigned int            isu_shift;
 269         unsigned int            isu_mask;
 270         unsigned int            irq_count;
 271         /* Number of sources */
 272         unsigned int            num_sources;
 273         /* Number of CPUs */
 274         unsigned int            num_cpus;
 275         /* default senses array */
 276         unsigned char           *senses;
 277         unsigned int            senses_count;
 278
 279 #ifdef CONFIG_MPIC_BROKEN_U3
 280         /* The fixup table */
 281         struct mpic_irq_fixup   *fixups;
 282         spinlock_t              fixup_lock;
 283 #endif
 284
 285         /* Register access method */
 286         enum mpic_reg_type      reg_type;
 287
 288         /* The various ioremap'ed bases */
 289         struct mpic_reg_bank    gregs;
 290         struct mpic_reg_bank    tmregs;
 291         struct mpic_reg_bank    cpuregs[MPIC_MAX_CPUS];
 292         struct mpic_reg_bank    isus[MPIC_MAX_ISU];
 293
 294 #ifdef CONFIG_PPC_DCR
 295         unsigned int            dcr_base;
 296 #endif
 297
 298 #ifdef CONFIG_MPIC_WEIRD
 299         /* Pointer to HW info array */
 300         u32                     *hw_set;
 301 #endif
 302
 303         /* link */
 304         struct mpic             *next;
 305 };
 306
 307 /*
 308  * MPIC flags (passed to mpic_alloc)
 309  *
 310  * The top 4 bits contain an MPIC bhw id that is used to index the
 311  * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
 312  * Note setting any ID (leaving those bits to 0) means standard MPIC
 313  */
 314
 315 /* This is the primary controller, only that one has IPIs and
 316  * has afinity control. A non-primary MPIC always uses CPU0
 317  * registers only
 318  */
 319 #define MPIC_PRIMARY                    0x00000001
 320
 321 /* Set this for a big-endian MPIC */
 322 #define MPIC_BIG_ENDIAN                 0x00000002
 323 /* Broken U3 MPIC */
 324 #define MPIC_BROKEN_U3                  0x00000004
 325 /* Broken IPI registers (autodetected) */
 326 #define MPIC_BROKEN_IPI                 0x00000008
 327 /* MPIC wants a reset */
 328 #define MPIC_WANTS_RESET                0x00000010
 329 /* Spurious vector requires EOI */
 330 #define MPIC_SPV_EOI                    0x00000020
 331 /* No passthrough disable */
 332 #define MPIC_NO_PTHROU_DIS              0x00000040
 333 /* DCR based MPIC */
 334 #define MPIC_USES_DCR                   0x00000080
 335
 336 /* MPIC HW modification ID */
 337 #define MPIC_REGSET_MASK                0xf0000000
 338 #define MPIC_REGSET(val)                (((val) & 0xf ) << 28)
 339 #define MPIC_GET_REGSET(flags)          (((flags) >> 28) & 0xf)
 340
 341 #define MPIC_REGSET_STANDARD            MPIC_REGSET(0)  /* Original MPIC */
 342 #define MPIC_REGSET_TSI108              MPIC_REGSET(1)  /* Tsi108/109 PIC */
 343
 344 /* Allocate the controller structure and setup the linux irq descs
 345  * for the range if interrupts passed in. No HW initialization is
 346  * actually performed.
 347  *
 348  * @phys_addr:  physial base address of the MPIC
 349  * @flags:      flags, see constants above
 350  * @isu_size:   number of interrupts in an ISU. Use 0 to use a
 351  *              standard ISU-less setup (aka powermac)
 352  * @irq_offset: first irq number to assign to this mpic
 353  * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
 354  *              to match the number of sources
 355  * @ipi_offset: first irq number to assign to this mpic IPI sources,
 356  *              used only on primary mpic
 357  * @senses:     array of sense values
 358  * @senses_num: number of entries in the array
 359  *
 360  * Note about the sense array. If none is passed, all interrupts are
 361  * setup to be level negative unless MPIC_BROKEN_U3 is set in which
 362  * case they are edge positive (and the array is ignored anyway).
 363  * The values in the array start at the first source of the MPIC,
 364  * that is senses[0] correspond to linux irq "irq_offset".
 365  */
 366 extern struct mpic *mpic_alloc(struct device_node *node,
 367                                phys_addr_t phys_addr,
 368                                unsigned int flags,
 369                                unsigned int isu_size,
 370                                unsigned int irq_count,
 371                                const char *name);
 372
 373 /* Assign ISUs, to call before mpic_init()
 374  *
 375  * @mpic:       controller structure as returned by mpic_alloc()
 376  * @isu_num:    ISU number
 377  * @phys_addr:  physical address of the ISU
 378  */
 379 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
 380                             phys_addr_t phys_addr);
 381
 382 /* Set default sense codes
 383  *
 384  * @mpic:       controller
 385  * @senses:     array of sense codes
 386  * @count:      size of above array
 387  *
 388  * Optionally provide an array (indexed on hardware interrupt numbers
 389  * for this MPIC) of default sense codes for the chip. Those are linux
 390  * sense codes IRQ_TYPE_*
 391  *
 392  * The driver gets ownership of the pointer, don't dispose of it or
 393  * anything like that. __init only.
 394  */
 395 extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
 396
 397
 398 /* Initialize the controller. After this has been called, none of the above
 399  * should be called again for this mpic
 400  */
 401 extern void mpic_init(struct mpic *mpic);
 402
 403 /*
 404  * All of the following functions must only be used after the
 405  * ISUs have been assigned and the controller fully initialized
 406  * with mpic_init()
 407  */
 408
 409
 410 /* Change/Read the priority of an interrupt. Default is 8 for irqs and
 411  * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
 412  * IPI number is then the offset'ed (linux irq number mapped to the IPI)
 413  */
 414 extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
 415 extern unsigned int mpic_irq_get_priority(unsigned int irq);
 416
 417 /* Setup a non-boot CPU */
 418 extern void mpic_setup_this_cpu(void);
 419
 420 /* Clean up for kexec (or cpu offline or ...) */
 421 extern void mpic_teardown_this_cpu(int secondary);
 422
 423 /* Get the current cpu priority for this cpu (0..15) */
 424 extern int mpic_cpu_get_priority(void);
 425
 426 /* Set the current cpu priority for this cpu */
 427 extern void mpic_cpu_set_priority(int prio);
 428
 429 /* Request IPIs on primary mpic */
 430 extern void mpic_request_ipis(void);
 431
 432 /* Send an IPI (non offseted number 0..3) */
 433 extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
 434
 435 /* Send a message (IPI) to a given target (cpu number or MSG_*) */
 436 void smp_mpic_message_pass(int target, int msg);
 437
 438 /* Fetch interrupt from a given mpic */
 439 extern unsigned int mpic_get_one_irq(struct mpic *mpic);
 440 /* This one gets to the primary mpic */
 441 extern unsigned int mpic_get_irq(void);
 442
 443 /* Set the EPIC clock ratio */
 444 void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
 445
 446 /* Enable/Disable EPIC serial interrupt mode */
 447 void mpic_set_serial_int(struct mpic *mpic, int enable);
 448
 449 #endif /* __KERNEL__ */
 450 #endif  /* _ASM_POWERPC_MPIC_H */