include/asm-sh/mmu_context.h

   1 /*
   2  * Copyright (C) 1999 Niibe Yutaka
   3  * Copyright (C) 2003 Paul Mundt
   4  *
   5  * ASID handling idea taken from MIPS implementation.
   6  */
   7 #ifndef __ASM_SH_MMU_CONTEXT_H
   8 #define __ASM_SH_MMU_CONTEXT_H
   9 #ifdef __KERNEL__
  10
  11 #include <asm/cpu/mmu_context.h>
  12 #include <asm/tlbflush.h>
  13 #include <asm/uaccess.h>
  14 #include <asm/io.h>
  15
  16 /*
  17  * The MMU "context" consists of two things:
  18  *    (a) TLB cache version (or round, cycle whatever expression you like)
  19  *    (b) ASID (Address Space IDentifier)
  20  */
  21
  22 /*
  23  * Cache of MMU context last used.
  24  */
  25 extern unsigned long mmu_context_cache;
  26
  27 #define MMU_CONTEXT_ASID_MASK           0x000000ff
  28 #define MMU_CONTEXT_VERSION_MASK        0xffffff00
  29 #define MMU_CONTEXT_FIRST_VERSION       0x00000100
  30 #define NO_CONTEXT                      0
  31
  32 /* ASID is 8-bit value, so it can't be 0x100 */
  33 #define MMU_NO_ASID                     0x100
  34
  35 /*
  36  * Virtual Page Number mask
  37  */
  38 #define MMU_VPN_MASK    0xfffff000
  39
  40 #ifdef CONFIG_MMU
  41 /*
  42  * Get MMU context if needed.
  43  */
  44 static inline void get_mmu_context(struct mm_struct *mm)
  45 {
  46         unsigned long mc = mmu_context_cache;
  47
  48         /* Check if we have old version of context. */
  49         if (((mm->context.id ^ mc) & MMU_CONTEXT_VERSION_MASK) == 0)
  50                 /* It's up to date, do nothing */
  51                 return;
  52
  53         /* It's old, we need to get new context with new version. */
  54         mc = ++mmu_context_cache;
  55         if (!(mc & MMU_CONTEXT_ASID_MASK)) {
  56                 /*
  57                  * We exhaust ASID of this version.
  58                  * Flush all TLB and start new cycle.
  59                  */
  60                 flush_tlb_all();
  61
  62                 /*
  63                  * Fix version; Note that we avoid version #0
  64                  * to distingush NO_CONTEXT.
  65                  */
  66                 if (!mc)
  67                         mmu_context_cache = mc = MMU_CONTEXT_FIRST_VERSION;
  68         }
  69         mm->context.id = mc;
  70 }
  71
  72 /*
  73  * Initialize the context related info for a new mm_struct
  74  * instance.
  75  */
  76 static inline int init_new_context(struct task_struct *tsk,
  77                                        struct mm_struct *mm)
  78 {
  79         mm->context.id = NO_CONTEXT;
  80         return 0;
  81 }
  82
  83 /*
  84  * Destroy context related info for an mm_struct that is about
  85  * to be put to rest.
  86  */
  87 static inline void destroy_context(struct mm_struct *mm)
  88 {
  89         /* Do nothing */
  90 }
  91
  92 static inline void set_asid(unsigned long asid)
  93 {
  94         unsigned long __dummy;
  95
  96         __asm__ __volatile__ ("mov.l    %2, %0\n\t"
  97                               "and      %3, %0\n\t"
  98                               "or       %1, %0\n\t"
  99                               "mov.l    %0, %2"
 100                               : "=&r" (__dummy)
 101                               : "r" (asid), "m" (__m(MMU_PTEH)),
 102                                 "r" (0xffffff00));
 103 }
 104
 105 static inline unsigned long get_asid(void)
 106 {
 107         unsigned long asid;
 108
 109         __asm__ __volatile__ ("mov.l    %1, %0"
 110                               : "=r" (asid)
 111                               : "m" (__m(MMU_PTEH)));
 112         asid &= MMU_CONTEXT_ASID_MASK;
 113         return asid;
 114 }
 115
 116 /*
 117  * After we have set current->mm to a new value, this activates
 118  * the context for the new mm so we see the new mappings.
 119  */
 120 static inline void activate_context(struct mm_struct *mm)
 121 {
 122         get_mmu_context(mm);
 123         set_asid(mm->context.id & MMU_CONTEXT_ASID_MASK);
 124 }
 125
 126 /* MMU_TTB is used for optimizing the fault handling. */
 127 static inline void set_TTB(pgd_t *pgd)
 128 {
 129         ctrl_outl((unsigned long)pgd, MMU_TTB);
 130 }
 131
 132 static inline pgd_t *get_TTB(void)
 133 {
 134         return (pgd_t *)ctrl_inl(MMU_TTB);
 135 }
 136
 137 static inline void switch_mm(struct mm_struct *prev,
 138                              struct mm_struct *next,
 139                              struct task_struct *tsk)
 140 {
 141         if (likely(prev != next)) {
 142                 set_TTB(next->pgd);
 143                 activate_context(next);
 144         }
 145 }
 146
 147 #define deactivate_mm(tsk,mm)   do { } while (0)
 148
 149 #define activate_mm(prev, next) \
 150         switch_mm((prev),(next),NULL)
 151
 152 static inline void
 153 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 154 {
 155 }
 156 #else /* !CONFIG_MMU */
 157 #define get_mmu_context(mm)             do { } while (0)
 158 #define init_new_context(tsk,mm)        (0)
 159 #define destroy_context(mm)             do { } while (0)
 160 #define set_asid(asid)                  do { } while (0)
 161 #define get_asid()                      (0)
 162 #define activate_context(mm)            do { } while (0)
 163 #define switch_mm(prev,next,tsk)        do { } while (0)
 164 #define deactivate_mm(tsk,mm)           do { } while (0)
 165 #define activate_mm(prev,next)          do { } while (0)
 166 #define enter_lazy_tlb(mm,tsk)          do { } while (0)
 167 #endif /* CONFIG_MMU */
 168
 169 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4)
 170 /*
 171  * If this processor has an MMU, we need methods to turn it off/on ..
 172  * paging_init() will also have to be updated for the processor in
 173  * question.
 174  */
 175 static inline void enable_mmu(void)
 176 {
 177         /* Enable MMU */
 178         ctrl_outl(MMU_CONTROL_INIT, MMUCR);
 179         ctrl_barrier();
 180
 181         if (mmu_context_cache == NO_CONTEXT)
 182                 mmu_context_cache = MMU_CONTEXT_FIRST_VERSION;
 183
 184         set_asid(mmu_context_cache & MMU_CONTEXT_ASID_MASK);
 185 }
 186
 187 static inline void disable_mmu(void)
 188 {
 189         unsigned long cr;
 190
 191         cr = ctrl_inl(MMUCR);
 192         cr &= ~MMU_CONTROL_INIT;
 193         ctrl_outl(cr, MMUCR);
 194
 195         ctrl_barrier();
 196 }
 197 #else
 198 /*
 199  * MMU control handlers for processors lacking memory
 200  * management hardware.
 201  */
 202 #define enable_mmu()    do { BUG(); } while (0)
 203 #define disable_mmu()   do { BUG(); } while (0)
 204 #endif
 205
 206 #endif /* __KERNEL__ */
 207 #endif /* __ASM_SH_MMU_CONTEXT_H */