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usb: xhci-plat: properly handle probe deferral for devm_clk_get()
[linux/fpc-iii.git] / arch / mips / math-emu / cp1emu.c
blob41d3e0e7defa71fb14d7c7f698f5a0597ce3bd50
1 /*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
35 */
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
41
42 #include <asm/branch.h>
43 #include <asm/inst.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
47
48 #include <asm/cpu-info.h>
49 #include <asm/processor.h>
50 #include <asm/fpu_emulator.h>
51 #include <asm/fpu.h>
52 #include <asm/mips-r2-to-r6-emul.h>
53
54 #include "ieee754.h"
55
56 /* Function which emulates a floating point instruction. */
57
58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
59 mips_instruction);
60
61 static int fpux_emu(struct pt_regs *,
62 struct mips_fpu_struct *, mips_instruction, void *__user *);
63
64 /* Control registers */
65
66 #define FPCREG_RID 0 /* $0 = revision id */
67 #define FPCREG_FCCR 25 /* $25 = fccr */
68 #define FPCREG_FEXR 26 /* $26 = fexr */
69 #define FPCREG_FENR 28 /* $28 = fenr */
70 #define FPCREG_CSR 31 /* $31 = csr */
71
72 /* convert condition code register number to csr bit */
73 const unsigned int fpucondbit[8] = {
74 FPU_CSR_COND,
75 FPU_CSR_COND1,
76 FPU_CSR_COND2,
77 FPU_CSR_COND3,
78 FPU_CSR_COND4,
79 FPU_CSR_COND5,
80 FPU_CSR_COND6,
81 FPU_CSR_COND7
82 };
83
84 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
85 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
86 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
87 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
88 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
89
90 /*
91 * This functions translates a 32-bit microMIPS instruction
92 * into a 32-bit MIPS32 instruction. Returns 0 on success
93 * and SIGILL otherwise.
94 */
95 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
96 {
97 union mips_instruction insn = *insn_ptr;
98 union mips_instruction mips32_insn = insn;
99 int func, fmt, op;
100
101 switch (insn.mm_i_format.opcode) {
102 case mm_ldc132_op:
103 mips32_insn.mm_i_format.opcode = ldc1_op;
104 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
105 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
106 break;
107 case mm_lwc132_op:
108 mips32_insn.mm_i_format.opcode = lwc1_op;
109 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
110 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
111 break;
112 case mm_sdc132_op:
113 mips32_insn.mm_i_format.opcode = sdc1_op;
114 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
115 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
116 break;
117 case mm_swc132_op:
118 mips32_insn.mm_i_format.opcode = swc1_op;
119 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
120 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
121 break;
122 case mm_pool32i_op:
123 /* NOTE: offset is << by 1 if in microMIPS mode. */
124 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
125 (insn.mm_i_format.rt == mm_bc1t_op)) {
126 mips32_insn.fb_format.opcode = cop1_op;
127 mips32_insn.fb_format.bc = bc_op;
128 mips32_insn.fb_format.flag =
129 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
130 } else
131 return SIGILL;
132 break;
133 case mm_pool32f_op:
134 switch (insn.mm_fp0_format.func) {
135 case mm_32f_01_op:
136 case mm_32f_11_op:
137 case mm_32f_02_op:
138 case mm_32f_12_op:
139 case mm_32f_41_op:
140 case mm_32f_51_op:
141 case mm_32f_42_op:
142 case mm_32f_52_op:
143 op = insn.mm_fp0_format.func;
144 if (op == mm_32f_01_op)
145 func = madd_s_op;
146 else if (op == mm_32f_11_op)
147 func = madd_d_op;
148 else if (op == mm_32f_02_op)
149 func = nmadd_s_op;
150 else if (op == mm_32f_12_op)
151 func = nmadd_d_op;
152 else if (op == mm_32f_41_op)
153 func = msub_s_op;
154 else if (op == mm_32f_51_op)
155 func = msub_d_op;
156 else if (op == mm_32f_42_op)
157 func = nmsub_s_op;
158 else
159 func = nmsub_d_op;
160 mips32_insn.fp6_format.opcode = cop1x_op;
161 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
162 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
163 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
164 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
165 mips32_insn.fp6_format.func = func;
166 break;
167 case mm_32f_10_op:
168 func = -1; /* Invalid */
169 op = insn.mm_fp5_format.op & 0x7;
170 if (op == mm_ldxc1_op)
171 func = ldxc1_op;
172 else if (op == mm_sdxc1_op)
173 func = sdxc1_op;
174 else if (op == mm_lwxc1_op)
175 func = lwxc1_op;
176 else if (op == mm_swxc1_op)
177 func = swxc1_op;
178
179 if (func != -1) {
180 mips32_insn.r_format.opcode = cop1x_op;
181 mips32_insn.r_format.rs =
182 insn.mm_fp5_format.base;
183 mips32_insn.r_format.rt =
184 insn.mm_fp5_format.index;
185 mips32_insn.r_format.rd = 0;
186 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
187 mips32_insn.r_format.func = func;
188 } else
189 return SIGILL;
190 break;
191 case mm_32f_40_op:
192 op = -1; /* Invalid */
193 if (insn.mm_fp2_format.op == mm_fmovt_op)
194 op = 1;
195 else if (insn.mm_fp2_format.op == mm_fmovf_op)
196 op = 0;
197 if (op != -1) {
198 mips32_insn.fp0_format.opcode = cop1_op;
199 mips32_insn.fp0_format.fmt =
200 sdps_format[insn.mm_fp2_format.fmt];
201 mips32_insn.fp0_format.ft =
202 (insn.mm_fp2_format.cc<<2) + op;
203 mips32_insn.fp0_format.fs =
204 insn.mm_fp2_format.fs;
205 mips32_insn.fp0_format.fd =
206 insn.mm_fp2_format.fd;
207 mips32_insn.fp0_format.func = fmovc_op;
208 } else
209 return SIGILL;
210 break;
211 case mm_32f_60_op:
212 func = -1; /* Invalid */
213 if (insn.mm_fp0_format.op == mm_fadd_op)
214 func = fadd_op;
215 else if (insn.mm_fp0_format.op == mm_fsub_op)
216 func = fsub_op;
217 else if (insn.mm_fp0_format.op == mm_fmul_op)
218 func = fmul_op;
219 else if (insn.mm_fp0_format.op == mm_fdiv_op)
220 func = fdiv_op;
221 if (func != -1) {
222 mips32_insn.fp0_format.opcode = cop1_op;
223 mips32_insn.fp0_format.fmt =
224 sdps_format[insn.mm_fp0_format.fmt];
225 mips32_insn.fp0_format.ft =
226 insn.mm_fp0_format.ft;
227 mips32_insn.fp0_format.fs =
228 insn.mm_fp0_format.fs;
229 mips32_insn.fp0_format.fd =
230 insn.mm_fp0_format.fd;
231 mips32_insn.fp0_format.func = func;
232 } else
233 return SIGILL;
234 break;
235 case mm_32f_70_op:
236 func = -1; /* Invalid */
237 if (insn.mm_fp0_format.op == mm_fmovn_op)
238 func = fmovn_op;
239 else if (insn.mm_fp0_format.op == mm_fmovz_op)
240 func = fmovz_op;
241 if (func != -1) {
242 mips32_insn.fp0_format.opcode = cop1_op;
243 mips32_insn.fp0_format.fmt =
244 sdps_format[insn.mm_fp0_format.fmt];
245 mips32_insn.fp0_format.ft =
246 insn.mm_fp0_format.ft;
247 mips32_insn.fp0_format.fs =
248 insn.mm_fp0_format.fs;
249 mips32_insn.fp0_format.fd =
250 insn.mm_fp0_format.fd;
251 mips32_insn.fp0_format.func = func;
252 } else
253 return SIGILL;
254 break;
255 case mm_32f_73_op: /* POOL32FXF */
256 switch (insn.mm_fp1_format.op) {
257 case mm_movf0_op:
258 case mm_movf1_op:
259 case mm_movt0_op:
260 case mm_movt1_op:
261 if ((insn.mm_fp1_format.op & 0x7f) ==
262 mm_movf0_op)
263 op = 0;
264 else
265 op = 1;
266 mips32_insn.r_format.opcode = spec_op;
267 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
268 mips32_insn.r_format.rt =
269 (insn.mm_fp4_format.cc << 2) + op;
270 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
271 mips32_insn.r_format.re = 0;
272 mips32_insn.r_format.func = movc_op;
273 break;
274 case mm_fcvtd0_op:
275 case mm_fcvtd1_op:
276 case mm_fcvts0_op:
277 case mm_fcvts1_op:
278 if ((insn.mm_fp1_format.op & 0x7f) ==
279 mm_fcvtd0_op) {
280 func = fcvtd_op;
281 fmt = swl_format[insn.mm_fp3_format.fmt];
282 } else {
283 func = fcvts_op;
284 fmt = dwl_format[insn.mm_fp3_format.fmt];
285 }
286 mips32_insn.fp0_format.opcode = cop1_op;
287 mips32_insn.fp0_format.fmt = fmt;
288 mips32_insn.fp0_format.ft = 0;
289 mips32_insn.fp0_format.fs =
290 insn.mm_fp3_format.fs;
291 mips32_insn.fp0_format.fd =
292 insn.mm_fp3_format.rt;
293 mips32_insn.fp0_format.func = func;
294 break;
295 case mm_fmov0_op:
296 case mm_fmov1_op:
297 case mm_fabs0_op:
298 case mm_fabs1_op:
299 case mm_fneg0_op:
300 case mm_fneg1_op:
301 if ((insn.mm_fp1_format.op & 0x7f) ==
302 mm_fmov0_op)
303 func = fmov_op;
304 else if ((insn.mm_fp1_format.op & 0x7f) ==
305 mm_fabs0_op)
306 func = fabs_op;
307 else
308 func = fneg_op;
309 mips32_insn.fp0_format.opcode = cop1_op;
310 mips32_insn.fp0_format.fmt =
311 sdps_format[insn.mm_fp3_format.fmt];
312 mips32_insn.fp0_format.ft = 0;
313 mips32_insn.fp0_format.fs =
314 insn.mm_fp3_format.fs;
315 mips32_insn.fp0_format.fd =
316 insn.mm_fp3_format.rt;
317 mips32_insn.fp0_format.func = func;
318 break;
319 case mm_ffloorl_op:
320 case mm_ffloorw_op:
321 case mm_fceill_op:
322 case mm_fceilw_op:
323 case mm_ftruncl_op:
324 case mm_ftruncw_op:
325 case mm_froundl_op:
326 case mm_froundw_op:
327 case mm_fcvtl_op:
328 case mm_fcvtw_op:
329 if (insn.mm_fp1_format.op == mm_ffloorl_op)
330 func = ffloorl_op;
331 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
332 func = ffloor_op;
333 else if (insn.mm_fp1_format.op == mm_fceill_op)
334 func = fceill_op;
335 else if (insn.mm_fp1_format.op == mm_fceilw_op)
336 func = fceil_op;
337 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
338 func = ftruncl_op;
339 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
340 func = ftrunc_op;
341 else if (insn.mm_fp1_format.op == mm_froundl_op)
342 func = froundl_op;
343 else if (insn.mm_fp1_format.op == mm_froundw_op)
344 func = fround_op;
345 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
346 func = fcvtl_op;
347 else
348 func = fcvtw_op;
349 mips32_insn.fp0_format.opcode = cop1_op;
350 mips32_insn.fp0_format.fmt =
351 sd_format[insn.mm_fp1_format.fmt];
352 mips32_insn.fp0_format.ft = 0;
353 mips32_insn.fp0_format.fs =
354 insn.mm_fp1_format.fs;
355 mips32_insn.fp0_format.fd =
356 insn.mm_fp1_format.rt;
357 mips32_insn.fp0_format.func = func;
358 break;
359 case mm_frsqrt_op:
360 case mm_fsqrt_op:
361 case mm_frecip_op:
362 if (insn.mm_fp1_format.op == mm_frsqrt_op)
363 func = frsqrt_op;
364 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
365 func = fsqrt_op;
366 else
367 func = frecip_op;
368 mips32_insn.fp0_format.opcode = cop1_op;
369 mips32_insn.fp0_format.fmt =
370 sdps_format[insn.mm_fp1_format.fmt];
371 mips32_insn.fp0_format.ft = 0;
372 mips32_insn.fp0_format.fs =
373 insn.mm_fp1_format.fs;
374 mips32_insn.fp0_format.fd =
375 insn.mm_fp1_format.rt;
376 mips32_insn.fp0_format.func = func;
377 break;
378 case mm_mfc1_op:
379 case mm_mtc1_op:
380 case mm_cfc1_op:
381 case mm_ctc1_op:
382 case mm_mfhc1_op:
383 case mm_mthc1_op:
384 if (insn.mm_fp1_format.op == mm_mfc1_op)
385 op = mfc_op;
386 else if (insn.mm_fp1_format.op == mm_mtc1_op)
387 op = mtc_op;
388 else if (insn.mm_fp1_format.op == mm_cfc1_op)
389 op = cfc_op;
390 else if (insn.mm_fp1_format.op == mm_ctc1_op)
391 op = ctc_op;
392 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
393 op = mfhc_op;
394 else
395 op = mthc_op;
396 mips32_insn.fp1_format.opcode = cop1_op;
397 mips32_insn.fp1_format.op = op;
398 mips32_insn.fp1_format.rt =
399 insn.mm_fp1_format.rt;
400 mips32_insn.fp1_format.fs =
401 insn.mm_fp1_format.fs;
402 mips32_insn.fp1_format.fd = 0;
403 mips32_insn.fp1_format.func = 0;
404 break;
405 default:
406 return SIGILL;
407 }
408 break;
409 case mm_32f_74_op: /* c.cond.fmt */
410 mips32_insn.fp0_format.opcode = cop1_op;
411 mips32_insn.fp0_format.fmt =
412 sdps_format[insn.mm_fp4_format.fmt];
413 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
414 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
415 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
416 mips32_insn.fp0_format.func =
417 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
418 break;
419 default:
420 return SIGILL;
421 }
422 break;
423 default:
424 return SIGILL;
425 }
426
427 *insn_ptr = mips32_insn;
428 return 0;
429 }
430
431 /*
432 * Redundant with logic already in kernel/branch.c,
433 * embedded in compute_return_epc. At some point,
434 * a single subroutine should be used across both
435 * modules.
436 */
437 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
438 unsigned long *contpc)
439 {
440 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
441 unsigned int fcr31;
442 unsigned int bit = 0;
443
444 switch (insn.i_format.opcode) {
445 case spec_op:
446 switch (insn.r_format.func) {
447 case jalr_op:
448 if (insn.r_format.rd != 0) {
449 regs->regs[insn.r_format.rd] =
450 regs->cp0_epc + dec_insn.pc_inc +
451 dec_insn.next_pc_inc;
452 }
453 /* Fall through */
454 case jr_op:
455 /* For R6, JR already emulated in jalr_op */
456 if (NO_R6EMU && insn.r_format.func == jr_op)
457 break;
458 *contpc = regs->regs[insn.r_format.rs];
459 return 1;
460 }
461 break;
462 case bcond_op:
463 switch (insn.i_format.rt) {
464 case bltzal_op:
465 case bltzall_op:
466 if (NO_R6EMU && (insn.i_format.rs ||
467 insn.i_format.rt == bltzall_op))
468 break;
469
470 regs->regs[31] = regs->cp0_epc +
471 dec_insn.pc_inc +
472 dec_insn.next_pc_inc;
473 /* Fall through */
474 case bltzl_op:
475 if (NO_R6EMU)
476 break;
477 case bltz_op:
478 if ((long)regs->regs[insn.i_format.rs] < 0)
479 *contpc = regs->cp0_epc +
480 dec_insn.pc_inc +
481 (insn.i_format.simmediate << 2);
482 else
483 *contpc = regs->cp0_epc +
484 dec_insn.pc_inc +
485 dec_insn.next_pc_inc;
486 return 1;
487 case bgezal_op:
488 case bgezall_op:
489 if (NO_R6EMU && (insn.i_format.rs ||
490 insn.i_format.rt == bgezall_op))
491 break;
492
493 regs->regs[31] = regs->cp0_epc +
494 dec_insn.pc_inc +
495 dec_insn.next_pc_inc;
496 /* Fall through */
497 case bgezl_op:
498 if (NO_R6EMU)
499 break;
500 case bgez_op:
501 if ((long)regs->regs[insn.i_format.rs] >= 0)
502 *contpc = regs->cp0_epc +
503 dec_insn.pc_inc +
504 (insn.i_format.simmediate << 2);
505 else
506 *contpc = regs->cp0_epc +
507 dec_insn.pc_inc +
508 dec_insn.next_pc_inc;
509 return 1;
510 }
511 break;
512 case jalx_op:
513 set_isa16_mode(bit);
514 case jal_op:
515 regs->regs[31] = regs->cp0_epc +
516 dec_insn.pc_inc +
517 dec_insn.next_pc_inc;
518 /* Fall through */
519 case j_op:
520 *contpc = regs->cp0_epc + dec_insn.pc_inc;
521 *contpc >>= 28;
522 *contpc <<= 28;
523 *contpc |= (insn.j_format.target << 2);
524 /* Set microMIPS mode bit: XOR for jalx. */
525 *contpc ^= bit;
526 return 1;
527 case beql_op:
528 if (NO_R6EMU)
529 break;
530 case beq_op:
531 if (regs->regs[insn.i_format.rs] ==
532 regs->regs[insn.i_format.rt])
533 *contpc = regs->cp0_epc +
534 dec_insn.pc_inc +
535 (insn.i_format.simmediate << 2);
536 else
537 *contpc = regs->cp0_epc +
538 dec_insn.pc_inc +
539 dec_insn.next_pc_inc;
540 return 1;
541 case bnel_op:
542 if (NO_R6EMU)
543 break;
544 case bne_op:
545 if (regs->regs[insn.i_format.rs] !=
546 regs->regs[insn.i_format.rt])
547 *contpc = regs->cp0_epc +
548 dec_insn.pc_inc +
549 (insn.i_format.simmediate << 2);
550 else
551 *contpc = regs->cp0_epc +
552 dec_insn.pc_inc +
553 dec_insn.next_pc_inc;
554 return 1;
555 case blezl_op:
556 if (!insn.i_format.rt && NO_R6EMU)
557 break;
558 case blez_op:
559
560 /*
561 * Compact branches for R6 for the
562 * blez and blezl opcodes.
563 * BLEZ | rs = 0 | rt != 0 == BLEZALC
564 * BLEZ | rs = rt != 0 == BGEZALC
565 * BLEZ | rs != 0 | rt != 0 == BGEUC
566 * BLEZL | rs = 0 | rt != 0 == BLEZC
567 * BLEZL | rs = rt != 0 == BGEZC
568 * BLEZL | rs != 0 | rt != 0 == BGEC
569 *
570 * For real BLEZ{,L}, rt is always 0.
571 */
572 if (cpu_has_mips_r6 && insn.i_format.rt) {
573 if ((insn.i_format.opcode == blez_op) &&
574 ((!insn.i_format.rs && insn.i_format.rt) ||
575 (insn.i_format.rs == insn.i_format.rt)))
576 regs->regs[31] = regs->cp0_epc +
577 dec_insn.pc_inc;
578 *contpc = regs->cp0_epc + dec_insn.pc_inc +
579 dec_insn.next_pc_inc;
580
581 return 1;
582 }
583 if ((long)regs->regs[insn.i_format.rs] <= 0)
584 *contpc = regs->cp0_epc +
585 dec_insn.pc_inc +
586 (insn.i_format.simmediate << 2);
587 else
588 *contpc = regs->cp0_epc +
589 dec_insn.pc_inc +
590 dec_insn.next_pc_inc;
591 return 1;
592 case bgtzl_op:
593 if (!insn.i_format.rt && NO_R6EMU)
594 break;
595 case bgtz_op:
596 /*
597 * Compact branches for R6 for the
598 * bgtz and bgtzl opcodes.
599 * BGTZ | rs = 0 | rt != 0 == BGTZALC
600 * BGTZ | rs = rt != 0 == BLTZALC
601 * BGTZ | rs != 0 | rt != 0 == BLTUC
602 * BGTZL | rs = 0 | rt != 0 == BGTZC
603 * BGTZL | rs = rt != 0 == BLTZC
604 * BGTZL | rs != 0 | rt != 0 == BLTC
605 *
606 * *ZALC varint for BGTZ &&& rt != 0
607 * For real GTZ{,L}, rt is always 0.
608 */
609 if (cpu_has_mips_r6 && insn.i_format.rt) {
610 if ((insn.i_format.opcode == blez_op) &&
611 ((!insn.i_format.rs && insn.i_format.rt) ||
612 (insn.i_format.rs == insn.i_format.rt)))
613 regs->regs[31] = regs->cp0_epc +
614 dec_insn.pc_inc;
615 *contpc = regs->cp0_epc + dec_insn.pc_inc +
616 dec_insn.next_pc_inc;
617
618 return 1;
619 }
620
621 if ((long)regs->regs[insn.i_format.rs] > 0)
622 *contpc = regs->cp0_epc +
623 dec_insn.pc_inc +
624 (insn.i_format.simmediate << 2);
625 else
626 *contpc = regs->cp0_epc +
627 dec_insn.pc_inc +
628 dec_insn.next_pc_inc;
629 return 1;
630 case cbcond0_op:
631 case cbcond1_op:
632 if (!cpu_has_mips_r6)
633 break;
634 if (insn.i_format.rt && !insn.i_format.rs)
635 regs->regs[31] = regs->cp0_epc + 4;
636 *contpc = regs->cp0_epc + dec_insn.pc_inc +
637 dec_insn.next_pc_inc;
638
639 return 1;
640 #ifdef CONFIG_CPU_CAVIUM_OCTEON
641 case lwc2_op: /* This is bbit0 on Octeon */
642 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
643 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
644 else
645 *contpc = regs->cp0_epc + 8;
646 return 1;
647 case ldc2_op: /* This is bbit032 on Octeon */
648 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
649 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
650 else
651 *contpc = regs->cp0_epc + 8;
652 return 1;
653 case swc2_op: /* This is bbit1 on Octeon */
654 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
655 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
656 else
657 *contpc = regs->cp0_epc + 8;
658 return 1;
659 case sdc2_op: /* This is bbit132 on Octeon */
660 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
661 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
662 else
663 *contpc = regs->cp0_epc + 8;
664 return 1;
665 #else
666 case bc6_op:
667 /*
668 * Only valid for MIPS R6 but we can still end up
669 * here from a broken userland so just tell emulator
670 * this is not a branch and let it break later on.
671 */
672 if (!cpu_has_mips_r6)
673 break;
674 *contpc = regs->cp0_epc + dec_insn.pc_inc +
675 dec_insn.next_pc_inc;
676
677 return 1;
678 case balc6_op:
679 if (!cpu_has_mips_r6)
680 break;
681 regs->regs[31] = regs->cp0_epc + 4;
682 *contpc = regs->cp0_epc + dec_insn.pc_inc +
683 dec_insn.next_pc_inc;
684
685 return 1;
686 case beqzcjic_op:
687 if (!cpu_has_mips_r6)
688 break;
689 *contpc = regs->cp0_epc + dec_insn.pc_inc +
690 dec_insn.next_pc_inc;
691
692 return 1;
693 case bnezcjialc_op:
694 if (!cpu_has_mips_r6)
695 break;
696 if (!insn.i_format.rs)
697 regs->regs[31] = regs->cp0_epc + 4;
698 *contpc = regs->cp0_epc + dec_insn.pc_inc +
699 dec_insn.next_pc_inc;
700
701 return 1;
702 #endif
703 case cop0_op:
704 case cop1_op:
705 /* Need to check for R6 bc1nez and bc1eqz branches */
706 if (cpu_has_mips_r6 &&
707 ((insn.i_format.rs == bc1eqz_op) ||
708 (insn.i_format.rs == bc1nez_op))) {
709 bit = 0;
710 switch (insn.i_format.rs) {
711 case bc1eqz_op:
712 if (get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
713 bit = 1;
714 break;
715 case bc1nez_op:
716 if (!(get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
717 bit = 1;
718 break;
719 }
720 if (bit)
721 *contpc = regs->cp0_epc +
722 dec_insn.pc_inc +
723 (insn.i_format.simmediate << 2);
724 else
725 *contpc = regs->cp0_epc +
726 dec_insn.pc_inc +
727 dec_insn.next_pc_inc;
728
729 return 1;
730 }
731 /* R2/R6 compatible cop1 instruction. Fall through */
732 case cop2_op:
733 case cop1x_op:
734 if (insn.i_format.rs == bc_op) {
735 preempt_disable();
736 if (is_fpu_owner())
737 fcr31 = read_32bit_cp1_register(CP1_STATUS);
738 else
739 fcr31 = current->thread.fpu.fcr31;
740 preempt_enable();
741
742 bit = (insn.i_format.rt >> 2);
743 bit += (bit != 0);
744 bit += 23;
745 switch (insn.i_format.rt & 3) {
746 case 0: /* bc1f */
747 case 2: /* bc1fl */
748 if (~fcr31 & (1 << bit))
749 *contpc = regs->cp0_epc +
750 dec_insn.pc_inc +
751 (insn.i_format.simmediate << 2);
752 else
753 *contpc = regs->cp0_epc +
754 dec_insn.pc_inc +
755 dec_insn.next_pc_inc;
756 return 1;
757 case 1: /* bc1t */
758 case 3: /* bc1tl */
759 if (fcr31 & (1 << bit))
760 *contpc = regs->cp0_epc +
761 dec_insn.pc_inc +
762 (insn.i_format.simmediate << 2);
763 else
764 *contpc = regs->cp0_epc +
765 dec_insn.pc_inc +
766 dec_insn.next_pc_inc;
767 return 1;
768 }
769 }
770 break;
771 }
772 return 0;
773 }
774
775 /*
776 * In the Linux kernel, we support selection of FPR format on the
777 * basis of the Status.FR bit. If an FPU is not present, the FR bit
778 * is hardwired to zero, which would imply a 32-bit FPU even for
779 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
780 * FPU emu is slow and bulky and optimizing this function offers fairly
781 * sizeable benefits so we try to be clever and make this function return
782 * a constant whenever possible, that is on 64-bit kernels without O32
783 * compatibility enabled and on 32-bit without 64-bit FPU support.
784 */
785 static inline int cop1_64bit(struct pt_regs *xcp)
786 {
787 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
788 return 1;
789 else if (config_enabled(CONFIG_32BIT) &&
790 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
791 return 0;
792
793 return !test_thread_flag(TIF_32BIT_FPREGS);
794 }
795
796 static inline bool hybrid_fprs(void)
797 {
798 return test_thread_flag(TIF_HYBRID_FPREGS);
799 }
800
801 #define SIFROMREG(si, x) \
802 do { \
803 if (cop1_64bit(xcp) && !hybrid_fprs()) \
804 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
805 else \
806 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
807 } while (0)
808
809 #define SITOREG(si, x) \
810 do { \
811 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
812 unsigned i; \
813 set_fpr32(&ctx->fpr[x], 0, si); \
814 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
815 set_fpr32(&ctx->fpr[x], i, 0); \
816 } else { \
817 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
818 } \
819 } while (0)
820
821 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
822
823 #define SITOHREG(si, x) \
824 do { \
825 unsigned i; \
826 set_fpr32(&ctx->fpr[x], 1, si); \
827 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
828 set_fpr32(&ctx->fpr[x], i, 0); \
829 } while (0)
830
831 #define DIFROMREG(di, x) \
832 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
833
834 #define DITOREG(di, x) \
835 do { \
836 unsigned fpr, i; \
837 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
838 set_fpr64(&ctx->fpr[fpr], 0, di); \
839 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
840 set_fpr64(&ctx->fpr[fpr], i, 0); \
841 } while (0)
842
843 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
844 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
845 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
846 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
847
848 /*
849 * Emulate a CFC1 instruction.
850 */
851 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
852 mips_instruction ir)
853 {
854 u32 fcr31 = ctx->fcr31;
855 u32 value = 0;
856
857 switch (MIPSInst_RD(ir)) {
858 case FPCREG_CSR:
859 value = fcr31;
860 pr_debug("%p gpr[%d]<-csr=%08x\n",
861 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
862 break;
863
864 case FPCREG_FENR:
865 if (!cpu_has_mips_r)
866 break;
867 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
868 MIPS_FENR_FS;
869 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
870 pr_debug("%p gpr[%d]<-enr=%08x\n",
871 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
872 break;
873
874 case FPCREG_FEXR:
875 if (!cpu_has_mips_r)
876 break;
877 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
878 pr_debug("%p gpr[%d]<-exr=%08x\n",
879 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
880 break;
881
882 case FPCREG_FCCR:
883 if (!cpu_has_mips_r)
884 break;
885 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
886 MIPS_FCCR_COND0;
887 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
888 (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
889 pr_debug("%p gpr[%d]<-ccr=%08x\n",
890 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
891 break;
892
893 case FPCREG_RID:
894 value = boot_cpu_data.fpu_id;
895 break;
896
897 default:
898 break;
899 }
900
901 if (MIPSInst_RT(ir))
902 xcp->regs[MIPSInst_RT(ir)] = value;
903 }
904
905 /*
906 * Emulate a CTC1 instruction.
907 */
908 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
909 mips_instruction ir)
910 {
911 u32 fcr31 = ctx->fcr31;
912 u32 value;
913 u32 mask;
914
915 if (MIPSInst_RT(ir) == 0)
916 value = 0;
917 else
918 value = xcp->regs[MIPSInst_RT(ir)];
919
920 switch (MIPSInst_RD(ir)) {
921 case FPCREG_CSR:
922 pr_debug("%p gpr[%d]->csr=%08x\n",
923 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
924
925 /* Preserve read-only bits. */
926 mask = boot_cpu_data.fpu_msk31;
927 fcr31 = (value & ~mask) | (fcr31 & mask);
928 break;
929
930 case FPCREG_FENR:
931 if (!cpu_has_mips_r)
932 break;
933 pr_debug("%p gpr[%d]->enr=%08x\n",
934 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
935 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
936 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
937 FPU_CSR_FS;
938 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
939 break;
940
941 case FPCREG_FEXR:
942 if (!cpu_has_mips_r)
943 break;
944 pr_debug("%p gpr[%d]->exr=%08x\n",
945 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
946 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
947 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
948 break;
949
950 case FPCREG_FCCR:
951 if (!cpu_has_mips_r)
952 break;
953 pr_debug("%p gpr[%d]->ccr=%08x\n",
954 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
955 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
956 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
957 FPU_CSR_COND;
958 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
959 FPU_CSR_CONDX;
960 break;
961
962 default:
963 break;
964 }
965
966 ctx->fcr31 = fcr31;
967 }
968
969 /*
970 * Emulate the single floating point instruction pointed at by EPC.
971 * Two instructions if the instruction is in a branch delay slot.
972 */
973
974 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
975 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
976 {
977 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
978 unsigned int cond, cbit;
979 mips_instruction ir;
980 int likely, pc_inc;
981 u32 __user *wva;
982 u64 __user *dva;
983 u32 wval;
984 u64 dval;
985 int sig;
986
987 /*
988 * These are giving gcc a gentle hint about what to expect in
989 * dec_inst in order to do better optimization.
990 */
991 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
992 unreachable();
993
994 /* XXX NEC Vr54xx bug workaround */
995 if (delay_slot(xcp)) {
996 if (dec_insn.micro_mips_mode) {
997 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
998 clear_delay_slot(xcp);
999 } else {
1000 if (!isBranchInstr(xcp, dec_insn, &contpc))
1001 clear_delay_slot(xcp);
1002 }
1003 }
1004
1005 if (delay_slot(xcp)) {
1006 /*
1007 * The instruction to be emulated is in a branch delay slot
1008 * which means that we have to emulate the branch instruction
1009 * BEFORE we do the cop1 instruction.
1010 *
1011 * This branch could be a COP1 branch, but in that case we
1012 * would have had a trap for that instruction, and would not
1013 * come through this route.
1014 *
1015 * Linux MIPS branch emulator operates on context, updating the
1016 * cp0_epc.
1017 */
1018 ir = dec_insn.next_insn; /* process delay slot instr */
1019 pc_inc = dec_insn.next_pc_inc;
1020 } else {
1021 ir = dec_insn.insn; /* process current instr */
1022 pc_inc = dec_insn.pc_inc;
1023 }
1024
1025 /*
1026 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1027 * instructions, we want to convert microMIPS FPU instructions
1028 * into MIPS32 instructions so that we could reuse all of the
1029 * FPU emulation code.
1030 *
1031 * NOTE: We cannot do this for branch instructions since they
1032 * are not a subset. Example: Cannot emulate a 16-bit
1033 * aligned target address with a MIPS32 instruction.
1034 */
1035 if (dec_insn.micro_mips_mode) {
1036 /*
1037 * If next instruction is a 16-bit instruction, then it
1038 * it cannot be a FPU instruction. This could happen
1039 * since we can be called for non-FPU instructions.
1040 */
1041 if ((pc_inc == 2) ||
1042 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1043 == SIGILL))
1044 return SIGILL;
1045 }
1046
1047 emul:
1048 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1049 MIPS_FPU_EMU_INC_STATS(emulated);
1050 switch (MIPSInst_OPCODE(ir)) {
1051 case ldc1_op:
1052 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1053 MIPSInst_SIMM(ir));
1054 MIPS_FPU_EMU_INC_STATS(loads);
1055
1056 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1057 MIPS_FPU_EMU_INC_STATS(errors);
1058 *fault_addr = dva;
1059 return SIGBUS;
1060 }
1061 if (__get_user(dval, dva)) {
1062 MIPS_FPU_EMU_INC_STATS(errors);
1063 *fault_addr = dva;
1064 return SIGSEGV;
1065 }
1066 DITOREG(dval, MIPSInst_RT(ir));
1067 break;
1068
1069 case sdc1_op:
1070 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1071 MIPSInst_SIMM(ir));
1072 MIPS_FPU_EMU_INC_STATS(stores);
1073 DIFROMREG(dval, MIPSInst_RT(ir));
1074 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1075 MIPS_FPU_EMU_INC_STATS(errors);
1076 *fault_addr = dva;
1077 return SIGBUS;
1078 }
1079 if (__put_user(dval, dva)) {
1080 MIPS_FPU_EMU_INC_STATS(errors);
1081 *fault_addr = dva;
1082 return SIGSEGV;
1083 }
1084 break;
1085
1086 case lwc1_op:
1087 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1088 MIPSInst_SIMM(ir));
1089 MIPS_FPU_EMU_INC_STATS(loads);
1090 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1091 MIPS_FPU_EMU_INC_STATS(errors);
1092 *fault_addr = wva;
1093 return SIGBUS;
1094 }
1095 if (__get_user(wval, wva)) {
1096 MIPS_FPU_EMU_INC_STATS(errors);
1097 *fault_addr = wva;
1098 return SIGSEGV;
1099 }
1100 SITOREG(wval, MIPSInst_RT(ir));
1101 break;
1102
1103 case swc1_op:
1104 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1105 MIPSInst_SIMM(ir));
1106 MIPS_FPU_EMU_INC_STATS(stores);
1107 SIFROMREG(wval, MIPSInst_RT(ir));
1108 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1109 MIPS_FPU_EMU_INC_STATS(errors);
1110 *fault_addr = wva;
1111 return SIGBUS;
1112 }
1113 if (__put_user(wval, wva)) {
1114 MIPS_FPU_EMU_INC_STATS(errors);
1115 *fault_addr = wva;
1116 return SIGSEGV;
1117 }
1118 break;
1119
1120 case cop1_op:
1121 switch (MIPSInst_RS(ir)) {
1122 case dmfc_op:
1123 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1124 return SIGILL;
1125
1126 /* copregister fs -> gpr[rt] */
1127 if (MIPSInst_RT(ir) != 0) {
1128 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1129 MIPSInst_RD(ir));
1130 }
1131 break;
1132
1133 case dmtc_op:
1134 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1135 return SIGILL;
1136
1137 /* copregister fs <- rt */
1138 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1139 break;
1140
1141 case mfhc_op:
1142 if (!cpu_has_mips_r2_r6)
1143 goto sigill;
1144
1145 /* copregister rd -> gpr[rt] */
1146 if (MIPSInst_RT(ir) != 0) {
1147 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1148 MIPSInst_RD(ir));
1149 }
1150 break;
1151
1152 case mthc_op:
1153 if (!cpu_has_mips_r2_r6)
1154 goto sigill;
1155
1156 /* copregister rd <- gpr[rt] */
1157 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1158 break;
1159
1160 case mfc_op:
1161 /* copregister rd -> gpr[rt] */
1162 if (MIPSInst_RT(ir) != 0) {
1163 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1164 MIPSInst_RD(ir));
1165 }
1166 break;
1167
1168 case mtc_op:
1169 /* copregister rd <- rt */
1170 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1171 break;
1172
1173 case cfc_op:
1174 /* cop control register rd -> gpr[rt] */
1175 cop1_cfc(xcp, ctx, ir);
1176 break;
1177
1178 case ctc_op:
1179 /* copregister rd <- rt */
1180 cop1_ctc(xcp, ctx, ir);
1181 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1182 return SIGFPE;
1183 }
1184 break;
1185
1186 case bc1eqz_op:
1187 case bc1nez_op:
1188 if (!cpu_has_mips_r6 || delay_slot(xcp))
1189 return SIGILL;
1190
1191 cond = likely = 0;
1192 switch (MIPSInst_RS(ir)) {
1193 case bc1eqz_op:
1194 if (get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)
1195 cond = 1;
1196 break;
1197 case bc1nez_op:
1198 if (!(get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1))
1199 cond = 1;
1200 break;
1201 }
1202 goto branch_common;
1203
1204 case bc_op:
1205 if (delay_slot(xcp))
1206 return SIGILL;
1207
1208 if (cpu_has_mips_4_5_r)
1209 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1210 else
1211 cbit = FPU_CSR_COND;
1212 cond = ctx->fcr31 & cbit;
1213
1214 likely = 0;
1215 switch (MIPSInst_RT(ir) & 3) {
1216 case bcfl_op:
1217 if (cpu_has_mips_2_3_4_5_r)
1218 likely = 1;
1219 /* Fall through */
1220 case bcf_op:
1221 cond = !cond;
1222 break;
1223 case bctl_op:
1224 if (cpu_has_mips_2_3_4_5_r)
1225 likely = 1;
1226 /* Fall through */
1227 case bct_op:
1228 break;
1229 }
1230 branch_common:
1231 set_delay_slot(xcp);
1232 if (cond) {
1233 /*
1234 * Branch taken: emulate dslot instruction
1235 */
1236 unsigned long bcpc;
1237
1238 /*
1239 * Remember EPC at the branch to point back
1240 * at so that any delay-slot instruction
1241 * signal is not silently ignored.
1242 */
1243 bcpc = xcp->cp0_epc;
1244 xcp->cp0_epc += dec_insn.pc_inc;
1245
1246 contpc = MIPSInst_SIMM(ir);
1247 ir = dec_insn.next_insn;
1248 if (dec_insn.micro_mips_mode) {
1249 contpc = (xcp->cp0_epc + (contpc << 1));
1250
1251 /* If 16-bit instruction, not FPU. */
1252 if ((dec_insn.next_pc_inc == 2) ||
1253 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1254
1255 /*
1256 * Since this instruction will
1257 * be put on the stack with
1258 * 32-bit words, get around
1259 * this problem by putting a
1260 * NOP16 as the second one.
1261 */
1262 if (dec_insn.next_pc_inc == 2)
1263 ir = (ir & (~0xffff)) | MM_NOP16;
1264
1265 /*
1266 * Single step the non-CP1
1267 * instruction in the dslot.
1268 */
1269 sig = mips_dsemul(xcp, ir,
1270 contpc);
1271 if (sig < 0)
1272 break;
1273 if (sig)
1274 xcp->cp0_epc = bcpc;
1275 /*
1276 * SIGILL forces out of
1277 * the emulation loop.
1278 */
1279 return sig ? sig : SIGILL;
1280 }
1281 } else
1282 contpc = (xcp->cp0_epc + (contpc << 2));
1283
1284 switch (MIPSInst_OPCODE(ir)) {
1285 case lwc1_op:
1286 case swc1_op:
1287 goto emul;
1288
1289 case ldc1_op:
1290 case sdc1_op:
1291 if (cpu_has_mips_2_3_4_5_r)
1292 goto emul;
1293
1294 goto bc_sigill;
1295
1296 case cop1_op:
1297 goto emul;
1298
1299 case cop1x_op:
1300 if (cpu_has_mips_4_5_64_r2_r6)
1301 /* its one of ours */
1302 goto emul;
1303
1304 goto bc_sigill;
1305
1306 case spec_op:
1307 switch (MIPSInst_FUNC(ir)) {
1308 case movc_op:
1309 if (cpu_has_mips_4_5_r)
1310 goto emul;
1311
1312 goto bc_sigill;
1313 }
1314 break;
1315
1316 bc_sigill:
1317 xcp->cp0_epc = bcpc;
1318 return SIGILL;
1319 }
1320
1321 /*
1322 * Single step the non-cp1
1323 * instruction in the dslot
1324 */
1325 sig = mips_dsemul(xcp, ir, contpc);
1326 if (sig < 0)
1327 break;
1328 if (sig)
1329 xcp->cp0_epc = bcpc;
1330 /* SIGILL forces out of the emulation loop. */
1331 return sig ? sig : SIGILL;
1332 } else if (likely) { /* branch not taken */
1333 /*
1334 * branch likely nullifies
1335 * dslot if not taken
1336 */
1337 xcp->cp0_epc += dec_insn.pc_inc;
1338 contpc += dec_insn.pc_inc;
1339 /*
1340 * else continue & execute
1341 * dslot as normal insn
1342 */
1343 }
1344 break;
1345
1346 default:
1347 if (!(MIPSInst_RS(ir) & 0x10))
1348 return SIGILL;
1349
1350 /* a real fpu computation instruction */
1351 if ((sig = fpu_emu(xcp, ctx, ir)))
1352 return sig;
1353 }
1354 break;
1355
1356 case cop1x_op:
1357 if (!cpu_has_mips_4_5_64_r2_r6)
1358 return SIGILL;
1359
1360 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1361 if (sig)
1362 return sig;
1363 break;
1364
1365 case spec_op:
1366 if (!cpu_has_mips_4_5_r)
1367 return SIGILL;
1368
1369 if (MIPSInst_FUNC(ir) != movc_op)
1370 return SIGILL;
1371 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1372 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1373 xcp->regs[MIPSInst_RD(ir)] =
1374 xcp->regs[MIPSInst_RS(ir)];
1375 break;
1376 default:
1377 sigill:
1378 return SIGILL;
1379 }
1380
1381 /* we did it !! */
1382 xcp->cp0_epc = contpc;
1383 clear_delay_slot(xcp);
1384
1385 return 0;
1386 }
1387
1388 /*
1389 * Conversion table from MIPS compare ops 48-63
1390 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1391 */
1392 static const unsigned char cmptab[8] = {
1393 0, /* cmp_0 (sig) cmp_sf */
1394 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1395 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1396 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1397 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1398 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1399 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1400 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1401 };
1402
1403 static const unsigned char negative_cmptab[8] = {
1404 0, /* Reserved */
1405 IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1406 IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1407 IEEE754_CLT | IEEE754_CGT,
1408 /* Reserved */
1409 };
1410
1411
1412 /*
1413 * Additional MIPS4 instructions
1414 */
1415
1416 #define DEF3OP(name, p, f1, f2, f3) \
1417 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1418 union ieee754##p s, union ieee754##p t) \
1419 { \
1420 struct _ieee754_csr ieee754_csr_save; \
1421 s = f1(s, t); \
1422 ieee754_csr_save = ieee754_csr; \
1423 s = f2(s, r); \
1424 ieee754_csr_save.cx |= ieee754_csr.cx; \
1425 ieee754_csr_save.sx |= ieee754_csr.sx; \
1426 s = f3(s); \
1427 ieee754_csr.cx |= ieee754_csr_save.cx; \
1428 ieee754_csr.sx |= ieee754_csr_save.sx; \
1429 return s; \
1430 }
1431
1432 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1433 {
1434 return ieee754dp_div(ieee754dp_one(0), d);
1435 }
1436
1437 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1438 {
1439 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1440 }
1441
1442 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1443 {
1444 return ieee754sp_div(ieee754sp_one(0), s);
1445 }
1446
1447 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1448 {
1449 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1450 }
1451
1452 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1453 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1454 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1455 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1456 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1457 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1458 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1459 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1460
1461 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1462 mips_instruction ir, void *__user *fault_addr)
1463 {
1464 unsigned rcsr = 0; /* resulting csr */
1465
1466 MIPS_FPU_EMU_INC_STATS(cp1xops);
1467
1468 switch (MIPSInst_FMA_FFMT(ir)) {
1469 case s_fmt:{ /* 0 */
1470
1471 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1472 union ieee754sp fd, fr, fs, ft;
1473 u32 __user *va;
1474 u32 val;
1475
1476 switch (MIPSInst_FUNC(ir)) {
1477 case lwxc1_op:
1478 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1479 xcp->regs[MIPSInst_FT(ir)]);
1480
1481 MIPS_FPU_EMU_INC_STATS(loads);
1482 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1483 MIPS_FPU_EMU_INC_STATS(errors);
1484 *fault_addr = va;
1485 return SIGBUS;
1486 }
1487 if (__get_user(val, va)) {
1488 MIPS_FPU_EMU_INC_STATS(errors);
1489 *fault_addr = va;
1490 return SIGSEGV;
1491 }
1492 SITOREG(val, MIPSInst_FD(ir));
1493 break;
1494
1495 case swxc1_op:
1496 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1497 xcp->regs[MIPSInst_FT(ir)]);
1498
1499 MIPS_FPU_EMU_INC_STATS(stores);
1500
1501 SIFROMREG(val, MIPSInst_FS(ir));
1502 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1503 MIPS_FPU_EMU_INC_STATS(errors);
1504 *fault_addr = va;
1505 return SIGBUS;
1506 }
1507 if (put_user(val, va)) {
1508 MIPS_FPU_EMU_INC_STATS(errors);
1509 *fault_addr = va;
1510 return SIGSEGV;
1511 }
1512 break;
1513
1514 case madd_s_op:
1515 handler = fpemu_sp_madd;
1516 goto scoptop;
1517 case msub_s_op:
1518 handler = fpemu_sp_msub;
1519 goto scoptop;
1520 case nmadd_s_op:
1521 handler = fpemu_sp_nmadd;
1522 goto scoptop;
1523 case nmsub_s_op:
1524 handler = fpemu_sp_nmsub;
1525 goto scoptop;
1526
1527 scoptop:
1528 SPFROMREG(fr, MIPSInst_FR(ir));
1529 SPFROMREG(fs, MIPSInst_FS(ir));
1530 SPFROMREG(ft, MIPSInst_FT(ir));
1531 fd = (*handler) (fr, fs, ft);
1532 SPTOREG(fd, MIPSInst_FD(ir));
1533
1534 copcsr:
1535 if (ieee754_cxtest(IEEE754_INEXACT)) {
1536 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1537 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1538 }
1539 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1540 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1541 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1542 }
1543 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1544 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1545 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1546 }
1547 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1548 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1549 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1550 }
1551
1552 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1553 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1554 /*printk ("SIGFPE: FPU csr = %08x\n",
1555 ctx->fcr31); */
1556 return SIGFPE;
1557 }
1558
1559 break;
1560
1561 default:
1562 return SIGILL;
1563 }
1564 break;
1565 }
1566
1567 case d_fmt:{ /* 1 */
1568 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1569 union ieee754dp fd, fr, fs, ft;
1570 u64 __user *va;
1571 u64 val;
1572
1573 switch (MIPSInst_FUNC(ir)) {
1574 case ldxc1_op:
1575 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1576 xcp->regs[MIPSInst_FT(ir)]);
1577
1578 MIPS_FPU_EMU_INC_STATS(loads);
1579 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1580 MIPS_FPU_EMU_INC_STATS(errors);
1581 *fault_addr = va;
1582 return SIGBUS;
1583 }
1584 if (__get_user(val, va)) {
1585 MIPS_FPU_EMU_INC_STATS(errors);
1586 *fault_addr = va;
1587 return SIGSEGV;
1588 }
1589 DITOREG(val, MIPSInst_FD(ir));
1590 break;
1591
1592 case sdxc1_op:
1593 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1594 xcp->regs[MIPSInst_FT(ir)]);
1595
1596 MIPS_FPU_EMU_INC_STATS(stores);
1597 DIFROMREG(val, MIPSInst_FS(ir));
1598 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1599 MIPS_FPU_EMU_INC_STATS(errors);
1600 *fault_addr = va;
1601 return SIGBUS;
1602 }
1603 if (__put_user(val, va)) {
1604 MIPS_FPU_EMU_INC_STATS(errors);
1605 *fault_addr = va;
1606 return SIGSEGV;
1607 }
1608 break;
1609
1610 case madd_d_op:
1611 handler = fpemu_dp_madd;
1612 goto dcoptop;
1613 case msub_d_op:
1614 handler = fpemu_dp_msub;
1615 goto dcoptop;
1616 case nmadd_d_op:
1617 handler = fpemu_dp_nmadd;
1618 goto dcoptop;
1619 case nmsub_d_op:
1620 handler = fpemu_dp_nmsub;
1621 goto dcoptop;
1622
1623 dcoptop:
1624 DPFROMREG(fr, MIPSInst_FR(ir));
1625 DPFROMREG(fs, MIPSInst_FS(ir));
1626 DPFROMREG(ft, MIPSInst_FT(ir));
1627 fd = (*handler) (fr, fs, ft);
1628 DPTOREG(fd, MIPSInst_FD(ir));
1629 goto copcsr;
1630
1631 default:
1632 return SIGILL;
1633 }
1634 break;
1635 }
1636
1637 case 0x3:
1638 if (MIPSInst_FUNC(ir) != pfetch_op)
1639 return SIGILL;
1640
1641 /* ignore prefx operation */
1642 break;
1643
1644 default:
1645 return SIGILL;
1646 }
1647
1648 return 0;
1649 }
1650
1651
1652
1653 /*
1654 * Emulate a single COP1 arithmetic instruction.
1655 */
1656 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1657 mips_instruction ir)
1658 {
1659 int rfmt; /* resulting format */
1660 unsigned rcsr = 0; /* resulting csr */
1661 unsigned int oldrm;
1662 unsigned int cbit;
1663 unsigned cond;
1664 union {
1665 union ieee754dp d;
1666 union ieee754sp s;
1667 int w;
1668 s64 l;
1669 } rv; /* resulting value */
1670 u64 bits;
1671
1672 MIPS_FPU_EMU_INC_STATS(cp1ops);
1673 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1674 case s_fmt: { /* 0 */
1675 union {
1676 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1677 union ieee754sp(*u) (union ieee754sp);
1678 } handler;
1679 union ieee754sp fs, ft;
1680
1681 switch (MIPSInst_FUNC(ir)) {
1682 /* binary ops */
1683 case fadd_op:
1684 handler.b = ieee754sp_add;
1685 goto scopbop;
1686 case fsub_op:
1687 handler.b = ieee754sp_sub;
1688 goto scopbop;
1689 case fmul_op:
1690 handler.b = ieee754sp_mul;
1691 goto scopbop;
1692 case fdiv_op:
1693 handler.b = ieee754sp_div;
1694 goto scopbop;
1695
1696 /* unary ops */
1697 case fsqrt_op:
1698 if (!cpu_has_mips_2_3_4_5_r)
1699 return SIGILL;
1700
1701 handler.u = ieee754sp_sqrt;
1702 goto scopuop;
1703
1704 /*
1705 * Note that on some MIPS IV implementations such as the
1706 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1707 * achieve full IEEE-754 accuracy - however this emulator does.
1708 */
1709 case frsqrt_op:
1710 if (!cpu_has_mips_4_5_64_r2_r6)
1711 return SIGILL;
1712
1713 handler.u = fpemu_sp_rsqrt;
1714 goto scopuop;
1715
1716 case frecip_op:
1717 if (!cpu_has_mips_4_5_64_r2_r6)
1718 return SIGILL;
1719
1720 handler.u = fpemu_sp_recip;
1721 goto scopuop;
1722
1723 case fmovc_op:
1724 if (!cpu_has_mips_4_5_r)
1725 return SIGILL;
1726
1727 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1728 if (((ctx->fcr31 & cond) != 0) !=
1729 ((MIPSInst_FT(ir) & 1) != 0))
1730 return 0;
1731 SPFROMREG(rv.s, MIPSInst_FS(ir));
1732 break;
1733
1734 case fmovz_op:
1735 if (!cpu_has_mips_4_5_r)
1736 return SIGILL;
1737
1738 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1739 return 0;
1740 SPFROMREG(rv.s, MIPSInst_FS(ir));
1741 break;
1742
1743 case fmovn_op:
1744 if (!cpu_has_mips_4_5_r)
1745 return SIGILL;
1746
1747 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1748 return 0;
1749 SPFROMREG(rv.s, MIPSInst_FS(ir));
1750 break;
1751
1752 case fseleqz_op:
1753 if (!cpu_has_mips_r6)
1754 return SIGILL;
1755
1756 SPFROMREG(rv.s, MIPSInst_FT(ir));
1757 if (rv.w & 0x1)
1758 rv.w = 0;
1759 else
1760 SPFROMREG(rv.s, MIPSInst_FS(ir));
1761 break;
1762
1763 case fselnez_op:
1764 if (!cpu_has_mips_r6)
1765 return SIGILL;
1766
1767 SPFROMREG(rv.s, MIPSInst_FT(ir));
1768 if (rv.w & 0x1)
1769 SPFROMREG(rv.s, MIPSInst_FS(ir));
1770 else
1771 rv.w = 0;
1772 break;
1773
1774 case fmaddf_op: {
1775 union ieee754sp ft, fs, fd;
1776
1777 if (!cpu_has_mips_r6)
1778 return SIGILL;
1779
1780 SPFROMREG(ft, MIPSInst_FT(ir));
1781 SPFROMREG(fs, MIPSInst_FS(ir));
1782 SPFROMREG(fd, MIPSInst_FD(ir));
1783 rv.s = ieee754sp_maddf(fd, fs, ft);
1784 break;
1785 }
1786
1787 case fmsubf_op: {
1788 union ieee754sp ft, fs, fd;
1789
1790 if (!cpu_has_mips_r6)
1791 return SIGILL;
1792
1793 SPFROMREG(ft, MIPSInst_FT(ir));
1794 SPFROMREG(fs, MIPSInst_FS(ir));
1795 SPFROMREG(fd, MIPSInst_FD(ir));
1796 rv.s = ieee754sp_msubf(fd, fs, ft);
1797 break;
1798 }
1799
1800 case frint_op: {
1801 union ieee754sp fs;
1802
1803 if (!cpu_has_mips_r6)
1804 return SIGILL;
1805
1806 SPFROMREG(fs, MIPSInst_FS(ir));
1807 rv.l = ieee754sp_tlong(fs);
1808 rv.s = ieee754sp_flong(rv.l);
1809 goto copcsr;
1810 }
1811
1812 case fclass_op: {
1813 union ieee754sp fs;
1814
1815 if (!cpu_has_mips_r6)
1816 return SIGILL;
1817
1818 SPFROMREG(fs, MIPSInst_FS(ir));
1819 rv.w = ieee754sp_2008class(fs);
1820 rfmt = w_fmt;
1821 break;
1822 }
1823
1824 case fmin_op: {
1825 union ieee754sp fs, ft;
1826
1827 if (!cpu_has_mips_r6)
1828 return SIGILL;
1829
1830 SPFROMREG(ft, MIPSInst_FT(ir));
1831 SPFROMREG(fs, MIPSInst_FS(ir));
1832 rv.s = ieee754sp_fmin(fs, ft);
1833 break;
1834 }
1835
1836 case fmina_op: {
1837 union ieee754sp fs, ft;
1838
1839 if (!cpu_has_mips_r6)
1840 return SIGILL;
1841
1842 SPFROMREG(ft, MIPSInst_FT(ir));
1843 SPFROMREG(fs, MIPSInst_FS(ir));
1844 rv.s = ieee754sp_fmina(fs, ft);
1845 break;
1846 }
1847
1848 case fmax_op: {
1849 union ieee754sp fs, ft;
1850
1851 if (!cpu_has_mips_r6)
1852 return SIGILL;
1853
1854 SPFROMREG(ft, MIPSInst_FT(ir));
1855 SPFROMREG(fs, MIPSInst_FS(ir));
1856 rv.s = ieee754sp_fmax(fs, ft);
1857 break;
1858 }
1859
1860 case fmaxa_op: {
1861 union ieee754sp fs, ft;
1862
1863 if (!cpu_has_mips_r6)
1864 return SIGILL;
1865
1866 SPFROMREG(ft, MIPSInst_FT(ir));
1867 SPFROMREG(fs, MIPSInst_FS(ir));
1868 rv.s = ieee754sp_fmaxa(fs, ft);
1869 break;
1870 }
1871
1872 case fabs_op:
1873 handler.u = ieee754sp_abs;
1874 goto scopuop;
1875
1876 case fneg_op:
1877 handler.u = ieee754sp_neg;
1878 goto scopuop;
1879
1880 case fmov_op:
1881 /* an easy one */
1882 SPFROMREG(rv.s, MIPSInst_FS(ir));
1883 goto copcsr;
1884
1885 /* binary op on handler */
1886 scopbop:
1887 SPFROMREG(fs, MIPSInst_FS(ir));
1888 SPFROMREG(ft, MIPSInst_FT(ir));
1889
1890 rv.s = (*handler.b) (fs, ft);
1891 goto copcsr;
1892 scopuop:
1893 SPFROMREG(fs, MIPSInst_FS(ir));
1894 rv.s = (*handler.u) (fs);
1895 goto copcsr;
1896 copcsr:
1897 if (ieee754_cxtest(IEEE754_INEXACT)) {
1898 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1899 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1900 }
1901 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1902 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1903 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1904 }
1905 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1906 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1907 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1908 }
1909 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1910 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1911 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1912 }
1913 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1914 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1915 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1916 }
1917 break;
1918
1919 /* unary conv ops */
1920 case fcvts_op:
1921 return SIGILL; /* not defined */
1922
1923 case fcvtd_op:
1924 SPFROMREG(fs, MIPSInst_FS(ir));
1925 rv.d = ieee754dp_fsp(fs);
1926 rfmt = d_fmt;
1927 goto copcsr;
1928
1929 case fcvtw_op:
1930 SPFROMREG(fs, MIPSInst_FS(ir));
1931 rv.w = ieee754sp_tint(fs);
1932 rfmt = w_fmt;
1933 goto copcsr;
1934
1935 case fround_op:
1936 case ftrunc_op:
1937 case fceil_op:
1938 case ffloor_op:
1939 if (!cpu_has_mips_2_3_4_5_r)
1940 return SIGILL;
1941
1942 oldrm = ieee754_csr.rm;
1943 SPFROMREG(fs, MIPSInst_FS(ir));
1944 ieee754_csr.rm = MIPSInst_FUNC(ir);
1945 rv.w = ieee754sp_tint(fs);
1946 ieee754_csr.rm = oldrm;
1947 rfmt = w_fmt;
1948 goto copcsr;
1949
1950 case fcvtl_op:
1951 if (!cpu_has_mips_3_4_5_64_r2_r6)
1952 return SIGILL;
1953
1954 SPFROMREG(fs, MIPSInst_FS(ir));
1955 rv.l = ieee754sp_tlong(fs);
1956 rfmt = l_fmt;
1957 goto copcsr;
1958
1959 case froundl_op:
1960 case ftruncl_op:
1961 case fceill_op:
1962 case ffloorl_op:
1963 if (!cpu_has_mips_3_4_5_64_r2_r6)
1964 return SIGILL;
1965
1966 oldrm = ieee754_csr.rm;
1967 SPFROMREG(fs, MIPSInst_FS(ir));
1968 ieee754_csr.rm = MIPSInst_FUNC(ir);
1969 rv.l = ieee754sp_tlong(fs);
1970 ieee754_csr.rm = oldrm;
1971 rfmt = l_fmt;
1972 goto copcsr;
1973
1974 default:
1975 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1976 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1977 union ieee754sp fs, ft;
1978
1979 SPFROMREG(fs, MIPSInst_FS(ir));
1980 SPFROMREG(ft, MIPSInst_FT(ir));
1981 rv.w = ieee754sp_cmp(fs, ft,
1982 cmptab[cmpop & 0x7], cmpop & 0x8);
1983 rfmt = -1;
1984 if ((cmpop & 0x8) && ieee754_cxtest
1985 (IEEE754_INVALID_OPERATION))
1986 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1987 else
1988 goto copcsr;
1989
1990 } else
1991 return SIGILL;
1992 break;
1993 }
1994 break;
1995 }
1996
1997 case d_fmt: {
1998 union ieee754dp fs, ft;
1999 union {
2000 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
2001 union ieee754dp(*u) (union ieee754dp);
2002 } handler;
2003
2004 switch (MIPSInst_FUNC(ir)) {
2005 /* binary ops */
2006 case fadd_op:
2007 handler.b = ieee754dp_add;
2008 goto dcopbop;
2009 case fsub_op:
2010 handler.b = ieee754dp_sub;
2011 goto dcopbop;
2012 case fmul_op:
2013 handler.b = ieee754dp_mul;
2014 goto dcopbop;
2015 case fdiv_op:
2016 handler.b = ieee754dp_div;
2017 goto dcopbop;
2018
2019 /* unary ops */
2020 case fsqrt_op:
2021 if (!cpu_has_mips_2_3_4_5_r)
2022 return SIGILL;
2023
2024 handler.u = ieee754dp_sqrt;
2025 goto dcopuop;
2026 /*
2027 * Note that on some MIPS IV implementations such as the
2028 * R5000 and R8000 the FSQRT and FRECIP instructions do not
2029 * achieve full IEEE-754 accuracy - however this emulator does.
2030 */
2031 case frsqrt_op:
2032 if (!cpu_has_mips_4_5_64_r2_r6)
2033 return SIGILL;
2034
2035 handler.u = fpemu_dp_rsqrt;
2036 goto dcopuop;
2037 case frecip_op:
2038 if (!cpu_has_mips_4_5_64_r2_r6)
2039 return SIGILL;
2040
2041 handler.u = fpemu_dp_recip;
2042 goto dcopuop;
2043 case fmovc_op:
2044 if (!cpu_has_mips_4_5_r)
2045 return SIGILL;
2046
2047 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
2048 if (((ctx->fcr31 & cond) != 0) !=
2049 ((MIPSInst_FT(ir) & 1) != 0))
2050 return 0;
2051 DPFROMREG(rv.d, MIPSInst_FS(ir));
2052 break;
2053 case fmovz_op:
2054 if (!cpu_has_mips_4_5_r)
2055 return SIGILL;
2056
2057 if (xcp->regs[MIPSInst_FT(ir)] != 0)
2058 return 0;
2059 DPFROMREG(rv.d, MIPSInst_FS(ir));
2060 break;
2061 case fmovn_op:
2062 if (!cpu_has_mips_4_5_r)
2063 return SIGILL;
2064
2065 if (xcp->regs[MIPSInst_FT(ir)] == 0)
2066 return 0;
2067 DPFROMREG(rv.d, MIPSInst_FS(ir));
2068 break;
2069
2070 case fseleqz_op:
2071 if (!cpu_has_mips_r6)
2072 return SIGILL;
2073
2074 DPFROMREG(rv.d, MIPSInst_FT(ir));
2075 if (rv.l & 0x1)
2076 rv.l = 0;
2077 else
2078 DPFROMREG(rv.d, MIPSInst_FS(ir));
2079 break;
2080
2081 case fselnez_op:
2082 if (!cpu_has_mips_r6)
2083 return SIGILL;
2084
2085 DPFROMREG(rv.d, MIPSInst_FT(ir));
2086 if (rv.l & 0x1)
2087 DPFROMREG(rv.d, MIPSInst_FS(ir));
2088 else
2089 rv.l = 0;
2090 break;
2091
2092 case fmaddf_op: {
2093 union ieee754dp ft, fs, fd;
2094
2095 if (!cpu_has_mips_r6)
2096 return SIGILL;
2097
2098 DPFROMREG(ft, MIPSInst_FT(ir));
2099 DPFROMREG(fs, MIPSInst_FS(ir));
2100 DPFROMREG(fd, MIPSInst_FD(ir));
2101 rv.d = ieee754dp_maddf(fd, fs, ft);
2102 break;
2103 }
2104
2105 case fmsubf_op: {
2106 union ieee754dp ft, fs, fd;
2107
2108 if (!cpu_has_mips_r6)
2109 return SIGILL;
2110
2111 DPFROMREG(ft, MIPSInst_FT(ir));
2112 DPFROMREG(fs, MIPSInst_FS(ir));
2113 DPFROMREG(fd, MIPSInst_FD(ir));
2114 rv.d = ieee754dp_msubf(fd, fs, ft);
2115 break;
2116 }
2117
2118 case frint_op: {
2119 union ieee754dp fs;
2120
2121 if (!cpu_has_mips_r6)
2122 return SIGILL;
2123
2124 DPFROMREG(fs, MIPSInst_FS(ir));
2125 rv.l = ieee754dp_tlong(fs);
2126 rv.d = ieee754dp_flong(rv.l);
2127 goto copcsr;
2128 }
2129
2130 case fclass_op: {
2131 union ieee754dp fs;
2132
2133 if (!cpu_has_mips_r6)
2134 return SIGILL;
2135
2136 DPFROMREG(fs, MIPSInst_FS(ir));
2137 rv.w = ieee754dp_2008class(fs);
2138 rfmt = w_fmt;
2139 break;
2140 }
2141
2142 case fmin_op: {
2143 union ieee754dp fs, ft;
2144
2145 if (!cpu_has_mips_r6)
2146 return SIGILL;
2147
2148 DPFROMREG(ft, MIPSInst_FT(ir));
2149 DPFROMREG(fs, MIPSInst_FS(ir));
2150 rv.d = ieee754dp_fmin(fs, ft);
2151 break;
2152 }
2153
2154 case fmina_op: {
2155 union ieee754dp fs, ft;
2156
2157 if (!cpu_has_mips_r6)
2158 return SIGILL;
2159
2160 DPFROMREG(ft, MIPSInst_FT(ir));
2161 DPFROMREG(fs, MIPSInst_FS(ir));
2162 rv.d = ieee754dp_fmina(fs, ft);
2163 break;
2164 }
2165
2166 case fmax_op: {
2167 union ieee754dp fs, ft;
2168
2169 if (!cpu_has_mips_r6)
2170 return SIGILL;
2171
2172 DPFROMREG(ft, MIPSInst_FT(ir));
2173 DPFROMREG(fs, MIPSInst_FS(ir));
2174 rv.d = ieee754dp_fmax(fs, ft);
2175 break;
2176 }
2177
2178 case fmaxa_op: {
2179 union ieee754dp fs, ft;
2180
2181 if (!cpu_has_mips_r6)
2182 return SIGILL;
2183
2184 DPFROMREG(ft, MIPSInst_FT(ir));
2185 DPFROMREG(fs, MIPSInst_FS(ir));
2186 rv.d = ieee754dp_fmaxa(fs, ft);
2187 break;
2188 }
2189
2190 case fabs_op:
2191 handler.u = ieee754dp_abs;
2192 goto dcopuop;
2193
2194 case fneg_op:
2195 handler.u = ieee754dp_neg;
2196 goto dcopuop;
2197
2198 case fmov_op:
2199 /* an easy one */
2200 DPFROMREG(rv.d, MIPSInst_FS(ir));
2201 goto copcsr;
2202
2203 /* binary op on handler */
2204 dcopbop:
2205 DPFROMREG(fs, MIPSInst_FS(ir));
2206 DPFROMREG(ft, MIPSInst_FT(ir));
2207
2208 rv.d = (*handler.b) (fs, ft);
2209 goto copcsr;
2210 dcopuop:
2211 DPFROMREG(fs, MIPSInst_FS(ir));
2212 rv.d = (*handler.u) (fs);
2213 goto copcsr;
2214
2215 /*
2216 * unary conv ops
2217 */
2218 case fcvts_op:
2219 DPFROMREG(fs, MIPSInst_FS(ir));
2220 rv.s = ieee754sp_fdp(fs);
2221 rfmt = s_fmt;
2222 goto copcsr;
2223
2224 case fcvtd_op:
2225 return SIGILL; /* not defined */
2226
2227 case fcvtw_op:
2228 DPFROMREG(fs, MIPSInst_FS(ir));
2229 rv.w = ieee754dp_tint(fs); /* wrong */
2230 rfmt = w_fmt;
2231 goto copcsr;
2232
2233 case fround_op:
2234 case ftrunc_op:
2235 case fceil_op:
2236 case ffloor_op:
2237 if (!cpu_has_mips_2_3_4_5_r)
2238 return SIGILL;
2239
2240 oldrm = ieee754_csr.rm;
2241 DPFROMREG(fs, MIPSInst_FS(ir));
2242 ieee754_csr.rm = MIPSInst_FUNC(ir);
2243 rv.w = ieee754dp_tint(fs);
2244 ieee754_csr.rm = oldrm;
2245 rfmt = w_fmt;
2246 goto copcsr;
2247
2248 case fcvtl_op:
2249 if (!cpu_has_mips_3_4_5_64_r2_r6)
2250 return SIGILL;
2251
2252 DPFROMREG(fs, MIPSInst_FS(ir));
2253 rv.l = ieee754dp_tlong(fs);
2254 rfmt = l_fmt;
2255 goto copcsr;
2256
2257 case froundl_op:
2258 case ftruncl_op:
2259 case fceill_op:
2260 case ffloorl_op:
2261 if (!cpu_has_mips_3_4_5_64_r2_r6)
2262 return SIGILL;
2263
2264 oldrm = ieee754_csr.rm;
2265 DPFROMREG(fs, MIPSInst_FS(ir));
2266 ieee754_csr.rm = MIPSInst_FUNC(ir);
2267 rv.l = ieee754dp_tlong(fs);
2268 ieee754_csr.rm = oldrm;
2269 rfmt = l_fmt;
2270 goto copcsr;
2271
2272 default:
2273 if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2274 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2275 union ieee754dp fs, ft;
2276
2277 DPFROMREG(fs, MIPSInst_FS(ir));
2278 DPFROMREG(ft, MIPSInst_FT(ir));
2279 rv.w = ieee754dp_cmp(fs, ft,
2280 cmptab[cmpop & 0x7], cmpop & 0x8);
2281 rfmt = -1;
2282 if ((cmpop & 0x8)
2283 &&
2284 ieee754_cxtest
2285 (IEEE754_INVALID_OPERATION))
2286 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2287 else
2288 goto copcsr;
2289
2290 }
2291 else {
2292 return SIGILL;
2293 }
2294 break;
2295 }
2296 break;
2297 }
2298
2299 case w_fmt: {
2300 union ieee754dp fs;
2301
2302 switch (MIPSInst_FUNC(ir)) {
2303 case fcvts_op:
2304 /* convert word to single precision real */
2305 SPFROMREG(fs, MIPSInst_FS(ir));
2306 rv.s = ieee754sp_fint(fs.bits);
2307 rfmt = s_fmt;
2308 goto copcsr;
2309 case fcvtd_op:
2310 /* convert word to double precision real */
2311 SPFROMREG(fs, MIPSInst_FS(ir));
2312 rv.d = ieee754dp_fint(fs.bits);
2313 rfmt = d_fmt;
2314 goto copcsr;
2315 default: {
2316 /* Emulating the new CMP.condn.fmt R6 instruction */
2317 #define CMPOP_MASK 0x7
2318 #define SIGN_BIT (0x1 << 3)
2319 #define PREDICATE_BIT (0x1 << 4)
2320
2321 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2322 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2323 union ieee754sp fs, ft;
2324
2325 /* This is an R6 only instruction */
2326 if (!cpu_has_mips_r6 ||
2327 (MIPSInst_FUNC(ir) & 0x20))
2328 return SIGILL;
2329
2330 /* fmt is w_fmt for single precision so fix it */
2331 rfmt = s_fmt;
2332 /* default to false */
2333 rv.w = 0;
2334
2335 /* CMP.condn.S */
2336 SPFROMREG(fs, MIPSInst_FS(ir));
2337 SPFROMREG(ft, MIPSInst_FT(ir));
2338
2339 /* positive predicates */
2340 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2341 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2342 sig))
2343 rv.w = -1; /* true, all 1s */
2344 if ((sig) &&
2345 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2346 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2347 else
2348 goto copcsr;
2349 } else {
2350 /* negative predicates */
2351 switch (cmpop) {
2352 case 1:
2353 case 2:
2354 case 3:
2355 if (ieee754sp_cmp(fs, ft,
2356 negative_cmptab[cmpop],
2357 sig))
2358 rv.w = -1; /* true, all 1s */
2359 if (sig &&
2360 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2361 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2362 else
2363 goto copcsr;
2364 break;
2365 default:
2366 /* Reserved R6 ops */
2367 pr_err("Reserved MIPS R6 CMP.condn.S operation\n");
2368 return SIGILL;
2369 }
2370 }
2371 break;
2372 }
2373 }
2374 }
2375
2376 case l_fmt:
2377
2378 if (!cpu_has_mips_3_4_5_64_r2_r6)
2379 return SIGILL;
2380
2381 DIFROMREG(bits, MIPSInst_FS(ir));
2382
2383 switch (MIPSInst_FUNC(ir)) {
2384 case fcvts_op:
2385 /* convert long to single precision real */
2386 rv.s = ieee754sp_flong(bits);
2387 rfmt = s_fmt;
2388 goto copcsr;
2389 case fcvtd_op:
2390 /* convert long to double precision real */
2391 rv.d = ieee754dp_flong(bits);
2392 rfmt = d_fmt;
2393 goto copcsr;
2394 default: {
2395 /* Emulating the new CMP.condn.fmt R6 instruction */
2396 int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2397 int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2398 union ieee754dp fs, ft;
2399
2400 if (!cpu_has_mips_r6 ||
2401 (MIPSInst_FUNC(ir) & 0x20))
2402 return SIGILL;
2403
2404 /* fmt is l_fmt for double precision so fix it */
2405 rfmt = d_fmt;
2406 /* default to false */
2407 rv.l = 0;
2408
2409 /* CMP.condn.D */
2410 DPFROMREG(fs, MIPSInst_FS(ir));
2411 DPFROMREG(ft, MIPSInst_FT(ir));
2412
2413 /* positive predicates */
2414 if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2415 if (ieee754dp_cmp(fs, ft,
2416 cmptab[cmpop], sig))
2417 rv.l = -1LL; /* true, all 1s */
2418 if (sig &&
2419 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2420 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2421 else
2422 goto copcsr;
2423 } else {
2424 /* negative predicates */
2425 switch (cmpop) {
2426 case 1:
2427 case 2:
2428 case 3:
2429 if (ieee754dp_cmp(fs, ft,
2430 negative_cmptab[cmpop],
2431 sig))
2432 rv.l = -1LL; /* true, all 1s */
2433 if (sig &&
2434 ieee754_cxtest(IEEE754_INVALID_OPERATION))
2435 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2436 else
2437 goto copcsr;
2438 break;
2439 default:
2440 /* Reserved R6 ops */
2441 pr_err("Reserved MIPS R6 CMP.condn.D operation\n");
2442 return SIGILL;
2443 }
2444 }
2445 break;
2446 }
2447 }
2448 default:
2449 return SIGILL;
2450 }
2451
2452 /*
2453 * Update the fpu CSR register for this operation.
2454 * If an exception is required, generate a tidy SIGFPE exception,
2455 * without updating the result register.
2456 * Note: cause exception bits do not accumulate, they are rewritten
2457 * for each op; only the flag/sticky bits accumulate.
2458 */
2459 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2460 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2461 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2462 return SIGFPE;
2463 }
2464
2465 /*
2466 * Now we can safely write the result back to the register file.
2467 */
2468 switch (rfmt) {
2469 case -1:
2470
2471 if (cpu_has_mips_4_5_r)
2472 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2473 else
2474 cbit = FPU_CSR_COND;
2475 if (rv.w)
2476 ctx->fcr31 |= cbit;
2477 else
2478 ctx->fcr31 &= ~cbit;
2479 break;
2480
2481 case d_fmt:
2482 DPTOREG(rv.d, MIPSInst_FD(ir));
2483 break;
2484 case s_fmt:
2485 SPTOREG(rv.s, MIPSInst_FD(ir));
2486 break;
2487 case w_fmt:
2488 SITOREG(rv.w, MIPSInst_FD(ir));
2489 break;
2490 case l_fmt:
2491 if (!cpu_has_mips_3_4_5_64_r2_r6)
2492 return SIGILL;
2493
2494 DITOREG(rv.l, MIPSInst_FD(ir));
2495 break;
2496 default:
2497 return SIGILL;
2498 }
2499
2500 return 0;
2501 }
2502
2503 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2504 int has_fpu, void *__user *fault_addr)
2505 {
2506 unsigned long oldepc, prevepc;
2507 struct mm_decoded_insn dec_insn;
2508 u16 instr[4];
2509 u16 *instr_ptr;
2510 int sig = 0;
2511
2512 oldepc = xcp->cp0_epc;
2513 do {
2514 prevepc = xcp->cp0_epc;
2515
2516 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2517 /*
2518 * Get next 2 microMIPS instructions and convert them
2519 * into 32-bit instructions.
2520 */
2521 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2522 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2523 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2524 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2525 MIPS_FPU_EMU_INC_STATS(errors);
2526 return SIGBUS;
2527 }
2528 instr_ptr = instr;
2529
2530 /* Get first instruction. */
2531 if (mm_insn_16bit(*instr_ptr)) {
2532 /* Duplicate the half-word. */
2533 dec_insn.insn = (*instr_ptr << 16) |
2534 (*instr_ptr);
2535 /* 16-bit instruction. */
2536 dec_insn.pc_inc = 2;
2537 instr_ptr += 1;
2538 } else {
2539 dec_insn.insn = (*instr_ptr << 16) |
2540 *(instr_ptr+1);
2541 /* 32-bit instruction. */
2542 dec_insn.pc_inc = 4;
2543 instr_ptr += 2;
2544 }
2545 /* Get second instruction. */
2546 if (mm_insn_16bit(*instr_ptr)) {
2547 /* Duplicate the half-word. */
2548 dec_insn.next_insn = (*instr_ptr << 16) |
2549 (*instr_ptr);
2550 /* 16-bit instruction. */
2551 dec_insn.next_pc_inc = 2;
2552 } else {
2553 dec_insn.next_insn = (*instr_ptr << 16) |
2554 *(instr_ptr+1);
2555 /* 32-bit instruction. */
2556 dec_insn.next_pc_inc = 4;
2557 }
2558 dec_insn.micro_mips_mode = 1;
2559 } else {
2560 if ((get_user(dec_insn.insn,
2561 (mips_instruction __user *) xcp->cp0_epc)) ||
2562 (get_user(dec_insn.next_insn,
2563 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2564 MIPS_FPU_EMU_INC_STATS(errors);
2565 return SIGBUS;
2566 }
2567 dec_insn.pc_inc = 4;
2568 dec_insn.next_pc_inc = 4;
2569 dec_insn.micro_mips_mode = 0;
2570 }
2571
2572 if ((dec_insn.insn == 0) ||
2573 ((dec_insn.pc_inc == 2) &&
2574 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2575 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2576 else {
2577 /*
2578 * The 'ieee754_csr' is an alias of ctx->fcr31.
2579 * No need to copy ctx->fcr31 to ieee754_csr.
2580 */
2581 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2582 }
2583
2584 if (has_fpu)
2585 break;
2586 if (sig)
2587 break;
2588
2589 cond_resched();
2590 } while (xcp->cp0_epc > prevepc);
2591
2592 /* SIGILL indicates a non-fpu instruction */
2593 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2594 /* but if EPC has advanced, then ignore it */
2595 sig = 0;
2596
2597 return sig;
2598 }
Linux with added FPC-III support