1 #include "amd64_edac.h"
3 #define EDAC_DCT_ATTR_SHOW(reg) \
4 static ssize_t amd64_##reg##_show(struct device *dev, \
5 struct device_attribute *mattr, \
8 struct mem_ctl_info *mci = to_mci(dev); \
9 struct amd64_pvt *pvt = mci->pvt_info; \
10 return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
13 EDAC_DCT_ATTR_SHOW(dhar
);
14 EDAC_DCT_ATTR_SHOW(dbam0
);
15 EDAC_DCT_ATTR_SHOW(top_mem
);
16 EDAC_DCT_ATTR_SHOW(top_mem2
);
18 static ssize_t
amd64_hole_show(struct device
*dev
,
19 struct device_attribute
*mattr
,
22 struct mem_ctl_info
*mci
= to_mci(dev
);
28 amd64_get_dram_hole_info(mci
, &hole_base
, &hole_offset
, &hole_size
);
30 return sprintf(data
, "%llx %llx %llx\n", hole_base
, hole_offset
,
35 * update NUM_DBG_ATTRS in case you add new members
37 static DEVICE_ATTR(dhar
, S_IRUGO
, amd64_dhar_show
, NULL
);
38 static DEVICE_ATTR(dbam
, S_IRUGO
, amd64_dbam0_show
, NULL
);
39 static DEVICE_ATTR(topmem
, S_IRUGO
, amd64_top_mem_show
, NULL
);
40 static DEVICE_ATTR(topmem2
, S_IRUGO
, amd64_top_mem2_show
, NULL
);
41 static DEVICE_ATTR(dram_hole
, S_IRUGO
, amd64_hole_show
, NULL
);
43 static struct attribute
*amd64_edac_dbg_attrs
[] = {
46 &dev_attr_topmem
.attr
,
47 &dev_attr_topmem2
.attr
,
48 &dev_attr_dram_hole
.attr
,
52 const struct attribute_group amd64_edac_dbg_group
= {
53 .attrs
= amd64_edac_dbg_attrs
,