2 * File: drivers/pci/pcie/aspm.c
3 * Enabling PCIe link L0s/L1 state and Clock Power Management
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/pci_regs.h>
15 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/slab.h>
19 #include <linux/jiffies.h>
20 #include <linux/delay.h>
21 #include <linux/pci-aspm.h>
24 #ifdef MODULE_PARAM_PREFIX
25 #undef MODULE_PARAM_PREFIX
27 #define MODULE_PARAM_PREFIX "pcie_aspm."
29 /* Note: those are not register definitions */
30 #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
31 #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
32 #define ASPM_STATE_L1 (4) /* L1 state */
33 #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
34 #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1)
37 u32 l0s
; /* L0s latency (nsec) */
38 u32 l1
; /* L1 latency (nsec) */
41 struct pcie_link_state
{
42 struct pci_dev
*pdev
; /* Upstream component of the Link */
43 struct pcie_link_state
*root
; /* pointer to the root port link */
44 struct pcie_link_state
*parent
; /* pointer to the parent Link state */
45 struct list_head sibling
; /* node in link_list */
46 struct list_head children
; /* list of child link states */
47 struct list_head link
; /* node in parent's children list */
50 u32 aspm_support
:3; /* Supported ASPM state */
51 u32 aspm_enabled
:3; /* Enabled ASPM state */
52 u32 aspm_capable
:3; /* Capable ASPM state with latency */
53 u32 aspm_default
:3; /* Default ASPM state by BIOS */
54 u32 aspm_disable
:3; /* Disabled ASPM state */
57 u32 clkpm_capable
:1; /* Clock PM capable? */
58 u32 clkpm_enabled
:1; /* Current Clock PM state */
59 u32 clkpm_default
:1; /* Default Clock PM state by BIOS */
62 struct aspm_latency latency_up
; /* Upstream direction exit latency */
63 struct aspm_latency latency_dw
; /* Downstream direction exit latency */
65 * Endpoint acceptable latencies. A pcie downstream port only
66 * has one slot under it, so at most there are 8 functions.
68 struct aspm_latency acceptable
[8];
71 static int aspm_disabled
, aspm_force
;
72 static bool aspm_support_enabled
= true;
73 static DEFINE_MUTEX(aspm_lock
);
74 static LIST_HEAD(link_list
);
76 #define POLICY_DEFAULT 0 /* BIOS default setting */
77 #define POLICY_PERFORMANCE 1 /* high performance */
78 #define POLICY_POWERSAVE 2 /* high power saving */
80 #ifdef CONFIG_PCIEASPM_PERFORMANCE
81 static int aspm_policy
= POLICY_PERFORMANCE
;
82 #elif defined CONFIG_PCIEASPM_POWERSAVE
83 static int aspm_policy
= POLICY_POWERSAVE
;
85 static int aspm_policy
;
88 static const char *policy_str
[] = {
89 [POLICY_DEFAULT
] = "default",
90 [POLICY_PERFORMANCE
] = "performance",
91 [POLICY_POWERSAVE
] = "powersave"
94 #define LINK_RETRAIN_TIMEOUT HZ
96 static int policy_to_aspm_state(struct pcie_link_state
*link
)
98 switch (aspm_policy
) {
99 case POLICY_PERFORMANCE
:
100 /* Disable ASPM and Clock PM */
102 case POLICY_POWERSAVE
:
103 /* Enable ASPM L0s/L1 */
104 return ASPM_STATE_ALL
;
106 return link
->aspm_default
;
111 static int policy_to_clkpm_state(struct pcie_link_state
*link
)
113 switch (aspm_policy
) {
114 case POLICY_PERFORMANCE
:
115 /* Disable ASPM and Clock PM */
117 case POLICY_POWERSAVE
:
118 /* Disable Clock PM */
121 return link
->clkpm_default
;
126 static void pcie_set_clkpm_nocheck(struct pcie_link_state
*link
, int enable
)
128 struct pci_dev
*child
;
129 struct pci_bus
*linkbus
= link
->pdev
->subordinate
;
130 u32 val
= enable
? PCI_EXP_LNKCTL_CLKREQ_EN
: 0;
132 list_for_each_entry(child
, &linkbus
->devices
, bus_list
)
133 pcie_capability_clear_and_set_word(child
, PCI_EXP_LNKCTL
,
134 PCI_EXP_LNKCTL_CLKREQ_EN
,
136 link
->clkpm_enabled
= !!enable
;
139 static void pcie_set_clkpm(struct pcie_link_state
*link
, int enable
)
141 /* Don't enable Clock PM if the link is not Clock PM capable */
142 if (!link
->clkpm_capable
&& enable
)
144 /* Need nothing if the specified equals to current state */
145 if (link
->clkpm_enabled
== enable
)
147 pcie_set_clkpm_nocheck(link
, enable
);
150 static void pcie_clkpm_cap_init(struct pcie_link_state
*link
, int blacklist
)
152 int capable
= 1, enabled
= 1;
155 struct pci_dev
*child
;
156 struct pci_bus
*linkbus
= link
->pdev
->subordinate
;
158 /* All functions should have the same cap and state, take the worst */
159 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
160 pcie_capability_read_dword(child
, PCI_EXP_LNKCAP
, ®32
);
161 if (!(reg32
& PCI_EXP_LNKCAP_CLKPM
)) {
166 pcie_capability_read_word(child
, PCI_EXP_LNKCTL
, ®16
);
167 if (!(reg16
& PCI_EXP_LNKCTL_CLKREQ_EN
))
170 link
->clkpm_enabled
= enabled
;
171 link
->clkpm_default
= enabled
;
172 link
->clkpm_capable
= (blacklist
) ? 0 : capable
;
176 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
177 * could use common clock. If they are, configure them to use the
178 * common clock. That will reduce the ASPM state exit latency.
180 static void pcie_aspm_configure_common_clock(struct pcie_link_state
*link
)
183 u16 reg16
, parent_reg
, child_reg
[8];
184 unsigned long start_jiffies
;
185 struct pci_dev
*child
, *parent
= link
->pdev
;
186 struct pci_bus
*linkbus
= parent
->subordinate
;
188 * All functions of a slot should have the same Slot Clock
189 * Configuration, so just check one function
191 child
= list_entry(linkbus
->devices
.next
, struct pci_dev
, bus_list
);
192 BUG_ON(!pci_is_pcie(child
));
194 /* Check downstream component if bit Slot Clock Configuration is 1 */
195 pcie_capability_read_word(child
, PCI_EXP_LNKSTA
, ®16
);
196 if (!(reg16
& PCI_EXP_LNKSTA_SLC
))
199 /* Check upstream component if bit Slot Clock Configuration is 1 */
200 pcie_capability_read_word(parent
, PCI_EXP_LNKSTA
, ®16
);
201 if (!(reg16
& PCI_EXP_LNKSTA_SLC
))
204 /* Configure downstream component, all functions */
205 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
206 pcie_capability_read_word(child
, PCI_EXP_LNKCTL
, ®16
);
207 child_reg
[PCI_FUNC(child
->devfn
)] = reg16
;
209 reg16
|= PCI_EXP_LNKCTL_CCC
;
211 reg16
&= ~PCI_EXP_LNKCTL_CCC
;
212 pcie_capability_write_word(child
, PCI_EXP_LNKCTL
, reg16
);
215 /* Configure upstream component */
216 pcie_capability_read_word(parent
, PCI_EXP_LNKCTL
, ®16
);
219 reg16
|= PCI_EXP_LNKCTL_CCC
;
221 reg16
&= ~PCI_EXP_LNKCTL_CCC
;
222 pcie_capability_write_word(parent
, PCI_EXP_LNKCTL
, reg16
);
225 reg16
|= PCI_EXP_LNKCTL_RL
;
226 pcie_capability_write_word(parent
, PCI_EXP_LNKCTL
, reg16
);
228 /* Wait for link training end. Break out after waiting for timeout */
229 start_jiffies
= jiffies
;
231 pcie_capability_read_word(parent
, PCI_EXP_LNKSTA
, ®16
);
232 if (!(reg16
& PCI_EXP_LNKSTA_LT
))
234 if (time_after(jiffies
, start_jiffies
+ LINK_RETRAIN_TIMEOUT
))
238 if (!(reg16
& PCI_EXP_LNKSTA_LT
))
241 /* Training failed. Restore common clock configurations */
242 dev_err(&parent
->dev
, "ASPM: Could not configure common clock\n");
243 list_for_each_entry(child
, &linkbus
->devices
, bus_list
)
244 pcie_capability_write_word(child
, PCI_EXP_LNKCTL
,
245 child_reg
[PCI_FUNC(child
->devfn
)]);
246 pcie_capability_write_word(parent
, PCI_EXP_LNKCTL
, parent_reg
);
249 /* Convert L0s latency encoding to ns */
250 static u32
calc_l0s_latency(u32 encoding
)
253 return (5 * 1000); /* > 4us */
254 return (64 << encoding
);
257 /* Convert L0s acceptable latency encoding to ns */
258 static u32
calc_l0s_acceptable(u32 encoding
)
262 return (64 << encoding
);
265 /* Convert L1 latency encoding to ns */
266 static u32
calc_l1_latency(u32 encoding
)
269 return (65 * 1000); /* > 64us */
270 return (1000 << encoding
);
273 /* Convert L1 acceptable latency encoding to ns */
274 static u32
calc_l1_acceptable(u32 encoding
)
278 return (1000 << encoding
);
281 struct aspm_register_info
{
284 u32 latency_encoding_l0s
;
285 u32 latency_encoding_l1
;
288 static void pcie_get_aspm_reg(struct pci_dev
*pdev
,
289 struct aspm_register_info
*info
)
294 pcie_capability_read_dword(pdev
, PCI_EXP_LNKCAP
, ®32
);
295 info
->support
= (reg32
& PCI_EXP_LNKCAP_ASPMS
) >> 10;
296 info
->latency_encoding_l0s
= (reg32
& PCI_EXP_LNKCAP_L0SEL
) >> 12;
297 info
->latency_encoding_l1
= (reg32
& PCI_EXP_LNKCAP_L1EL
) >> 15;
298 pcie_capability_read_word(pdev
, PCI_EXP_LNKCTL
, ®16
);
299 info
->enabled
= reg16
& PCI_EXP_LNKCTL_ASPMC
;
302 static void pcie_aspm_check_latency(struct pci_dev
*endpoint
)
304 u32 latency
, l1_switch_latency
= 0;
305 struct aspm_latency
*acceptable
;
306 struct pcie_link_state
*link
;
308 /* Device not in D0 doesn't need latency check */
309 if ((endpoint
->current_state
!= PCI_D0
) &&
310 (endpoint
->current_state
!= PCI_UNKNOWN
))
313 link
= endpoint
->bus
->self
->link_state
;
314 acceptable
= &link
->acceptable
[PCI_FUNC(endpoint
->devfn
)];
317 /* Check upstream direction L0s latency */
318 if ((link
->aspm_capable
& ASPM_STATE_L0S_UP
) &&
319 (link
->latency_up
.l0s
> acceptable
->l0s
))
320 link
->aspm_capable
&= ~ASPM_STATE_L0S_UP
;
322 /* Check downstream direction L0s latency */
323 if ((link
->aspm_capable
& ASPM_STATE_L0S_DW
) &&
324 (link
->latency_dw
.l0s
> acceptable
->l0s
))
325 link
->aspm_capable
&= ~ASPM_STATE_L0S_DW
;
328 * Every switch on the path to root complex need 1
329 * more microsecond for L1. Spec doesn't mention L0s.
331 latency
= max_t(u32
, link
->latency_up
.l1
, link
->latency_dw
.l1
);
332 if ((link
->aspm_capable
& ASPM_STATE_L1
) &&
333 (latency
+ l1_switch_latency
> acceptable
->l1
))
334 link
->aspm_capable
&= ~ASPM_STATE_L1
;
335 l1_switch_latency
+= 1000;
341 static void pcie_aspm_cap_init(struct pcie_link_state
*link
, int blacklist
)
343 struct pci_dev
*child
, *parent
= link
->pdev
;
344 struct pci_bus
*linkbus
= parent
->subordinate
;
345 struct aspm_register_info upreg
, dwreg
;
348 /* Set enabled/disable so that we will disable ASPM later */
349 link
->aspm_enabled
= ASPM_STATE_ALL
;
350 link
->aspm_disable
= ASPM_STATE_ALL
;
354 /* Configure common clock before checking latencies */
355 pcie_aspm_configure_common_clock(link
);
357 /* Get upstream/downstream components' register state */
358 pcie_get_aspm_reg(parent
, &upreg
);
359 child
= list_entry(linkbus
->devices
.next
, struct pci_dev
, bus_list
);
360 pcie_get_aspm_reg(child
, &dwreg
);
365 * Note that we must not enable L0s in either direction on a
366 * given link unless components on both sides of the link each
369 if (dwreg
.support
& upreg
.support
& PCIE_LINK_STATE_L0S
)
370 link
->aspm_support
|= ASPM_STATE_L0S
;
371 if (dwreg
.enabled
& PCIE_LINK_STATE_L0S
)
372 link
->aspm_enabled
|= ASPM_STATE_L0S_UP
;
373 if (upreg
.enabled
& PCIE_LINK_STATE_L0S
)
374 link
->aspm_enabled
|= ASPM_STATE_L0S_DW
;
375 link
->latency_up
.l0s
= calc_l0s_latency(upreg
.latency_encoding_l0s
);
376 link
->latency_dw
.l0s
= calc_l0s_latency(dwreg
.latency_encoding_l0s
);
379 if (upreg
.support
& dwreg
.support
& PCIE_LINK_STATE_L1
)
380 link
->aspm_support
|= ASPM_STATE_L1
;
381 if (upreg
.enabled
& dwreg
.enabled
& PCIE_LINK_STATE_L1
)
382 link
->aspm_enabled
|= ASPM_STATE_L1
;
383 link
->latency_up
.l1
= calc_l1_latency(upreg
.latency_encoding_l1
);
384 link
->latency_dw
.l1
= calc_l1_latency(dwreg
.latency_encoding_l1
);
386 /* Save default state */
387 link
->aspm_default
= link
->aspm_enabled
;
389 /* Setup initial capable state. Will be updated later */
390 link
->aspm_capable
= link
->aspm_support
;
392 * If the downstream component has pci bridge function, don't
395 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
396 if (pci_pcie_type(child
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
397 link
->aspm_disable
= ASPM_STATE_ALL
;
402 /* Get and check endpoint acceptable latencies */
403 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
405 struct aspm_latency
*acceptable
=
406 &link
->acceptable
[PCI_FUNC(child
->devfn
)];
408 if (pci_pcie_type(child
) != PCI_EXP_TYPE_ENDPOINT
&&
409 pci_pcie_type(child
) != PCI_EXP_TYPE_LEG_END
)
412 pcie_capability_read_dword(child
, PCI_EXP_DEVCAP
, ®32
);
413 /* Calculate endpoint L0s acceptable latency */
414 encoding
= (reg32
& PCI_EXP_DEVCAP_L0S
) >> 6;
415 acceptable
->l0s
= calc_l0s_acceptable(encoding
);
416 /* Calculate endpoint L1 acceptable latency */
417 encoding
= (reg32
& PCI_EXP_DEVCAP_L1
) >> 9;
418 acceptable
->l1
= calc_l1_acceptable(encoding
);
420 pcie_aspm_check_latency(child
);
424 static void pcie_config_aspm_dev(struct pci_dev
*pdev
, u32 val
)
426 pcie_capability_clear_and_set_word(pdev
, PCI_EXP_LNKCTL
,
427 PCI_EXP_LNKCTL_ASPMC
, val
);
430 static void pcie_config_aspm_link(struct pcie_link_state
*link
, u32 state
)
432 u32 upstream
= 0, dwstream
= 0;
433 struct pci_dev
*child
, *parent
= link
->pdev
;
434 struct pci_bus
*linkbus
= parent
->subordinate
;
436 /* Nothing to do if the link is already in the requested state */
437 state
&= (link
->aspm_capable
& ~link
->aspm_disable
);
438 if (link
->aspm_enabled
== state
)
440 /* Convert ASPM state to upstream/downstream ASPM register state */
441 if (state
& ASPM_STATE_L0S_UP
)
442 dwstream
|= PCI_EXP_LNKCTL_ASPM_L0S
;
443 if (state
& ASPM_STATE_L0S_DW
)
444 upstream
|= PCI_EXP_LNKCTL_ASPM_L0S
;
445 if (state
& ASPM_STATE_L1
) {
446 upstream
|= PCI_EXP_LNKCTL_ASPM_L1
;
447 dwstream
|= PCI_EXP_LNKCTL_ASPM_L1
;
450 * Spec 2.0 suggests all functions should be configured the
451 * same setting for ASPM. Enabling ASPM L1 should be done in
452 * upstream component first and then downstream, and vice
453 * versa for disabling ASPM L1. Spec doesn't mention L0S.
455 if (state
& ASPM_STATE_L1
)
456 pcie_config_aspm_dev(parent
, upstream
);
457 list_for_each_entry(child
, &linkbus
->devices
, bus_list
)
458 pcie_config_aspm_dev(child
, dwstream
);
459 if (!(state
& ASPM_STATE_L1
))
460 pcie_config_aspm_dev(parent
, upstream
);
462 link
->aspm_enabled
= state
;
465 static void pcie_config_aspm_path(struct pcie_link_state
*link
)
468 pcie_config_aspm_link(link
, policy_to_aspm_state(link
));
473 static void free_link_state(struct pcie_link_state
*link
)
475 link
->pdev
->link_state
= NULL
;
479 static int pcie_aspm_sanity_check(struct pci_dev
*pdev
)
481 struct pci_dev
*child
;
485 * Some functions in a slot might not all be PCIe functions,
486 * very strange. Disable ASPM for the whole slot
488 list_for_each_entry(child
, &pdev
->subordinate
->devices
, bus_list
) {
489 if (!pci_is_pcie(child
))
493 * If ASPM is disabled then we're not going to change
494 * the BIOS state. It's safe to continue even if it's a
502 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
503 * RBER bit to determine if a function is 1.1 version device
505 pcie_capability_read_dword(child
, PCI_EXP_DEVCAP
, ®32
);
506 if (!(reg32
& PCI_EXP_DEVCAP_RBER
) && !aspm_force
) {
507 dev_info(&child
->dev
, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
514 static struct pcie_link_state
*alloc_pcie_link_state(struct pci_dev
*pdev
)
516 struct pcie_link_state
*link
;
518 link
= kzalloc(sizeof(*link
), GFP_KERNEL
);
521 INIT_LIST_HEAD(&link
->sibling
);
522 INIT_LIST_HEAD(&link
->children
);
523 INIT_LIST_HEAD(&link
->link
);
525 if (pci_pcie_type(pdev
) != PCI_EXP_TYPE_ROOT_PORT
) {
526 struct pcie_link_state
*parent
;
527 parent
= pdev
->bus
->parent
->self
->link_state
;
532 link
->parent
= parent
;
533 list_add(&link
->link
, &parent
->children
);
535 /* Setup a pointer to the root port link */
539 link
->root
= link
->parent
->root
;
541 list_add(&link
->sibling
, &link_list
);
542 pdev
->link_state
= link
;
547 * pcie_aspm_init_link_state: Initiate PCI express link state.
548 * It is called after the pcie and its children devices are scanned.
549 * @pdev: the root port or switch downstream port
551 void pcie_aspm_init_link_state(struct pci_dev
*pdev
)
553 struct pcie_link_state
*link
;
554 int blacklist
= !!pcie_aspm_sanity_check(pdev
);
556 if (!aspm_support_enabled
)
559 if (pdev
->link_state
)
563 * We allocate pcie_link_state for the component on the upstream
564 * end of a Link, so there's nothing to do unless this device has a
565 * Link on its secondary side.
567 if (!pdev
->has_secondary_link
)
570 /* VIA has a strange chipset, root port is under a bridge */
571 if (pci_pcie_type(pdev
) == PCI_EXP_TYPE_ROOT_PORT
&&
575 down_read(&pci_bus_sem
);
576 if (list_empty(&pdev
->subordinate
->devices
))
579 mutex_lock(&aspm_lock
);
580 link
= alloc_pcie_link_state(pdev
);
584 * Setup initial ASPM state. Note that we need to configure
585 * upstream links also because capable state of them can be
586 * update through pcie_aspm_cap_init().
588 pcie_aspm_cap_init(link
, blacklist
);
590 /* Setup initial Clock PM state */
591 pcie_clkpm_cap_init(link
, blacklist
);
594 * At this stage drivers haven't had an opportunity to change the
595 * link policy setting. Enabling ASPM on broken hardware can cripple
596 * it even before the driver has had a chance to disable ASPM, so
597 * default to a safe level right now. If we're enabling ASPM beyond
598 * the BIOS's expectation, we'll do so once pci_enable_device() is
601 if (aspm_policy
!= POLICY_POWERSAVE
) {
602 pcie_config_aspm_path(link
);
603 pcie_set_clkpm(link
, policy_to_clkpm_state(link
));
607 mutex_unlock(&aspm_lock
);
609 up_read(&pci_bus_sem
);
612 /* Recheck latencies and update aspm_capable for links under the root */
613 static void pcie_update_aspm_capable(struct pcie_link_state
*root
)
615 struct pcie_link_state
*link
;
616 BUG_ON(root
->parent
);
617 list_for_each_entry(link
, &link_list
, sibling
) {
618 if (link
->root
!= root
)
620 link
->aspm_capable
= link
->aspm_support
;
622 list_for_each_entry(link
, &link_list
, sibling
) {
623 struct pci_dev
*child
;
624 struct pci_bus
*linkbus
= link
->pdev
->subordinate
;
625 if (link
->root
!= root
)
627 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
628 if ((pci_pcie_type(child
) != PCI_EXP_TYPE_ENDPOINT
) &&
629 (pci_pcie_type(child
) != PCI_EXP_TYPE_LEG_END
))
631 pcie_aspm_check_latency(child
);
636 /* @pdev: the endpoint device */
637 void pcie_aspm_exit_link_state(struct pci_dev
*pdev
)
639 struct pci_dev
*parent
= pdev
->bus
->self
;
640 struct pcie_link_state
*link
, *root
, *parent_link
;
642 if (!parent
|| !parent
->link_state
)
645 down_read(&pci_bus_sem
);
646 mutex_lock(&aspm_lock
);
648 * All PCIe functions are in one slot, remove one function will remove
649 * the whole slot, so just wait until we are the last function left.
651 if (!list_is_last(&pdev
->bus_list
, &parent
->subordinate
->devices
))
654 link
= parent
->link_state
;
656 parent_link
= link
->parent
;
658 /* All functions are removed, so just disable ASPM for the link */
659 pcie_config_aspm_link(link
, 0);
660 list_del(&link
->sibling
);
661 list_del(&link
->link
);
662 /* Clock PM is for endpoint device */
663 free_link_state(link
);
665 /* Recheck latencies and configure upstream links */
667 pcie_update_aspm_capable(root
);
668 pcie_config_aspm_path(parent_link
);
671 mutex_unlock(&aspm_lock
);
672 up_read(&pci_bus_sem
);
675 /* @pdev: the root port or switch downstream port */
676 void pcie_aspm_pm_state_change(struct pci_dev
*pdev
)
678 struct pcie_link_state
*link
= pdev
->link_state
;
680 if (aspm_disabled
|| !link
)
683 * Devices changed PM state, we should recheck if latency
684 * meets all functions' requirement
686 down_read(&pci_bus_sem
);
687 mutex_lock(&aspm_lock
);
688 pcie_update_aspm_capable(link
->root
);
689 pcie_config_aspm_path(link
);
690 mutex_unlock(&aspm_lock
);
691 up_read(&pci_bus_sem
);
694 void pcie_aspm_powersave_config_link(struct pci_dev
*pdev
)
696 struct pcie_link_state
*link
= pdev
->link_state
;
698 if (aspm_disabled
|| !link
)
701 if (aspm_policy
!= POLICY_POWERSAVE
)
704 down_read(&pci_bus_sem
);
705 mutex_lock(&aspm_lock
);
706 pcie_config_aspm_path(link
);
707 pcie_set_clkpm(link
, policy_to_clkpm_state(link
));
708 mutex_unlock(&aspm_lock
);
709 up_read(&pci_bus_sem
);
712 static void __pci_disable_link_state(struct pci_dev
*pdev
, int state
, bool sem
)
714 struct pci_dev
*parent
= pdev
->bus
->self
;
715 struct pcie_link_state
*link
;
717 if (!pci_is_pcie(pdev
))
720 if (pdev
->has_secondary_link
)
722 if (!parent
|| !parent
->link_state
)
726 * A driver requested that ASPM be disabled on this device, but
727 * if we don't have permission to manage ASPM (e.g., on ACPI
728 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
729 * the _OSC method), we can't honor that request. Windows has
730 * a similar mechanism using "PciASPMOptOut", which is also
731 * ignored in this situation.
734 dev_warn(&pdev
->dev
, "can't disable ASPM; OS doesn't have ASPM control\n");
739 down_read(&pci_bus_sem
);
740 mutex_lock(&aspm_lock
);
741 link
= parent
->link_state
;
742 if (state
& PCIE_LINK_STATE_L0S
)
743 link
->aspm_disable
|= ASPM_STATE_L0S
;
744 if (state
& PCIE_LINK_STATE_L1
)
745 link
->aspm_disable
|= ASPM_STATE_L1
;
746 pcie_config_aspm_link(link
, policy_to_aspm_state(link
));
748 if (state
& PCIE_LINK_STATE_CLKPM
) {
749 link
->clkpm_capable
= 0;
750 pcie_set_clkpm(link
, 0);
752 mutex_unlock(&aspm_lock
);
754 up_read(&pci_bus_sem
);
757 void pci_disable_link_state_locked(struct pci_dev
*pdev
, int state
)
759 __pci_disable_link_state(pdev
, state
, false);
761 EXPORT_SYMBOL(pci_disable_link_state_locked
);
764 * pci_disable_link_state - Disable device's link state, so the link will
765 * never enter specific states. Note that if the BIOS didn't grant ASPM
766 * control to the OS, this does nothing because we can't touch the LNKCTL
770 * @state: ASPM link state to disable
772 void pci_disable_link_state(struct pci_dev
*pdev
, int state
)
774 __pci_disable_link_state(pdev
, state
, true);
776 EXPORT_SYMBOL(pci_disable_link_state
);
778 static int pcie_aspm_set_policy(const char *val
, struct kernel_param
*kp
)
781 struct pcie_link_state
*link
;
785 for (i
= 0; i
< ARRAY_SIZE(policy_str
); i
++)
786 if (!strncmp(val
, policy_str
[i
], strlen(policy_str
[i
])))
788 if (i
>= ARRAY_SIZE(policy_str
))
790 if (i
== aspm_policy
)
793 down_read(&pci_bus_sem
);
794 mutex_lock(&aspm_lock
);
796 list_for_each_entry(link
, &link_list
, sibling
) {
797 pcie_config_aspm_link(link
, policy_to_aspm_state(link
));
798 pcie_set_clkpm(link
, policy_to_clkpm_state(link
));
800 mutex_unlock(&aspm_lock
);
801 up_read(&pci_bus_sem
);
805 static int pcie_aspm_get_policy(char *buffer
, struct kernel_param
*kp
)
808 for (i
= 0; i
< ARRAY_SIZE(policy_str
); i
++)
809 if (i
== aspm_policy
)
810 cnt
+= sprintf(buffer
+ cnt
, "[%s] ", policy_str
[i
]);
812 cnt
+= sprintf(buffer
+ cnt
, "%s ", policy_str
[i
]);
816 module_param_call(policy
, pcie_aspm_set_policy
, pcie_aspm_get_policy
,
819 #ifdef CONFIG_PCIEASPM_DEBUG
820 static ssize_t
link_state_show(struct device
*dev
,
821 struct device_attribute
*attr
,
824 struct pci_dev
*pci_device
= to_pci_dev(dev
);
825 struct pcie_link_state
*link_state
= pci_device
->link_state
;
827 return sprintf(buf
, "%d\n", link_state
->aspm_enabled
);
830 static ssize_t
link_state_store(struct device
*dev
,
831 struct device_attribute
*attr
,
835 struct pci_dev
*pdev
= to_pci_dev(dev
);
836 struct pcie_link_state
*link
, *root
= pdev
->link_state
->root
;
842 if (kstrtouint(buf
, 10, &state
))
844 if ((state
& ~ASPM_STATE_ALL
) != 0)
847 down_read(&pci_bus_sem
);
848 mutex_lock(&aspm_lock
);
849 list_for_each_entry(link
, &link_list
, sibling
) {
850 if (link
->root
!= root
)
852 pcie_config_aspm_link(link
, state
);
854 mutex_unlock(&aspm_lock
);
855 up_read(&pci_bus_sem
);
859 static ssize_t
clk_ctl_show(struct device
*dev
,
860 struct device_attribute
*attr
,
863 struct pci_dev
*pci_device
= to_pci_dev(dev
);
864 struct pcie_link_state
*link_state
= pci_device
->link_state
;
866 return sprintf(buf
, "%d\n", link_state
->clkpm_enabled
);
869 static ssize_t
clk_ctl_store(struct device
*dev
,
870 struct device_attribute
*attr
,
874 struct pci_dev
*pdev
= to_pci_dev(dev
);
877 if (strtobool(buf
, &state
))
880 down_read(&pci_bus_sem
);
881 mutex_lock(&aspm_lock
);
882 pcie_set_clkpm_nocheck(pdev
->link_state
, state
);
883 mutex_unlock(&aspm_lock
);
884 up_read(&pci_bus_sem
);
889 static DEVICE_ATTR(link_state
, 0644, link_state_show
, link_state_store
);
890 static DEVICE_ATTR(clk_ctl
, 0644, clk_ctl_show
, clk_ctl_store
);
892 static char power_group
[] = "power";
893 void pcie_aspm_create_sysfs_dev_files(struct pci_dev
*pdev
)
895 struct pcie_link_state
*link_state
= pdev
->link_state
;
900 if (link_state
->aspm_support
)
901 sysfs_add_file_to_group(&pdev
->dev
.kobj
,
902 &dev_attr_link_state
.attr
, power_group
);
903 if (link_state
->clkpm_capable
)
904 sysfs_add_file_to_group(&pdev
->dev
.kobj
,
905 &dev_attr_clk_ctl
.attr
, power_group
);
908 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev
*pdev
)
910 struct pcie_link_state
*link_state
= pdev
->link_state
;
915 if (link_state
->aspm_support
)
916 sysfs_remove_file_from_group(&pdev
->dev
.kobj
,
917 &dev_attr_link_state
.attr
, power_group
);
918 if (link_state
->clkpm_capable
)
919 sysfs_remove_file_from_group(&pdev
->dev
.kobj
,
920 &dev_attr_clk_ctl
.attr
, power_group
);
924 static int __init
pcie_aspm_disable(char *str
)
926 if (!strcmp(str
, "off")) {
927 aspm_policy
= POLICY_DEFAULT
;
929 aspm_support_enabled
= false;
930 printk(KERN_INFO
"PCIe ASPM is disabled\n");
931 } else if (!strcmp(str
, "force")) {
933 printk(KERN_INFO
"PCIe ASPM is forcibly enabled\n");
938 __setup("pcie_aspm=", pcie_aspm_disable
);
940 void pcie_no_aspm(void)
943 * Disabling ASPM is intended to prevent the kernel from modifying
944 * existing hardware state, not to clear existing state. To that end:
945 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
946 * (b) prevent userspace from changing policy
949 aspm_policy
= POLICY_DEFAULT
;
954 bool pcie_aspm_support_enabled(void)
956 return aspm_support_enabled
;
958 EXPORT_SYMBOL(pcie_aspm_support_enabled
);