1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
4 * Author: Stepan Moskovchenko <stepanm@codeaurora.org>
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/platform_device.h>
11 #include <linux/errno.h>
13 #include <linux/io-pgtable.h>
14 #include <linux/interrupt.h>
15 #include <linux/list.h>
16 #include <linux/spinlock.h>
17 #include <linux/slab.h>
18 #include <linux/iommu.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/of_iommu.h>
23 #include <asm/cacheflush.h>
24 #include <linux/sizes.h>
26 #include "msm_iommu_hw-8xxx.h"
27 #include "msm_iommu.h"
29 #define MRC(reg, processor, op1, crn, crm, op2) \
30 __asm__ __volatile__ ( \
31 " mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \
34 /* bitmap of the page sizes currently supported */
35 #define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
37 DEFINE_SPINLOCK(msm_iommu_lock
);
38 static LIST_HEAD(qcom_iommu_devices
);
39 static struct iommu_ops msm_iommu_ops
;
42 struct list_head list_attached
;
43 struct iommu_domain domain
;
44 struct io_pgtable_cfg cfg
;
45 struct io_pgtable_ops
*iop
;
47 spinlock_t pgtlock
; /* pagetable lock */
50 static struct msm_priv
*to_msm_priv(struct iommu_domain
*dom
)
52 return container_of(dom
, struct msm_priv
, domain
);
55 static int __enable_clocks(struct msm_iommu_dev
*iommu
)
59 ret
= clk_enable(iommu
->pclk
);
64 ret
= clk_enable(iommu
->clk
);
66 clk_disable(iommu
->pclk
);
72 static void __disable_clocks(struct msm_iommu_dev
*iommu
)
75 clk_disable(iommu
->clk
);
76 clk_disable(iommu
->pclk
);
79 static void msm_iommu_reset(void __iomem
*base
, int ncb
)
85 SET_ESRRESTORE(base
, 0);
89 SET_TESTBUSCR(base
, 0);
91 SET_GLOBAL_TLBIALL(base
, 0);
93 SET_TLBLKCRWE(base
, 1);
95 for (ctx
= 0; ctx
< ncb
; ctx
++) {
96 SET_BPRCOSH(base
, ctx
, 0);
97 SET_BPRCISH(base
, ctx
, 0);
98 SET_BPRCNSH(base
, ctx
, 0);
99 SET_BPSHCFG(base
, ctx
, 0);
100 SET_BPMTCFG(base
, ctx
, 0);
101 SET_ACTLR(base
, ctx
, 0);
102 SET_SCTLR(base
, ctx
, 0);
103 SET_FSRRESTORE(base
, ctx
, 0);
104 SET_TTBR0(base
, ctx
, 0);
105 SET_TTBR1(base
, ctx
, 0);
106 SET_TTBCR(base
, ctx
, 0);
107 SET_BFBCR(base
, ctx
, 0);
108 SET_PAR(base
, ctx
, 0);
109 SET_FAR(base
, ctx
, 0);
110 SET_CTX_TLBIALL(base
, ctx
, 0);
111 SET_TLBFLPTER(base
, ctx
, 0);
112 SET_TLBSLPTER(base
, ctx
, 0);
113 SET_TLBLKCR(base
, ctx
, 0);
114 SET_CONTEXTIDR(base
, ctx
, 0);
118 static void __flush_iotlb(void *cookie
)
120 struct msm_priv
*priv
= cookie
;
121 struct msm_iommu_dev
*iommu
= NULL
;
122 struct msm_iommu_ctx_dev
*master
;
125 list_for_each_entry(iommu
, &priv
->list_attached
, dom_node
) {
126 ret
= __enable_clocks(iommu
);
130 list_for_each_entry(master
, &iommu
->ctx_list
, list
)
131 SET_CTX_TLBIALL(iommu
->base
, master
->num
, 0);
133 __disable_clocks(iommu
);
139 static void __flush_iotlb_range(unsigned long iova
, size_t size
,
140 size_t granule
, bool leaf
, void *cookie
)
142 struct msm_priv
*priv
= cookie
;
143 struct msm_iommu_dev
*iommu
= NULL
;
144 struct msm_iommu_ctx_dev
*master
;
148 list_for_each_entry(iommu
, &priv
->list_attached
, dom_node
) {
149 ret
= __enable_clocks(iommu
);
153 list_for_each_entry(master
, &iommu
->ctx_list
, list
) {
157 iova
|= GET_CONTEXTIDR_ASID(iommu
->base
,
159 SET_TLBIVA(iommu
->base
, master
->num
, iova
);
161 } while (temp_size
-= granule
);
164 __disable_clocks(iommu
);
171 static void __flush_iotlb_sync(void *cookie
)
174 * Nothing is needed here, the barrier to guarantee
175 * completion of the tlb sync operation is implicitly
176 * taken care when the iommu client does a writel before
177 * kick starting the other master.
181 static const struct iommu_gather_ops msm_iommu_gather_ops
= {
182 .tlb_flush_all
= __flush_iotlb
,
183 .tlb_add_flush
= __flush_iotlb_range
,
184 .tlb_sync
= __flush_iotlb_sync
,
187 static int msm_iommu_alloc_ctx(unsigned long *map
, int start
, int end
)
192 idx
= find_next_zero_bit(map
, end
, start
);
195 } while (test_and_set_bit(idx
, map
));
200 static void msm_iommu_free_ctx(unsigned long *map
, int idx
)
205 static void config_mids(struct msm_iommu_dev
*iommu
,
206 struct msm_iommu_ctx_dev
*master
)
210 for (i
= 0; i
< master
->num_mids
; i
++) {
211 mid
= master
->mids
[i
];
214 SET_M2VCBR_N(iommu
->base
, mid
, 0);
215 SET_CBACR_N(iommu
->base
, ctx
, 0);
218 SET_VMID(iommu
->base
, mid
, 0);
220 /* Set the context number for that MID to this context */
221 SET_CBNDX(iommu
->base
, mid
, ctx
);
223 /* Set MID associated with this context bank to 0*/
224 SET_CBVMID(iommu
->base
, ctx
, 0);
226 /* Set the ASID for TLB tagging for this context */
227 SET_CONTEXTIDR_ASID(iommu
->base
, ctx
, ctx
);
229 /* Set security bit override to be Non-secure */
230 SET_NSCFG(iommu
->base
, mid
, 3);
234 static void __reset_context(void __iomem
*base
, int ctx
)
236 SET_BPRCOSH(base
, ctx
, 0);
237 SET_BPRCISH(base
, ctx
, 0);
238 SET_BPRCNSH(base
, ctx
, 0);
239 SET_BPSHCFG(base
, ctx
, 0);
240 SET_BPMTCFG(base
, ctx
, 0);
241 SET_ACTLR(base
, ctx
, 0);
242 SET_SCTLR(base
, ctx
, 0);
243 SET_FSRRESTORE(base
, ctx
, 0);
244 SET_TTBR0(base
, ctx
, 0);
245 SET_TTBR1(base
, ctx
, 0);
246 SET_TTBCR(base
, ctx
, 0);
247 SET_BFBCR(base
, ctx
, 0);
248 SET_PAR(base
, ctx
, 0);
249 SET_FAR(base
, ctx
, 0);
250 SET_CTX_TLBIALL(base
, ctx
, 0);
251 SET_TLBFLPTER(base
, ctx
, 0);
252 SET_TLBSLPTER(base
, ctx
, 0);
253 SET_TLBLKCR(base
, ctx
, 0);
256 static void __program_context(void __iomem
*base
, int ctx
,
257 struct msm_priv
*priv
)
259 __reset_context(base
, ctx
);
261 /* Turn on TEX Remap */
262 SET_TRE(base
, ctx
, 1);
263 SET_AFE(base
, ctx
, 1);
265 /* Set up HTW mode */
266 /* TLB miss configuration: perform HTW on miss */
267 SET_TLBMCFG(base
, ctx
, 0x3);
269 /* V2P configuration: HTW for access */
270 SET_V2PCFG(base
, ctx
, 0x3);
272 SET_TTBCR(base
, ctx
, priv
->cfg
.arm_v7s_cfg
.tcr
);
273 SET_TTBR0(base
, ctx
, priv
->cfg
.arm_v7s_cfg
.ttbr
[0]);
274 SET_TTBR1(base
, ctx
, priv
->cfg
.arm_v7s_cfg
.ttbr
[1]);
276 /* Set prrr and nmrr */
277 SET_PRRR(base
, ctx
, priv
->cfg
.arm_v7s_cfg
.prrr
);
278 SET_NMRR(base
, ctx
, priv
->cfg
.arm_v7s_cfg
.nmrr
);
280 /* Invalidate the TLB for this context */
281 SET_CTX_TLBIALL(base
, ctx
, 0);
283 /* Set interrupt number to "secure" interrupt */
284 SET_IRPTNDX(base
, ctx
, 0);
286 /* Enable context fault interrupt */
287 SET_CFEIE(base
, ctx
, 1);
289 /* Stall access on a context fault and let the handler deal with it */
290 SET_CFCFG(base
, ctx
, 1);
292 /* Redirect all cacheable requests to L2 slave port. */
293 SET_RCISH(base
, ctx
, 1);
294 SET_RCOSH(base
, ctx
, 1);
295 SET_RCNSH(base
, ctx
, 1);
297 /* Turn on BFB prefetch */
298 SET_BFBDFE(base
, ctx
, 1);
304 static struct iommu_domain
*msm_iommu_domain_alloc(unsigned type
)
306 struct msm_priv
*priv
;
308 if (type
!= IOMMU_DOMAIN_UNMANAGED
)
311 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
315 INIT_LIST_HEAD(&priv
->list_attached
);
317 priv
->domain
.geometry
.aperture_start
= 0;
318 priv
->domain
.geometry
.aperture_end
= (1ULL << 32) - 1;
319 priv
->domain
.geometry
.force_aperture
= true;
321 return &priv
->domain
;
328 static void msm_iommu_domain_free(struct iommu_domain
*domain
)
330 struct msm_priv
*priv
;
333 spin_lock_irqsave(&msm_iommu_lock
, flags
);
334 priv
= to_msm_priv(domain
);
336 spin_unlock_irqrestore(&msm_iommu_lock
, flags
);
339 static int msm_iommu_domain_config(struct msm_priv
*priv
)
341 spin_lock_init(&priv
->pgtlock
);
343 priv
->cfg
= (struct io_pgtable_cfg
) {
344 .quirks
= IO_PGTABLE_QUIRK_TLBI_ON_MAP
,
345 .pgsize_bitmap
= msm_iommu_ops
.pgsize_bitmap
,
348 .tlb
= &msm_iommu_gather_ops
,
349 .iommu_dev
= priv
->dev
,
352 priv
->iop
= alloc_io_pgtable_ops(ARM_V7S
, &priv
->cfg
, priv
);
354 dev_err(priv
->dev
, "Failed to allocate pgtable\n");
358 msm_iommu_ops
.pgsize_bitmap
= priv
->cfg
.pgsize_bitmap
;
363 /* Must be called under msm_iommu_lock */
364 static struct msm_iommu_dev
*find_iommu_for_dev(struct device
*dev
)
366 struct msm_iommu_dev
*iommu
, *ret
= NULL
;
367 struct msm_iommu_ctx_dev
*master
;
369 list_for_each_entry(iommu
, &qcom_iommu_devices
, dev_node
) {
370 master
= list_first_entry(&iommu
->ctx_list
,
371 struct msm_iommu_ctx_dev
,
373 if (master
->of_node
== dev
->of_node
) {
382 static int msm_iommu_add_device(struct device
*dev
)
384 struct msm_iommu_dev
*iommu
;
385 struct iommu_group
*group
;
388 spin_lock_irqsave(&msm_iommu_lock
, flags
);
389 iommu
= find_iommu_for_dev(dev
);
390 spin_unlock_irqrestore(&msm_iommu_lock
, flags
);
393 iommu_device_link(&iommu
->iommu
, dev
);
397 group
= iommu_group_get_for_dev(dev
);
399 return PTR_ERR(group
);
401 iommu_group_put(group
);
406 static void msm_iommu_remove_device(struct device
*dev
)
408 struct msm_iommu_dev
*iommu
;
411 spin_lock_irqsave(&msm_iommu_lock
, flags
);
412 iommu
= find_iommu_for_dev(dev
);
413 spin_unlock_irqrestore(&msm_iommu_lock
, flags
);
416 iommu_device_unlink(&iommu
->iommu
, dev
);
418 iommu_group_remove_device(dev
);
421 static int msm_iommu_attach_dev(struct iommu_domain
*domain
, struct device
*dev
)
425 struct msm_iommu_dev
*iommu
;
426 struct msm_priv
*priv
= to_msm_priv(domain
);
427 struct msm_iommu_ctx_dev
*master
;
430 msm_iommu_domain_config(priv
);
432 spin_lock_irqsave(&msm_iommu_lock
, flags
);
433 list_for_each_entry(iommu
, &qcom_iommu_devices
, dev_node
) {
434 master
= list_first_entry(&iommu
->ctx_list
,
435 struct msm_iommu_ctx_dev
,
437 if (master
->of_node
== dev
->of_node
) {
438 ret
= __enable_clocks(iommu
);
442 list_for_each_entry(master
, &iommu
->ctx_list
, list
) {
444 dev_err(dev
, "domain already attached");
449 msm_iommu_alloc_ctx(iommu
->context_map
,
451 if (IS_ERR_VALUE(master
->num
)) {
455 config_mids(iommu
, master
);
456 __program_context(iommu
->base
, master
->num
,
459 __disable_clocks(iommu
);
460 list_add(&iommu
->dom_node
, &priv
->list_attached
);
465 spin_unlock_irqrestore(&msm_iommu_lock
, flags
);
470 static void msm_iommu_detach_dev(struct iommu_domain
*domain
,
473 struct msm_priv
*priv
= to_msm_priv(domain
);
475 struct msm_iommu_dev
*iommu
;
476 struct msm_iommu_ctx_dev
*master
;
479 free_io_pgtable_ops(priv
->iop
);
481 spin_lock_irqsave(&msm_iommu_lock
, flags
);
482 list_for_each_entry(iommu
, &priv
->list_attached
, dom_node
) {
483 ret
= __enable_clocks(iommu
);
487 list_for_each_entry(master
, &iommu
->ctx_list
, list
) {
488 msm_iommu_free_ctx(iommu
->context_map
, master
->num
);
489 __reset_context(iommu
->base
, master
->num
);
491 __disable_clocks(iommu
);
494 spin_unlock_irqrestore(&msm_iommu_lock
, flags
);
497 static int msm_iommu_map(struct iommu_domain
*domain
, unsigned long iova
,
498 phys_addr_t pa
, size_t len
, int prot
)
500 struct msm_priv
*priv
= to_msm_priv(domain
);
504 spin_lock_irqsave(&priv
->pgtlock
, flags
);
505 ret
= priv
->iop
->map(priv
->iop
, iova
, pa
, len
, prot
);
506 spin_unlock_irqrestore(&priv
->pgtlock
, flags
);
511 static size_t msm_iommu_unmap(struct iommu_domain
*domain
, unsigned long iova
,
514 struct msm_priv
*priv
= to_msm_priv(domain
);
517 spin_lock_irqsave(&priv
->pgtlock
, flags
);
518 len
= priv
->iop
->unmap(priv
->iop
, iova
, len
);
519 spin_unlock_irqrestore(&priv
->pgtlock
, flags
);
524 static phys_addr_t
msm_iommu_iova_to_phys(struct iommu_domain
*domain
,
527 struct msm_priv
*priv
;
528 struct msm_iommu_dev
*iommu
;
529 struct msm_iommu_ctx_dev
*master
;
534 spin_lock_irqsave(&msm_iommu_lock
, flags
);
536 priv
= to_msm_priv(domain
);
537 iommu
= list_first_entry(&priv
->list_attached
,
538 struct msm_iommu_dev
, dom_node
);
540 if (list_empty(&iommu
->ctx_list
))
543 master
= list_first_entry(&iommu
->ctx_list
,
544 struct msm_iommu_ctx_dev
, list
);
548 ret
= __enable_clocks(iommu
);
552 /* Invalidate context TLB */
553 SET_CTX_TLBIALL(iommu
->base
, master
->num
, 0);
554 SET_V2PPR(iommu
->base
, master
->num
, va
& V2Pxx_VA
);
556 par
= GET_PAR(iommu
->base
, master
->num
);
558 /* We are dealing with a supersection */
559 if (GET_NOFAULT_SS(iommu
->base
, master
->num
))
560 ret
= (par
& 0xFF000000) | (va
& 0x00FFFFFF);
561 else /* Upper 20 bits from PAR, lower 12 from VA */
562 ret
= (par
& 0xFFFFF000) | (va
& 0x00000FFF);
564 if (GET_FAULT(iommu
->base
, master
->num
))
567 __disable_clocks(iommu
);
569 spin_unlock_irqrestore(&msm_iommu_lock
, flags
);
573 static bool msm_iommu_capable(enum iommu_cap cap
)
578 static void print_ctx_regs(void __iomem
*base
, int ctx
)
580 unsigned int fsr
= GET_FSR(base
, ctx
);
581 pr_err("FAR = %08x PAR = %08x\n",
582 GET_FAR(base
, ctx
), GET_PAR(base
, ctx
));
583 pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr
,
584 (fsr
& 0x02) ? "TF " : "",
585 (fsr
& 0x04) ? "AFF " : "",
586 (fsr
& 0x08) ? "APF " : "",
587 (fsr
& 0x10) ? "TLBMF " : "",
588 (fsr
& 0x20) ? "HTWDEEF " : "",
589 (fsr
& 0x40) ? "HTWSEEF " : "",
590 (fsr
& 0x80) ? "MHF " : "",
591 (fsr
& 0x10000) ? "SL " : "",
592 (fsr
& 0x40000000) ? "SS " : "",
593 (fsr
& 0x80000000) ? "MULTI " : "");
595 pr_err("FSYNR0 = %08x FSYNR1 = %08x\n",
596 GET_FSYNR0(base
, ctx
), GET_FSYNR1(base
, ctx
));
597 pr_err("TTBR0 = %08x TTBR1 = %08x\n",
598 GET_TTBR0(base
, ctx
), GET_TTBR1(base
, ctx
));
599 pr_err("SCTLR = %08x ACTLR = %08x\n",
600 GET_SCTLR(base
, ctx
), GET_ACTLR(base
, ctx
));
603 static void insert_iommu_master(struct device
*dev
,
604 struct msm_iommu_dev
**iommu
,
605 struct of_phandle_args
*spec
)
607 struct msm_iommu_ctx_dev
*master
= dev
->archdata
.iommu
;
610 if (list_empty(&(*iommu
)->ctx_list
)) {
611 master
= kzalloc(sizeof(*master
), GFP_ATOMIC
);
612 master
->of_node
= dev
->of_node
;
613 list_add(&master
->list
, &(*iommu
)->ctx_list
);
614 dev
->archdata
.iommu
= master
;
617 for (sid
= 0; sid
< master
->num_mids
; sid
++)
618 if (master
->mids
[sid
] == spec
->args
[0]) {
619 dev_warn(dev
, "Stream ID 0x%hx repeated; ignoring\n",
624 master
->mids
[master
->num_mids
++] = spec
->args
[0];
627 static int qcom_iommu_of_xlate(struct device
*dev
,
628 struct of_phandle_args
*spec
)
630 struct msm_iommu_dev
*iommu
;
634 spin_lock_irqsave(&msm_iommu_lock
, flags
);
635 list_for_each_entry(iommu
, &qcom_iommu_devices
, dev_node
)
636 if (iommu
->dev
->of_node
== spec
->np
)
639 if (!iommu
|| iommu
->dev
->of_node
!= spec
->np
) {
644 insert_iommu_master(dev
, &iommu
, spec
);
646 spin_unlock_irqrestore(&msm_iommu_lock
, flags
);
651 irqreturn_t
msm_iommu_fault_handler(int irq
, void *dev_id
)
653 struct msm_iommu_dev
*iommu
= dev_id
;
657 spin_lock(&msm_iommu_lock
);
660 pr_err("Invalid device ID in context interrupt handler\n");
664 pr_err("Unexpected IOMMU page fault!\n");
665 pr_err("base = %08x\n", (unsigned int)iommu
->base
);
667 ret
= __enable_clocks(iommu
);
671 for (i
= 0; i
< iommu
->ncb
; i
++) {
672 fsr
= GET_FSR(iommu
->base
, i
);
674 pr_err("Fault occurred in context %d.\n", i
);
675 pr_err("Interesting registers:\n");
676 print_ctx_regs(iommu
->base
, i
);
677 SET_FSR(iommu
->base
, i
, 0x4000000F);
680 __disable_clocks(iommu
);
682 spin_unlock(&msm_iommu_lock
);
686 static struct iommu_ops msm_iommu_ops
= {
687 .capable
= msm_iommu_capable
,
688 .domain_alloc
= msm_iommu_domain_alloc
,
689 .domain_free
= msm_iommu_domain_free
,
690 .attach_dev
= msm_iommu_attach_dev
,
691 .detach_dev
= msm_iommu_detach_dev
,
692 .map
= msm_iommu_map
,
693 .unmap
= msm_iommu_unmap
,
694 .iova_to_phys
= msm_iommu_iova_to_phys
,
695 .add_device
= msm_iommu_add_device
,
696 .remove_device
= msm_iommu_remove_device
,
697 .device_group
= generic_device_group
,
698 .pgsize_bitmap
= MSM_IOMMU_PGSIZES
,
699 .of_xlate
= qcom_iommu_of_xlate
,
702 static int msm_iommu_probe(struct platform_device
*pdev
)
705 resource_size_t ioaddr
;
706 struct msm_iommu_dev
*iommu
;
709 iommu
= devm_kzalloc(&pdev
->dev
, sizeof(*iommu
), GFP_KERNEL
);
713 iommu
->dev
= &pdev
->dev
;
714 INIT_LIST_HEAD(&iommu
->ctx_list
);
716 iommu
->pclk
= devm_clk_get(iommu
->dev
, "smmu_pclk");
717 if (IS_ERR(iommu
->pclk
)) {
718 dev_err(iommu
->dev
, "could not get smmu_pclk\n");
719 return PTR_ERR(iommu
->pclk
);
722 ret
= clk_prepare(iommu
->pclk
);
724 dev_err(iommu
->dev
, "could not prepare smmu_pclk\n");
728 iommu
->clk
= devm_clk_get(iommu
->dev
, "iommu_clk");
729 if (IS_ERR(iommu
->clk
)) {
730 dev_err(iommu
->dev
, "could not get iommu_clk\n");
731 clk_unprepare(iommu
->pclk
);
732 return PTR_ERR(iommu
->clk
);
735 ret
= clk_prepare(iommu
->clk
);
737 dev_err(iommu
->dev
, "could not prepare iommu_clk\n");
738 clk_unprepare(iommu
->pclk
);
742 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
743 iommu
->base
= devm_ioremap_resource(iommu
->dev
, r
);
744 if (IS_ERR(iommu
->base
)) {
745 dev_err(iommu
->dev
, "could not get iommu base\n");
746 ret
= PTR_ERR(iommu
->base
);
751 iommu
->irq
= platform_get_irq(pdev
, 0);
752 if (iommu
->irq
< 0) {
753 dev_err(iommu
->dev
, "could not get iommu irq\n");
758 ret
= of_property_read_u32(iommu
->dev
->of_node
, "qcom,ncb", &val
);
760 dev_err(iommu
->dev
, "could not get ncb\n");
765 msm_iommu_reset(iommu
->base
, iommu
->ncb
);
766 SET_M(iommu
->base
, 0, 1);
767 SET_PAR(iommu
->base
, 0, 0);
768 SET_V2PCFG(iommu
->base
, 0, 1);
769 SET_V2PPR(iommu
->base
, 0, 0);
770 par
= GET_PAR(iommu
->base
, 0);
771 SET_V2PCFG(iommu
->base
, 0, 0);
772 SET_M(iommu
->base
, 0, 0);
775 pr_err("Invalid PAR value detected\n");
780 ret
= devm_request_threaded_irq(iommu
->dev
, iommu
->irq
, NULL
,
781 msm_iommu_fault_handler
,
782 IRQF_ONESHOT
| IRQF_SHARED
,
783 "msm_iommu_secure_irpt_handler",
786 pr_err("Request IRQ %d failed with ret=%d\n", iommu
->irq
, ret
);
790 list_add(&iommu
->dev_node
, &qcom_iommu_devices
);
792 ret
= iommu_device_sysfs_add(&iommu
->iommu
, iommu
->dev
, NULL
,
793 "msm-smmu.%pa", &ioaddr
);
795 pr_err("Could not add msm-smmu at %pa to sysfs\n", &ioaddr
);
799 iommu_device_set_ops(&iommu
->iommu
, &msm_iommu_ops
);
800 iommu_device_set_fwnode(&iommu
->iommu
, &pdev
->dev
.of_node
->fwnode
);
802 ret
= iommu_device_register(&iommu
->iommu
);
804 pr_err("Could not register msm-smmu at %pa\n", &ioaddr
);
808 bus_set_iommu(&platform_bus_type
, &msm_iommu_ops
);
810 pr_info("device mapped at %p, irq %d with %d ctx banks\n",
811 iommu
->base
, iommu
->irq
, iommu
->ncb
);
815 clk_unprepare(iommu
->clk
);
816 clk_unprepare(iommu
->pclk
);
820 static const struct of_device_id msm_iommu_dt_match
[] = {
821 { .compatible
= "qcom,apq8064-iommu" },
825 static int msm_iommu_remove(struct platform_device
*pdev
)
827 struct msm_iommu_dev
*iommu
= platform_get_drvdata(pdev
);
829 clk_unprepare(iommu
->clk
);
830 clk_unprepare(iommu
->pclk
);
834 static struct platform_driver msm_iommu_driver
= {
837 .of_match_table
= msm_iommu_dt_match
,
839 .probe
= msm_iommu_probe
,
840 .remove
= msm_iommu_remove
,
843 static int __init
msm_iommu_driver_init(void)
847 ret
= platform_driver_register(&msm_iommu_driver
);
849 pr_err("Failed to register IOMMU driver\n");
853 subsys_initcall(msm_iommu_driver_init
);