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[linux/fpc-iii.git] / drivers / iommu / msm_iommu.c
blobb25e2eb9e038d9460a94b487d66c718693f3c8cc
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
4 * Author: Stepan Moskovchenko <stepanm@codeaurora.org>
5 */
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/platform_device.h>
11 #include <linux/errno.h>
12 #include <linux/io.h>
13 #include <linux/io-pgtable.h>
14 #include <linux/interrupt.h>
15 #include <linux/list.h>
16 #include <linux/spinlock.h>
17 #include <linux/slab.h>
18 #include <linux/iommu.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/of_iommu.h>
23 #include <asm/cacheflush.h>
24 #include <linux/sizes.h>
26 #include "msm_iommu_hw-8xxx.h"
27 #include "msm_iommu.h"
29 #define MRC(reg, processor, op1, crn, crm, op2) \
30 __asm__ __volatile__ ( \
31 " mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \
32 : "=r" (reg))
34 /* bitmap of the page sizes currently supported */
35 #define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
37 DEFINE_SPINLOCK(msm_iommu_lock);
38 static LIST_HEAD(qcom_iommu_devices);
39 static struct iommu_ops msm_iommu_ops;
41 struct msm_priv {
42 struct list_head list_attached;
43 struct iommu_domain domain;
44 struct io_pgtable_cfg cfg;
45 struct io_pgtable_ops *iop;
46 struct device *dev;
47 spinlock_t pgtlock; /* pagetable lock */
50 static struct msm_priv *to_msm_priv(struct iommu_domain *dom)
52 return container_of(dom, struct msm_priv, domain);
55 static int __enable_clocks(struct msm_iommu_dev *iommu)
57 int ret;
59 ret = clk_enable(iommu->pclk);
60 if (ret)
61 goto fail;
63 if (iommu->clk) {
64 ret = clk_enable(iommu->clk);
65 if (ret)
66 clk_disable(iommu->pclk);
68 fail:
69 return ret;
72 static void __disable_clocks(struct msm_iommu_dev *iommu)
74 if (iommu->clk)
75 clk_disable(iommu->clk);
76 clk_disable(iommu->pclk);
79 static void msm_iommu_reset(void __iomem *base, int ncb)
81 int ctx;
83 SET_RPUE(base, 0);
84 SET_RPUEIE(base, 0);
85 SET_ESRRESTORE(base, 0);
86 SET_TBE(base, 0);
87 SET_CR(base, 0);
88 SET_SPDMBE(base, 0);
89 SET_TESTBUSCR(base, 0);
90 SET_TLBRSW(base, 0);
91 SET_GLOBAL_TLBIALL(base, 0);
92 SET_RPU_ACR(base, 0);
93 SET_TLBLKCRWE(base, 1);
95 for (ctx = 0; ctx < ncb; ctx++) {
96 SET_BPRCOSH(base, ctx, 0);
97 SET_BPRCISH(base, ctx, 0);
98 SET_BPRCNSH(base, ctx, 0);
99 SET_BPSHCFG(base, ctx, 0);
100 SET_BPMTCFG(base, ctx, 0);
101 SET_ACTLR(base, ctx, 0);
102 SET_SCTLR(base, ctx, 0);
103 SET_FSRRESTORE(base, ctx, 0);
104 SET_TTBR0(base, ctx, 0);
105 SET_TTBR1(base, ctx, 0);
106 SET_TTBCR(base, ctx, 0);
107 SET_BFBCR(base, ctx, 0);
108 SET_PAR(base, ctx, 0);
109 SET_FAR(base, ctx, 0);
110 SET_CTX_TLBIALL(base, ctx, 0);
111 SET_TLBFLPTER(base, ctx, 0);
112 SET_TLBSLPTER(base, ctx, 0);
113 SET_TLBLKCR(base, ctx, 0);
114 SET_CONTEXTIDR(base, ctx, 0);
118 static void __flush_iotlb(void *cookie)
120 struct msm_priv *priv = cookie;
121 struct msm_iommu_dev *iommu = NULL;
122 struct msm_iommu_ctx_dev *master;
123 int ret = 0;
125 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
126 ret = __enable_clocks(iommu);
127 if (ret)
128 goto fail;
130 list_for_each_entry(master, &iommu->ctx_list, list)
131 SET_CTX_TLBIALL(iommu->base, master->num, 0);
133 __disable_clocks(iommu);
135 fail:
136 return;
139 static void __flush_iotlb_range(unsigned long iova, size_t size,
140 size_t granule, bool leaf, void *cookie)
142 struct msm_priv *priv = cookie;
143 struct msm_iommu_dev *iommu = NULL;
144 struct msm_iommu_ctx_dev *master;
145 int ret = 0;
146 int temp_size;
148 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
149 ret = __enable_clocks(iommu);
150 if (ret)
151 goto fail;
153 list_for_each_entry(master, &iommu->ctx_list, list) {
154 temp_size = size;
155 do {
156 iova &= TLBIVA_VA;
157 iova |= GET_CONTEXTIDR_ASID(iommu->base,
158 master->num);
159 SET_TLBIVA(iommu->base, master->num, iova);
160 iova += granule;
161 } while (temp_size -= granule);
164 __disable_clocks(iommu);
167 fail:
168 return;
171 static void __flush_iotlb_sync(void *cookie)
174 * Nothing is needed here, the barrier to guarantee
175 * completion of the tlb sync operation is implicitly
176 * taken care when the iommu client does a writel before
177 * kick starting the other master.
181 static const struct iommu_gather_ops msm_iommu_gather_ops = {
182 .tlb_flush_all = __flush_iotlb,
183 .tlb_add_flush = __flush_iotlb_range,
184 .tlb_sync = __flush_iotlb_sync,
187 static int msm_iommu_alloc_ctx(unsigned long *map, int start, int end)
189 int idx;
191 do {
192 idx = find_next_zero_bit(map, end, start);
193 if (idx == end)
194 return -ENOSPC;
195 } while (test_and_set_bit(idx, map));
197 return idx;
200 static void msm_iommu_free_ctx(unsigned long *map, int idx)
202 clear_bit(idx, map);
205 static void config_mids(struct msm_iommu_dev *iommu,
206 struct msm_iommu_ctx_dev *master)
208 int mid, ctx, i;
210 for (i = 0; i < master->num_mids; i++) {
211 mid = master->mids[i];
212 ctx = master->num;
214 SET_M2VCBR_N(iommu->base, mid, 0);
215 SET_CBACR_N(iommu->base, ctx, 0);
217 /* Set VMID = 0 */
218 SET_VMID(iommu->base, mid, 0);
220 /* Set the context number for that MID to this context */
221 SET_CBNDX(iommu->base, mid, ctx);
223 /* Set MID associated with this context bank to 0*/
224 SET_CBVMID(iommu->base, ctx, 0);
226 /* Set the ASID for TLB tagging for this context */
227 SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);
229 /* Set security bit override to be Non-secure */
230 SET_NSCFG(iommu->base, mid, 3);
234 static void __reset_context(void __iomem *base, int ctx)
236 SET_BPRCOSH(base, ctx, 0);
237 SET_BPRCISH(base, ctx, 0);
238 SET_BPRCNSH(base, ctx, 0);
239 SET_BPSHCFG(base, ctx, 0);
240 SET_BPMTCFG(base, ctx, 0);
241 SET_ACTLR(base, ctx, 0);
242 SET_SCTLR(base, ctx, 0);
243 SET_FSRRESTORE(base, ctx, 0);
244 SET_TTBR0(base, ctx, 0);
245 SET_TTBR1(base, ctx, 0);
246 SET_TTBCR(base, ctx, 0);
247 SET_BFBCR(base, ctx, 0);
248 SET_PAR(base, ctx, 0);
249 SET_FAR(base, ctx, 0);
250 SET_CTX_TLBIALL(base, ctx, 0);
251 SET_TLBFLPTER(base, ctx, 0);
252 SET_TLBSLPTER(base, ctx, 0);
253 SET_TLBLKCR(base, ctx, 0);
256 static void __program_context(void __iomem *base, int ctx,
257 struct msm_priv *priv)
259 __reset_context(base, ctx);
261 /* Turn on TEX Remap */
262 SET_TRE(base, ctx, 1);
263 SET_AFE(base, ctx, 1);
265 /* Set up HTW mode */
266 /* TLB miss configuration: perform HTW on miss */
267 SET_TLBMCFG(base, ctx, 0x3);
269 /* V2P configuration: HTW for access */
270 SET_V2PCFG(base, ctx, 0x3);
272 SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr);
273 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[0]);
274 SET_TTBR1(base, ctx, priv->cfg.arm_v7s_cfg.ttbr[1]);
276 /* Set prrr and nmrr */
277 SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr);
278 SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr);
280 /* Invalidate the TLB for this context */
281 SET_CTX_TLBIALL(base, ctx, 0);
283 /* Set interrupt number to "secure" interrupt */
284 SET_IRPTNDX(base, ctx, 0);
286 /* Enable context fault interrupt */
287 SET_CFEIE(base, ctx, 1);
289 /* Stall access on a context fault and let the handler deal with it */
290 SET_CFCFG(base, ctx, 1);
292 /* Redirect all cacheable requests to L2 slave port. */
293 SET_RCISH(base, ctx, 1);
294 SET_RCOSH(base, ctx, 1);
295 SET_RCNSH(base, ctx, 1);
297 /* Turn on BFB prefetch */
298 SET_BFBDFE(base, ctx, 1);
300 /* Enable the MMU */
301 SET_M(base, ctx, 1);
304 static struct iommu_domain *msm_iommu_domain_alloc(unsigned type)
306 struct msm_priv *priv;
308 if (type != IOMMU_DOMAIN_UNMANAGED)
309 return NULL;
311 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
312 if (!priv)
313 goto fail_nomem;
315 INIT_LIST_HEAD(&priv->list_attached);
317 priv->domain.geometry.aperture_start = 0;
318 priv->domain.geometry.aperture_end = (1ULL << 32) - 1;
319 priv->domain.geometry.force_aperture = true;
321 return &priv->domain;
323 fail_nomem:
324 kfree(priv);
325 return NULL;
328 static void msm_iommu_domain_free(struct iommu_domain *domain)
330 struct msm_priv *priv;
331 unsigned long flags;
333 spin_lock_irqsave(&msm_iommu_lock, flags);
334 priv = to_msm_priv(domain);
335 kfree(priv);
336 spin_unlock_irqrestore(&msm_iommu_lock, flags);
339 static int msm_iommu_domain_config(struct msm_priv *priv)
341 spin_lock_init(&priv->pgtlock);
343 priv->cfg = (struct io_pgtable_cfg) {
344 .quirks = IO_PGTABLE_QUIRK_TLBI_ON_MAP,
345 .pgsize_bitmap = msm_iommu_ops.pgsize_bitmap,
346 .ias = 32,
347 .oas = 32,
348 .tlb = &msm_iommu_gather_ops,
349 .iommu_dev = priv->dev,
352 priv->iop = alloc_io_pgtable_ops(ARM_V7S, &priv->cfg, priv);
353 if (!priv->iop) {
354 dev_err(priv->dev, "Failed to allocate pgtable\n");
355 return -EINVAL;
358 msm_iommu_ops.pgsize_bitmap = priv->cfg.pgsize_bitmap;
360 return 0;
363 /* Must be called under msm_iommu_lock */
364 static struct msm_iommu_dev *find_iommu_for_dev(struct device *dev)
366 struct msm_iommu_dev *iommu, *ret = NULL;
367 struct msm_iommu_ctx_dev *master;
369 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
370 master = list_first_entry(&iommu->ctx_list,
371 struct msm_iommu_ctx_dev,
372 list);
373 if (master->of_node == dev->of_node) {
374 ret = iommu;
375 break;
379 return ret;
382 static int msm_iommu_add_device(struct device *dev)
384 struct msm_iommu_dev *iommu;
385 struct iommu_group *group;
386 unsigned long flags;
388 spin_lock_irqsave(&msm_iommu_lock, flags);
389 iommu = find_iommu_for_dev(dev);
390 spin_unlock_irqrestore(&msm_iommu_lock, flags);
392 if (iommu)
393 iommu_device_link(&iommu->iommu, dev);
394 else
395 return -ENODEV;
397 group = iommu_group_get_for_dev(dev);
398 if (IS_ERR(group))
399 return PTR_ERR(group);
401 iommu_group_put(group);
403 return 0;
406 static void msm_iommu_remove_device(struct device *dev)
408 struct msm_iommu_dev *iommu;
409 unsigned long flags;
411 spin_lock_irqsave(&msm_iommu_lock, flags);
412 iommu = find_iommu_for_dev(dev);
413 spin_unlock_irqrestore(&msm_iommu_lock, flags);
415 if (iommu)
416 iommu_device_unlink(&iommu->iommu, dev);
418 iommu_group_remove_device(dev);
421 static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
423 int ret = 0;
424 unsigned long flags;
425 struct msm_iommu_dev *iommu;
426 struct msm_priv *priv = to_msm_priv(domain);
427 struct msm_iommu_ctx_dev *master;
429 priv->dev = dev;
430 msm_iommu_domain_config(priv);
432 spin_lock_irqsave(&msm_iommu_lock, flags);
433 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
434 master = list_first_entry(&iommu->ctx_list,
435 struct msm_iommu_ctx_dev,
436 list);
437 if (master->of_node == dev->of_node) {
438 ret = __enable_clocks(iommu);
439 if (ret)
440 goto fail;
442 list_for_each_entry(master, &iommu->ctx_list, list) {
443 if (master->num) {
444 dev_err(dev, "domain already attached");
445 ret = -EEXIST;
446 goto fail;
448 master->num =
449 msm_iommu_alloc_ctx(iommu->context_map,
450 0, iommu->ncb);
451 if (IS_ERR_VALUE(master->num)) {
452 ret = -ENODEV;
453 goto fail;
455 config_mids(iommu, master);
456 __program_context(iommu->base, master->num,
457 priv);
459 __disable_clocks(iommu);
460 list_add(&iommu->dom_node, &priv->list_attached);
464 fail:
465 spin_unlock_irqrestore(&msm_iommu_lock, flags);
467 return ret;
470 static void msm_iommu_detach_dev(struct iommu_domain *domain,
471 struct device *dev)
473 struct msm_priv *priv = to_msm_priv(domain);
474 unsigned long flags;
475 struct msm_iommu_dev *iommu;
476 struct msm_iommu_ctx_dev *master;
477 int ret;
479 free_io_pgtable_ops(priv->iop);
481 spin_lock_irqsave(&msm_iommu_lock, flags);
482 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
483 ret = __enable_clocks(iommu);
484 if (ret)
485 goto fail;
487 list_for_each_entry(master, &iommu->ctx_list, list) {
488 msm_iommu_free_ctx(iommu->context_map, master->num);
489 __reset_context(iommu->base, master->num);
491 __disable_clocks(iommu);
493 fail:
494 spin_unlock_irqrestore(&msm_iommu_lock, flags);
497 static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova,
498 phys_addr_t pa, size_t len, int prot)
500 struct msm_priv *priv = to_msm_priv(domain);
501 unsigned long flags;
502 int ret;
504 spin_lock_irqsave(&priv->pgtlock, flags);
505 ret = priv->iop->map(priv->iop, iova, pa, len, prot);
506 spin_unlock_irqrestore(&priv->pgtlock, flags);
508 return ret;
511 static size_t msm_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
512 size_t len)
514 struct msm_priv *priv = to_msm_priv(domain);
515 unsigned long flags;
517 spin_lock_irqsave(&priv->pgtlock, flags);
518 len = priv->iop->unmap(priv->iop, iova, len);
519 spin_unlock_irqrestore(&priv->pgtlock, flags);
521 return len;
524 static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
525 dma_addr_t va)
527 struct msm_priv *priv;
528 struct msm_iommu_dev *iommu;
529 struct msm_iommu_ctx_dev *master;
530 unsigned int par;
531 unsigned long flags;
532 phys_addr_t ret = 0;
534 spin_lock_irqsave(&msm_iommu_lock, flags);
536 priv = to_msm_priv(domain);
537 iommu = list_first_entry(&priv->list_attached,
538 struct msm_iommu_dev, dom_node);
540 if (list_empty(&iommu->ctx_list))
541 goto fail;
543 master = list_first_entry(&iommu->ctx_list,
544 struct msm_iommu_ctx_dev, list);
545 if (!master)
546 goto fail;
548 ret = __enable_clocks(iommu);
549 if (ret)
550 goto fail;
552 /* Invalidate context TLB */
553 SET_CTX_TLBIALL(iommu->base, master->num, 0);
554 SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);
556 par = GET_PAR(iommu->base, master->num);
558 /* We are dealing with a supersection */
559 if (GET_NOFAULT_SS(iommu->base, master->num))
560 ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
561 else /* Upper 20 bits from PAR, lower 12 from VA */
562 ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
564 if (GET_FAULT(iommu->base, master->num))
565 ret = 0;
567 __disable_clocks(iommu);
568 fail:
569 spin_unlock_irqrestore(&msm_iommu_lock, flags);
570 return ret;
573 static bool msm_iommu_capable(enum iommu_cap cap)
575 return false;
578 static void print_ctx_regs(void __iomem *base, int ctx)
580 unsigned int fsr = GET_FSR(base, ctx);
581 pr_err("FAR = %08x PAR = %08x\n",
582 GET_FAR(base, ctx), GET_PAR(base, ctx));
583 pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
584 (fsr & 0x02) ? "TF " : "",
585 (fsr & 0x04) ? "AFF " : "",
586 (fsr & 0x08) ? "APF " : "",
587 (fsr & 0x10) ? "TLBMF " : "",
588 (fsr & 0x20) ? "HTWDEEF " : "",
589 (fsr & 0x40) ? "HTWSEEF " : "",
590 (fsr & 0x80) ? "MHF " : "",
591 (fsr & 0x10000) ? "SL " : "",
592 (fsr & 0x40000000) ? "SS " : "",
593 (fsr & 0x80000000) ? "MULTI " : "");
595 pr_err("FSYNR0 = %08x FSYNR1 = %08x\n",
596 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
597 pr_err("TTBR0 = %08x TTBR1 = %08x\n",
598 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
599 pr_err("SCTLR = %08x ACTLR = %08x\n",
600 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
603 static void insert_iommu_master(struct device *dev,
604 struct msm_iommu_dev **iommu,
605 struct of_phandle_args *spec)
607 struct msm_iommu_ctx_dev *master = dev->archdata.iommu;
608 int sid;
610 if (list_empty(&(*iommu)->ctx_list)) {
611 master = kzalloc(sizeof(*master), GFP_ATOMIC);
612 master->of_node = dev->of_node;
613 list_add(&master->list, &(*iommu)->ctx_list);
614 dev->archdata.iommu = master;
617 for (sid = 0; sid < master->num_mids; sid++)
618 if (master->mids[sid] == spec->args[0]) {
619 dev_warn(dev, "Stream ID 0x%hx repeated; ignoring\n",
620 sid);
621 return;
624 master->mids[master->num_mids++] = spec->args[0];
627 static int qcom_iommu_of_xlate(struct device *dev,
628 struct of_phandle_args *spec)
630 struct msm_iommu_dev *iommu;
631 unsigned long flags;
632 int ret = 0;
634 spin_lock_irqsave(&msm_iommu_lock, flags);
635 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node)
636 if (iommu->dev->of_node == spec->np)
637 break;
639 if (!iommu || iommu->dev->of_node != spec->np) {
640 ret = -ENODEV;
641 goto fail;
644 insert_iommu_master(dev, &iommu, spec);
645 fail:
646 spin_unlock_irqrestore(&msm_iommu_lock, flags);
648 return ret;
651 irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
653 struct msm_iommu_dev *iommu = dev_id;
654 unsigned int fsr;
655 int i, ret;
657 spin_lock(&msm_iommu_lock);
659 if (!iommu) {
660 pr_err("Invalid device ID in context interrupt handler\n");
661 goto fail;
664 pr_err("Unexpected IOMMU page fault!\n");
665 pr_err("base = %08x\n", (unsigned int)iommu->base);
667 ret = __enable_clocks(iommu);
668 if (ret)
669 goto fail;
671 for (i = 0; i < iommu->ncb; i++) {
672 fsr = GET_FSR(iommu->base, i);
673 if (fsr) {
674 pr_err("Fault occurred in context %d.\n", i);
675 pr_err("Interesting registers:\n");
676 print_ctx_regs(iommu->base, i);
677 SET_FSR(iommu->base, i, 0x4000000F);
680 __disable_clocks(iommu);
681 fail:
682 spin_unlock(&msm_iommu_lock);
683 return 0;
686 static struct iommu_ops msm_iommu_ops = {
687 .capable = msm_iommu_capable,
688 .domain_alloc = msm_iommu_domain_alloc,
689 .domain_free = msm_iommu_domain_free,
690 .attach_dev = msm_iommu_attach_dev,
691 .detach_dev = msm_iommu_detach_dev,
692 .map = msm_iommu_map,
693 .unmap = msm_iommu_unmap,
694 .iova_to_phys = msm_iommu_iova_to_phys,
695 .add_device = msm_iommu_add_device,
696 .remove_device = msm_iommu_remove_device,
697 .device_group = generic_device_group,
698 .pgsize_bitmap = MSM_IOMMU_PGSIZES,
699 .of_xlate = qcom_iommu_of_xlate,
702 static int msm_iommu_probe(struct platform_device *pdev)
704 struct resource *r;
705 resource_size_t ioaddr;
706 struct msm_iommu_dev *iommu;
707 int ret, par, val;
709 iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);
710 if (!iommu)
711 return -ENODEV;
713 iommu->dev = &pdev->dev;
714 INIT_LIST_HEAD(&iommu->ctx_list);
716 iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk");
717 if (IS_ERR(iommu->pclk)) {
718 dev_err(iommu->dev, "could not get smmu_pclk\n");
719 return PTR_ERR(iommu->pclk);
722 ret = clk_prepare(iommu->pclk);
723 if (ret) {
724 dev_err(iommu->dev, "could not prepare smmu_pclk\n");
725 return ret;
728 iommu->clk = devm_clk_get(iommu->dev, "iommu_clk");
729 if (IS_ERR(iommu->clk)) {
730 dev_err(iommu->dev, "could not get iommu_clk\n");
731 clk_unprepare(iommu->pclk);
732 return PTR_ERR(iommu->clk);
735 ret = clk_prepare(iommu->clk);
736 if (ret) {
737 dev_err(iommu->dev, "could not prepare iommu_clk\n");
738 clk_unprepare(iommu->pclk);
739 return ret;
742 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
743 iommu->base = devm_ioremap_resource(iommu->dev, r);
744 if (IS_ERR(iommu->base)) {
745 dev_err(iommu->dev, "could not get iommu base\n");
746 ret = PTR_ERR(iommu->base);
747 goto fail;
749 ioaddr = r->start;
751 iommu->irq = platform_get_irq(pdev, 0);
752 if (iommu->irq < 0) {
753 dev_err(iommu->dev, "could not get iommu irq\n");
754 ret = -ENODEV;
755 goto fail;
758 ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val);
759 if (ret) {
760 dev_err(iommu->dev, "could not get ncb\n");
761 goto fail;
763 iommu->ncb = val;
765 msm_iommu_reset(iommu->base, iommu->ncb);
766 SET_M(iommu->base, 0, 1);
767 SET_PAR(iommu->base, 0, 0);
768 SET_V2PCFG(iommu->base, 0, 1);
769 SET_V2PPR(iommu->base, 0, 0);
770 par = GET_PAR(iommu->base, 0);
771 SET_V2PCFG(iommu->base, 0, 0);
772 SET_M(iommu->base, 0, 0);
774 if (!par) {
775 pr_err("Invalid PAR value detected\n");
776 ret = -ENODEV;
777 goto fail;
780 ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL,
781 msm_iommu_fault_handler,
782 IRQF_ONESHOT | IRQF_SHARED,
783 "msm_iommu_secure_irpt_handler",
784 iommu);
785 if (ret) {
786 pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret);
787 goto fail;
790 list_add(&iommu->dev_node, &qcom_iommu_devices);
792 ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL,
793 "msm-smmu.%pa", &ioaddr);
794 if (ret) {
795 pr_err("Could not add msm-smmu at %pa to sysfs\n", &ioaddr);
796 goto fail;
799 iommu_device_set_ops(&iommu->iommu, &msm_iommu_ops);
800 iommu_device_set_fwnode(&iommu->iommu, &pdev->dev.of_node->fwnode);
802 ret = iommu_device_register(&iommu->iommu);
803 if (ret) {
804 pr_err("Could not register msm-smmu at %pa\n", &ioaddr);
805 goto fail;
808 bus_set_iommu(&platform_bus_type, &msm_iommu_ops);
810 pr_info("device mapped at %p, irq %d with %d ctx banks\n",
811 iommu->base, iommu->irq, iommu->ncb);
813 return ret;
814 fail:
815 clk_unprepare(iommu->clk);
816 clk_unprepare(iommu->pclk);
817 return ret;
820 static const struct of_device_id msm_iommu_dt_match[] = {
821 { .compatible = "qcom,apq8064-iommu" },
825 static int msm_iommu_remove(struct platform_device *pdev)
827 struct msm_iommu_dev *iommu = platform_get_drvdata(pdev);
829 clk_unprepare(iommu->clk);
830 clk_unprepare(iommu->pclk);
831 return 0;
834 static struct platform_driver msm_iommu_driver = {
835 .driver = {
836 .name = "msm_iommu",
837 .of_match_table = msm_iommu_dt_match,
839 .probe = msm_iommu_probe,
840 .remove = msm_iommu_remove,
843 static int __init msm_iommu_driver_init(void)
845 int ret;
847 ret = platform_driver_register(&msm_iommu_driver);
848 if (ret != 0)
849 pr_err("Failed to register IOMMU driver\n");
851 return ret;
853 subsys_initcall(msm_iommu_driver_init);