drivers/pinctrl/sh-pfc/pfc-r8a7794.c

   1 /*
   2  * r8a7794 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
   5  * Copyright (C) 2015 Renesas Solutions Corp.
   6  * Copyright (C) 2015-2016 Cogent Embedded, Inc., <source@cogentembedded.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2
  10  * as published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14
  15 #include "core.h"
  16 #include "sh_pfc.h"
  17
  18 #define CPU_ALL_PORT(fn, sfx)                                           \
  19         PORT_GP_32(0, fn, sfx),                                         \
  20         PORT_GP_26(1, fn, sfx),                                         \
  21         PORT_GP_32(2, fn, sfx),                                         \
  22         PORT_GP_32(3, fn, sfx),                                         \
  23         PORT_GP_32(4, fn, sfx),                                         \
  24         PORT_GP_28(5, fn, sfx),                                         \
  25         PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),          \
  26         PORT_GP_1(6, 24, fn, sfx),                                      \
  27         PORT_GP_1(6, 25, fn, sfx)
  28
  29 enum {
  30         PINMUX_RESERVED = 0,
  31
  32         PINMUX_DATA_BEGIN,
  33         GP_ALL(DATA),
  34         PINMUX_DATA_END,
  35
  36         PINMUX_FUNCTION_BEGIN,
  37         GP_ALL(FN),
  38
  39         /* GPSR0 */
  40         FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
  41         FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
  42         FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
  43         FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
  44         FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
  45         FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
  46         FN_IP2_17_16,
  47
  48         /* GPSR1 */
  49         FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
  50         FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
  51         FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
  52         FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
  53         FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
  54
  55         /* GPSR2 */
  56         FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
  57         FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
  58         FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
  59         FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
  60         FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
  61         FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
  62         FN_IP6_5_4, FN_IP6_7_6,
  63
  64         /* GPSR3 */
  65         FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
  66         FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
  67         FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
  68         FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
  69         FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
  70         FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
  71         FN_IP8_22_20,
  72
  73         /* GPSR4 */
  74         FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
  75         FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
  76         FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
  77         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
  78         FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
  79         FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
  80         FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
  81
  82         /* GPSR5 */
  83         FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
  84         FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
  85         FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
  86         FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
  87         FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
  88         FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
  89
  90         /* GPSR6 */
  91         FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
  92         FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
  93         FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
  94         FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
  95         FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
  96
  97         /* IPSR0 */
  98         FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
  99         FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
 100         FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
 101         FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
 102         FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
 103         FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
 104         FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
 105         FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
 106
 107         /* IPSR1 */
 108         FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, FN_D7, FN_IRQ3, FN_TCLK1,
 109         FN_PWM6_B, FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, FN_D9, FN_HSCIF2_HTX,
 110         FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6,
 111         FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
 112         FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13,
 113         FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD,
 114         FN_IIC0_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, FN_A0,
 115         FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK,
 116         FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
 117         FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
 118
 119         /* IPSR2 */
 120         FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, FN_A8, FN_MSIOF1_RXD,
 121         FN_SCIFA0_RXD_B, FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, FN_A10,
 122         FN_MSIOF1_SCK, FN_IIC1_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B,
 123         FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2,
 124         FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
 125         FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16,
 126         FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C,
 127         FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
 128         FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E,
 129         FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4,
 130         FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1,
 131
 132         /* IPSR3 */
 133         FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5,
 134         FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3,
 135         FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8,
 136         FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N,
 137         FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0,
 138         FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD,
 139         FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
 140         FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N,
 141         FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK,
 142         FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E,
 143         FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
 144         FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B,
 145         FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N,
 146
 147         /* IPSR4 */
 148         FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0,
 149         FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0,
 150         FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1,
 151         FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19,
 152         FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5,
 153         FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6,
 154         FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8,
 155         FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9,
 156         FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10,
 157         FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4,
 158         FN_LCDOUT12, FN_CC50_STATE12,
 159
 160         /* IPSR5 */
 161         FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14,
 162         FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0,
 163         FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
 164         FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
 165         FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18,
 166         FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4,
 167         FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6,
 168         FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23,
 169         FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0,
 170         FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
 171         FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27,
 172
 173         /* IPSR6 */
 174         FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
 175         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
 176         FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
 177         FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
 178         FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
 179         FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
 180         FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
 181         FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
 182         FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
 183         FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
 184         FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
 185         FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
 186         FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
 187         FN_ADIDATA, FN_AD_DI,
 188
 189         /* IPSR7 */
 190         FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
 191         FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
 192         FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
 193         FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
 194         FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
 195         FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
 196         FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
 197         FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
 198         FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
 199         FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
 200         FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
 201         FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
 202         FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
 203
 204         /* IPSR8 */
 205         FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
 206         FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C,
 207         FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX,
 208         FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B,
 209         FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
 210         FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7,
 211         FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
 212         FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
 213         FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
 214         FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
 215         FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
 216         FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
 217         FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
 218         FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
 219         FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
 220
 221         /* IPSR9 */
 222         FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B,
 223         FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0,
 224         FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC,
 225         FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1,
 226         FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B,
 227         FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
 228         FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL,
 229         FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
 230         FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
 231         FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK,
 232         FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32,
 233         FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
 234         FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2,
 235         FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34,
 236
 237         /* IPSR10 */
 238         FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0,
 239         FN_CC50_STATE35, FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
 240         FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC1_SCL,
 241         FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2,
 242         FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
 243         FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1,
 244         FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4,
 245         FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
 246         FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
 247         FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
 248         FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD,
 249         FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
 250         FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6,
 251         FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA,
 252         FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9,
 253         FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
 254
 255         /* IPSR11 */
 256         FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
 257         FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
 258         FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
 259         FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
 260         FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
 261         FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
 262         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
 263         FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
 264         FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
 265         FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
 266         FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
 267         FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
 268         FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
 269         FN_ADICLK_B, FN_AD_CLK_B,
 270
 271         /* IPSR12 */
 272         FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
 273         FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B,
 274         FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3,
 275         FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C,
 276         FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4,
 277         FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT,
 278         FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B,
 279         FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1,
 280         FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
 281         FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B,
 282         FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH,
 283         FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1,
 284         FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,
 285         FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B,
 286
 287         /* IPSR13 */
 288         FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ,
 289         FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B,
 290         FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B,
 291         FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N,
 292         FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E,
 293         FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9,
 294         FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N,
 295         FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D,
 296         FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B,
 297         FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
 298         FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC,
 299         FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C,
 300         FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B,
 301         FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B,
 302         FN_FMIN_E, FN_RDS_DATA_D,
 303
 304         /* MOD_SEL */
 305         FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
 306         FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
 307         FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
 308         FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
 309         FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
 310         FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
 311         FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
 312         FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
 313         FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
 314         FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
 315         FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
 316         FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
 317         FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
 318         FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
 319
 320         /* MOD_SEL2 */
 321         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
 322         FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
 323         FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
 324         FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
 325         FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
 326         FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
 327         FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
 328         FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
 329         FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
 330         FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
 331         FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
 332         FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
 333         FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
 334         FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
 335         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
 336         FN_SEL_RDS_2, FN_SEL_RDS_3,
 337
 338         /* MOD_SEL3 */
 339         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 340         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
 341         FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
 342         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 343         FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
 344         FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
 345         FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
 346         FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
 347         FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
 348         FN_SEL_SSI9_1,
 349         PINMUX_FUNCTION_END,
 350
 351         PINMUX_MARK_BEGIN,
 352         A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
 353
 354         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 355
 356         SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
 357         SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
 358
 359         SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
 360         SD1_DATA2_MARK, SD1_DATA3_MARK,
 361
 362         /* IPSR0 */
 363         SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
 364         MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
 365         SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
 366         SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
 367         MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
 368         CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
 369         CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
 370         SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
 371         SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
 372         SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
 373
 374         /* IPSR1 */
 375         D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, D7_MARK, IRQ3_MARK,
 376         TCLK1_MARK, PWM6_B_MARK, D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
 377         D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, D10_MARK,
 378         HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
 379         D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
 380         D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
 381         D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK,
 382         D14_MARK, SCIFA1_RXD_MARK, IIC0_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK,
 383         IIC0_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK,
 384         SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK,
 385         A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, A6_MARK,
 386         SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
 387
 388         /* IPSR2 */
 389         A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, A8_MARK, MSIOF1_RXD_MARK,
 390         SCIFA0_RXD_B_MARK, A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
 391         A10_MARK, MSIOF1_SCK_MARK, IIC1_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK,
 392         IIC1_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
 393         A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK,
 394         HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK,
 395         HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK,
 396         HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK,
 397         TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK,
 398         CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK,
 399         SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK,
 400         MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK,
 401         SPCLK_MARK, MOUT1_MARK,
 402
 403         /* IPSR3 */
 404         A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK,
 405         MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK,
 406         ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK,
 407         ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK,
 408         VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK,
 409         TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK,
 410         PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK,
 411         TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK,
 412         SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK,
 413         BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK,
 414         SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK,
 415         FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK,
 416         SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK,
 417         FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK,
 418         PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK,
 419         ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK,
 420
 421         /* IPSR4 */
 422         EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK,
 423         DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
 424         CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK,
 425         I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK,
 426         CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK,
 427         DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK,
 428         LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK,
 429         CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK,
 430         DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
 431         CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK,
 432         I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK,
 433         CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK,
 434         DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK,
 435
 436         /* IPSR5 */
 437         DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK,
 438         LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK,
 439         CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK,
 440         I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK,
 441         LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK,
 442         CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK,
 443         DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK,
 444         LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK,
 445         CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK,
 446         DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK,
 447         QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK,
 448         QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
 449         CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
 450         CC50_STATE27_MARK,
 451
 452         /* IPSR6 */
 453         DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
 454         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
 455         DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
 456         CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
 457         AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
 458         VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
 459         AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
 460         VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
 461         AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
 462         I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
 463         VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
 464         AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
 465         IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
 466         I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
 467         VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
 468         ADIDATA_MARK, AD_DI_MARK,
 469
 470         /* IPSR7 */
 471         ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
 472         AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
 473         MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
 474         AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
 475         CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
 476         ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
 477         AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
 478         MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
 479         ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
 480         SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
 481         IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
 482         VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK,
 483         SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
 484         AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
 485         SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
 486         DREQ0_N_MARK, SCIFB1_RXD_MARK,
 487
 488         /* IPSR8 */
 489         ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
 490         AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
 491         I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
 492         HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
 493         AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
 494         SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
 495         HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
 496         AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
 497         HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
 498         I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
 499         AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
 500         SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
 501         CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
 502         DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
 503         I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
 504         TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
 505         I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
 506         FMCLK_C_MARK, RDS_CLK_MARK,
 507
 508         /* IPSR9 */
 509         MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
 510         RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK,
 511         MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK,
 512         TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK,
 513         RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK,
 514         TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK,
 515         MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
 516         RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK,
 517         I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK,
 518         I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK,
 519         PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK,
 520         VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK,
 521         DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK,
 522         CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK,
 523         DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK,
 524         SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
 525         CAN_TXCLK_MARK, CC50_STATE34_MARK,
 526
 527         /* IPSR10 */
 528         SCIF1_RXD_MARK, IIC0_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
 529         CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, IIC0_SDA_MARK,
 530         DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK,
 531         SCIF2_RXD_MARK, IIC1_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
 532         USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK,
 533         IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK,
 534         CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK,
 535         DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK,
 536         CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK,
 537         DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK,
 538         CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK,
 539         DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK,
 540         RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK,
 541         DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK,
 542         RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK,
 543         AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK,
 544         SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK,
 545         SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK,
 546
 547         /* IPSR11 */
 548         SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
 549         CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
 550         DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
 551         SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
 552         SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
 553         DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
 554         SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
 555         CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
 556         DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
 557         DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
 558         AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
 559         MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
 560         PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
 561         ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
 562         PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
 563
 564         /* IPSR12 */
 565         SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
 566         AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK,
 567         SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK,
 568         SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
 569         CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
 570         IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK,
 571         SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK,
 572         SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
 573         DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK,
 574         IIC1_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK,
 575         ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK,
 576         VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK,
 577         SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK,
 578         ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,
 579         VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK,
 580
 581         /* IPSR13 */
 582         SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
 583         SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK,
 584         HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK,
 585         ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK,
 586         PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK,
 587         ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK,
 588         VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK,
 589         SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK,
 590         ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK,
 591         VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK,
 592         AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
 593         TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
 594         AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
 595         TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK,
 596         AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
 597         TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK,
 598         PINMUX_MARK_END,
 599 };
 600
 601 static const u16 pinmux_data[] = {
 602         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 603
 604         PINMUX_SINGLE(A2),
 605         PINMUX_SINGLE(WE0_N),
 606         PINMUX_SINGLE(WE1_N),
 607         PINMUX_SINGLE(DACK0),
 608         PINMUX_SINGLE(USB0_PWEN),
 609         PINMUX_SINGLE(USB0_OVC),
 610         PINMUX_SINGLE(USB1_PWEN),
 611         PINMUX_SINGLE(USB1_OVC),
 612         PINMUX_SINGLE(SD0_CLK),
 613         PINMUX_SINGLE(SD0_CMD),
 614         PINMUX_SINGLE(SD0_DATA0),
 615         PINMUX_SINGLE(SD0_DATA1),
 616         PINMUX_SINGLE(SD0_DATA2),
 617         PINMUX_SINGLE(SD0_DATA3),
 618         PINMUX_SINGLE(SD0_CD),
 619         PINMUX_SINGLE(SD0_WP),
 620         PINMUX_SINGLE(SD1_CLK),
 621         PINMUX_SINGLE(SD1_CMD),
 622         PINMUX_SINGLE(SD1_DATA0),
 623         PINMUX_SINGLE(SD1_DATA1),
 624         PINMUX_SINGLE(SD1_DATA2),
 625         PINMUX_SINGLE(SD1_DATA3),
 626
 627         /* IPSR0 */
 628         PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
 629         PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
 630         PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
 631         PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
 632         PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
 633         PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
 634         PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
 635         PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
 636         PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
 637         PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
 638         PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
 639         PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
 640         PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
 641         PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
 642         PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
 643         PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
 644         PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
 645         PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
 646         PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
 647         PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
 648         PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
 649         PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
 650         PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
 651         PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
 652         PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
 653         PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
 654         PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
 655         PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
 656         PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
 657         PINMUX_IPSR_GPSR(IP0_23_22, D0),
 658         PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
 659         PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
 660         PINMUX_IPSR_GPSR(IP0_24, D1),
 661         PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
 662         PINMUX_IPSR_GPSR(IP0_25, D2),
 663         PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
 664         PINMUX_IPSR_GPSR(IP0_27_26, D3),
 665         PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
 666         PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
 667         PINMUX_IPSR_GPSR(IP0_29_28, D4),
 668         PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
 669         PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
 670         PINMUX_IPSR_GPSR(IP0_31_30, D5),
 671         PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
 672         PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
 673
 674         /* IPSR1 */
 675         PINMUX_IPSR_GPSR(IP1_1_0, D6),
 676         PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
 677         PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
 678         PINMUX_IPSR_GPSR(IP1_3_2, D7),
 679         PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
 680         PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
 681         PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
 682         PINMUX_IPSR_GPSR(IP1_5_4, D8),
 683         PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
 684         PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
 685         PINMUX_IPSR_GPSR(IP1_7_6, D9),
 686         PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
 687         PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
 688         PINMUX_IPSR_GPSR(IP1_10_8, D10),
 689         PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
 690         PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
 691         PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
 692         PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
 693         PINMUX_IPSR_GPSR(IP1_12_11, D11),
 694         PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
 695         PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
 696         PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
 697         PINMUX_IPSR_GPSR(IP1_14_13, D12),
 698         PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
 699         PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
 700         PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
 701         PINMUX_IPSR_GPSR(IP1_17_15, D13),
 702         PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
 703         PINMUX_IPSR_GPSR(IP1_17_15, TANS1),
 704         PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
 705         PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
 706         PINMUX_IPSR_GPSR(IP1_19_18, D14),
 707         PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
 708         PINMUX_IPSR_MSEL(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1),
 709         PINMUX_IPSR_GPSR(IP1_21_20, D15),
 710         PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
 711         PINMUX_IPSR_MSEL(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1),
 712         PINMUX_IPSR_GPSR(IP1_23_22, A0),
 713         PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
 714         PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
 715         PINMUX_IPSR_GPSR(IP1_24, A1),
 716         PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
 717         PINMUX_IPSR_GPSR(IP1_26, A3),
 718         PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
 719         PINMUX_IPSR_GPSR(IP1_27, A4),
 720         PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
 721         PINMUX_IPSR_GPSR(IP1_29_28, A5),
 722         PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
 723         PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
 724         PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
 725         PINMUX_IPSR_GPSR(IP1_31_30, A6),
 726         PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
 727         PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
 728         PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
 729
 730         /* IPSR2 */
 731         PINMUX_IPSR_GPSR(IP2_1_0, A7),
 732         PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
 733         PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
 734         PINMUX_IPSR_GPSR(IP2_3_2, A8),
 735         PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
 736         PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
 737         PINMUX_IPSR_GPSR(IP2_5_4, A9),
 738         PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
 739         PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
 740         PINMUX_IPSR_GPSR(IP2_7_6, A10),
 741         PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
 742         PINMUX_IPSR_MSEL(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1),
 743         PINMUX_IPSR_GPSR(IP2_9_8, A11),
 744         PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
 745         PINMUX_IPSR_MSEL(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1),
 746         PINMUX_IPSR_GPSR(IP2_11_10, A12),
 747         PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
 748         PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
 749         PINMUX_IPSR_GPSR(IP2_13_12, A13),
 750         PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
 751         PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
 752         PINMUX_IPSR_GPSR(IP2_15_14, A14),
 753         PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
 754         PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
 755         PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
 756         PINMUX_IPSR_GPSR(IP2_17_16, A15),
 757         PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
 758         PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
 759         PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
 760         PINMUX_IPSR_GPSR(IP2_20_18, A16),
 761         PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
 762         PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
 763         PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
 764         PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0),
 765         PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
 766         PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
 767         PINMUX_IPSR_GPSR(IP2_23_21, A17),
 768         PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
 769         PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
 770         PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
 771         PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
 772         PINMUX_IPSR_GPSR(IP2_26_24, A18),
 773         PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
 774         PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
 775         PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
 776         PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1),
 777         PINMUX_IPSR_GPSR(IP2_29_27, A19),
 778         PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
 779         PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
 780         PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
 781         PINMUX_IPSR_GPSR(IP2_29_27, MOUT0),
 782         PINMUX_IPSR_GPSR(IP2_31_30, A20),
 783         PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
 784         PINMUX_IPSR_GPSR(IP2_29_27, MOUT1),
 785
 786         /* IPSR3 */
 787         PINMUX_IPSR_GPSR(IP3_1_0, A21),
 788         PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
 789         PINMUX_IPSR_GPSR(IP3_1_0, MOUT2),
 790         PINMUX_IPSR_GPSR(IP3_3_2, A22),
 791         PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
 792         PINMUX_IPSR_GPSR(IP3_3_2, MOUT5),
 793         PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
 794         PINMUX_IPSR_GPSR(IP3_5_4, A23),
 795         PINMUX_IPSR_GPSR(IP3_5_4, IO2),
 796         PINMUX_IPSR_GPSR(IP3_5_4, MOUT6),
 797         PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
 798         PINMUX_IPSR_GPSR(IP3_7_6, A24),
 799         PINMUX_IPSR_GPSR(IP3_7_6, IO3),
 800         PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
 801         PINMUX_IPSR_GPSR(IP3_9_8, A25),
 802         PINMUX_IPSR_GPSR(IP3_9_8, SSL),
 803         PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
 804         PINMUX_IPSR_GPSR(IP3_10, CS0_N),
 805         PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
 806         PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
 807         PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
 808         PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
 809         PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
 810         PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
 811         PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
 812         PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
 813         PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
 814         PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
 815         PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
 816         PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
 817         PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
 818         PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0),
 819         PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
 820         PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
 821         PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1),
 822         PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
 823         PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
 824         PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
 825         PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
 826         PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0),
 827         PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
 828         PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
 829         PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1),
 830         PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
 831         PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
 832         PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
 833         PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
 834         PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0),
 835         PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
 836         PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
 837         PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1),
 838         PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
 839         PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
 840         PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
 841         PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
 842         PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0),
 843         PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
 844         PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
 845         PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1),
 846         PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
 847         PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
 848         PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
 849         PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
 850         PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
 851         PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1),
 852         PINMUX_IPSR_GPSR(IP3_30, RD_N),
 853         PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
 854         PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
 855         PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
 856
 857         /* IPSR4 */
 858         PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
 859         PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
 860         PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
 861         PINMUX_IPSR_GPSR(IP4_1_0, PWMFSW0),
 862         PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
 863         PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
 864         PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
 865         PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
 866         PINMUX_IPSR_GPSR(IP4_4_2, CC50_STATE0),
 867         PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
 868         PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
 869         PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
 870         PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
 871         PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE1),
 872         PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
 873         PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
 874         PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE2),
 875         PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
 876         PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
 877         PINMUX_IPSR_GPSR(IP4_11_10, CC50_STATE3),
 878         PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
 879         PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
 880         PINMUX_IPSR_GPSR(IP4_13_12, CC50_STATE4),
 881         PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
 882         PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
 883         PINMUX_IPSR_GPSR(IP4_15_14, CC50_STATE5),
 884         PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
 885         PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
 886         PINMUX_IPSR_GPSR(IP4_17_16, CC50_STATE6),
 887         PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
 888         PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
 889         PINMUX_IPSR_GPSR(IP4_19_18, CC50_STATE7),
 890         PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
 891         PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
 892         PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
 893         PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
 894         PINMUX_IPSR_GPSR(IP4_22_20, CC50_STATE8),
 895         PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
 896         PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
 897         PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
 898         PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
 899         PINMUX_IPSR_GPSR(IP4_25_23, CC50_STATE9),
 900         PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
 901         PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
 902         PINMUX_IPSR_GPSR(IP4_27_26, CC50_STATE10),
 903         PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
 904         PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
 905         PINMUX_IPSR_GPSR(IP4_29_28, CC50_STATE11),
 906         PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
 907         PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
 908         PINMUX_IPSR_GPSR(IP4_31_30, CC50_STATE12),
 909
 910         /* IPSR5 */
 911         PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
 912         PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
 913         PINMUX_IPSR_GPSR(IP5_1_0, CC50_STATE13),
 914         PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
 915         PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
 916         PINMUX_IPSR_GPSR(IP5_3_2, CC50_STATE14),
 917         PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
 918         PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
 919         PINMUX_IPSR_GPSR(IP5_5_4, CC50_STATE15),
 920         PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
 921         PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
 922         PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
 923         PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
 924         PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
 925         PINMUX_IPSR_GPSR(IP5_8_6, CC50_STATE16),
 926         PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
 927         PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
 928         PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
 929         PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
 930         PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
 931         PINMUX_IPSR_GPSR(IP5_11_9, CC50_STATE17),
 932         PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
 933         PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
 934         PINMUX_IPSR_GPSR(IP5_13_12, CC50_STATE18),
 935         PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
 936         PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
 937         PINMUX_IPSR_GPSR(IP5_15_14, CC50_STATE19),
 938         PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
 939         PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
 940         PINMUX_IPSR_GPSR(IP5_17_16, CC50_STATE20),
 941         PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
 942         PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
 943         PINMUX_IPSR_GPSR(IP5_19_18, CC50_STATE21),
 944         PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
 945         PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
 946         PINMUX_IPSR_GPSR(IP5_21_20, CC50_STATE22),
 947         PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
 948         PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
 949         PINMUX_IPSR_GPSR(IP5_23_22, CC50_STATE23),
 950         PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
 951         PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
 952         PINMUX_IPSR_GPSR(IP5_25_24, CC50_STATE24),
 953         PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
 954         PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
 955         PINMUX_IPSR_GPSR(IP5_27_26, CC50_STATE25),
 956         PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
 957         PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
 958         PINMUX_IPSR_GPSR(IP5_29_28, CC50_STATE26),
 959         PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
 960         PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
 961         PINMUX_IPSR_GPSR(IP5_31_30, CC50_STATE27),
 962
 963         /* IPSR6 */
 964         PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
 965         PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
 966         PINMUX_IPSR_GPSR(IP6_1_0, CC50_STATE28),
 967         PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 968         PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
 969         PINMUX_IPSR_GPSR(IP6_3_2, CC50_STATE29),
 970         PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
 971         PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
 972         PINMUX_IPSR_GPSR(IP6_5_4, CC50_STATE30),
 973         PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
 974         PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
 975         PINMUX_IPSR_GPSR(IP6_7_6, CC50_STATE31),
 976         PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
 977         PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
 978         PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
 979         PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
 980         PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
 981         PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
 982         PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
 983         PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
 984         PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
 985         PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
 986         PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
 987         PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
 988         PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
 989         PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
 990         PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
 991         PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
 992         PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
 993         PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
 994         PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
 995         PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
 996         PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
 997         PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
 998         PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
 999         PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
1000         PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
1001         PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
1002         PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
1003         PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
1004         PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
1005         PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
1006         PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
1007         PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
1008         PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
1009         PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
1010         PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
1011         PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
1012         PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
1013         PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
1014         PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
1015         PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
1016         PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
1017         PINMUX_IPSR_MSEL(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
1018         PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
1019         PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
1020         PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0),
1021
1022         /* IPSR7 */
1023         PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
1024         PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
1025         PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
1026         PINMUX_IPSR_MSEL(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
1027         PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
1028         PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
1029         PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0),
1030         PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
1031         PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
1032         PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
1033         PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
1034         PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
1035         PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
1036         PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0),
1037         PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
1038         PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
1039         PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
1040         PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
1041         PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
1042         PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
1043         PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0),
1044         PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
1045         PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
1046         PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
1047         PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
1048         PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
1049         PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
1050         PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
1051         PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
1052         PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
1053         PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
1054         PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
1055         PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
1056         PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
1057         PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
1058         PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
1059         PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
1060         PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
1061         PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
1062         PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
1063         PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
1064         PINMUX_IPSR_MSEL(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
1065         PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
1066         PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
1067         PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
1068         PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
1069         PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
1070         PINMUX_IPSR_MSEL(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
1071         PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
1072         PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
1073         PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
1074         PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
1075         PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
1076         PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
1077         PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
1078         PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
1079         PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
1080         PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
1081         PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
1082         PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
1083         PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
1084         PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
1085         PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
1086
1087         /* IPSR8 */
1088         PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
1089         PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
1090         PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
1091         PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
1092         PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
1093         PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
1094         PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
1095         PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
1096         PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
1097         PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
1098         PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
1099         PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
1100         PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
1101         PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
1102         PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
1103         PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1104         PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
1105         PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
1106         PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
1107         PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
1108         PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
1109         PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
1110         PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
1111         PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
1112         PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
1113         PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
1114         PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
1115         PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
1116         PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
1117         PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
1118         PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
1119         PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
1120         PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
1121         PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
1122         PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
1123         PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
1124         PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
1125         PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
1126         PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
1127         PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
1128         PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
1129         PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
1130         PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
1131         PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
1132         PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
1133         PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
1134         PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
1135         PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
1136         PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
1137         PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
1138         PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
1139         PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
1140         PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
1141         PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
1142         PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
1143         PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
1144         PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
1145         PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
1146         PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
1147         PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
1148         PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
1149         PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
1150         PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
1151         PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
1152         PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
1153         PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
1154         PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
1155         PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
1156         PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0),
1157
1158         /* IPSR9 */
1159         PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
1160         PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
1161         PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
1162         PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
1163         PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1),
1164         PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
1165         PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
1166         PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0),
1167         PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
1168         PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
1169         PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
1170         PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
1171         PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0),
1172         PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
1173         PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
1174         PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
1175         PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
1176         PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
1177         PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0),
1178         PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
1179         PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
1180         PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
1181         PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
1182         PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
1183         PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0),
1184         PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
1185         PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1),
1186         PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
1187         PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
1188         PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
1189         PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
1190         PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0),
1191         PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
1192         PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1),
1193         PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
1194         PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
1195         PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
1196         PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
1197         PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
1198         PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
1199         PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
1200         PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
1201         PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
1202         PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
1203         PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
1204         PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
1205         PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
1206         PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
1207         PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1),
1208         PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
1209         PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
1210         PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
1211         PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
1212         PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
1213         PINMUX_IPSR_GPSR(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
1214         PINMUX_IPSR_GPSR(IP9_24_22, CC50_STATE32),
1215         PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
1216         PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
1217         PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
1218         PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
1219         PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
1220         PINMUX_IPSR_GPSR(IP9_27_25, CAN_STEP0),
1221         PINMUX_IPSR_GPSR(IP9_27_25, CC50_STATE33),
1222         PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
1223         PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
1224         PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
1225         PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
1226         PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
1227         PINMUX_IPSR_GPSR(IP9_30_28, CAN_TXCLK),
1228         PINMUX_IPSR_GPSR(IP9_30_28, CC50_STATE34),
1229
1230         /* IPSR10 */
1231         PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
1232         PINMUX_IPSR_MSEL(IP10_2_0, IIC0_SCL, SEL_IIC00_0),
1233         PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
1234         PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
1235         PINMUX_IPSR_GPSR(IP10_2_0, CAN_DEBUGOUT0),
1236         PINMUX_IPSR_GPSR(IP10_2_0, CC50_STATE35),
1237         PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
1238         PINMUX_IPSR_MSEL(IP10_5_3, IIC0_SDA, SEL_IIC00_0),
1239         PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
1240         PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
1241         PINMUX_IPSR_GPSR(IP10_5_3, CAN_DEBUGOUT1),
1242         PINMUX_IPSR_GPSR(IP10_5_3, CC50_STATE36),
1243         PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
1244         PINMUX_IPSR_MSEL(IP10_8_6, IIC1_SCL, SEL_IIC01_0),
1245         PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
1246         PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
1247         PINMUX_IPSR_GPSR(IP10_8_6, USB0_EXTLP),
1248         PINMUX_IPSR_GPSR(IP10_8_6, CAN_DEBUGOUT2),
1249         PINMUX_IPSR_GPSR(IP10_8_6, CC50_STATE37),
1250         PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
1251         PINMUX_IPSR_MSEL(IP10_11_9, IIC1_SDA, SEL_IIC01_0),
1252         PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
1253         PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
1254         PINMUX_IPSR_GPSR(IP10_11_9, USB0_OVC1),
1255         PINMUX_IPSR_GPSR(IP10_11_9, CAN_DEBUGOUT3),
1256         PINMUX_IPSR_GPSR(IP10_11_9, CC50_STATE38),
1257         PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
1258         PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
1259         PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
1260         PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
1261         PINMUX_IPSR_GPSR(IP10_14_12, USB0_IDIN),
1262         PINMUX_IPSR_GPSR(IP10_14_12, CAN_DEBUGOUT4),
1263         PINMUX_IPSR_GPSR(IP10_14_12, CC50_STATE39),
1264         PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
1265         PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
1266         PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
1267         PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
1268         PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
1269         PINMUX_IPSR_GPSR(IP10_17_15, TANS2),
1270         PINMUX_IPSR_GPSR(IP10_17_15, CAN_DEBUGOUT5),
1271         PINMUX_IPSR_GPSR(IP10_17_15, CC50_OSCOUT),
1272         PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
1273         PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
1274         PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
1275         PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
1276         PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
1277         PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
1278         PINMUX_IPSR_GPSR(IP10_20_18, CAN_DEBUGOUT6),
1279         PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2),
1280         PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
1281         PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
1282         PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
1283         PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
1284         PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
1285         PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
1286         PINMUX_IPSR_GPSR(IP10_23_21, CAN_DEBUGOUT7),
1287         PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2),
1288         PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
1289         PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
1290         PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
1291         PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
1292         PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
1293         PINMUX_IPSR_GPSR(IP10_26_24, CAN_DEBUGOUT8),
1294         PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
1295         PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
1296         PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
1297         PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
1298         PINMUX_IPSR_GPSR(IP10_29_27, CAN_DEBUGOUT9),
1299         PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
1300         PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
1301         PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
1302         PINMUX_IPSR_GPSR(IP10_31_30, CAN_DEBUGOUT10),
1303
1304         /* IPSR11 */
1305         PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
1306         PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1307         PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
1308         PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
1309         PINMUX_IPSR_GPSR(IP11_2_0, CAN_DEBUGOUT11),
1310         PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
1311         PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
1312         PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
1313         PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
1314         PINMUX_IPSR_GPSR(IP11_5_3, CAN_DEBUGOUT12),
1315         PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
1316         PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
1317         PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
1318         PINMUX_IPSR_GPSR(IP11_7_6, CAN_DEBUGOUT13),
1319         PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
1320         PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
1321         PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
1322         PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
1323         PINMUX_IPSR_GPSR(IP11_10_8, CAN_DEBUGOUT14),
1324         PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
1325         PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
1326         PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
1327         PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1328         PINMUX_IPSR_GPSR(IP11_13_11, CAN_DEBUGOUT15),
1329         PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
1330         PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
1331         PINMUX_IPSR_MSEL(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
1332         PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
1333         PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
1334         PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
1335         PINMUX_IPSR_MSEL(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
1336         PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
1337         PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
1338         PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
1339         PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
1340         PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
1341         PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
1342         PINMUX_IPSR_GPSR(IP11_20_18, PCMOE_N),
1343         PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
1344         PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
1345         PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
1346         PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
1347         PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1),
1348         PINMUX_IPSR_GPSR(IP11_23_21, PCMWE_N),
1349         PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
1350         PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
1351         PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
1352         PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
1353         PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1),
1354         PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
1355         PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
1356         PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
1357         PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
1358         PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1),
1359
1360         /* IPSR12 */
1361         PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
1362         PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
1363         PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
1364         PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
1365         PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1),
1366         PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
1367         PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
1368         PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
1369         PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
1370         PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
1371         PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
1372         PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
1373         PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
1374         PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
1375         PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
1376         PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
1377         PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
1378         PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
1379         PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
1380         PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
1381         PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
1382         PINMUX_IPSR_GPSR(IP12_10_9, IRD_TX),
1383         PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
1384         PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
1385         PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
1386         PINMUX_IPSR_GPSR(IP12_12_11, IRD_RX),
1387         PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
1388         PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
1389         PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
1390         PINMUX_IPSR_GPSR(IP12_14_13, IRD_SCK),
1391         PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
1392         PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
1393         PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
1394         PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
1395         PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
1396         PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
1397         PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
1398         PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
1399         PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
1400         PINMUX_IPSR_MSEL(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2),
1401         PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
1402         PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
1403         PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0),
1404         PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
1405         PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
1406         PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
1407         PINMUX_IPSR_MSEL(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2),
1408         PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
1409         PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
1410         PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0),
1411         PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
1412         PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
1413         PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
1414         PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
1415         PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0),
1416         PINMUX_IPSR_GPSR(IP12_26_24, ATAG0_N),
1417         PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
1418         PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
1419         PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
1420         PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
1421         PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0),
1422         PINMUX_IPSR_GPSR(IP12_29_27, ATAWR0_N),
1423         PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
1424
1425         /* IPSR13 */
1426         PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
1427         PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
1428         PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
1429         PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
1430         PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0),
1431         PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
1432         PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
1433         PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
1434         PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
1435         PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
1436         PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
1437         PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0),
1438         PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
1439         PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
1440         PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
1441         PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
1442         PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
1443         PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
1444         PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0),
1445         PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
1446         PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
1447         PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
1448         PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
1449         PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
1450         PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
1451         PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
1452         PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
1453         PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
1454         PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
1455         PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
1456         PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
1457         PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
1458         PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
1459         PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
1460         PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
1461         PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
1462         PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
1463         PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
1464         PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1),
1465         PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
1466         PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
1467         PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
1468         PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
1469         PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
1470         PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
1471         PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1),
1472         PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
1473         PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
1474         PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
1475         PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
1476         PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
1477         PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
1478         PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
1479         PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1),
1480         PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
1481         PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3),
1482         PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
1483         PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
1484         PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
1485         PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
1486         PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
1487         PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1),
1488         PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
1489         PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3),
1490 };
1491
1492 static const struct sh_pfc_pin pinmux_pins[] = {
1493         PINMUX_GPIO_GP_ALL(),
1494 };
1495
1496 /* - Audio Clock ------------------------------------------------------------ */
1497 static const unsigned int audio_clka_pins[] = {
1498         /* CLKA */
1499         RCAR_GP_PIN(5, 20),
1500 };
1501 static const unsigned int audio_clka_mux[] = {
1502         AUDIO_CLKA_MARK,
1503 };
1504 static const unsigned int audio_clka_b_pins[] = {
1505         /* CLKA */
1506         RCAR_GP_PIN(3, 25),
1507 };
1508 static const unsigned int audio_clka_b_mux[] = {
1509         AUDIO_CLKA_B_MARK,
1510 };
1511 static const unsigned int audio_clka_c_pins[] = {
1512         /* CLKA */
1513         RCAR_GP_PIN(4, 20),
1514 };
1515 static const unsigned int audio_clka_c_mux[] = {
1516         AUDIO_CLKA_C_MARK,
1517 };
1518 static const unsigned int audio_clka_d_pins[] = {
1519         /* CLKA */
1520         RCAR_GP_PIN(5, 0),
1521 };
1522 static const unsigned int audio_clka_d_mux[] = {
1523         AUDIO_CLKA_D_MARK,
1524 };
1525 static const unsigned int audio_clkb_pins[] = {
1526         /* CLKB */
1527         RCAR_GP_PIN(5, 21),
1528 };
1529 static const unsigned int audio_clkb_mux[] = {
1530         AUDIO_CLKB_MARK,
1531 };
1532 static const unsigned int audio_clkb_b_pins[] = {
1533         /* CLKB */
1534         RCAR_GP_PIN(3, 26),
1535 };
1536 static const unsigned int audio_clkb_b_mux[] = {
1537         AUDIO_CLKB_B_MARK,
1538 };
1539 static const unsigned int audio_clkb_c_pins[] = {
1540         /* CLKB */
1541         RCAR_GP_PIN(4, 21),
1542 };
1543 static const unsigned int audio_clkb_c_mux[] = {
1544         AUDIO_CLKB_C_MARK,
1545 };
1546 static const unsigned int audio_clkc_pins[] = {
1547         /* CLKC */
1548         RCAR_GP_PIN(5, 22),
1549 };
1550 static const unsigned int audio_clkc_mux[] = {
1551         AUDIO_CLKC_MARK,
1552 };
1553 static const unsigned int audio_clkc_b_pins[] = {
1554         /* CLKC */
1555         RCAR_GP_PIN(3, 29),
1556 };
1557 static const unsigned int audio_clkc_b_mux[] = {
1558         AUDIO_CLKC_B_MARK,
1559 };
1560 static const unsigned int audio_clkc_c_pins[] = {
1561         /* CLKC */
1562         RCAR_GP_PIN(4, 22),
1563 };
1564 static const unsigned int audio_clkc_c_mux[] = {
1565         AUDIO_CLKC_C_MARK,
1566 };
1567 static const unsigned int audio_clkout_pins[] = {
1568         /* CLKOUT */
1569         RCAR_GP_PIN(5, 23),
1570 };
1571 static const unsigned int audio_clkout_mux[] = {
1572         AUDIO_CLKOUT_MARK,
1573 };
1574 static const unsigned int audio_clkout_b_pins[] = {
1575         /* CLKOUT */
1576         RCAR_GP_PIN(3, 12),
1577 };
1578 static const unsigned int audio_clkout_b_mux[] = {
1579         AUDIO_CLKOUT_B_MARK,
1580 };
1581 static const unsigned int audio_clkout_c_pins[] = {
1582         /* CLKOUT */
1583         RCAR_GP_PIN(4, 23),
1584 };
1585 static const unsigned int audio_clkout_c_mux[] = {
1586         AUDIO_CLKOUT_C_MARK,
1587 };
1588 /* - AVB -------------------------------------------------------------------- */
1589 static const unsigned int avb_link_pins[] = {
1590         RCAR_GP_PIN(3, 26),
1591 };
1592 static const unsigned int avb_link_mux[] = {
1593         AVB_LINK_MARK,
1594 };
1595 static const unsigned int avb_magic_pins[] = {
1596         RCAR_GP_PIN(3, 27),
1597 };
1598 static const unsigned int avb_magic_mux[] = {
1599         AVB_MAGIC_MARK,
1600 };
1601 static const unsigned int avb_phy_int_pins[] = {
1602         RCAR_GP_PIN(3, 28),
1603 };
1604 static const unsigned int avb_phy_int_mux[] = {
1605         AVB_PHY_INT_MARK,
1606 };
1607 static const unsigned int avb_mdio_pins[] = {
1608         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
1609 };
1610 static const unsigned int avb_mdio_mux[] = {
1611         AVB_MDC_MARK, AVB_MDIO_MARK,
1612 };
1613 static const unsigned int avb_mii_pins[] = {
1614         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1615         RCAR_GP_PIN(3, 17),
1616
1617         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1618         RCAR_GP_PIN(3, 5),
1619
1620         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1621         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
1622         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
1623 };
1624 static const unsigned int avb_mii_mux[] = {
1625         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1626         AVB_TXD3_MARK,
1627
1628         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1629         AVB_RXD3_MARK,
1630
1631         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1632         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1633         AVB_TX_CLK_MARK, AVB_COL_MARK,
1634 };
1635 static const unsigned int avb_gmii_pins[] = {
1636         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1637         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1638         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1639
1640         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1641         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1642         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1643
1644         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1645         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
1646         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
1647         RCAR_GP_PIN(3, 11),
1648 };
1649 static const unsigned int avb_gmii_mux[] = {
1650         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1651         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1652         AVB_TXD6_MARK, AVB_TXD7_MARK,
1653
1654         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1655         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1656         AVB_RXD6_MARK, AVB_RXD7_MARK,
1657
1658         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1659         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1660         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1661         AVB_COL_MARK,
1662 };
1663 static const unsigned int avb_avtp_capture_pins[] = {
1664         RCAR_GP_PIN(5, 11),
1665 };
1666 static const unsigned int avb_avtp_capture_mux[] = {
1667         AVB_AVTP_CAPTURE_MARK,
1668 };
1669 static const unsigned int avb_avtp_match_pins[] = {
1670         RCAR_GP_PIN(5, 12),
1671 };
1672 static const unsigned int avb_avtp_match_mux[] = {
1673         AVB_AVTP_MATCH_MARK,
1674 };
1675 static const unsigned int avb_avtp_capture_b_pins[] = {
1676         RCAR_GP_PIN(1, 1),
1677 };
1678 static const unsigned int avb_avtp_capture_b_mux[] = {
1679         AVB_AVTP_CAPTURE_B_MARK,
1680 };
1681 static const unsigned int avb_avtp_match_b_pins[] = {
1682         RCAR_GP_PIN(1, 2),
1683 };
1684 static const unsigned int avb_avtp_match_b_mux[] = {
1685         AVB_AVTP_MATCH_B_MARK,
1686 };
1687 /* - DU --------------------------------------------------------------------- */
1688 static const unsigned int du0_rgb666_pins[] = {
1689         /* R[7:2], G[7:2], B[7:2] */
1690         RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
1691         RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
1692         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1693         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1694         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1695         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1696 };
1697 static const unsigned int du0_rgb666_mux[] = {
1698         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1699         DU0_DR3_MARK, DU0_DR2_MARK,
1700         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1701         DU0_DG3_MARK, DU0_DG2_MARK,
1702         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1703         DU0_DB3_MARK, DU0_DB2_MARK,
1704 };
1705 static const unsigned int du0_rgb888_pins[] = {
1706         /* R[7:0], G[7:0], B[7:0] */
1707         RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 5),
1708         RCAR_GP_PIN(2, 4),  RCAR_GP_PIN(2, 3),  RCAR_GP_PIN(2, 2),
1709         RCAR_GP_PIN(2, 1),  RCAR_GP_PIN(2, 0),
1710         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1711         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1712         RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 8),
1713         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1714         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1715         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1716 };
1717 static const unsigned int du0_rgb888_mux[] = {
1718         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1719         DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1720         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1721         DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1722         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1723         DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1724 };
1725 static const unsigned int du0_clk0_out_pins[] = {
1726         /* DOTCLKOUT0 */
1727         RCAR_GP_PIN(2, 25),
1728 };
1729 static const unsigned int du0_clk0_out_mux[] = {
1730         DU0_DOTCLKOUT0_MARK
1731 };
1732 static const unsigned int du0_clk1_out_pins[] = {
1733         /* DOTCLKOUT1 */
1734         RCAR_GP_PIN(2, 26),
1735 };
1736 static const unsigned int du0_clk1_out_mux[] = {
1737         DU0_DOTCLKOUT1_MARK
1738 };
1739 static const unsigned int du0_clk_in_pins[] = {
1740         /* CLKIN */
1741         RCAR_GP_PIN(2, 24),
1742 };
1743 static const unsigned int du0_clk_in_mux[] = {
1744         DU0_DOTCLKIN_MARK
1745 };
1746 static const unsigned int du0_sync_pins[] = {
1747         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1748         RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
1749 };
1750 static const unsigned int du0_sync_mux[] = {
1751         DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
1752 };
1753 static const unsigned int du0_oddf_pins[] = {
1754         /* EXODDF/ODDF/DISP/CDE */
1755         RCAR_GP_PIN(2, 29),
1756 };
1757 static const unsigned int du0_oddf_mux[] = {
1758         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
1759 };
1760 static const unsigned int du0_cde_pins[] = {
1761         /* CDE */
1762         RCAR_GP_PIN(2, 31),
1763 };
1764 static const unsigned int du0_cde_mux[] = {
1765         DU0_CDE_MARK,
1766 };
1767 static const unsigned int du0_disp_pins[] = {
1768         /* DISP */
1769         RCAR_GP_PIN(2, 30),
1770 };
1771 static const unsigned int du0_disp_mux[] = {
1772         DU0_DISP_MARK
1773 };
1774 static const unsigned int du1_rgb666_pins[] = {
1775         /* R[7:2], G[7:2], B[7:2] */
1776         RCAR_GP_PIN(4, 7),  RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),
1777         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 3),  RCAR_GP_PIN(4, 2),
1778         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1779         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1780         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
1781         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1782 };
1783 static const unsigned int du1_rgb666_mux[] = {
1784         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1785         DU1_DR3_MARK, DU1_DR2_MARK,
1786         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1787         DU1_DG3_MARK, DU1_DG2_MARK,
1788         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1789         DU1_DB3_MARK, DU1_DB2_MARK,
1790 };
1791 static const unsigned int du1_rgb888_pins[] = {
1792         /* R[7:0], G[7:0], B[7:0] */
1793         RCAR_GP_PIN(4, 7),  RCAR_GP_PIN(4, 6),  RCAR_GP_PIN(4, 5),
1794         RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 3),  RCAR_GP_PIN(4, 2),
1795         RCAR_GP_PIN(4, 1),  RCAR_GP_PIN(4, 0),
1796         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1797         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1798         RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 8),
1799         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
1800         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1801         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1802 };
1803 static const unsigned int du1_rgb888_mux[] = {
1804         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1805         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1806         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1807         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1808         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1809         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1810 };
1811 static const unsigned int du1_clk0_out_pins[] = {
1812         /* DOTCLKOUT0 */
1813         RCAR_GP_PIN(4, 25),
1814 };
1815 static const unsigned int du1_clk0_out_mux[] = {
1816         DU1_DOTCLKOUT0_MARK
1817 };
1818 static const unsigned int du1_clk1_out_pins[] = {
1819         /* DOTCLKOUT1 */
1820         RCAR_GP_PIN(4, 26),
1821 };
1822 static const unsigned int du1_clk1_out_mux[] = {
1823         DU1_DOTCLKOUT1_MARK
1824 };
1825 static const unsigned int du1_clk_in_pins[] = {
1826         /* DOTCLKIN */
1827         RCAR_GP_PIN(4, 24),
1828 };
1829 static const unsigned int du1_clk_in_mux[] = {
1830         DU1_DOTCLKIN_MARK
1831 };
1832 static const unsigned int du1_sync_pins[] = {
1833         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1834         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
1835 };
1836 static const unsigned int du1_sync_mux[] = {
1837         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1838 };
1839 static const unsigned int du1_oddf_pins[] = {
1840         /* EXODDF/ODDF/DISP/CDE */
1841         RCAR_GP_PIN(4, 29),
1842 };
1843 static const unsigned int du1_oddf_mux[] = {
1844         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1845 };
1846 static const unsigned int du1_cde_pins[] = {
1847         /* CDE */
1848         RCAR_GP_PIN(4, 31),
1849 };
1850 static const unsigned int du1_cde_mux[] = {
1851         DU1_CDE_MARK
1852 };
1853 static const unsigned int du1_disp_pins[] = {
1854         /* DISP */
1855         RCAR_GP_PIN(4, 30),
1856 };
1857 static const unsigned int du1_disp_mux[] = {
1858         DU1_DISP_MARK
1859 };
1860 /* - ETH -------------------------------------------------------------------- */
1861 static const unsigned int eth_link_pins[] = {
1862         /* LINK */
1863         RCAR_GP_PIN(3, 18),
1864 };
1865 static const unsigned int eth_link_mux[] = {
1866         ETH_LINK_MARK,
1867 };
1868 static const unsigned int eth_magic_pins[] = {
1869         /* MAGIC */
1870         RCAR_GP_PIN(3, 22),
1871 };
1872 static const unsigned int eth_magic_mux[] = {
1873         ETH_MAGIC_MARK,
1874 };
1875 static const unsigned int eth_mdio_pins[] = {
1876         /* MDC, MDIO */
1877         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
1878 };
1879 static const unsigned int eth_mdio_mux[] = {
1880         ETH_MDC_MARK, ETH_MDIO_MARK,
1881 };
1882 static const unsigned int eth_rmii_pins[] = {
1883         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1884         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
1885         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
1886         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
1887 };
1888 static const unsigned int eth_rmii_mux[] = {
1889         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1890         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1891 };
1892 static const unsigned int eth_link_b_pins[] = {
1893         /* LINK */
1894         RCAR_GP_PIN(5, 15),
1895 };
1896 static const unsigned int eth_link_b_mux[] = {
1897         ETH_LINK_B_MARK,
1898 };
1899 static const unsigned int eth_magic_b_pins[] = {
1900         /* MAGIC */
1901         RCAR_GP_PIN(5, 19),
1902 };
1903 static const unsigned int eth_magic_b_mux[] = {
1904         ETH_MAGIC_B_MARK,
1905 };
1906 static const unsigned int eth_mdio_b_pins[] = {
1907         /* MDC, MDIO */
1908         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
1909 };
1910 static const unsigned int eth_mdio_b_mux[] = {
1911         ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
1912 };
1913 static const unsigned int eth_rmii_b_pins[] = {
1914         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1915         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
1916         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
1917         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
1918 };
1919 static const unsigned int eth_rmii_b_mux[] = {
1920         ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
1921         ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
1922 };
1923 /* - HSCIF0 ----------------------------------------------------------------- */
1924 static const unsigned int hscif0_data_pins[] = {
1925         /* RX, TX */
1926         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1927 };
1928 static const unsigned int hscif0_data_mux[] = {
1929         HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
1930 };
1931 static const unsigned int hscif0_clk_pins[] = {
1932         /* SCK */
1933         RCAR_GP_PIN(3, 29),
1934 };
1935 static const unsigned int hscif0_clk_mux[] = {
1936         HSCIF0_HSCK_MARK,
1937 };
1938 static const unsigned int hscif0_ctrl_pins[] = {
1939         /* RTS, CTS */
1940         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1941 };
1942 static const unsigned int hscif0_ctrl_mux[] = {
1943         HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
1944 };
1945 static const unsigned int hscif0_data_b_pins[] = {
1946         /* RX, TX */
1947         RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
1948 };
1949 static const unsigned int hscif0_data_b_mux[] = {
1950         HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
1951 };
1952 static const unsigned int hscif0_clk_b_pins[] = {
1953         /* SCK */
1954         RCAR_GP_PIN(1, 0),
1955 };
1956 static const unsigned int hscif0_clk_b_mux[] = {
1957         HSCIF0_HSCK_B_MARK,
1958 };
1959 /* - HSCIF1 ----------------------------------------------------------------- */
1960 static const unsigned int hscif1_data_pins[] = {
1961         /* RX, TX */
1962         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1963 };
1964 static const unsigned int hscif1_data_mux[] = {
1965         HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
1966 };
1967 static const unsigned int hscif1_clk_pins[] = {
1968         /* SCK */
1969         RCAR_GP_PIN(4, 10),
1970 };
1971 static const unsigned int hscif1_clk_mux[] = {
1972         HSCIF1_HSCK_MARK,
1973 };
1974 static const unsigned int hscif1_ctrl_pins[] = {
1975         /* RTS, CTS */
1976         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
1977 };
1978 static const unsigned int hscif1_ctrl_mux[] = {
1979         HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
1980 };
1981 static const unsigned int hscif1_data_b_pins[] = {
1982         /* RX, TX */
1983         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1984 };
1985 static const unsigned int hscif1_data_b_mux[] = {
1986         HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
1987 };
1988 static const unsigned int hscif1_ctrl_b_pins[] = {
1989         /* RTS, CTS */
1990         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1991 };
1992 static const unsigned int hscif1_ctrl_b_mux[] = {
1993         HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
1994 };
1995 /* - HSCIF2 ----------------------------------------------------------------- */
1996 static const unsigned int hscif2_data_pins[] = {
1997         /* RX, TX */
1998         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1999 };
2000 static const unsigned int hscif2_data_mux[] = {
2001         HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
2002 };
2003 static const unsigned int hscif2_clk_pins[] = {
2004         /* SCK */
2005         RCAR_GP_PIN(0, 10),
2006 };
2007 static const unsigned int hscif2_clk_mux[] = {
2008         HSCIF2_HSCK_MARK,
2009 };
2010 static const unsigned int hscif2_ctrl_pins[] = {
2011         /* RTS, CTS */
2012         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2013 };
2014 static const unsigned int hscif2_ctrl_mux[] = {
2015         HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
2016 };
2017 /* - I2C0 ------------------------------------------------------------------- */
2018 static const unsigned int i2c0_pins[] = {
2019         /* SCL, SDA */
2020         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2021 };
2022 static const unsigned int i2c0_mux[] = {
2023         I2C0_SCL_MARK, I2C0_SDA_MARK,
2024 };
2025 static const unsigned int i2c0_b_pins[] = {
2026         /* SCL, SDA */
2027         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2028 };
2029 static const unsigned int i2c0_b_mux[] = {
2030         I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
2031 };
2032 static const unsigned int i2c0_c_pins[] = {
2033         /* SCL, SDA */
2034         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2035 };
2036 static const unsigned int i2c0_c_mux[] = {
2037         I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
2038 };
2039 static const unsigned int i2c0_d_pins[] = {
2040         /* SCL, SDA */
2041         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2042 };
2043 static const unsigned int i2c0_d_mux[] = {
2044         I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
2045 };
2046 static const unsigned int i2c0_e_pins[] = {
2047         /* SCL, SDA */
2048         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2049 };
2050 static const unsigned int i2c0_e_mux[] = {
2051         I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
2052 };
2053 /* - I2C1 ------------------------------------------------------------------- */
2054 static const unsigned int i2c1_pins[] = {
2055         /* SCL, SDA */
2056         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2057 };
2058 static const unsigned int i2c1_mux[] = {
2059         I2C1_SCL_MARK, I2C1_SDA_MARK,
2060 };
2061 static const unsigned int i2c1_b_pins[] = {
2062         /* SCL, SDA */
2063         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
2064 };
2065 static const unsigned int i2c1_b_mux[] = {
2066         I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2067 };
2068 static const unsigned int i2c1_c_pins[] = {
2069         /* SCL, SDA */
2070         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
2071 };
2072 static const unsigned int i2c1_c_mux[] = {
2073         I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2074 };
2075 static const unsigned int i2c1_d_pins[] = {
2076         /* SCL, SDA */
2077         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2078 };
2079 static const unsigned int i2c1_d_mux[] = {
2080         I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2081 };
2082 static const unsigned int i2c1_e_pins[] = {
2083         /* SCL, SDA */
2084         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2085 };
2086 static const unsigned int i2c1_e_mux[] = {
2087         I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2088 };
2089 /* - I2C2 ------------------------------------------------------------------- */
2090 static const unsigned int i2c2_pins[] = {
2091         /* SCL, SDA */
2092         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2093 };
2094 static const unsigned int i2c2_mux[] = {
2095         I2C2_SCL_MARK, I2C2_SDA_MARK,
2096 };
2097 static const unsigned int i2c2_b_pins[] = {
2098         /* SCL, SDA */
2099         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2100 };
2101 static const unsigned int i2c2_b_mux[] = {
2102         I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2103 };
2104 static const unsigned int i2c2_c_pins[] = {
2105         /* SCL, SDA */
2106         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2107 };
2108 static const unsigned int i2c2_c_mux[] = {
2109         I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2110 };
2111 static const unsigned int i2c2_d_pins[] = {
2112         /* SCL, SDA */
2113         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2114 };
2115 static const unsigned int i2c2_d_mux[] = {
2116         I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2117 };
2118 static const unsigned int i2c2_e_pins[] = {
2119         /* SCL, SDA */
2120         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2121 };
2122 static const unsigned int i2c2_e_mux[] = {
2123         I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2124 };
2125 /* - I2C3 ------------------------------------------------------------------- */
2126 static const unsigned int i2c3_pins[] = {
2127         /* SCL, SDA */
2128         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
2129 };
2130 static const unsigned int i2c3_mux[] = {
2131         I2C3_SCL_MARK, I2C3_SDA_MARK,
2132 };
2133 static const unsigned int i2c3_b_pins[] = {
2134         /* SCL, SDA */
2135         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2136 };
2137 static const unsigned int i2c3_b_mux[] = {
2138         I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2139 };
2140 static const unsigned int i2c3_c_pins[] = {
2141         /* SCL, SDA */
2142         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2143 };
2144 static const unsigned int i2c3_c_mux[] = {
2145         I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2146 };
2147 static const unsigned int i2c3_d_pins[] = {
2148         /* SCL, SDA */
2149         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2150 };
2151 static const unsigned int i2c3_d_mux[] = {
2152         I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2153 };
2154 static const unsigned int i2c3_e_pins[] = {
2155         /* SCL, SDA */
2156         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2157 };
2158 static const unsigned int i2c3_e_mux[] = {
2159         I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
2160 };
2161 /* - I2C4 ------------------------------------------------------------------- */
2162 static const unsigned int i2c4_pins[] = {
2163         /* SCL, SDA */
2164         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
2165 };
2166 static const unsigned int i2c4_mux[] = {
2167         I2C4_SCL_MARK, I2C4_SDA_MARK,
2168 };
2169 static const unsigned int i2c4_b_pins[] = {
2170         /* SCL, SDA */
2171         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2172 };
2173 static const unsigned int i2c4_b_mux[] = {
2174         I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2175 };
2176 static const unsigned int i2c4_c_pins[] = {
2177         /* SCL, SDA */
2178         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2179 };
2180 static const unsigned int i2c4_c_mux[] = {
2181         I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2182 };
2183 static const unsigned int i2c4_d_pins[] = {
2184         /* SCL, SDA */
2185         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2186 };
2187 static const unsigned int i2c4_d_mux[] = {
2188         I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
2189 };
2190 static const unsigned int i2c4_e_pins[] = {
2191         /* SCL, SDA */
2192         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2193 };
2194 static const unsigned int i2c4_e_mux[] = {
2195         I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
2196 };
2197 /* - INTC ------------------------------------------------------------------- */
2198 static const unsigned int intc_irq0_pins[] = {
2199         /* IRQ0 */
2200         RCAR_GP_PIN(4, 4),
2201 };
2202 static const unsigned int intc_irq0_mux[] = {
2203         IRQ0_MARK,
2204 };
2205 static const unsigned int intc_irq1_pins[] = {
2206         /* IRQ1 */
2207         RCAR_GP_PIN(4, 18),
2208 };
2209 static const unsigned int intc_irq1_mux[] = {
2210         IRQ1_MARK,
2211 };
2212 static const unsigned int intc_irq2_pins[] = {
2213         /* IRQ2 */
2214         RCAR_GP_PIN(4, 19),
2215 };
2216 static const unsigned int intc_irq2_mux[] = {
2217         IRQ2_MARK,
2218 };
2219 static const unsigned int intc_irq3_pins[] = {
2220         /* IRQ3 */
2221         RCAR_GP_PIN(0, 7),
2222 };
2223 static const unsigned int intc_irq3_mux[] = {
2224         IRQ3_MARK,
2225 };
2226 static const unsigned int intc_irq4_pins[] = {
2227         /* IRQ4 */
2228         RCAR_GP_PIN(0, 0),
2229 };
2230 static const unsigned int intc_irq4_mux[] = {
2231         IRQ4_MARK,
2232 };
2233 static const unsigned int intc_irq5_pins[] = {
2234         /* IRQ5 */
2235         RCAR_GP_PIN(4, 1),
2236 };
2237 static const unsigned int intc_irq5_mux[] = {
2238         IRQ5_MARK,
2239 };
2240 static const unsigned int intc_irq6_pins[] = {
2241         /* IRQ6 */
2242         RCAR_GP_PIN(0, 10),
2243 };
2244 static const unsigned int intc_irq6_mux[] = {
2245         IRQ6_MARK,
2246 };
2247 static const unsigned int intc_irq7_pins[] = {
2248         /* IRQ7 */
2249         RCAR_GP_PIN(6, 15),
2250 };
2251 static const unsigned int intc_irq7_mux[] = {
2252         IRQ7_MARK,
2253 };
2254 static const unsigned int intc_irq8_pins[] = {
2255         /* IRQ8 */
2256         RCAR_GP_PIN(5, 0),
2257 };
2258 static const unsigned int intc_irq8_mux[] = {
2259         IRQ8_MARK,
2260 };
2261 static const unsigned int intc_irq9_pins[] = {
2262         /* IRQ9 */
2263         RCAR_GP_PIN(5, 10),
2264 };
2265 static const unsigned int intc_irq9_mux[] = {
2266         IRQ9_MARK,
2267 };
2268 /* - MMCIF ------------------------------------------------------------------ */
2269 static const unsigned int mmc_data1_pins[] = {
2270         /* D[0] */
2271         RCAR_GP_PIN(6, 18),
2272 };
2273 static const unsigned int mmc_data1_mux[] = {
2274         MMC_D0_MARK,
2275 };
2276 static const unsigned int mmc_data4_pins[] = {
2277         /* D[0:3] */
2278         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2279         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2280 };
2281 static const unsigned int mmc_data4_mux[] = {
2282         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2283 };
2284 static const unsigned int mmc_data8_pins[] = {
2285         /* D[0:7] */
2286         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2287         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2288         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2289         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2290 };
2291 static const unsigned int mmc_data8_mux[] = {
2292         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2293         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2294 };
2295 static const unsigned int mmc_ctrl_pins[] = {
2296         /* CLK, CMD */
2297         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2298 };
2299 static const unsigned int mmc_ctrl_mux[] = {
2300         MMC_CLK_MARK, MMC_CMD_MARK,
2301 };
2302 /* - MSIOF0 ----------------------------------------------------------------- */
2303 static const unsigned int msiof0_clk_pins[] = {
2304         /* SCK */
2305         RCAR_GP_PIN(4, 4),
2306 };
2307 static const unsigned int msiof0_clk_mux[] = {
2308         MSIOF0_SCK_MARK,
2309 };
2310 static const unsigned int msiof0_sync_pins[] = {
2311         /* SYNC */
2312         RCAR_GP_PIN(4, 5),
2313 };
2314 static const unsigned int msiof0_sync_mux[] = {
2315         MSIOF0_SYNC_MARK,
2316 };
2317 static const unsigned int msiof0_ss1_pins[] = {
2318         /* SS1 */
2319         RCAR_GP_PIN(4, 6),
2320 };
2321 static const unsigned int msiof0_ss1_mux[] = {
2322         MSIOF0_SS1_MARK,
2323 };
2324 static const unsigned int msiof0_ss2_pins[] = {
2325         /* SS2 */
2326         RCAR_GP_PIN(4, 7),
2327 };
2328 static const unsigned int msiof0_ss2_mux[] = {
2329         MSIOF0_SS2_MARK,
2330 };
2331 static const unsigned int msiof0_rx_pins[] = {
2332         /* RXD */
2333         RCAR_GP_PIN(4, 2),
2334 };
2335 static const unsigned int msiof0_rx_mux[] = {
2336         MSIOF0_RXD_MARK,
2337 };
2338 static const unsigned int msiof0_tx_pins[] = {
2339         /* TXD */
2340         RCAR_GP_PIN(4, 3),
2341 };
2342 static const unsigned int msiof0_tx_mux[] = {
2343         MSIOF0_TXD_MARK,
2344 };
2345 /* - MSIOF1 ----------------------------------------------------------------- */
2346 static const unsigned int msiof1_clk_pins[] = {
2347         /* SCK */
2348         RCAR_GP_PIN(0, 26),
2349 };
2350 static const unsigned int msiof1_clk_mux[] = {
2351         MSIOF1_SCK_MARK,
2352 };
2353 static const unsigned int msiof1_sync_pins[] = {
2354         /* SYNC */
2355         RCAR_GP_PIN(0, 27),
2356 };
2357 static const unsigned int msiof1_sync_mux[] = {
2358         MSIOF1_SYNC_MARK,
2359 };
2360 static const unsigned int msiof1_ss1_pins[] = {
2361         /* SS1 */
2362         RCAR_GP_PIN(0, 28),
2363 };
2364 static const unsigned int msiof1_ss1_mux[] = {
2365         MSIOF1_SS1_MARK,
2366 };
2367 static const unsigned int msiof1_ss2_pins[] = {
2368         /* SS2 */
2369         RCAR_GP_PIN(0, 29),
2370 };
2371 static const unsigned int msiof1_ss2_mux[] = {
2372         MSIOF1_SS2_MARK,
2373 };
2374 static const unsigned int msiof1_rx_pins[] = {
2375         /* RXD */
2376         RCAR_GP_PIN(0, 24),
2377 };
2378 static const unsigned int msiof1_rx_mux[] = {
2379         MSIOF1_RXD_MARK,
2380 };
2381 static const unsigned int msiof1_tx_pins[] = {
2382         /* TXD */
2383         RCAR_GP_PIN(0, 25),
2384 };
2385 static const unsigned int msiof1_tx_mux[] = {
2386         MSIOF1_TXD_MARK,
2387 };
2388 static const unsigned int msiof1_clk_b_pins[] = {
2389         /* SCK */
2390         RCAR_GP_PIN(5, 3),
2391 };
2392 static const unsigned int msiof1_clk_b_mux[] = {
2393         MSIOF1_SCK_B_MARK,
2394 };
2395 static const unsigned int msiof1_sync_b_pins[] = {
2396         /* SYNC */
2397         RCAR_GP_PIN(5, 4),
2398 };
2399 static const unsigned int msiof1_sync_b_mux[] = {
2400         MSIOF1_SYNC_B_MARK,
2401 };
2402 static const unsigned int msiof1_ss1_b_pins[] = {
2403         /* SS1 */
2404         RCAR_GP_PIN(5, 5),
2405 };
2406 static const unsigned int msiof1_ss1_b_mux[] = {
2407         MSIOF1_SS1_B_MARK,
2408 };
2409 static const unsigned int msiof1_ss2_b_pins[] = {
2410         /* SS2 */
2411         RCAR_GP_PIN(5, 6),
2412 };
2413 static const unsigned int msiof1_ss2_b_mux[] = {
2414         MSIOF1_SS2_B_MARK,
2415 };
2416 static const unsigned int msiof1_rx_b_pins[] = {
2417         /* RXD */
2418         RCAR_GP_PIN(5, 1),
2419 };
2420 static const unsigned int msiof1_rx_b_mux[] = {
2421         MSIOF1_RXD_B_MARK,
2422 };
2423 static const unsigned int msiof1_tx_b_pins[] = {
2424         /* TXD */
2425         RCAR_GP_PIN(5, 2),
2426 };
2427 static const unsigned int msiof1_tx_b_mux[] = {
2428         MSIOF1_TXD_B_MARK,
2429 };
2430 /* - MSIOF2 ----------------------------------------------------------------- */
2431 static const unsigned int msiof2_clk_pins[] = {
2432         /* SCK */
2433         RCAR_GP_PIN(1, 0),
2434 };
2435 static const unsigned int msiof2_clk_mux[] = {
2436         MSIOF2_SCK_MARK,
2437 };
2438 static const unsigned int msiof2_sync_pins[] = {
2439         /* SYNC */
2440         RCAR_GP_PIN(1, 1),
2441 };
2442 static const unsigned int msiof2_sync_mux[] = {
2443         MSIOF2_SYNC_MARK,
2444 };
2445 static const unsigned int msiof2_ss1_pins[] = {
2446         /* SS1 */
2447         RCAR_GP_PIN(1, 2),
2448 };
2449 static const unsigned int msiof2_ss1_mux[] = {
2450         MSIOF2_SS1_MARK,
2451 };
2452 static const unsigned int msiof2_ss2_pins[] = {
2453         /* SS2 */
2454         RCAR_GP_PIN(1, 3),
2455 };
2456 static const unsigned int msiof2_ss2_mux[] = {
2457         MSIOF2_SS2_MARK,
2458 };
2459 static const unsigned int msiof2_rx_pins[] = {
2460         /* RXD */
2461         RCAR_GP_PIN(0, 30),
2462 };
2463 static const unsigned int msiof2_rx_mux[] = {
2464         MSIOF2_RXD_MARK,
2465 };
2466 static const unsigned int msiof2_tx_pins[] = {
2467         /* TXD */
2468         RCAR_GP_PIN(0, 31),
2469 };
2470 static const unsigned int msiof2_tx_mux[] = {
2471         MSIOF2_TXD_MARK,
2472 };
2473 static const unsigned int msiof2_clk_b_pins[] = {
2474         /* SCK */
2475         RCAR_GP_PIN(3, 15),
2476 };
2477 static const unsigned int msiof2_clk_b_mux[] = {
2478         MSIOF2_SCK_B_MARK,
2479 };
2480 static const unsigned int msiof2_sync_b_pins[] = {
2481         /* SYNC */
2482         RCAR_GP_PIN(3, 16),
2483 };
2484 static const unsigned int msiof2_sync_b_mux[] = {
2485         MSIOF2_SYNC_B_MARK,
2486 };
2487 static const unsigned int msiof2_ss1_b_pins[] = {
2488         /* SS1 */
2489         RCAR_GP_PIN(3, 17),
2490 };
2491 static const unsigned int msiof2_ss1_b_mux[] = {
2492         MSIOF2_SS1_B_MARK,
2493 };
2494 static const unsigned int msiof2_ss2_b_pins[] = {
2495         /* SS2 */
2496         RCAR_GP_PIN(3, 18),
2497 };
2498 static const unsigned int msiof2_ss2_b_mux[] = {
2499         MSIOF2_SS2_B_MARK,
2500 };
2501 static const unsigned int msiof2_rx_b_pins[] = {
2502         /* RXD */
2503         RCAR_GP_PIN(3, 13),
2504 };
2505 static const unsigned int msiof2_rx_b_mux[] = {
2506         MSIOF2_RXD_B_MARK,
2507 };
2508 static const unsigned int msiof2_tx_b_pins[] = {
2509         /* TXD */
2510         RCAR_GP_PIN(3, 14),
2511 };
2512 static const unsigned int msiof2_tx_b_mux[] = {
2513         MSIOF2_TXD_B_MARK,
2514 };
2515 /* - QSPI ------------------------------------------------------------------- */
2516 static const unsigned int qspi_ctrl_pins[] = {
2517         /* SPCLK, SSL */
2518         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2519 };
2520 static const unsigned int qspi_ctrl_mux[] = {
2521         SPCLK_MARK, SSL_MARK,
2522 };
2523 static const unsigned int qspi_data2_pins[] = {
2524         /* MOSI_IO0, MISO_IO1 */
2525         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2526 };
2527 static const unsigned int qspi_data2_mux[] = {
2528         MOSI_IO0_MARK, MISO_IO1_MARK,
2529 };
2530 static const unsigned int qspi_data4_pins[] = {
2531         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2532         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2533         RCAR_GP_PIN(1, 8),
2534 };
2535 static const unsigned int qspi_data4_mux[] = {
2536         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2537 };
2538 /* - SCIF0 ------------------------------------------------------------------ */
2539 static const unsigned int scif0_data_pins[] = {
2540         /* RX, TX */
2541         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2542 };
2543 static const unsigned int scif0_data_mux[] = {
2544         SCIF0_RXD_MARK, SCIF0_TXD_MARK,
2545 };
2546 static const unsigned int scif0_data_b_pins[] = {
2547         /* RX, TX */
2548         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2549 };
2550 static const unsigned int scif0_data_b_mux[] = {
2551         SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
2552 };
2553 static const unsigned int scif0_data_c_pins[] = {
2554         /* RX, TX */
2555         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2556 };
2557 static const unsigned int scif0_data_c_mux[] = {
2558         SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
2559 };
2560 static const unsigned int scif0_data_d_pins[] = {
2561         /* RX, TX */
2562         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2563 };
2564 static const unsigned int scif0_data_d_mux[] = {
2565         SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
2566 };
2567 /* - SCIF1 ------------------------------------------------------------------ */
2568 static const unsigned int scif1_data_pins[] = {
2569         /* RX, TX */
2570         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2571 };
2572 static const unsigned int scif1_data_mux[] = {
2573         SCIF1_RXD_MARK, SCIF1_TXD_MARK,
2574 };
2575 static const unsigned int scif1_clk_pins[] = {
2576         /* SCK */
2577         RCAR_GP_PIN(4, 13),
2578 };
2579 static const unsigned int scif1_clk_mux[] = {
2580         SCIF1_SCK_MARK,
2581 };
2582 static const unsigned int scif1_data_b_pins[] = {
2583         /* RX, TX */
2584         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2585 };
2586 static const unsigned int scif1_data_b_mux[] = {
2587         SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
2588 };
2589 static const unsigned int scif1_clk_b_pins[] = {
2590         /* SCK */
2591         RCAR_GP_PIN(5, 10),
2592 };
2593 static const unsigned int scif1_clk_b_mux[] = {
2594         SCIF1_SCK_B_MARK,
2595 };
2596 static const unsigned int scif1_data_c_pins[] = {
2597         /* RX, TX */
2598         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2599 };
2600 static const unsigned int scif1_data_c_mux[] = {
2601         SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
2602 };
2603 static const unsigned int scif1_clk_c_pins[] = {
2604         /* SCK */
2605         RCAR_GP_PIN(0, 10),
2606 };
2607 static const unsigned int scif1_clk_c_mux[] = {
2608         SCIF1_SCK_C_MARK,
2609 };
2610 /* - SCIF2 ------------------------------------------------------------------ */
2611 static const unsigned int scif2_data_pins[] = {
2612         /* RX, TX */
2613         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2614 };
2615 static const unsigned int scif2_data_mux[] = {
2616         SCIF2_RXD_MARK, SCIF2_TXD_MARK,
2617 };
2618 static const unsigned int scif2_clk_pins[] = {
2619         /* SCK */
2620         RCAR_GP_PIN(4, 18),
2621 };
2622 static const unsigned int scif2_clk_mux[] = {
2623         SCIF2_SCK_MARK,
2624 };
2625 static const unsigned int scif2_data_b_pins[] = {
2626         /* RX, TX */
2627         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2628 };
2629 static const unsigned int scif2_data_b_mux[] = {
2630         SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
2631 };
2632 static const unsigned int scif2_clk_b_pins[] = {
2633         /* SCK */
2634         RCAR_GP_PIN(5, 17),
2635 };
2636 static const unsigned int scif2_clk_b_mux[] = {
2637         SCIF2_SCK_B_MARK,
2638 };
2639 static const unsigned int scif2_data_c_pins[] = {
2640         /* RX, TX */
2641         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2642 };
2643 static const unsigned int scif2_data_c_mux[] = {
2644         SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
2645 };
2646 static const unsigned int scif2_clk_c_pins[] = {
2647         /* SCK */
2648         RCAR_GP_PIN(3, 19),
2649 };
2650 static const unsigned int scif2_clk_c_mux[] = {
2651         SCIF2_SCK_C_MARK,
2652 };
2653 /* - SCIF3 ------------------------------------------------------------------ */
2654 static const unsigned int scif3_data_pins[] = {
2655         /* RX, TX */
2656         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2657 };
2658 static const unsigned int scif3_data_mux[] = {
2659         SCIF3_RXD_MARK, SCIF3_TXD_MARK,
2660 };
2661 static const unsigned int scif3_clk_pins[] = {
2662         /* SCK */
2663         RCAR_GP_PIN(4, 19),
2664 };
2665 static const unsigned int scif3_clk_mux[] = {
2666         SCIF3_SCK_MARK,
2667 };
2668 static const unsigned int scif3_data_b_pins[] = {
2669         /* RX, TX */
2670         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2671 };
2672 static const unsigned int scif3_data_b_mux[] = {
2673         SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
2674 };
2675 static const unsigned int scif3_clk_b_pins[] = {
2676         /* SCK */
2677         RCAR_GP_PIN(3, 22),
2678 };
2679 static const unsigned int scif3_clk_b_mux[] = {
2680         SCIF3_SCK_B_MARK,
2681 };
2682 /* - SCIF4 ------------------------------------------------------------------ */
2683 static const unsigned int scif4_data_pins[] = {
2684         /* RX, TX */
2685         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2686 };
2687 static const unsigned int scif4_data_mux[] = {
2688         SCIF4_RXD_MARK, SCIF4_TXD_MARK,
2689 };
2690 static const unsigned int scif4_data_b_pins[] = {
2691         /* RX, TX */
2692         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2693 };
2694 static const unsigned int scif4_data_b_mux[] = {
2695         SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
2696 };
2697 static const unsigned int scif4_data_c_pins[] = {
2698         /* RX, TX */
2699         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
2700 };
2701 static const unsigned int scif4_data_c_mux[] = {
2702         SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
2703 };
2704 static const unsigned int scif4_data_d_pins[] = {
2705         /* RX, TX */
2706         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2707 };
2708 static const unsigned int scif4_data_d_mux[] = {
2709         SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
2710 };
2711 static const unsigned int scif4_data_e_pins[] = {
2712         /* RX, TX */
2713         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
2714 };
2715 static const unsigned int scif4_data_e_mux[] = {
2716         SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
2717 };
2718 /* - SCIF5 ------------------------------------------------------------------ */
2719 static const unsigned int scif5_data_pins[] = {
2720         /* RX, TX */
2721         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2722 };
2723 static const unsigned int scif5_data_mux[] = {
2724         SCIF5_RXD_MARK, SCIF5_TXD_MARK,
2725 };
2726 static const unsigned int scif5_data_b_pins[] = {
2727         /* RX, TX */
2728         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2729 };
2730 static const unsigned int scif5_data_b_mux[] = {
2731         SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
2732 };
2733 static const unsigned int scif5_data_c_pins[] = {
2734         /* RX, TX */
2735         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
2736 };
2737 static const unsigned int scif5_data_c_mux[] = {
2738         SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
2739 };
2740 static const unsigned int scif5_data_d_pins[] = {
2741         /* RX, TX */
2742         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2743 };
2744 static const unsigned int scif5_data_d_mux[] = {
2745         SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
2746 };
2747 /* - SCIFA0 ----------------------------------------------------------------- */
2748 static const unsigned int scifa0_data_pins[] = {
2749         /* RXD, TXD */
2750         RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
2751 };
2752 static const unsigned int scifa0_data_mux[] = {
2753         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2754 };
2755 static const unsigned int scifa0_data_b_pins[] = {
2756         /* RXD, TXD */
2757         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2758 };
2759 static const unsigned int scifa0_data_b_mux[] = {
2760         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2761 };
2762 static const unsigned int scifa0_data_c_pins[] = {
2763         /* RXD, TXD */
2764         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2765 };
2766 static const unsigned int scifa0_data_c_mux[] = {
2767         SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
2768 };
2769 static const unsigned int scifa0_data_d_pins[] = {
2770         /* RXD, TXD */
2771         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2772 };
2773 static const unsigned int scifa0_data_d_mux[] = {
2774         SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
2775 };
2776 /* - SCIFA1 ----------------------------------------------------------------- */
2777 static const unsigned int scifa1_data_pins[] = {
2778         /* RXD, TXD */
2779         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2780 };
2781 static const unsigned int scifa1_data_mux[] = {
2782         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2783 };
2784 static const unsigned int scifa1_clk_pins[] = {
2785         /* SCK */
2786         RCAR_GP_PIN(0, 13),
2787 };
2788 static const unsigned int scifa1_clk_mux[] = {
2789         SCIFA1_SCK_MARK,
2790 };
2791 static const unsigned int scifa1_data_b_pins[] = {
2792         /* RXD, TXD */
2793         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2794 };
2795 static const unsigned int scifa1_data_b_mux[] = {
2796         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2797 };
2798 static const unsigned int scifa1_clk_b_pins[] = {
2799         /* SCK */
2800         RCAR_GP_PIN(4, 27),
2801 };
2802 static const unsigned int scifa1_clk_b_mux[] = {
2803         SCIFA1_SCK_B_MARK,
2804 };
2805 static const unsigned int scifa1_data_c_pins[] = {
2806         /* RXD, TXD */
2807         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2808 };
2809 static const unsigned int scifa1_data_c_mux[] = {
2810         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2811 };
2812 static const unsigned int scifa1_clk_c_pins[] = {
2813         /* SCK */
2814         RCAR_GP_PIN(5, 4),
2815 };
2816 static const unsigned int scifa1_clk_c_mux[] = {
2817         SCIFA1_SCK_C_MARK,
2818 };
2819 /* - SCIFA2 ----------------------------------------------------------------- */
2820 static const unsigned int scifa2_data_pins[] = {
2821         /* RXD, TXD */
2822         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2823 };
2824 static const unsigned int scifa2_data_mux[] = {
2825         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2826 };
2827 static const unsigned int scifa2_clk_pins[] = {
2828         /* SCK */
2829         RCAR_GP_PIN(1, 15),
2830 };
2831 static const unsigned int scifa2_clk_mux[] = {
2832         SCIFA2_SCK_MARK,
2833 };
2834 static const unsigned int scifa2_data_b_pins[] = {
2835         /* RXD, TXD */
2836         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
2837 };
2838 static const unsigned int scifa2_data_b_mux[] = {
2839         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2840 };
2841 static const unsigned int scifa2_clk_b_pins[] = {
2842         /* SCK */
2843         RCAR_GP_PIN(4, 30),
2844 };
2845 static const unsigned int scifa2_clk_b_mux[] = {
2846         SCIFA2_SCK_B_MARK,
2847 };
2848 /* - SCIFA3 ----------------------------------------------------------------- */
2849 static const unsigned int scifa3_data_pins[] = {
2850         /* RXD, TXD */
2851         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2852 };
2853 static const unsigned int scifa3_data_mux[] = {
2854         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2855 };
2856 static const unsigned int scifa3_clk_pins[] = {
2857         /* SCK */
2858         RCAR_GP_PIN(4, 24),
2859 };
2860 static const unsigned int scifa3_clk_mux[] = {
2861         SCIFA3_SCK_MARK,
2862 };
2863 static const unsigned int scifa3_data_b_pins[] = {
2864         /* RXD, TXD */
2865         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
2866 };
2867 static const unsigned int scifa3_data_b_mux[] = {
2868         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
2869 };
2870 static const unsigned int scifa3_clk_b_pins[] = {
2871         /* SCK */
2872         RCAR_GP_PIN(0, 0),
2873 };
2874 static const unsigned int scifa3_clk_b_mux[] = {
2875         SCIFA3_SCK_B_MARK,
2876 };
2877 /* - SCIFA4 ----------------------------------------------------------------- */
2878 static const unsigned int scifa4_data_pins[] = {
2879         /* RXD, TXD */
2880         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
2881 };
2882 static const unsigned int scifa4_data_mux[] = {
2883         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2884 };
2885 static const unsigned int scifa4_data_b_pins[] = {
2886         /* RXD, TXD */
2887         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
2888 };
2889 static const unsigned int scifa4_data_b_mux[] = {
2890         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
2891 };
2892 static const unsigned int scifa4_data_c_pins[] = {
2893         /* RXD, TXD */
2894         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2895 };
2896 static const unsigned int scifa4_data_c_mux[] = {
2897         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
2898 };
2899 static const unsigned int scifa4_data_d_pins[] = {
2900         /* RXD, TXD */
2901         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2902 };
2903 static const unsigned int scifa4_data_d_mux[] = {
2904         SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
2905 };
2906 /* - SCIFA5 ----------------------------------------------------------------- */
2907 static const unsigned int scifa5_data_pins[] = {
2908         /* RXD, TXD */
2909         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2910 };
2911 static const unsigned int scifa5_data_mux[] = {
2912         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
2913 };
2914 static const unsigned int scifa5_data_b_pins[] = {
2915         /* RXD, TXD */
2916         RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
2917 };
2918 static const unsigned int scifa5_data_b_mux[] = {
2919         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
2920 };
2921 static const unsigned int scifa5_data_c_pins[] = {
2922         /* RXD, TXD */
2923         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
2924 };
2925 static const unsigned int scifa5_data_c_mux[] = {
2926         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
2927 };
2928 static const unsigned int scifa5_data_d_pins[] = {
2929         /* RXD, TXD */
2930         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2931 };
2932 static const unsigned int scifa5_data_d_mux[] = {
2933         SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
2934 };
2935 /* - SCIFB0 ----------------------------------------------------------------- */
2936 static const unsigned int scifb0_data_pins[] = {
2937         /* RXD, TXD */
2938         RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
2939 };
2940 static const unsigned int scifb0_data_mux[] = {
2941         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2942 };
2943 static const unsigned int scifb0_clk_pins[] = {
2944         /* SCK */
2945         RCAR_GP_PIN(0, 19),
2946 };
2947 static const unsigned int scifb0_clk_mux[] = {
2948         SCIFB0_SCK_MARK,
2949 };
2950 static const unsigned int scifb0_ctrl_pins[] = {
2951         /* RTS, CTS */
2952         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
2953 };
2954 static const unsigned int scifb0_ctrl_mux[] = {
2955         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2956 };
2957 /* - SCIFB1 ----------------------------------------------------------------- */
2958 static const unsigned int scifb1_data_pins[] = {
2959         /* RXD, TXD */
2960         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
2961 };
2962 static const unsigned int scifb1_data_mux[] = {
2963         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2964 };
2965 static const unsigned int scifb1_clk_pins[] = {
2966         /* SCK */
2967         RCAR_GP_PIN(0, 16),
2968 };
2969 static const unsigned int scifb1_clk_mux[] = {
2970         SCIFB1_SCK_MARK,
2971 };
2972 /* - SCIFB2 ----------------------------------------------------------------- */
2973 static const unsigned int scifb2_data_pins[] = {
2974         /* RXD, TXD */
2975         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2976 };
2977 static const unsigned int scifb2_data_mux[] = {
2978         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2979 };
2980 static const unsigned int scifb2_clk_pins[] = {
2981         /* SCK */
2982         RCAR_GP_PIN(1, 15),
2983 };
2984 static const unsigned int scifb2_clk_mux[] = {
2985         SCIFB2_SCK_MARK,
2986 };
2987 static const unsigned int scifb2_ctrl_pins[] = {
2988         /* RTS, CTS */
2989         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2990 };
2991 static const unsigned int scifb2_ctrl_mux[] = {
2992         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2993 };
2994 /* - SCIF Clock ------------------------------------------------------------- */
2995 static const unsigned int scif_clk_pins[] = {
2996         /* SCIF_CLK */
2997         RCAR_GP_PIN(1, 23),
2998 };
2999 static const unsigned int scif_clk_mux[] = {
3000         SCIF_CLK_MARK,
3001 };
3002 static const unsigned int scif_clk_b_pins[] = {
3003         /* SCIF_CLK */
3004         RCAR_GP_PIN(3, 29),
3005 };
3006 static const unsigned int scif_clk_b_mux[] = {
3007         SCIF_CLK_B_MARK,
3008 };
3009 /* - SDHI0 ------------------------------------------------------------------ */
3010 static const unsigned int sdhi0_data1_pins[] = {
3011         /* D0 */
3012         RCAR_GP_PIN(6, 2),
3013 };
3014 static const unsigned int sdhi0_data1_mux[] = {
3015         SD0_DATA0_MARK,
3016 };
3017 static const unsigned int sdhi0_data4_pins[] = {
3018         /* D[0:3] */
3019         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3020         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3021 };
3022 static const unsigned int sdhi0_data4_mux[] = {
3023         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3024 };
3025 static const unsigned int sdhi0_ctrl_pins[] = {
3026         /* CLK, CMD */
3027         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3028 };
3029 static const unsigned int sdhi0_ctrl_mux[] = {
3030         SD0_CLK_MARK, SD0_CMD_MARK,
3031 };
3032 static const unsigned int sdhi0_cd_pins[] = {
3033         /* CD */
3034         RCAR_GP_PIN(6, 6),
3035 };
3036 static const unsigned int sdhi0_cd_mux[] = {
3037         SD0_CD_MARK,
3038 };
3039 static const unsigned int sdhi0_wp_pins[] = {
3040         /* WP */
3041         RCAR_GP_PIN(6, 7),
3042 };
3043 static const unsigned int sdhi0_wp_mux[] = {
3044         SD0_WP_MARK,
3045 };
3046 /* - SDHI1 ------------------------------------------------------------------ */
3047 static const unsigned int sdhi1_data1_pins[] = {
3048         /* D0 */
3049         RCAR_GP_PIN(6, 10),
3050 };
3051 static const unsigned int sdhi1_data1_mux[] = {
3052         SD1_DATA0_MARK,
3053 };
3054 static const unsigned int sdhi1_data4_pins[] = {
3055         /* D[0:3] */
3056         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3057         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3058 };
3059 static const unsigned int sdhi1_data4_mux[] = {
3060         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3061 };
3062 static const unsigned int sdhi1_ctrl_pins[] = {
3063         /* CLK, CMD */
3064         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3065 };
3066 static const unsigned int sdhi1_ctrl_mux[] = {
3067         SD1_CLK_MARK, SD1_CMD_MARK,
3068 };
3069 static const unsigned int sdhi1_cd_pins[] = {
3070         /* CD */
3071         RCAR_GP_PIN(6, 14),
3072 };
3073 static const unsigned int sdhi1_cd_mux[] = {
3074         SD1_CD_MARK,
3075 };
3076 static const unsigned int sdhi1_wp_pins[] = {
3077         /* WP */
3078         RCAR_GP_PIN(6, 15),
3079 };
3080 static const unsigned int sdhi1_wp_mux[] = {
3081         SD1_WP_MARK,
3082 };
3083 /* - SDHI2 ------------------------------------------------------------------ */
3084 static const unsigned int sdhi2_data1_pins[] = {
3085         /* D0 */
3086         RCAR_GP_PIN(6, 18),
3087 };
3088 static const unsigned int sdhi2_data1_mux[] = {
3089         SD2_DATA0_MARK,
3090 };
3091 static const unsigned int sdhi2_data4_pins[] = {
3092         /* D[0:3] */
3093         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3094         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3095 };
3096 static const unsigned int sdhi2_data4_mux[] = {
3097         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3098 };
3099 static const unsigned int sdhi2_ctrl_pins[] = {
3100         /* CLK, CMD */
3101         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3102 };
3103 static const unsigned int sdhi2_ctrl_mux[] = {
3104         SD2_CLK_MARK, SD2_CMD_MARK,
3105 };
3106 static const unsigned int sdhi2_cd_pins[] = {
3107         /* CD */
3108         RCAR_GP_PIN(6, 22),
3109 };
3110 static const unsigned int sdhi2_cd_mux[] = {
3111         SD2_CD_MARK,
3112 };
3113 static const unsigned int sdhi2_wp_pins[] = {
3114         /* WP */
3115         RCAR_GP_PIN(6, 23),
3116 };
3117 static const unsigned int sdhi2_wp_mux[] = {
3118         SD2_WP_MARK,
3119 };
3120 /* - SSI -------------------------------------------------------------------- */
3121 static const unsigned int ssi0_data_pins[] = {
3122         /* SDATA0 */
3123         RCAR_GP_PIN(5, 3),
3124 };
3125 static const unsigned int ssi0_data_mux[] = {
3126         SSI_SDATA0_MARK,
3127 };
3128 static const unsigned int ssi0129_ctrl_pins[] = {
3129         /* SCK0129, WS0129 */
3130         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3131 };
3132 static const unsigned int ssi0129_ctrl_mux[] = {
3133         SSI_SCK0129_MARK, SSI_WS0129_MARK,
3134 };
3135 static const unsigned int ssi1_data_pins[] = {
3136         /* SDATA1 */
3137         RCAR_GP_PIN(5, 13),
3138 };
3139 static const unsigned int ssi1_data_mux[] = {
3140         SSI_SDATA1_MARK,
3141 };
3142 static const unsigned int ssi1_ctrl_pins[] = {
3143         /* SCK1, WS1 */
3144         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
3145 };
3146 static const unsigned int ssi1_ctrl_mux[] = {
3147         SSI_SCK1_MARK, SSI_WS1_MARK,
3148 };
3149 static const unsigned int ssi1_data_b_pins[] = {
3150         /* SDATA1 */
3151         RCAR_GP_PIN(4, 13),
3152 };
3153 static const unsigned int ssi1_data_b_mux[] = {
3154         SSI_SDATA1_B_MARK,
3155 };
3156 static const unsigned int ssi1_ctrl_b_pins[] = {
3157         /* SCK1, WS1 */
3158         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3159 };
3160 static const unsigned int ssi1_ctrl_b_mux[] = {
3161         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3162 };
3163 static const unsigned int ssi2_data_pins[] = {
3164         /* SDATA2 */
3165         RCAR_GP_PIN(5, 16),
3166 };
3167 static const unsigned int ssi2_data_mux[] = {
3168         SSI_SDATA2_MARK,
3169 };
3170 static const unsigned int ssi2_ctrl_pins[] = {
3171         /* SCK2, WS2 */
3172         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3173 };
3174 static const unsigned int ssi2_ctrl_mux[] = {
3175         SSI_SCK2_MARK, SSI_WS2_MARK,
3176 };
3177 static const unsigned int ssi2_data_b_pins[] = {
3178         /* SDATA2 */
3179         RCAR_GP_PIN(4, 16),
3180 };
3181 static const unsigned int ssi2_data_b_mux[] = {
3182         SSI_SDATA2_B_MARK,
3183 };
3184 static const unsigned int ssi2_ctrl_b_pins[] = {
3185         /* SCK2, WS2 */
3186         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3187 };
3188 static const unsigned int ssi2_ctrl_b_mux[] = {
3189         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3190 };
3191 static const unsigned int ssi3_data_pins[] = {
3192         /* SDATA3 */
3193         RCAR_GP_PIN(5, 6),
3194 };
3195 static const unsigned int ssi3_data_mux[] = {
3196         SSI_SDATA3_MARK
3197 };
3198 static const unsigned int ssi34_ctrl_pins[] = {
3199         /* SCK34, WS34 */
3200         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
3201 };
3202 static const unsigned int ssi34_ctrl_mux[] = {
3203         SSI_SCK34_MARK, SSI_WS34_MARK,
3204 };
3205 static const unsigned int ssi4_data_pins[] = {
3206         /* SDATA4 */
3207         RCAR_GP_PIN(5, 9),
3208 };
3209 static const unsigned int ssi4_data_mux[] = {
3210         SSI_SDATA4_MARK,
3211 };
3212 static const unsigned int ssi4_ctrl_pins[] = {
3213         /* SCK4, WS4 */
3214         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
3215 };
3216 static const unsigned int ssi4_ctrl_mux[] = {
3217         SSI_SCK4_MARK, SSI_WS4_MARK,
3218 };
3219 static const unsigned int ssi4_data_b_pins[] = {
3220         /* SDATA4 */
3221         RCAR_GP_PIN(4, 22),
3222 };
3223 static const unsigned int ssi4_data_b_mux[] = {
3224         SSI_SDATA4_B_MARK,
3225 };
3226 static const unsigned int ssi4_ctrl_b_pins[] = {
3227         /* SCK4, WS4 */
3228         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3229 };
3230 static const unsigned int ssi4_ctrl_b_mux[] = {
3231         SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
3232 };
3233 static const unsigned int ssi5_data_pins[] = {
3234         /* SDATA5 */
3235         RCAR_GP_PIN(4, 26),
3236 };
3237 static const unsigned int ssi5_data_mux[] = {
3238         SSI_SDATA5_MARK,
3239 };
3240 static const unsigned int ssi5_ctrl_pins[] = {
3241         /* SCK5, WS5 */
3242         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
3243 };
3244 static const unsigned int ssi5_ctrl_mux[] = {
3245         SSI_SCK5_MARK, SSI_WS5_MARK,
3246 };
3247 static const unsigned int ssi5_data_b_pins[] = {
3248         /* SDATA5 */
3249         RCAR_GP_PIN(3, 21),
3250 };
3251 static const unsigned int ssi5_data_b_mux[] = {
3252         SSI_SDATA5_B_MARK,
3253 };
3254 static const unsigned int ssi5_ctrl_b_pins[] = {
3255         /* SCK5, WS5 */
3256         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3257 };
3258 static const unsigned int ssi5_ctrl_b_mux[] = {
3259         SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
3260 };
3261 static const unsigned int ssi6_data_pins[] = {
3262         /* SDATA6 */
3263         RCAR_GP_PIN(4, 29),
3264 };
3265 static const unsigned int ssi6_data_mux[] = {
3266         SSI_SDATA6_MARK,
3267 };
3268 static const unsigned int ssi6_ctrl_pins[] = {
3269         /* SCK6, WS6 */
3270         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3271 };
3272 static const unsigned int ssi6_ctrl_mux[] = {
3273         SSI_SCK6_MARK, SSI_WS6_MARK,
3274 };
3275 static const unsigned int ssi6_data_b_pins[] = {
3276         /* SDATA6 */
3277         RCAR_GP_PIN(3, 24),
3278 };
3279 static const unsigned int ssi6_data_b_mux[] = {
3280         SSI_SDATA6_B_MARK,
3281 };
3282 static const unsigned int ssi6_ctrl_b_pins[] = {
3283         /* SCK6, WS6 */
3284         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
3285 };
3286 static const unsigned int ssi6_ctrl_b_mux[] = {
3287         SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3288 };
3289 static const unsigned int ssi7_data_pins[] = {
3290         /* SDATA7 */
3291         RCAR_GP_PIN(5, 0),
3292 };
3293 static const unsigned int ssi7_data_mux[] = {
3294         SSI_SDATA7_MARK,
3295 };
3296 static const unsigned int ssi78_ctrl_pins[] = {
3297         /* SCK78, WS78 */
3298         RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
3299 };
3300 static const unsigned int ssi78_ctrl_mux[] = {
3301         SSI_SCK78_MARK, SSI_WS78_MARK,
3302 };
3303 static const unsigned int ssi7_data_b_pins[] = {
3304         /* SDATA7 */
3305         RCAR_GP_PIN(3, 27),
3306 };
3307 static const unsigned int ssi7_data_b_mux[] = {
3308         SSI_SDATA7_B_MARK,
3309 };
3310 static const unsigned int ssi78_ctrl_b_pins[] = {
3311         /* SCK78, WS78 */
3312         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3313 };
3314 static const unsigned int ssi78_ctrl_b_mux[] = {
3315         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3316 };
3317 static const unsigned int ssi8_data_pins[] = {
3318         /* SDATA8 */
3319         RCAR_GP_PIN(5, 10),
3320 };
3321 static const unsigned int ssi8_data_mux[] = {
3322         SSI_SDATA8_MARK,
3323 };
3324 static const unsigned int ssi8_data_b_pins[] = {
3325         /* SDATA8 */
3326         RCAR_GP_PIN(3, 28),
3327 };
3328 static const unsigned int ssi8_data_b_mux[] = {
3329         SSI_SDATA8_B_MARK,
3330 };
3331 static const unsigned int ssi9_data_pins[] = {
3332         /* SDATA9 */
3333         RCAR_GP_PIN(5, 19),
3334 };
3335 static const unsigned int ssi9_data_mux[] = {
3336         SSI_SDATA9_MARK,
3337 };
3338 static const unsigned int ssi9_ctrl_pins[] = {
3339         /* SCK9, WS9 */
3340         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
3341 };
3342 static const unsigned int ssi9_ctrl_mux[] = {
3343         SSI_SCK9_MARK, SSI_WS9_MARK,
3344 };
3345 static const unsigned int ssi9_data_b_pins[] = {
3346         /* SDATA9 */
3347         RCAR_GP_PIN(4, 19),
3348 };
3349 static const unsigned int ssi9_data_b_mux[] = {
3350         SSI_SDATA9_B_MARK,
3351 };
3352 static const unsigned int ssi9_ctrl_b_pins[] = {
3353         /* SCK9, WS9 */
3354         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3355 };
3356 static const unsigned int ssi9_ctrl_b_mux[] = {
3357         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3358 };
3359 /* - USB0 ------------------------------------------------------------------- */
3360 static const unsigned int usb0_pins[] = {
3361         RCAR_GP_PIN(5, 24), /* PWEN */
3362         RCAR_GP_PIN(5, 25), /* OVC */
3363 };
3364 static const unsigned int usb0_mux[] = {
3365         USB0_PWEN_MARK,
3366         USB0_OVC_MARK,
3367 };
3368 /* - USB1 ------------------------------------------------------------------- */
3369 static const unsigned int usb1_pins[] = {
3370         RCAR_GP_PIN(5, 26), /* PWEN */
3371         RCAR_GP_PIN(5, 27), /* OVC */
3372 };
3373 static const unsigned int usb1_mux[] = {
3374         USB1_PWEN_MARK,
3375         USB1_OVC_MARK,
3376 };
3377 /* - VIN0 ------------------------------------------------------------------- */
3378 static const union vin_data vin0_data_pins = {
3379         .data24 = {
3380                 /* B */
3381                 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
3382                 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3383                 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3384                 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3385                 /* G */
3386                 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
3387                 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3388                 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3389                 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3390                 /* R */
3391                 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
3392                 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3393                 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3394                 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3395         },
3396 };
3397 static const union vin_data vin0_data_mux = {
3398         .data24 = {
3399                 /* B */
3400                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3401                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3402                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3403                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3404                 /* G */
3405                 VI0_G0_MARK, VI0_G1_MARK,
3406                 VI0_G2_MARK, VI0_G3_MARK,
3407                 VI0_G4_MARK, VI0_G5_MARK,
3408                 VI0_G6_MARK, VI0_G7_MARK,
3409                 /* R */
3410                 VI0_R0_MARK, VI0_R1_MARK,
3411                 VI0_R2_MARK, VI0_R3_MARK,
3412                 VI0_R4_MARK, VI0_R5_MARK,
3413                 VI0_R6_MARK, VI0_R7_MARK,
3414         },
3415 };
3416 static const unsigned int vin0_data18_pins[] = {
3417         /* B */
3418         RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3419         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3420         RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3421         /* G */
3422         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3423         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3424         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3425         /* R */
3426         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3427         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3428         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3429 };
3430 static const unsigned int vin0_data18_mux[] = {
3431         /* B */
3432         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3433         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3434         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3435         /* G */
3436         VI0_G2_MARK, VI0_G3_MARK,
3437         VI0_G4_MARK, VI0_G5_MARK,
3438         VI0_G6_MARK, VI0_G7_MARK,
3439         /* R */
3440         VI0_R2_MARK, VI0_R3_MARK,
3441         VI0_R4_MARK, VI0_R5_MARK,
3442         VI0_R6_MARK, VI0_R7_MARK,
3443 };
3444 static const unsigned int vin0_sync_pins[] = {
3445         RCAR_GP_PIN(3, 11), /* HSYNC */
3446         RCAR_GP_PIN(3, 12), /* VSYNC */
3447 };
3448 static const unsigned int vin0_sync_mux[] = {
3449         VI0_HSYNC_N_MARK,
3450         VI0_VSYNC_N_MARK,
3451 };
3452 static const unsigned int vin0_field_pins[] = {
3453         RCAR_GP_PIN(3, 10),
3454 };
3455 static const unsigned int vin0_field_mux[] = {
3456         VI0_FIELD_MARK,
3457 };
3458 static const unsigned int vin0_clkenb_pins[] = {
3459         RCAR_GP_PIN(3, 9),
3460 };
3461 static const unsigned int vin0_clkenb_mux[] = {
3462         VI0_CLKENB_MARK,
3463 };
3464 static const unsigned int vin0_clk_pins[] = {
3465         RCAR_GP_PIN(3, 0),
3466 };
3467 static const unsigned int vin0_clk_mux[] = {
3468         VI0_CLK_MARK,
3469 };
3470 /* - VIN1 ------------------------------------------------------------------- */
3471 static const union vin_data vin1_data_pins = {
3472         .data12 = {
3473                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
3474                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3475                 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
3476                 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3477                 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
3478                 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3479         },
3480 };
3481 static const union vin_data vin1_data_mux = {
3482         .data12 = {
3483                 VI1_DATA0_MARK, VI1_DATA1_MARK,
3484                 VI1_DATA2_MARK, VI1_DATA3_MARK,
3485                 VI1_DATA4_MARK, VI1_DATA5_MARK,
3486                 VI1_DATA6_MARK, VI1_DATA7_MARK,
3487                 VI1_DATA8_MARK, VI1_DATA9_MARK,
3488                 VI1_DATA10_MARK, VI1_DATA11_MARK,
3489         },
3490 };
3491 static const unsigned int vin1_sync_pins[] = {
3492         RCAR_GP_PIN(5, 22), /* HSYNC */
3493         RCAR_GP_PIN(5, 23), /* VSYNC */
3494 };
3495 static const unsigned int vin1_sync_mux[] = {
3496         VI1_HSYNC_N_MARK,
3497         VI1_VSYNC_N_MARK,
3498 };
3499 static const unsigned int vin1_field_pins[] = {
3500         RCAR_GP_PIN(5, 21),
3501 };
3502 static const unsigned int vin1_field_mux[] = {
3503         VI1_FIELD_MARK,
3504 };
3505 static const unsigned int vin1_clkenb_pins[] = {
3506         RCAR_GP_PIN(5, 20),
3507 };
3508 static const unsigned int vin1_clkenb_mux[] = {
3509         VI1_CLKENB_MARK,
3510 };
3511 static const unsigned int vin1_clk_pins[] = {
3512         RCAR_GP_PIN(5, 11),
3513 };
3514 static const unsigned int vin1_clk_mux[] = {
3515         VI1_CLK_MARK,
3516 };
3517
3518 static const struct sh_pfc_pin_group pinmux_groups[] = {
3519         SH_PFC_PIN_GROUP(audio_clka),
3520         SH_PFC_PIN_GROUP(audio_clka_b),
3521         SH_PFC_PIN_GROUP(audio_clka_c),
3522         SH_PFC_PIN_GROUP(audio_clka_d),
3523         SH_PFC_PIN_GROUP(audio_clkb),
3524         SH_PFC_PIN_GROUP(audio_clkb_b),
3525         SH_PFC_PIN_GROUP(audio_clkb_c),
3526         SH_PFC_PIN_GROUP(audio_clkc),
3527         SH_PFC_PIN_GROUP(audio_clkc_b),
3528         SH_PFC_PIN_GROUP(audio_clkc_c),
3529         SH_PFC_PIN_GROUP(audio_clkout),
3530         SH_PFC_PIN_GROUP(audio_clkout_b),
3531         SH_PFC_PIN_GROUP(audio_clkout_c),
3532         SH_PFC_PIN_GROUP(avb_link),
3533         SH_PFC_PIN_GROUP(avb_magic),
3534         SH_PFC_PIN_GROUP(avb_phy_int),
3535         SH_PFC_PIN_GROUP(avb_mdio),
3536         SH_PFC_PIN_GROUP(avb_mii),
3537         SH_PFC_PIN_GROUP(avb_gmii),
3538         SH_PFC_PIN_GROUP(avb_avtp_capture),
3539         SH_PFC_PIN_GROUP(avb_avtp_match),
3540         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3541         SH_PFC_PIN_GROUP(avb_avtp_match_b),
3542         SH_PFC_PIN_GROUP(du0_rgb666),
3543         SH_PFC_PIN_GROUP(du0_rgb888),
3544         SH_PFC_PIN_GROUP(du0_clk0_out),
3545         SH_PFC_PIN_GROUP(du0_clk1_out),
3546         SH_PFC_PIN_GROUP(du0_clk_in),
3547         SH_PFC_PIN_GROUP(du0_sync),
3548         SH_PFC_PIN_GROUP(du0_oddf),
3549         SH_PFC_PIN_GROUP(du0_cde),
3550         SH_PFC_PIN_GROUP(du0_disp),
3551         SH_PFC_PIN_GROUP(du1_rgb666),
3552         SH_PFC_PIN_GROUP(du1_rgb888),
3553         SH_PFC_PIN_GROUP(du1_clk0_out),
3554         SH_PFC_PIN_GROUP(du1_clk1_out),
3555         SH_PFC_PIN_GROUP(du1_clk_in),
3556         SH_PFC_PIN_GROUP(du1_sync),
3557         SH_PFC_PIN_GROUP(du1_oddf),
3558         SH_PFC_PIN_GROUP(du1_cde),
3559         SH_PFC_PIN_GROUP(du1_disp),
3560         SH_PFC_PIN_GROUP(eth_link),
3561         SH_PFC_PIN_GROUP(eth_magic),
3562         SH_PFC_PIN_GROUP(eth_mdio),
3563         SH_PFC_PIN_GROUP(eth_rmii),
3564         SH_PFC_PIN_GROUP(eth_link_b),
3565         SH_PFC_PIN_GROUP(eth_magic_b),
3566         SH_PFC_PIN_GROUP(eth_mdio_b),
3567         SH_PFC_PIN_GROUP(eth_rmii_b),
3568         SH_PFC_PIN_GROUP(hscif0_data),
3569         SH_PFC_PIN_GROUP(hscif0_clk),
3570         SH_PFC_PIN_GROUP(hscif0_ctrl),
3571         SH_PFC_PIN_GROUP(hscif0_data_b),
3572         SH_PFC_PIN_GROUP(hscif0_clk_b),
3573         SH_PFC_PIN_GROUP(hscif1_data),
3574         SH_PFC_PIN_GROUP(hscif1_clk),
3575         SH_PFC_PIN_GROUP(hscif1_ctrl),
3576         SH_PFC_PIN_GROUP(hscif1_data_b),
3577         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3578         SH_PFC_PIN_GROUP(hscif2_data),
3579         SH_PFC_PIN_GROUP(hscif2_clk),
3580         SH_PFC_PIN_GROUP(hscif2_ctrl),
3581         SH_PFC_PIN_GROUP(i2c0),
3582         SH_PFC_PIN_GROUP(i2c0_b),
3583         SH_PFC_PIN_GROUP(i2c0_c),
3584         SH_PFC_PIN_GROUP(i2c0_d),
3585         SH_PFC_PIN_GROUP(i2c0_e),
3586         SH_PFC_PIN_GROUP(i2c1),
3587         SH_PFC_PIN_GROUP(i2c1_b),
3588         SH_PFC_PIN_GROUP(i2c1_c),
3589         SH_PFC_PIN_GROUP(i2c1_d),
3590         SH_PFC_PIN_GROUP(i2c1_e),
3591         SH_PFC_PIN_GROUP(i2c2),
3592         SH_PFC_PIN_GROUP(i2c2_b),
3593         SH_PFC_PIN_GROUP(i2c2_c),
3594         SH_PFC_PIN_GROUP(i2c2_d),
3595         SH_PFC_PIN_GROUP(i2c2_e),
3596         SH_PFC_PIN_GROUP(i2c3),
3597         SH_PFC_PIN_GROUP(i2c3_b),
3598         SH_PFC_PIN_GROUP(i2c3_c),
3599         SH_PFC_PIN_GROUP(i2c3_d),
3600         SH_PFC_PIN_GROUP(i2c3_e),
3601         SH_PFC_PIN_GROUP(i2c4),
3602         SH_PFC_PIN_GROUP(i2c4_b),
3603         SH_PFC_PIN_GROUP(i2c4_c),
3604         SH_PFC_PIN_GROUP(i2c4_d),
3605         SH_PFC_PIN_GROUP(i2c4_e),
3606         SH_PFC_PIN_GROUP(intc_irq0),
3607         SH_PFC_PIN_GROUP(intc_irq1),
3608         SH_PFC_PIN_GROUP(intc_irq2),
3609         SH_PFC_PIN_GROUP(intc_irq3),
3610         SH_PFC_PIN_GROUP(intc_irq4),
3611         SH_PFC_PIN_GROUP(intc_irq5),
3612         SH_PFC_PIN_GROUP(intc_irq6),
3613         SH_PFC_PIN_GROUP(intc_irq7),
3614         SH_PFC_PIN_GROUP(intc_irq8),
3615         SH_PFC_PIN_GROUP(intc_irq9),
3616         SH_PFC_PIN_GROUP(mmc_data1),
3617         SH_PFC_PIN_GROUP(mmc_data4),
3618         SH_PFC_PIN_GROUP(mmc_data8),
3619         SH_PFC_PIN_GROUP(mmc_ctrl),
3620         SH_PFC_PIN_GROUP(msiof0_clk),
3621         SH_PFC_PIN_GROUP(msiof0_sync),
3622         SH_PFC_PIN_GROUP(msiof0_ss1),
3623         SH_PFC_PIN_GROUP(msiof0_ss2),
3624         SH_PFC_PIN_GROUP(msiof0_rx),
3625         SH_PFC_PIN_GROUP(msiof0_tx),
3626         SH_PFC_PIN_GROUP(msiof1_clk),
3627         SH_PFC_PIN_GROUP(msiof1_sync),
3628         SH_PFC_PIN_GROUP(msiof1_ss1),
3629         SH_PFC_PIN_GROUP(msiof1_ss2),
3630         SH_PFC_PIN_GROUP(msiof1_rx),
3631         SH_PFC_PIN_GROUP(msiof1_tx),
3632         SH_PFC_PIN_GROUP(msiof1_clk_b),
3633         SH_PFC_PIN_GROUP(msiof1_sync_b),
3634         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3635         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3636         SH_PFC_PIN_GROUP(msiof1_rx_b),
3637         SH_PFC_PIN_GROUP(msiof1_tx_b),
3638         SH_PFC_PIN_GROUP(msiof2_clk),
3639         SH_PFC_PIN_GROUP(msiof2_sync),
3640         SH_PFC_PIN_GROUP(msiof2_ss1),
3641         SH_PFC_PIN_GROUP(msiof2_ss2),
3642         SH_PFC_PIN_GROUP(msiof2_rx),
3643         SH_PFC_PIN_GROUP(msiof2_tx),
3644         SH_PFC_PIN_GROUP(msiof2_clk_b),
3645         SH_PFC_PIN_GROUP(msiof2_sync_b),
3646         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3647         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3648         SH_PFC_PIN_GROUP(msiof2_rx_b),
3649         SH_PFC_PIN_GROUP(msiof2_tx_b),
3650         SH_PFC_PIN_GROUP(qspi_ctrl),
3651         SH_PFC_PIN_GROUP(qspi_data2),
3652         SH_PFC_PIN_GROUP(qspi_data4),
3653         SH_PFC_PIN_GROUP(scif0_data),
3654         SH_PFC_PIN_GROUP(scif0_data_b),
3655         SH_PFC_PIN_GROUP(scif0_data_c),
3656         SH_PFC_PIN_GROUP(scif0_data_d),
3657         SH_PFC_PIN_GROUP(scif1_data),
3658         SH_PFC_PIN_GROUP(scif1_clk),
3659         SH_PFC_PIN_GROUP(scif1_data_b),
3660         SH_PFC_PIN_GROUP(scif1_clk_b),
3661         SH_PFC_PIN_GROUP(scif1_data_c),
3662         SH_PFC_PIN_GROUP(scif1_clk_c),
3663         SH_PFC_PIN_GROUP(scif2_data),
3664         SH_PFC_PIN_GROUP(scif2_clk),
3665         SH_PFC_PIN_GROUP(scif2_data_b),
3666         SH_PFC_PIN_GROUP(scif2_clk_b),
3667         SH_PFC_PIN_GROUP(scif2_data_c),
3668         SH_PFC_PIN_GROUP(scif2_clk_c),
3669         SH_PFC_PIN_GROUP(scif3_data),
3670         SH_PFC_PIN_GROUP(scif3_clk),
3671         SH_PFC_PIN_GROUP(scif3_data_b),
3672         SH_PFC_PIN_GROUP(scif3_clk_b),
3673         SH_PFC_PIN_GROUP(scif4_data),
3674         SH_PFC_PIN_GROUP(scif4_data_b),
3675         SH_PFC_PIN_GROUP(scif4_data_c),
3676         SH_PFC_PIN_GROUP(scif4_data_d),
3677         SH_PFC_PIN_GROUP(scif4_data_e),
3678         SH_PFC_PIN_GROUP(scif5_data),
3679         SH_PFC_PIN_GROUP(scif5_data_b),
3680         SH_PFC_PIN_GROUP(scif5_data_c),
3681         SH_PFC_PIN_GROUP(scif5_data_d),
3682         SH_PFC_PIN_GROUP(scifa0_data),
3683         SH_PFC_PIN_GROUP(scifa0_data_b),
3684         SH_PFC_PIN_GROUP(scifa0_data_c),
3685         SH_PFC_PIN_GROUP(scifa0_data_d),
3686         SH_PFC_PIN_GROUP(scifa1_data),
3687         SH_PFC_PIN_GROUP(scifa1_clk),
3688         SH_PFC_PIN_GROUP(scifa1_data_b),
3689         SH_PFC_PIN_GROUP(scifa1_clk_b),
3690         SH_PFC_PIN_GROUP(scifa1_data_c),
3691         SH_PFC_PIN_GROUP(scifa1_clk_c),
3692         SH_PFC_PIN_GROUP(scifa2_data),
3693         SH_PFC_PIN_GROUP(scifa2_clk),
3694         SH_PFC_PIN_GROUP(scifa2_data_b),
3695         SH_PFC_PIN_GROUP(scifa2_clk_b),
3696         SH_PFC_PIN_GROUP(scifa3_data),
3697         SH_PFC_PIN_GROUP(scifa3_clk),
3698         SH_PFC_PIN_GROUP(scifa3_data_b),
3699         SH_PFC_PIN_GROUP(scifa3_clk_b),
3700         SH_PFC_PIN_GROUP(scifa4_data),
3701         SH_PFC_PIN_GROUP(scifa4_data_b),
3702         SH_PFC_PIN_GROUP(scifa4_data_c),
3703         SH_PFC_PIN_GROUP(scifa4_data_d),
3704         SH_PFC_PIN_GROUP(scifa5_data),
3705         SH_PFC_PIN_GROUP(scifa5_data_b),
3706         SH_PFC_PIN_GROUP(scifa5_data_c),
3707         SH_PFC_PIN_GROUP(scifa5_data_d),
3708         SH_PFC_PIN_GROUP(scifb0_data),
3709         SH_PFC_PIN_GROUP(scifb0_clk),
3710         SH_PFC_PIN_GROUP(scifb0_ctrl),
3711         SH_PFC_PIN_GROUP(scifb1_data),
3712         SH_PFC_PIN_GROUP(scifb1_clk),
3713         SH_PFC_PIN_GROUP(scifb2_data),
3714         SH_PFC_PIN_GROUP(scifb2_clk),
3715         SH_PFC_PIN_GROUP(scifb2_ctrl),
3716         SH_PFC_PIN_GROUP(scif_clk),
3717         SH_PFC_PIN_GROUP(scif_clk_b),
3718         SH_PFC_PIN_GROUP(sdhi0_data1),
3719         SH_PFC_PIN_GROUP(sdhi0_data4),
3720         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3721         SH_PFC_PIN_GROUP(sdhi0_cd),
3722         SH_PFC_PIN_GROUP(sdhi0_wp),
3723         SH_PFC_PIN_GROUP(sdhi1_data1),
3724         SH_PFC_PIN_GROUP(sdhi1_data4),
3725         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3726         SH_PFC_PIN_GROUP(sdhi1_cd),
3727         SH_PFC_PIN_GROUP(sdhi1_wp),
3728         SH_PFC_PIN_GROUP(sdhi2_data1),
3729         SH_PFC_PIN_GROUP(sdhi2_data4),
3730         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3731         SH_PFC_PIN_GROUP(sdhi2_cd),
3732         SH_PFC_PIN_GROUP(sdhi2_wp),
3733         SH_PFC_PIN_GROUP(ssi0_data),
3734         SH_PFC_PIN_GROUP(ssi0129_ctrl),
3735         SH_PFC_PIN_GROUP(ssi1_data),
3736         SH_PFC_PIN_GROUP(ssi1_ctrl),
3737         SH_PFC_PIN_GROUP(ssi1_data_b),
3738         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
3739         SH_PFC_PIN_GROUP(ssi2_data),
3740         SH_PFC_PIN_GROUP(ssi2_ctrl),
3741         SH_PFC_PIN_GROUP(ssi2_data_b),
3742         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
3743         SH_PFC_PIN_GROUP(ssi3_data),
3744         SH_PFC_PIN_GROUP(ssi34_ctrl),
3745         SH_PFC_PIN_GROUP(ssi4_data),
3746         SH_PFC_PIN_GROUP(ssi4_ctrl),
3747         SH_PFC_PIN_GROUP(ssi4_data_b),
3748         SH_PFC_PIN_GROUP(ssi4_ctrl_b),
3749         SH_PFC_PIN_GROUP(ssi5_data),
3750         SH_PFC_PIN_GROUP(ssi5_ctrl),
3751         SH_PFC_PIN_GROUP(ssi5_data_b),
3752         SH_PFC_PIN_GROUP(ssi5_ctrl_b),
3753         SH_PFC_PIN_GROUP(ssi6_data),
3754         SH_PFC_PIN_GROUP(ssi6_ctrl),
3755         SH_PFC_PIN_GROUP(ssi6_data_b),
3756         SH_PFC_PIN_GROUP(ssi6_ctrl_b),
3757         SH_PFC_PIN_GROUP(ssi7_data),
3758         SH_PFC_PIN_GROUP(ssi78_ctrl),
3759         SH_PFC_PIN_GROUP(ssi7_data_b),
3760         SH_PFC_PIN_GROUP(ssi78_ctrl_b),
3761         SH_PFC_PIN_GROUP(ssi8_data),
3762         SH_PFC_PIN_GROUP(ssi8_data_b),
3763         SH_PFC_PIN_GROUP(ssi9_data),
3764         SH_PFC_PIN_GROUP(ssi9_ctrl),
3765         SH_PFC_PIN_GROUP(ssi9_data_b),
3766         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
3767         SH_PFC_PIN_GROUP(usb0),
3768         SH_PFC_PIN_GROUP(usb1),
3769         VIN_DATA_PIN_GROUP(vin0_data, 24),
3770         VIN_DATA_PIN_GROUP(vin0_data, 20),
3771         SH_PFC_PIN_GROUP(vin0_data18),
3772         VIN_DATA_PIN_GROUP(vin0_data, 16),
3773         VIN_DATA_PIN_GROUP(vin0_data, 12),
3774         VIN_DATA_PIN_GROUP(vin0_data, 10),
3775         VIN_DATA_PIN_GROUP(vin0_data, 8),
3776         SH_PFC_PIN_GROUP(vin0_sync),
3777         SH_PFC_PIN_GROUP(vin0_field),
3778         SH_PFC_PIN_GROUP(vin0_clkenb),
3779         SH_PFC_PIN_GROUP(vin0_clk),
3780         VIN_DATA_PIN_GROUP(vin1_data, 12),
3781         VIN_DATA_PIN_GROUP(vin1_data, 10),
3782         VIN_DATA_PIN_GROUP(vin1_data, 8),
3783         SH_PFC_PIN_GROUP(vin1_sync),
3784         SH_PFC_PIN_GROUP(vin1_field),
3785         SH_PFC_PIN_GROUP(vin1_clkenb),
3786         SH_PFC_PIN_GROUP(vin1_clk),
3787 };
3788
3789 static const char * const audio_clk_groups[] = {
3790         "audio_clka",
3791         "audio_clka_b",
3792         "audio_clka_c",
3793         "audio_clka_d",
3794         "audio_clkb",
3795         "audio_clkb_b",
3796         "audio_clkb_c",
3797         "audio_clkc",
3798         "audio_clkc_b",
3799         "audio_clkc_c",
3800         "audio_clkout",
3801         "audio_clkout_b",
3802         "audio_clkout_c",
3803 };
3804
3805 static const char * const avb_groups[] = {
3806         "avb_link",
3807         "avb_magic",
3808         "avb_phy_int",
3809         "avb_mdio",
3810         "avb_mii",
3811         "avb_gmii",
3812         "avb_avtp_capture",
3813         "avb_avtp_match",
3814         "avb_avtp_capture_b",
3815         "avb_avtp_match_b",
3816 };
3817
3818 static const char * const du0_groups[] = {
3819         "du0_rgb666",
3820         "du0_rgb888",
3821         "du0_clk0_out",
3822         "du0_clk1_out",
3823         "du0_clk_in",
3824         "du0_sync",
3825         "du0_oddf",
3826         "du0_cde",
3827         "du0_disp",
3828 };
3829
3830 static const char * const du1_groups[] = {
3831         "du1_rgb666",
3832         "du1_rgb888",
3833         "du1_clk0_out",
3834         "du1_clk1_out",
3835         "du1_clk_in",
3836         "du1_sync",
3837         "du1_oddf",
3838         "du1_cde",
3839         "du1_disp",
3840 };
3841
3842 static const char * const eth_groups[] = {
3843         "eth_link",
3844         "eth_magic",
3845         "eth_mdio",
3846         "eth_rmii",
3847         "eth_link_b",
3848         "eth_magic_b",
3849         "eth_mdio_b",
3850         "eth_rmii_b",
3851 };
3852
3853 static const char * const hscif0_groups[] = {
3854         "hscif0_data",
3855         "hscif0_clk",
3856         "hscif0_ctrl",
3857         "hscif0_data_b",
3858         "hscif0_clk_b",
3859 };
3860
3861 static const char * const hscif1_groups[] = {
3862         "hscif1_data",
3863         "hscif1_clk",
3864         "hscif1_ctrl",
3865         "hscif1_data_b",
3866         "hscif1_ctrl_b",
3867 };
3868
3869 static const char * const hscif2_groups[] = {
3870         "hscif2_data",
3871         "hscif2_clk",
3872         "hscif2_ctrl",
3873 };
3874
3875 static const char * const i2c0_groups[] = {
3876         "i2c0",
3877         "i2c0_b",
3878         "i2c0_c",
3879         "i2c0_d",
3880         "i2c0_e",
3881 };
3882
3883 static const char * const i2c1_groups[] = {
3884         "i2c1",
3885         "i2c1_b",
3886         "i2c1_c",
3887         "i2c1_d",
3888         "i2c1_e",
3889 };
3890
3891 static const char * const i2c2_groups[] = {
3892         "i2c2",
3893         "i2c2_b",
3894         "i2c2_c",
3895         "i2c2_d",
3896         "i2c2_e",
3897 };
3898
3899 static const char * const i2c3_groups[] = {
3900         "i2c3",
3901         "i2c3_b",
3902         "i2c3_c",
3903         "i2c3_d",
3904         "i2c3_e",
3905 };
3906
3907 static const char * const i2c4_groups[] = {
3908         "i2c4",
3909         "i2c4_b",
3910         "i2c4_c",
3911         "i2c4_d",
3912         "i2c4_e",
3913 };
3914
3915 static const char * const intc_groups[] = {
3916         "intc_irq0",
3917         "intc_irq1",
3918         "intc_irq2",
3919         "intc_irq3",
3920         "intc_irq4",
3921         "intc_irq5",
3922         "intc_irq6",
3923         "intc_irq7",
3924         "intc_irq8",
3925         "intc_irq9",
3926 };
3927
3928 static const char * const mmc_groups[] = {
3929         "mmc_data1",
3930         "mmc_data4",
3931         "mmc_data8",
3932         "mmc_ctrl",
3933 };
3934
3935 static const char * const msiof0_groups[] = {
3936         "msiof0_clk",
3937         "msiof0_sync",
3938         "msiof0_ss1",
3939         "msiof0_ss2",
3940         "msiof0_rx",
3941         "msiof0_tx",
3942 };
3943
3944 static const char * const msiof1_groups[] = {
3945         "msiof1_clk",
3946         "msiof1_sync",
3947         "msiof1_ss1",
3948         "msiof1_ss2",
3949         "msiof1_rx",
3950         "msiof1_tx",
3951         "msiof1_clk_b",
3952         "msiof1_sync_b",
3953         "msiof1_ss1_b",
3954         "msiof1_ss2_b",
3955         "msiof1_rx_b",
3956         "msiof1_tx_b",
3957 };
3958
3959 static const char * const msiof2_groups[] = {
3960         "msiof2_clk",
3961         "msiof2_sync",
3962         "msiof2_ss1",
3963         "msiof2_ss2",
3964         "msiof2_rx",
3965         "msiof2_tx",
3966         "msiof2_clk_b",
3967         "msiof2_sync_b",
3968         "msiof2_ss1_b",
3969         "msiof2_ss2_b",
3970         "msiof2_rx_b",
3971         "msiof2_tx_b",
3972 };
3973
3974 static const char * const qspi_groups[] = {
3975         "qspi_ctrl",
3976         "qspi_data2",
3977         "qspi_data4",
3978 };
3979
3980 static const char * const scif0_groups[] = {
3981         "scif0_data",
3982         "scif0_data_b",
3983         "scif0_data_c",
3984         "scif0_data_d",
3985 };
3986
3987 static const char * const scif1_groups[] = {
3988         "scif1_data",
3989         "scif1_clk",
3990         "scif1_data_b",
3991         "scif1_clk_b",
3992         "scif1_data_c",
3993         "scif1_clk_c",
3994 };
3995
3996 static const char * const scif2_groups[] = {
3997         "scif2_data",
3998         "scif2_clk",
3999         "scif2_data_b",
4000         "scif2_clk_b",
4001         "scif2_data_c",
4002         "scif2_clk_c",
4003 };
4004
4005 static const char * const scif3_groups[] = {
4006         "scif3_data",
4007         "scif3_clk",
4008         "scif3_data_b",
4009         "scif3_clk_b",
4010 };
4011
4012 static const char * const scif4_groups[] = {
4013         "scif4_data",
4014         "scif4_data_b",
4015         "scif4_data_c",
4016         "scif4_data_d",
4017         "scif4_data_e",
4018 };
4019
4020 static const char * const scif5_groups[] = {
4021         "scif5_data",
4022         "scif5_data_b",
4023         "scif5_data_c",
4024         "scif5_data_d",
4025 };
4026
4027 static const char * const scifa0_groups[] = {
4028         "scifa0_data",
4029         "scifa0_data_b",
4030         "scifa0_data_c",
4031         "scifa0_data_d",
4032 };
4033
4034 static const char * const scifa1_groups[] = {
4035         "scifa1_data",
4036         "scifa1_clk",
4037         "scifa1_data_b",
4038         "scifa1_clk_b",
4039         "scifa1_data_c",
4040         "scifa1_clk_c",
4041 };
4042
4043 static const char * const scifa2_groups[] = {
4044         "scifa2_data",
4045         "scifa2_clk",
4046         "scifa2_data_b",
4047         "scifa2_clk_b",
4048 };
4049
4050 static const char * const scifa3_groups[] = {
4051         "scifa3_data",
4052         "scifa3_clk",
4053         "scifa3_data_b",
4054         "scifa3_clk_b",
4055 };
4056
4057 static const char * const scifa4_groups[] = {
4058         "scifa4_data",
4059         "scifa4_data_b",
4060         "scifa4_data_c",
4061         "scifa4_data_d",
4062 };
4063
4064 static const char * const scifa5_groups[] = {
4065         "scifa5_data",
4066         "scifa5_data_b",
4067         "scifa5_data_c",
4068         "scifa5_data_d",
4069 };
4070
4071 static const char * const scifb0_groups[] = {
4072         "scifb0_data",
4073         "scifb0_clk",
4074         "scifb0_ctrl",
4075 };
4076
4077 static const char * const scifb1_groups[] = {
4078         "scifb1_data",
4079         "scifb1_clk",
4080 };
4081
4082 static const char * const scifb2_groups[] = {
4083         "scifb2_data",
4084         "scifb2_clk",
4085         "scifb2_ctrl",
4086 };
4087
4088 static const char * const scif_clk_groups[] = {
4089         "scif_clk",
4090         "scif_clk_b",
4091 };
4092
4093 static const char * const sdhi0_groups[] = {
4094         "sdhi0_data1",
4095         "sdhi0_data4",
4096         "sdhi0_ctrl",
4097         "sdhi0_cd",
4098         "sdhi0_wp",
4099 };
4100
4101 static const char * const sdhi1_groups[] = {
4102         "sdhi1_data1",
4103         "sdhi1_data4",
4104         "sdhi1_ctrl",
4105         "sdhi1_cd",
4106         "sdhi1_wp",
4107 };
4108
4109 static const char * const sdhi2_groups[] = {
4110         "sdhi2_data1",
4111         "sdhi2_data4",
4112         "sdhi2_ctrl",
4113         "sdhi2_cd",
4114         "sdhi2_wp",
4115 };
4116
4117 static const char * const ssi_groups[] = {
4118         "ssi0_data",
4119         "ssi0129_ctrl",
4120         "ssi1_data",
4121         "ssi1_ctrl",
4122         "ssi1_data_b",
4123         "ssi1_ctrl_b",
4124         "ssi2_data",
4125         "ssi2_ctrl",
4126         "ssi2_data_b",
4127         "ssi2_ctrl_b",
4128         "ssi3_data",
4129         "ssi34_ctrl",
4130         "ssi4_data",
4131         "ssi4_ctrl",
4132         "ssi4_data_b",
4133         "ssi4_ctrl_b",
4134         "ssi5_data",
4135         "ssi5_ctrl",
4136         "ssi5_data_b",
4137         "ssi5_ctrl_b",
4138         "ssi6_data",
4139         "ssi6_ctrl",
4140         "ssi6_data_b",
4141         "ssi6_ctrl_b",
4142         "ssi7_data",
4143         "ssi78_ctrl",
4144         "ssi7_data_b",
4145         "ssi78_ctrl_b",
4146         "ssi8_data",
4147         "ssi8_data_b",
4148         "ssi9_data",
4149         "ssi9_ctrl",
4150         "ssi9_data_b",
4151         "ssi9_ctrl_b",
4152 };
4153
4154 static const char * const usb0_groups[] = {
4155         "usb0",
4156 };
4157
4158 static const char * const usb1_groups[] = {
4159         "usb1",
4160 };
4161
4162 static const char * const vin0_groups[] = {
4163         "vin0_data24",
4164         "vin0_data20",
4165         "vin0_data18",
4166         "vin0_data16",
4167         "vin0_data12",
4168         "vin0_data10",
4169         "vin0_data8",
4170         "vin0_sync",
4171         "vin0_field",
4172         "vin0_clkenb",
4173         "vin0_clk",
4174 };
4175
4176 static const char * const vin1_groups[] = {
4177         "vin1_data12",
4178         "vin1_data10",
4179         "vin1_data8",
4180         "vin1_sync",
4181         "vin1_field",
4182         "vin1_clkenb",
4183         "vin1_clk",
4184 };
4185
4186 static const struct sh_pfc_function pinmux_functions[] = {
4187         SH_PFC_FUNCTION(audio_clk),
4188         SH_PFC_FUNCTION(avb),
4189         SH_PFC_FUNCTION(du0),
4190         SH_PFC_FUNCTION(du1),
4191         SH_PFC_FUNCTION(eth),
4192         SH_PFC_FUNCTION(hscif0),
4193         SH_PFC_FUNCTION(hscif1),
4194         SH_PFC_FUNCTION(hscif2),
4195         SH_PFC_FUNCTION(i2c0),
4196         SH_PFC_FUNCTION(i2c1),
4197         SH_PFC_FUNCTION(i2c2),
4198         SH_PFC_FUNCTION(i2c3),
4199         SH_PFC_FUNCTION(i2c4),
4200         SH_PFC_FUNCTION(intc),
4201         SH_PFC_FUNCTION(mmc),
4202         SH_PFC_FUNCTION(msiof0),
4203         SH_PFC_FUNCTION(msiof1),
4204         SH_PFC_FUNCTION(msiof2),
4205         SH_PFC_FUNCTION(qspi),
4206         SH_PFC_FUNCTION(scif0),
4207         SH_PFC_FUNCTION(scif1),
4208         SH_PFC_FUNCTION(scif2),
4209         SH_PFC_FUNCTION(scif3),
4210         SH_PFC_FUNCTION(scif4),
4211         SH_PFC_FUNCTION(scif5),
4212         SH_PFC_FUNCTION(scifa0),
4213         SH_PFC_FUNCTION(scifa1),
4214         SH_PFC_FUNCTION(scifa2),
4215         SH_PFC_FUNCTION(scifa3),
4216         SH_PFC_FUNCTION(scifa4),
4217         SH_PFC_FUNCTION(scifa5),
4218         SH_PFC_FUNCTION(scifb0),
4219         SH_PFC_FUNCTION(scifb1),
4220         SH_PFC_FUNCTION(scifb2),
4221         SH_PFC_FUNCTION(scif_clk),
4222         SH_PFC_FUNCTION(sdhi0),
4223         SH_PFC_FUNCTION(sdhi1),
4224         SH_PFC_FUNCTION(sdhi2),
4225         SH_PFC_FUNCTION(ssi),
4226         SH_PFC_FUNCTION(usb0),
4227         SH_PFC_FUNCTION(usb1),
4228         SH_PFC_FUNCTION(vin0),
4229         SH_PFC_FUNCTION(vin1),
4230 };
4231
4232 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4233         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4234                 GP_0_31_FN, FN_IP2_17_16,
4235                 GP_0_30_FN, FN_IP2_15_14,
4236                 GP_0_29_FN, FN_IP2_13_12,
4237                 GP_0_28_FN, FN_IP2_11_10,
4238                 GP_0_27_FN, FN_IP2_9_8,
4239                 GP_0_26_FN, FN_IP2_7_6,
4240                 GP_0_25_FN, FN_IP2_5_4,
4241                 GP_0_24_FN, FN_IP2_3_2,
4242                 GP_0_23_FN, FN_IP2_1_0,
4243                 GP_0_22_FN, FN_IP1_31_30,
4244                 GP_0_21_FN, FN_IP1_29_28,
4245                 GP_0_20_FN, FN_IP1_27,
4246                 GP_0_19_FN, FN_IP1_26,
4247                 GP_0_18_FN, FN_A2,
4248                 GP_0_17_FN, FN_IP1_24,
4249                 GP_0_16_FN, FN_IP1_23_22,
4250                 GP_0_15_FN, FN_IP1_21_20,
4251                 GP_0_14_FN, FN_IP1_19_18,
4252                 GP_0_13_FN, FN_IP1_17_15,
4253                 GP_0_12_FN, FN_IP1_14_13,
4254                 GP_0_11_FN, FN_IP1_12_11,
4255                 GP_0_10_FN, FN_IP1_10_8,
4256                 GP_0_9_FN, FN_IP1_7_6,
4257                 GP_0_8_FN, FN_IP1_5_4,
4258                 GP_0_7_FN, FN_IP1_3_2,
4259                 GP_0_6_FN, FN_IP1_1_0,
4260                 GP_0_5_FN, FN_IP0_31_30,
4261                 GP_0_4_FN, FN_IP0_29_28,
4262                 GP_0_3_FN, FN_IP0_27_26,
4263                 GP_0_2_FN, FN_IP0_25,
4264                 GP_0_1_FN, FN_IP0_24,
4265                 GP_0_0_FN, FN_IP0_23_22, }
4266         },
4267         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4268                 0, 0,
4269                 0, 0,
4270                 0, 0,
4271                 0, 0,
4272                 0, 0,
4273                 0, 0,
4274                 GP_1_25_FN, FN_DACK0,
4275                 GP_1_24_FN, FN_IP7_31,
4276                 GP_1_23_FN, FN_IP4_1_0,
4277                 GP_1_22_FN, FN_WE1_N,
4278                 GP_1_21_FN, FN_WE0_N,
4279                 GP_1_20_FN, FN_IP3_31,
4280                 GP_1_19_FN, FN_IP3_30,
4281                 GP_1_18_FN, FN_IP3_29_27,
4282                 GP_1_17_FN, FN_IP3_26_24,
4283                 GP_1_16_FN, FN_IP3_23_21,
4284                 GP_1_15_FN, FN_IP3_20_18,
4285                 GP_1_14_FN, FN_IP3_17_15,
4286                 GP_1_13_FN, FN_IP3_14_13,
4287                 GP_1_12_FN, FN_IP3_12,
4288                 GP_1_11_FN, FN_IP3_11,
4289                 GP_1_10_FN, FN_IP3_10,
4290                 GP_1_9_FN, FN_IP3_9_8,
4291                 GP_1_8_FN, FN_IP3_7_6,
4292                 GP_1_7_FN, FN_IP3_5_4,
4293                 GP_1_6_FN, FN_IP3_3_2,
4294                 GP_1_5_FN, FN_IP3_1_0,
4295                 GP_1_4_FN, FN_IP2_31_30,
4296                 GP_1_3_FN, FN_IP2_29_27,
4297                 GP_1_2_FN, FN_IP2_26_24,
4298                 GP_1_1_FN, FN_IP2_23_21,
4299                 GP_1_0_FN, FN_IP2_20_18, }
4300         },
4301         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4302                 GP_2_31_FN, FN_IP6_7_6,
4303                 GP_2_30_FN, FN_IP6_5_4,
4304                 GP_2_29_FN, FN_IP6_3_2,
4305                 GP_2_28_FN, FN_IP6_1_0,
4306                 GP_2_27_FN, FN_IP5_31_30,
4307                 GP_2_26_FN, FN_IP5_29_28,
4308                 GP_2_25_FN, FN_IP5_27_26,
4309                 GP_2_24_FN, FN_IP5_25_24,
4310                 GP_2_23_FN, FN_IP5_23_22,
4311                 GP_2_22_FN, FN_IP5_21_20,
4312                 GP_2_21_FN, FN_IP5_19_18,
4313                 GP_2_20_FN, FN_IP5_17_16,
4314                 GP_2_19_FN, FN_IP5_15_14,
4315                 GP_2_18_FN, FN_IP5_13_12,
4316                 GP_2_17_FN, FN_IP5_11_9,
4317                 GP_2_16_FN, FN_IP5_8_6,
4318                 GP_2_15_FN, FN_IP5_5_4,
4319                 GP_2_14_FN, FN_IP5_3_2,
4320                 GP_2_13_FN, FN_IP5_1_0,
4321                 GP_2_12_FN, FN_IP4_31_30,
4322                 GP_2_11_FN, FN_IP4_29_28,
4323                 GP_2_10_FN, FN_IP4_27_26,
4324                 GP_2_9_FN, FN_IP4_25_23,
4325                 GP_2_8_FN, FN_IP4_22_20,
4326                 GP_2_7_FN, FN_IP4_19_18,
4327                 GP_2_6_FN, FN_IP4_17_16,
4328                 GP_2_5_FN, FN_IP4_15_14,
4329                 GP_2_4_FN, FN_IP4_13_12,
4330                 GP_2_3_FN, FN_IP4_11_10,
4331                 GP_2_2_FN, FN_IP4_9_8,
4332                 GP_2_1_FN, FN_IP4_7_5,
4333                 GP_2_0_FN, FN_IP4_4_2 }
4334         },
4335         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4336                 GP_3_31_FN, FN_IP8_22_20,
4337                 GP_3_30_FN, FN_IP8_19_17,
4338                 GP_3_29_FN, FN_IP8_16_15,
4339                 GP_3_28_FN, FN_IP8_14_12,
4340                 GP_3_27_FN, FN_IP8_11_9,
4341                 GP_3_26_FN, FN_IP8_8_6,
4342                 GP_3_25_FN, FN_IP8_5_3,
4343                 GP_3_24_FN, FN_IP8_2_0,
4344                 GP_3_23_FN, FN_IP7_29_27,
4345                 GP_3_22_FN, FN_IP7_26_24,
4346                 GP_3_21_FN, FN_IP7_23_21,
4347                 GP_3_20_FN, FN_IP7_20_18,
4348                 GP_3_19_FN, FN_IP7_17_15,
4349                 GP_3_18_FN, FN_IP7_14_12,
4350                 GP_3_17_FN, FN_IP7_11_9,
4351                 GP_3_16_FN, FN_IP7_8_6,
4352                 GP_3_15_FN, FN_IP7_5_3,
4353                 GP_3_14_FN, FN_IP7_2_0,
4354                 GP_3_13_FN, FN_IP6_31_29,
4355                 GP_3_12_FN, FN_IP6_28_26,
4356                 GP_3_11_FN, FN_IP6_25_23,
4357                 GP_3_10_FN, FN_IP6_22_20,
4358                 GP_3_9_FN, FN_IP6_19_17,
4359                 GP_3_8_FN, FN_IP6_16,
4360                 GP_3_7_FN, FN_IP6_15,
4361                 GP_3_6_FN, FN_IP6_14,
4362                 GP_3_5_FN, FN_IP6_13,
4363                 GP_3_4_FN, FN_IP6_12,
4364                 GP_3_3_FN, FN_IP6_11,
4365                 GP_3_2_FN, FN_IP6_10,
4366                 GP_3_1_FN, FN_IP6_9,
4367                 GP_3_0_FN, FN_IP6_8 }
4368         },
4369         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4370                 GP_4_31_FN, FN_IP11_17_16,
4371                 GP_4_30_FN, FN_IP11_15_14,
4372                 GP_4_29_FN, FN_IP11_13_11,
4373                 GP_4_28_FN, FN_IP11_10_8,
4374                 GP_4_27_FN, FN_IP11_7_6,
4375                 GP_4_26_FN, FN_IP11_5_3,
4376                 GP_4_25_FN, FN_IP11_2_0,
4377                 GP_4_24_FN, FN_IP10_31_30,
4378                 GP_4_23_FN, FN_IP10_29_27,
4379                 GP_4_22_FN, FN_IP10_26_24,
4380                 GP_4_21_FN, FN_IP10_23_21,
4381                 GP_4_20_FN, FN_IP10_20_18,
4382                 GP_4_19_FN, FN_IP10_17_15,
4383                 GP_4_18_FN, FN_IP10_14_12,
4384                 GP_4_17_FN, FN_IP10_11_9,
4385                 GP_4_16_FN, FN_IP10_8_6,
4386                 GP_4_15_FN, FN_IP10_5_3,
4387                 GP_4_14_FN, FN_IP10_2_0,
4388                 GP_4_13_FN, FN_IP9_30_28,
4389                 GP_4_12_FN, FN_IP9_27_25,
4390                 GP_4_11_FN, FN_IP9_24_22,
4391                 GP_4_10_FN, FN_IP9_21_19,
4392                 GP_4_9_FN, FN_IP9_18_17,
4393                 GP_4_8_FN, FN_IP9_16_15,
4394                 GP_4_7_FN, FN_IP9_14_12,
4395                 GP_4_6_FN, FN_IP9_11_9,
4396                 GP_4_5_FN, FN_IP9_8_6,
4397                 GP_4_4_FN, FN_IP9_5_3,
4398                 GP_4_3_FN, FN_IP9_2_0,
4399                 GP_4_2_FN, FN_IP8_31_29,
4400                 GP_4_1_FN, FN_IP8_28_26,
4401                 GP_4_0_FN, FN_IP8_25_23 }
4402         },
4403         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4404                 0, 0,
4405                 0, 0,
4406                 0, 0,
4407                 0, 0,
4408                 GP_5_27_FN, FN_USB1_OVC,
4409                 GP_5_26_FN, FN_USB1_PWEN,
4410                 GP_5_25_FN, FN_USB0_OVC,
4411                 GP_5_24_FN, FN_USB0_PWEN,
4412                 GP_5_23_FN, FN_IP13_26_24,
4413                 GP_5_22_FN, FN_IP13_23_21,
4414                 GP_5_21_FN, FN_IP13_20_18,
4415                 GP_5_20_FN, FN_IP13_17_15,
4416                 GP_5_19_FN, FN_IP13_14_12,
4417                 GP_5_18_FN, FN_IP13_11_9,
4418                 GP_5_17_FN, FN_IP13_8_6,
4419                 GP_5_16_FN, FN_IP13_5_3,
4420                 GP_5_15_FN, FN_IP13_2_0,
4421                 GP_5_14_FN, FN_IP12_29_27,
4422                 GP_5_13_FN, FN_IP12_26_24,
4423                 GP_5_12_FN, FN_IP12_23_21,
4424                 GP_5_11_FN, FN_IP12_20_18,
4425                 GP_5_10_FN, FN_IP12_17_15,
4426                 GP_5_9_FN, FN_IP12_14_13,
4427                 GP_5_8_FN, FN_IP12_12_11,
4428                 GP_5_7_FN, FN_IP12_10_9,
4429                 GP_5_6_FN, FN_IP12_8_6,
4430                 GP_5_5_FN, FN_IP12_5_3,
4431                 GP_5_4_FN, FN_IP12_2_0,
4432                 GP_5_3_FN, FN_IP11_29_27,
4433                 GP_5_2_FN, FN_IP11_26_24,
4434                 GP_5_1_FN, FN_IP11_23_21,
4435                 GP_5_0_FN, FN_IP11_20_18 }
4436         },
4437         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
4438                 0, 0,
4439                 0, 0,
4440                 0, 0,
4441                 0, 0,
4442                 0, 0,
4443                 0, 0,
4444                 GP_6_25_FN, FN_IP0_21_20,
4445                 GP_6_24_FN, FN_IP0_19_18,
4446                 GP_6_23_FN, FN_IP0_17,
4447                 GP_6_22_FN, FN_IP0_16,
4448                 GP_6_21_FN, FN_IP0_15,
4449                 GP_6_20_FN, FN_IP0_14,
4450                 GP_6_19_FN, FN_IP0_13,
4451                 GP_6_18_FN, FN_IP0_12,
4452                 GP_6_17_FN, FN_IP0_11,
4453                 GP_6_16_FN, FN_IP0_10,
4454                 GP_6_15_FN, FN_IP0_9_8,
4455                 GP_6_14_FN, FN_IP0_0,
4456                 GP_6_13_FN, FN_SD1_DATA3,
4457                 GP_6_12_FN, FN_SD1_DATA2,
4458                 GP_6_11_FN, FN_SD1_DATA1,
4459                 GP_6_10_FN, FN_SD1_DATA0,
4460                 GP_6_9_FN, FN_SD1_CMD,
4461                 GP_6_8_FN, FN_SD1_CLK,
4462                 GP_6_7_FN, FN_SD0_WP,
4463                 GP_6_6_FN, FN_SD0_CD,
4464                 GP_6_5_FN, FN_SD0_DATA3,
4465                 GP_6_4_FN, FN_SD0_DATA2,
4466                 GP_6_3_FN, FN_SD0_DATA1,
4467                 GP_6_2_FN, FN_SD0_DATA0,
4468                 GP_6_1_FN, FN_SD0_CMD,
4469                 GP_6_0_FN, FN_SD0_CLK }
4470         },
4471         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4472                              2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
4473                              2, 1, 1, 1, 1, 1, 1, 1, 1) {
4474                 /* IP0_31_30 [2] */
4475                 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
4476                 /* IP0_29_28 [2] */
4477                 FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
4478                 /* IP0_27_26 [2] */
4479                 FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
4480                 /* IP0_25 [1] */
4481                 FN_D2, FN_SCIFA3_TXD_B,
4482                 /* IP0_24 [1] */
4483                 FN_D1, FN_SCIFA3_RXD_B,
4484                 /* IP0_23_22 [2] */
4485                 FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
4486                 /* IP0_21_20 [2] */
4487                 FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
4488                 /* IP0_19_18 [2] */
4489                 FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
4490                 /* IP0_17 [1] */
4491                 FN_MMC_D5, FN_SD2_WP,
4492                 /* IP0_16 [1] */
4493                 FN_MMC_D4, FN_SD2_CD,
4494                 /* IP0_15 [1] */
4495                 FN_MMC_D3, FN_SD2_DATA3,
4496                 /* IP0_14 [1] */
4497                 FN_MMC_D2, FN_SD2_DATA2,
4498                 /* IP0_13 [1] */
4499                 FN_MMC_D1, FN_SD2_DATA1,
4500                 /* IP0_12 [1] */
4501                 FN_MMC_D0, FN_SD2_DATA0,
4502                 /* IP0_11 [1] */
4503                 FN_MMC_CMD, FN_SD2_CMD,
4504                 /* IP0_10 [1] */
4505                 FN_MMC_CLK, FN_SD2_CLK,
4506                 /* IP0_9_8 [2] */
4507                 FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
4508                 /* IP0_7 [1] */
4509                 0, 0,
4510                 /* IP0_6 [1] */
4511                 0, 0,
4512                 /* IP0_5 [1] */
4513                 0, 0,
4514                 /* IP0_4 [1] */
4515                 0, 0,
4516                 /* IP0_3 [1] */
4517                 0, 0,
4518                 /* IP0_2 [1] */
4519                 0, 0,
4520                 /* IP0_1 [1] */
4521                 0, 0,
4522                 /* IP0_0 [1] */
4523                 FN_SD1_CD, FN_CAN0_RX, }
4524         },
4525         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4526                              2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2,
4527                              2, 2) {
4528                 /* IP1_31_30 [2] */
4529                 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
4530                 /* IP1_29_28 [2] */
4531                 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
4532                 /* IP1_27 [1] */
4533                 FN_A4, FN_SCIFB0_TXD,
4534                 /* IP1_26 [1] */
4535                 FN_A3, FN_SCIFB0_SCK,
4536                 /* IP1_25 [1] */
4537                 0, 0,
4538                 /* IP1_24 [1] */
4539                 FN_A1, FN_SCIFB1_TXD,
4540                 /* IP1_23_22 [2] */
4541                 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
4542                 /* IP1_21_20 [2] */
4543                 FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, 0,
4544                 /* IP1_19_18 [2] */
4545                 FN_D14, FN_SCIFA1_RXD, FN_IIC0_SCL_B, 0,
4546                 /* IP1_17_15 [3] */
4547                 FN_D13, FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B,
4548                 0, 0, 0,
4549                 /* IP1_14_13 [2] */
4550                 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
4551                 /* IP1_12_11 [2] */
4552                 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
4553                 /* IP1_10_8 [3] */
4554                 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
4555                 0, 0, 0,
4556                 /* IP1_7_6 [2] */
4557                 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
4558                 /* IP1_5_4 [2] */
4559                 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
4560                 /* IP1_3_2 [2] */
4561                 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
4562                 /* IP1_1_0 [2] */
4563                 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, }
4564         },
4565         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4566                              2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
4567                 /* IP2_31_30 [2] */
4568                 FN_A20, FN_SPCLK, FN_MOUT1, 0,
4569                 /* IP2_29_27 [3] */
4570                 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
4571                 FN_MOUT0, 0, 0, 0,
4572                 /* IP2_26_24 [3] */
4573                 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
4574                 FN_AVB_AVTP_MATCH_B, 0, 0, 0,
4575                 /* IP2_23_21 [3] */
4576                 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
4577                 FN_AVB_AVTP_CAPTURE_B, 0, 0, 0,
4578                 /* IP2_20_18 [3] */
4579                 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
4580                 FN_VSP, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
4581                 /* IP2_17_16 [2] */
4582                 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
4583                 /* IP2_15_14 [2] */
4584                 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
4585                 /* IP2_13_12 [2] */
4586                 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
4587                 /* IP2_11_10 [2] */
4588                 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
4589                 /* IP2_9_8 [2] */
4590                 FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, 0,
4591                 /* IP2_7_6 [2] */
4592                 FN_A10, FN_MSIOF1_SCK, FN_IIC1_SCL_B, 0,
4593                 /* IP2_5_4 [2] */
4594                 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
4595                 /* IP2_3_2 [2] */
4596                 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
4597                 /* IP2_1_0 [2] */
4598                 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, }
4599         },
4600         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4601                              1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) {
4602                 /* IP3_31 [1] */
4603                 FN_RD_WR_N, FN_ATAG1_N,
4604                 /* IP3_30 [1] */
4605                 FN_RD_N, FN_ATACS11_N,
4606                 /* IP3_29_27 [3] */
4607                 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
4608                 FN_MTS_N_B, 0, 0,
4609                 /* IP3_26_24 [3] */
4610                 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
4611                 FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
4612                 /* IP3_23_21 [3] */
4613                 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
4614                 FN_RIF0_D0, FN_FMCLK, FN_SCIFB2_CTS_N, FN_SCKZ_B,
4615                 /* IP3_20_18 [3] */
4616                 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
4617                 FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B,
4618                 /* IP3_17_15 [3] */
4619                 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
4620                 FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, FN_SDATA_B,
4621                 /* IP3_14_13 [2] */
4622                 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
4623                 /* IP3_12 [1] */
4624                 FN_EX_CS0_N, FN_VI1_DATA10,
4625                 /* IP3_11 [1] */
4626                 FN_CS1_N_A26, FN_VI1_DATA9,
4627                 /* IP3_10 [1] */
4628                 FN_CS0_N, FN_VI1_DATA8,
4629                 /* IP3_9_8 [2] */
4630                 FN_A25, FN_SSL, FN_ATARD1_N, 0,
4631                 /* IP3_7_6 [2] */
4632                 FN_A24, FN_IO3, FN_EX_WAIT2, 0,
4633                 /* IP3_5_4 [2] */
4634                 FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N,
4635                 /* IP3_3_2 [2] */
4636                 FN_A22, FN_MISO_IO1, FN_MOUT5, FN_ATADIR1_N,
4637                 /* IP3_1_0 [2] */
4638                 FN_A21, FN_MOSI_IO0, FN_MOUT2, 0, }
4639         },
4640         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
4641                              2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
4642                 /* IP4_31_30 [2] */
4643                 FN_DU0_DG4, FN_LCDOUT12, FN_CC50_STATE12, 0,
4644                 /* IP4_29_28 [2] */
4645                 FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, 0,
4646                 /* IP4_27_26 [2] */
4647                 FN_DU0_DG2, FN_LCDOUT10, FN_CC50_STATE10, 0,
4648                 /* IP4_25_23 [3] */
4649                 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
4650                 FN_CC50_STATE9, 0, 0, 0,
4651                 /* IP4_22_20 [3] */
4652                 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
4653                 FN_CC50_STATE8, 0, 0, 0,
4654                 /* IP4_19_18 [2] */
4655                 FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, 0,
4656                 /* IP4_17_16 [2] */
4657                 FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, 0,
4658                 /* IP4_15_14 [2] */
4659                 FN_DU0_DR5, FN_LCDOUT21, FN_CC50_STATE5, 0,
4660                 /* IP4_13_12 [2] */
4661                 FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, 0,
4662                 /* IP4_11_10 [2] */
4663                 FN_DU0_DR3, FN_LCDOUT19, FN_CC50_STATE3, 0,
4664                 /* IP4_9_8 [2] */
4665                 FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, 0,
4666                 /* IP4_7_5 [3] */
4667                 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
4668                 FN_CC50_STATE1, 0, 0, 0,
4669                 /* IP4_4_2 [3] */
4670                 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
4671                 FN_CC50_STATE0, 0, 0, 0,
4672                 /* IP4_1_0 [2] */
4673                 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, }
4674         },
4675         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
4676                              2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
4677                 /* IP5_31_30 [2] */
4678                 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, 0,
4679                 /* IP5_29_28 [2] */
4680                 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_CC50_STATE26, 0,
4681                 /* IP5_27_26 [2] */
4682                 FN_DU0_DOTCLKOUT0, FN_QCLK, FN_CC50_STATE25, 0,
4683                 /* IP5_25_24 [2] */
4684                 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, 0,
4685                 /* IP5_23_22 [2] */
4686                 FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, 0,
4687                 /* IP5_21_20 [2] */
4688                 FN_DU0_DB6, FN_LCDOUT6, FN_CC50_STATE22, 0,
4689                 /* IP5_19_18 [2] */
4690                 FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, 0,
4691                 /* IP5_17_16 [2] */
4692                 FN_DU0_DB4, FN_LCDOUT4, FN_CC50_STATE20, 0,
4693                 /* IP5_15_14 [2] */
4694                 FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, 0,
4695                 /* IP5_13_12 [2] */
4696                 FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, 0,
4697                 /* IP5_11_9 [3] */
4698                 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
4699                 FN_CAN0_TX_C, FN_CC50_STATE17, 0, 0,
4700                 /* IP5_8_6 [3] */
4701                 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
4702                 FN_CAN0_RX_C, FN_CC50_STATE16, 0, 0,
4703                 /* IP5_5_4 [2] */
4704                 FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, 0,
4705                 /* IP5_3_2 [2] */
4706                 FN_DU0_DG6, FN_LCDOUT14, FN_CC50_STATE14, 0,
4707                 /* IP5_1_0 [2] */
4708                 FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, 0, }
4709         },
4710         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
4711                              3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
4712                              2, 2) {
4713                 /* IP6_31_29 [3] */
4714                 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D,
4715                 FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
4716                 /* IP6_28_26 [3] */
4717                 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
4718                 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
4719                 /* IP6_25_23 [3] */
4720                 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
4721                 FN_AVB_COL, 0, 0, 0,
4722                 /* IP6_22_20 [3] */
4723                 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
4724                 FN_AVB_RX_ER, 0, 0, 0,
4725                 /* IP6_19_17 [3] */
4726                 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
4727                 FN_AVB_RXD7, 0, 0, 0,
4728                 /* IP6_16 [1] */
4729                 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
4730                 /* IP6_15 [1] */
4731                 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
4732                 /* IP6_14 [1] */
4733                 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
4734                 /* IP6_13 [1] */
4735                 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
4736                 /* IP6_12 [1] */
4737                 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
4738                 /* IP6_11 [1] */
4739                 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
4740                 /* IP6_10 [1] */
4741                 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
4742                 /* IP6_9 [1] */
4743                 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
4744                 /* IP6_8 [1] */
4745                 FN_VI0_CLK, FN_AVB_RX_CLK,
4746                 /* IP6_7_6 [2] */
4747                 FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0,
4748                 /* IP6_5_4 [2] */
4749                 FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
4750                 /* IP6_3_2 [2] */
4751                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
4752                 0,
4753                 /* IP6_1_0 [2] */
4754                 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
4755         },
4756         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4757                              1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4758                 /* IP7_31 [1] */
4759                 FN_DREQ0_N, FN_SCIFB1_RXD,
4760                 /* IP7_30 [1] */
4761                 0, 0,
4762                 /* IP7_29_27 [3] */
4763                 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
4764                 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
4765                 /* IP7_26_24 [3] */
4766                 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
4767                 FN_SSI_SCK6_B, 0, 0, 0,
4768                 /* IP7_23_21 [3] */
4769                 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D,
4770                 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
4771                 /* IP7_20_18 [3] */
4772                 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D,
4773                 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
4774                 /* IP7_17_15 [3] */
4775                 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
4776                 FN_SSI_SCK5_B, 0, 0, 0,
4777                 /* IP7_14_12 [3] */
4778                 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
4779                 FN_AVB_TXD4, FN_ADICHS2, 0, 0,
4780                 /* IP7_11_9 [3] */
4781                 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
4782                 FN_AVB_TXD3, FN_ADICHS1, 0, 0,
4783                 /* IP7_8_6 [3] */
4784                 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
4785                 FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0,
4786                 /* IP7_5_3 [3] */
4787                 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
4788                 FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
4789                 /* IP7_2_0 [3] */
4790                 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D,
4791                 FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
4792         },
4793         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4794                              3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
4795                 /* IP8_31_29 [3] */
4796                 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
4797                 FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
4798                 /* IP8_28_26 [3] */
4799                 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
4800                 FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0,
4801                 /* IP8_25_23 [3] */
4802                 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
4803                 FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
4804                 /* IP8_22_20 [3] */
4805                 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
4806                 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
4807                 /* IP8_19_17 [3] */
4808                 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
4809                 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
4810                 /* IP8_16_15 [2] */
4811                 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
4812                 /* IP8_14_12 [3] */
4813                 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
4814                 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
4815                 /* IP8_11_9 [3] */
4816                 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
4817                 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
4818                 /* IP8_8_6 [3] */
4819                 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
4820                 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
4821                 /* IP8_5_3 [3] */
4822                 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
4823                 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
4824                 /* IP8_2_0 [3] */
4825                 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
4826                 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
4827         },
4828         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
4829                              1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) {
4830                 /* IP9_31 [1] */
4831                 0, 0,
4832                 /* IP9_30_28 [3] */
4833                 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
4834                 FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, 0,
4835                 /* IP9_27_25 [3] */
4836                 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
4837                 FN_SSI_WS1_B, FN_CAN_STEP0, FN_CC50_STATE33, 0,
4838                 /* IP9_24_22 [3] */
4839                 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
4840                 FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, 0,
4841                 /* IP9_21_19 [3] */
4842                 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
4843                 FN_REMOCON_B, FN_SPEEDIN_B, FN_VSP_B, 0,
4844                 /* IP9_18_17 [2] */
4845                 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
4846                 /* IP9_16_15 [2] */
4847                 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
4848                 /* IP9_14_12 [3] */
4849                 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
4850                 FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, 0,
4851                 /* IP9_11_9 [3] */
4852                 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
4853                 FN_RIF1_D0, FN_FMCLK_B, FN_RDS_CLK_B, 0,
4854                 /* IP9_8_6 [3] */
4855                 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
4856                 FN_RIF1_CLK, FN_BPFCLK_B, 0, 0,
4857                 /* IP9_5_3 [3] */
4858                 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
4859                 FN_RIF1_SYNC, FN_TPUTO1_C, 0, 0,
4860                 /* IP9_2_0 [3] */
4861                 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
4862                 FN_RIF1_D1_B, FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, }
4863         },
4864         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
4865                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4866                 /* IP10_31_30 [2] */
4867                 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
4868                 /* IP10_29_27 [3] */
4869                 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
4870                 FN_CAN_DEBUGOUT9, 0, 0, 0,
4871                 /* IP10_26_24 [3] */
4872                 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
4873                 FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, 0, 0,
4874                 /* IP10_23_21 [3] */
4875                 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
4876                 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7, FN_RDS_DATA_C,
4877                 /* IP10_20_18 [3] */
4878                 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
4879                 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C,
4880                 /* IP10_17_15 [3] */
4881                 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
4882                 FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
4883                 /* IP10_14_12 [3] */
4884                 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
4885                 FN_USB0_IDIN, FN_CAN_DEBUGOUT4, FN_CC50_STATE39, 0,
4886                 /* IP10_11_9 [3] */
4887                 FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
4888                 FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, 0,
4889                 /* IP10_8_6 [3] */
4890                 FN_SCIF2_RXD, FN_IIC1_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
4891                 FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, FN_CC50_STATE37, 0,
4892                 /* IP10_5_3 [3] */
4893                 FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
4894                 FN_CAN_DEBUGOUT1, FN_CC50_STATE36, 0, 0,
4895                 /* IP10_2_0 [3] */
4896                 FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
4897                 FN_CAN_DEBUGOUT0, FN_CC50_STATE35, 0, 0, }
4898         },
4899         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
4900                              2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
4901                 /* IP11_31_30 [2] */
4902                 0, 0, 0, 0,
4903                 /* IP11_29_27 [3] */
4904                 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
4905                 FN_AD_CLK_B, 0, 0, 0,
4906                 /* IP11_26_24 [3] */
4907                 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
4908                 FN_AD_DO_B, 0, 0, 0,
4909                 /* IP11_23_21 [3] */
4910                 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
4911                 FN_AD_DI_B, FN_PCMWE_N, 0, 0,
4912                 /* IP11_20_18 [3] */
4913                 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
4914                 FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
4915                 /* IP11_17_16 [2] */
4916                 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
4917                 /* IP11_15_14 [2] */
4918                 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
4919                 /* IP11_13_11 [3] */
4920                 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
4921                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
4922                 /* IP11_10_8 [3] */
4923                 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
4924                 FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0,
4925                 /* IP11_7_6 [2] */
4926                 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
4927                 FN_CAN_DEBUGOUT13,
4928                 /* IP11_5_3 [3] */
4929                 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
4930                 FN_CAN_DEBUGOUT12, 0, 0, 0,
4931                 /* IP11_2_0 [3] */
4932                 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
4933                 FN_CAN_DEBUGOUT11, 0, 0, 0, }
4934         },
4935         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
4936                              2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
4937                 /* IP12_31_30 [2] */
4938                 0, 0, 0, 0,
4939                 /* IP12_29_27 [3] */
4940                 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA,
4941                 FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0,
4942                 /* IP12_26_24 [3] */
4943                 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA,
4944                 FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0,
4945                 /* IP12_23_21 [3] */
4946                 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0,
4947                 FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0,
4948                 /* IP12_20_18 [3] */
4949                 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK,
4950                 FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, 0,
4951                 /* IP12_17_15 [3] */
4952                 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
4953                 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
4954                 /* IP12_14_13 [2] */
4955                 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, FN_IRD_SCK,
4956                 /* IP12_12_11 [2] */
4957                 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX,
4958                 /* IP12_10_9 [2] */
4959                 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX,
4960                 /* IP12_8_6 [3] */
4961                 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
4962                 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
4963                 /* IP12_5_3 [3] */
4964                 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
4965                 FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
4966                 /* IP12_2_0 [3] */
4967                 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
4968                 FN_AD_NCS_N_B, FN_DREQ1_N_B, 0, 0, }
4969         },
4970         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
4971                              1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4972                 /* IP13_31 [1] */
4973                 0, 0,
4974                 /* IP13_30 [1] */
4975                 0, 0,
4976                 /* IP13_29 [1] */
4977                 0, 0,
4978                 /* IP13_28 [1] */
4979                 0, 0,
4980                 /* IP13_27 [1] */
4981                 0, 0,
4982                 /* IP13_26_24 [3] */
4983                 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
4984                 FN_TS_SPSYNC_C, FN_RIF0_D1_B, FN_FMIN_E, FN_RDS_DATA_D,
4985                 /* IP13_23_21 [3] */
4986                 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
4987                 FN_TS_SDEN_C, FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D,
4988                 /* IP13_20_18 [3] */
4989                 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
4990                 FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B,
4991                 /* IP13_17_15 [3] */
4992                 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
4993                 FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, 0,
4994                 /* IP13_14_12 [3] */
4995                 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
4996                 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
4997                 /* IP13_11_9 [3] */
4998                 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
4999                 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
5000                 /* IP13_8_6 [3] */
5001                 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
5002                 FN_MTS_N, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
5003                 /* IP13_5_3 [2] */
5004                 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
5005                 FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
5006                 /* IP13_2_0 [3] */
5007                 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
5008                 FN_SCKZ, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
5009         },
5010         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5011                              2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3,
5012                              2, 1) {
5013                 /* SEL_ADG [2] */
5014                 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
5015                 /* SEL_ADI [1] */
5016                 FN_SEL_ADI_0, FN_SEL_ADI_1,
5017                 /* SEL_CAN [2] */
5018                 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
5019                 /* SEL_DARC [3] */
5020                 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
5021                 FN_SEL_DARC_4, 0, 0, 0,
5022                 /* SEL_DR0 [1] */
5023                 FN_SEL_DR0_0, FN_SEL_DR0_1,
5024                 /* SEL_DR1 [1] */
5025                 FN_SEL_DR1_0, FN_SEL_DR1_1,
5026                 /* SEL_DR2 [1] */
5027                 FN_SEL_DR2_0, FN_SEL_DR2_1,
5028                 /* SEL_DR3 [1] */
5029                 FN_SEL_DR3_0, FN_SEL_DR3_1,
5030                 /* SEL_ETH [1] */
5031                 FN_SEL_ETH_0, FN_SEL_ETH_1,
5032                 /* SLE_FSN [1] */
5033                 FN_SEL_FSN_0, FN_SEL_FSN_1,
5034                 /* SEL_IC200 [3] */
5035                 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
5036                 FN_SEL_I2C00_4, 0, 0, 0,
5037                 /* SEL_I2C01 [3] */
5038                 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
5039                 FN_SEL_I2C01_4, 0, 0, 0,
5040                 /* SEL_I2C02 [3] */
5041                 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
5042                 FN_SEL_I2C02_4, 0, 0, 0,
5043                 /* SEL_I2C03 [3] */
5044                 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
5045                 FN_SEL_I2C03_4, 0, 0, 0,
5046                 /* SEL_I2C04 [3] */
5047                 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
5048                 FN_SEL_I2C04_4, 0, 0, 0,
5049                 /* SEL_IIC00 [2] */
5050                 FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3,
5051                 /* SEL_AVB [1] */
5052                 FN_SEL_AVB_0, FN_SEL_AVB_1, }
5053         },
5054         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5055                              2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
5056                              2, 2, 2, 1, 1, 2) {
5057                 /* SEL_IEB [2] */
5058                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5059                 /* SEL_IIC0 [2] */
5060                 FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
5061                 /* SEL_LBS [1] */
5062                 FN_SEL_LBS_0, FN_SEL_LBS_1,
5063                 /* SEL_MSI1 [1] */
5064                 FN_SEL_MSI1_0, FN_SEL_MSI1_1,
5065                 /* SEL_MSI2 [1] */
5066                 FN_SEL_MSI2_0, FN_SEL_MSI2_1,
5067                 /* SEL_RAD [1] */
5068                 FN_SEL_RAD_0, FN_SEL_RAD_1,
5069                 /* SEL_RCN [1] */
5070                 FN_SEL_RCN_0, FN_SEL_RCN_1,
5071                 /* SEL_RSP [1] */
5072                 FN_SEL_RSP_0, FN_SEL_RSP_1,
5073                 /* SEL_SCIFA0 [2] */
5074                 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
5075                 FN_SEL_SCIFA0_3,
5076                 /* SEL_SCIFA1 [2] */
5077                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
5078                 /* SEL_SCIFA2 [1] */
5079                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
5080                 /* SEL_SCIFA3 [1] */
5081                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
5082                 /* SEL_SCIFA4 [2] */
5083                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
5084                 FN_SEL_SCIFA4_3,
5085                 /* SEL_SCIFA5 [2] */
5086                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
5087                 FN_SEL_SCIFA5_3,
5088                 /* SEL_SPDM [1] */
5089                 FN_SEL_SPDM_0, FN_SEL_SPDM_1,
5090                 /* SEL_TMU [1] */
5091                 FN_SEL_TMU_0, FN_SEL_TMU_1,
5092                 /* SEL_TSIF0 [2] */
5093                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5094                 /* SEL_CAN0 [2] */
5095                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5096                 /* SEL_CAN1 [2] */
5097                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
5098                 /* SEL_HSCIF0 [1] */
5099                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
5100                 /* SEL_HSCIF1 [1] */
5101                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5102                 /* SEL_RDS [2] */
5103                 FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
5104         },
5105         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5106                              2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
5107                              1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
5108                 /* SEL_SCIF0 [2] */
5109                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
5110                 /* SEL_SCIF1 [2] */
5111                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
5112                 /* SEL_SCIF2 [2] */
5113                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
5114                 /* SEL_SCIF3 [1] */
5115                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
5116                 /* SEL_SCIF4 [3] */
5117                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
5118                 FN_SEL_SCIF4_4, 0, 0, 0,
5119                 /* SEL_SCIF5 [2] */
5120                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
5121                 /* SEL_SSI1 [1] */
5122                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
5123                 /* SEL_SSI2 [1] */
5124                 FN_SEL_SSI2_0, FN_SEL_SSI2_1,
5125                 /* SEL_SSI4 [1] */
5126                 FN_SEL_SSI4_0, FN_SEL_SSI4_1,
5127                 /* SEL_SSI5 [1] */
5128                 FN_SEL_SSI5_0, FN_SEL_SSI5_1,
5129                 /* SEL_SSI6 [1] */
5130                 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5131                 /* SEL_SSI7 [1] */
5132                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
5133                 /* SEL_SSI8 [1] */
5134                 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
5135                 /* SEL_SSI9 [1] */
5136                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
5137                 /* RESERVED [1] */
5138                 0, 0,
5139                 /* RESERVED [1] */
5140                 0, 0,
5141                 /* RESERVED [1] */
5142                 0, 0,
5143                 /* RESERVED [1] */
5144                 0, 0,
5145                 /* RESERVED [1] */
5146                 0, 0,
5147                 /* RESERVED [1] */
5148                 0, 0,
5149                 /* RESERVED [1] */
5150                 0, 0,
5151                 /* RESERVED [1] */
5152                 0, 0,
5153                 /* RESERVED [1] */
5154                 0, 0,
5155                 /* RESERVED [1] */
5156                 0, 0,
5157                 /* RESERVED [1] */
5158                 0, 0,
5159                 /* RESERVED [1] */
5160                 0, 0, }
5161         },
5162         { },
5163 };
5164
5165 static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5166 {
5167         *pocctrl = 0xe606006c;
5168
5169         switch (pin & 0x1f) {
5170         case 6: return 23;
5171         case 7: return 16;
5172         case 14: return 15;
5173         case 15: return 8;
5174         case 0 ... 5:
5175         case 8 ... 13:
5176                 return 22 - (pin & 0x1f);
5177         case 16 ... 23:
5178                 return 47 - (pin & 0x1f);
5179         }
5180
5181         return -EINVAL;
5182 }
5183
5184 static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
5185         .pin_to_pocctrl = r8a7794_pin_to_pocctrl,
5186 };
5187
5188 const struct sh_pfc_soc_info r8a7794_pinmux_info = {
5189         .name = "r8a77940_pfc",
5190         .ops = &r8a7794_pinmux_ops,
5191         .unlock_reg = 0xe6060000, /* PMMR */
5192
5193         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5194
5195         .pins = pinmux_pins,
5196         .nr_pins = ARRAY_SIZE(pinmux_pins),
5197         .groups = pinmux_groups,
5198         .nr_groups = ARRAY_SIZE(pinmux_groups),
5199         .functions = pinmux_functions,
5200         .nr_functions = ARRAY_SIZE(pinmux_functions),
5201
5202         .cfg_regs = pinmux_config_regs,
5203
5204         .pinmux_data = pinmux_data,
5205         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5206 };