drivers/spi/spi-bcm2835aux.c

   1 /*
   2  * Driver for Broadcom BCM2835 auxiliary SPI Controllers
   3  *
   4  * the driver does not rely on the native chipselects at all
   5  * but only uses the gpio type chipselects
   6  *
   7  * Based on: spi-bcm2835.c
   8  *
   9  * Copyright (C) 2015 Martin Sperl
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  */
  21
  22 #include <linux/clk.h>
  23 #include <linux/completion.h>
  24 #include <linux/delay.h>
  25 #include <linux/err.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/of.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_device.h>
  33 #include <linux/of_gpio.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/regmap.h>
  36 #include <linux/spi/spi.h>
  37 #include <linux/spinlock.h>
  38
  39 /*
  40  * spi register defines
  41  *
  42  * note there is garbage in the "official" documentation,
  43  * so some data is taken from the file:
  44  *   brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
  45  * inside of:
  46  *   http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
  47  */
  48
  49 /* SPI register offsets */
  50 #define BCM2835_AUX_SPI_CNTL0   0x00
  51 #define BCM2835_AUX_SPI_CNTL1   0x04
  52 #define BCM2835_AUX_SPI_STAT    0x08
  53 #define BCM2835_AUX_SPI_PEEK    0x0C
  54 #define BCM2835_AUX_SPI_IO      0x20
  55 #define BCM2835_AUX_SPI_TXHOLD  0x30
  56
  57 /* Bitfields in CNTL0 */
  58 #define BCM2835_AUX_SPI_CNTL0_SPEED     0xFFF00000
  59 #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF
  60 #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT       20
  61 #define BCM2835_AUX_SPI_CNTL0_CS        0x000E0000
  62 #define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000
  63 #define BCM2835_AUX_SPI_CNTL0_VAR_CS    0x00008000
  64 #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000
  65 #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD  0x00003000
  66 #define BCM2835_AUX_SPI_CNTL0_ENABLE    0x00000800
  67 #define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400
  68 #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200
  69 #define BCM2835_AUX_SPI_CNTL0_OUT_RISING        0x00000100
  70 #define BCM2835_AUX_SPI_CNTL0_CPOL      0x00000080
  71 #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT  0x00000040
  72 #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN  0x0000003F
  73
  74 /* Bitfields in CNTL1 */
  75 #define BCM2835_AUX_SPI_CNTL1_CSHIGH    0x00000700
  76 #define BCM2835_AUX_SPI_CNTL1_TXEMPTY   0x00000080
  77 #define BCM2835_AUX_SPI_CNTL1_IDLE      0x00000040
  78 #define BCM2835_AUX_SPI_CNTL1_MSBF_IN   0x00000002
  79 #define BCM2835_AUX_SPI_CNTL1_KEEP_IN   0x00000001
  80
  81 /* Bitfields in STAT */
  82 #define BCM2835_AUX_SPI_STAT_TX_LVL     0xFF000000
  83 #define BCM2835_AUX_SPI_STAT_RX_LVL     0x00FF0000
  84 #define BCM2835_AUX_SPI_STAT_TX_FULL    0x00000400
  85 #define BCM2835_AUX_SPI_STAT_TX_EMPTY   0x00000200
  86 #define BCM2835_AUX_SPI_STAT_RX_FULL    0x00000100
  87 #define BCM2835_AUX_SPI_STAT_RX_EMPTY   0x00000080
  88 #define BCM2835_AUX_SPI_STAT_BUSY       0x00000040
  89 #define BCM2835_AUX_SPI_STAT_BITCOUNT   0x0000003F
  90
  91 /* timeout values */
  92 #define BCM2835_AUX_SPI_POLLING_LIMIT_US        30
  93 #define BCM2835_AUX_SPI_POLLING_JIFFIES         2
  94
  95 struct bcm2835aux_spi {
  96         void __iomem *regs;
  97         struct clk *clk;
  98         int irq;
  99         u32 cntl[2];
 100         const u8 *tx_buf;
 101         u8 *rx_buf;
 102         int tx_len;
 103         int rx_len;
 104         int pending;
 105 };
 106
 107 static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg)
 108 {
 109         return readl(bs->regs + reg);
 110 }
 111
 112 static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg,
 113                                  u32 val)
 114 {
 115         writel(val, bs->regs + reg);
 116 }
 117
 118 static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
 119 {
 120         u32 data;
 121         int count = min(bs->rx_len, 3);
 122
 123         data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
 124         if (bs->rx_buf) {
 125                 switch (count) {
 126                 case 4:
 127                         *bs->rx_buf++ = (data >> 24) & 0xff;
 128                         /* fallthrough */
 129                 case 3:
 130                         *bs->rx_buf++ = (data >> 16) & 0xff;
 131                         /* fallthrough */
 132                 case 2:
 133                         *bs->rx_buf++ = (data >> 8) & 0xff;
 134                         /* fallthrough */
 135                 case 1:
 136                         *bs->rx_buf++ = (data >> 0) & 0xff;
 137                         /* fallthrough - no default */
 138                 }
 139         }
 140         bs->rx_len -= count;
 141         bs->pending -= count;
 142 }
 143
 144 static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
 145 {
 146         u32 data;
 147         u8 byte;
 148         int count;
 149         int i;
 150
 151         /* gather up to 3 bytes to write to the FIFO */
 152         count = min(bs->tx_len, 3);
 153         data = 0;
 154         for (i = 0; i < count; i++) {
 155                 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
 156                 data |= byte << (8 * (2 - i));
 157         }
 158
 159         /* and set the variable bit-length */
 160         data |= (count * 8) << 24;
 161
 162         /* and decrement length */
 163         bs->tx_len -= count;
 164         bs->pending += count;
 165
 166         /* write to the correct TX-register */
 167         if (bs->tx_len)
 168                 bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
 169         else
 170                 bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
 171 }
 172
 173 static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
 174 {
 175         /* disable spi clearing fifo and interrupts */
 176         bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
 177         bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
 178                       BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
 179 }
 180
 181 static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
 182 {
 183         struct spi_master *master = dev_id;
 184         struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 185         irqreturn_t ret = IRQ_NONE;
 186
 187         /* IRQ may be shared, so return if our interrupts are disabled */
 188         if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
 189               (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))
 190                 return ret;
 191
 192         /* check if we have data to read */
 193         while (bs->rx_len &&
 194                (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
 195                   BCM2835_AUX_SPI_STAT_RX_EMPTY))) {
 196                 bcm2835aux_rd_fifo(bs);
 197                 ret = IRQ_HANDLED;
 198         }
 199
 200         /* check if we have data to write */
 201         while (bs->tx_len &&
 202                (bs->pending < 12) &&
 203                (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
 204                   BCM2835_AUX_SPI_STAT_TX_FULL))) {
 205                 bcm2835aux_wr_fifo(bs);
 206                 ret = IRQ_HANDLED;
 207         }
 208
 209         /* and check if we have reached "done" */
 210         while (bs->rx_len &&
 211                (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
 212                   BCM2835_AUX_SPI_STAT_BUSY))) {
 213                 bcm2835aux_rd_fifo(bs);
 214                 ret = IRQ_HANDLED;
 215         }
 216
 217         if (!bs->tx_len) {
 218                 /* disable tx fifo empty interrupt */
 219                 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
 220                         BCM2835_AUX_SPI_CNTL1_IDLE);
 221         }
 222
 223         /* and if rx_len is 0 then disable interrupts and wake up completion */
 224         if (!bs->rx_len) {
 225                 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
 226                 complete(&master->xfer_completion);
 227         }
 228
 229         /* and return */
 230         return ret;
 231 }
 232
 233 static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
 234                                              struct spi_device *spi,
 235                                              struct spi_transfer *tfr)
 236 {
 237         struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 238
 239         /* enable interrupts */
 240         bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
 241                 BCM2835_AUX_SPI_CNTL1_TXEMPTY |
 242                 BCM2835_AUX_SPI_CNTL1_IDLE);
 243
 244         /* and wait for finish... */
 245         return 1;
 246 }
 247
 248 static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
 249                                            struct spi_device *spi,
 250                                            struct spi_transfer *tfr)
 251 {
 252         struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 253
 254         /* fill in registers and fifos before enabling interrupts */
 255         bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
 256         bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
 257
 258         /* fill in tx fifo with data before enabling interrupts */
 259         while ((bs->tx_len) &&
 260                (bs->pending < 12) &&
 261                (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
 262                   BCM2835_AUX_SPI_STAT_TX_FULL))) {
 263                 bcm2835aux_wr_fifo(bs);
 264         }
 265
 266         /* now run the interrupt mode */
 267         return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
 268 }
 269
 270 static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
 271                                             struct spi_device *spi,
 272                                         struct spi_transfer *tfr)
 273 {
 274         struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 275         unsigned long timeout;
 276         u32 stat;
 277
 278         /* configure spi */
 279         bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
 280         bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
 281
 282         /* set the timeout */
 283         timeout = jiffies + BCM2835_AUX_SPI_POLLING_JIFFIES;
 284
 285         /* loop until finished the transfer */
 286         while (bs->rx_len) {
 287                 /* read status */
 288                 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);
 289
 290                 /* fill in tx fifo with remaining data */
 291                 if ((bs->tx_len) && (!(stat & BCM2835_AUX_SPI_STAT_TX_FULL))) {
 292                         bcm2835aux_wr_fifo(bs);
 293                         continue;
 294                 }
 295
 296                 /* read data from fifo for both cases */
 297                 if (!(stat & BCM2835_AUX_SPI_STAT_RX_EMPTY)) {
 298                         bcm2835aux_rd_fifo(bs);
 299                         continue;
 300                 }
 301                 if (!(stat & BCM2835_AUX_SPI_STAT_BUSY)) {
 302                         bcm2835aux_rd_fifo(bs);
 303                         continue;
 304                 }
 305
 306                 /* there is still data pending to read check the timeout */
 307                 if (bs->rx_len && time_after(jiffies, timeout)) {
 308                         dev_dbg_ratelimited(&spi->dev,
 309                                             "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
 310                                             jiffies - timeout,
 311                                             bs->tx_len, bs->rx_len);
 312                         /* forward to interrupt handler */
 313                         return __bcm2835aux_spi_transfer_one_irq(master,
 314                                                                spi, tfr);
 315                 }
 316         }
 317
 318         /* and return without waiting for completion */
 319         return 0;
 320 }
 321
 322 static int bcm2835aux_spi_transfer_one(struct spi_master *master,
 323                                        struct spi_device *spi,
 324                                        struct spi_transfer *tfr)
 325 {
 326         struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 327         unsigned long spi_hz, clk_hz, speed;
 328         unsigned long spi_used_hz;
 329
 330         /* calculate the registers to handle
 331          *
 332          * note that we use the variable data mode, which
 333          * is not optimal for longer transfers as we waste registers
 334          * resulting (potentially) in more interrupts when transferring
 335          * more than 12 bytes
 336          */
 337
 338         /* set clock */
 339         spi_hz = tfr->speed_hz;
 340         clk_hz = clk_get_rate(bs->clk);
 341
 342         if (spi_hz >= clk_hz / 2) {
 343                 speed = 0;
 344         } else if (spi_hz) {
 345                 speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
 346                 if (speed >  BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
 347                         speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
 348         } else { /* the slowest we can go */
 349                 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
 350         }
 351         /* mask out old speed from previous spi_transfer */
 352         bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);
 353         /* set the new speed */
 354         bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;
 355
 356         spi_used_hz = clk_hz / (2 * (speed + 1));
 357
 358         /* set transmit buffers and length */
 359         bs->tx_buf = tfr->tx_buf;
 360         bs->rx_buf = tfr->rx_buf;
 361         bs->tx_len = tfr->len;
 362         bs->rx_len = tfr->len;
 363         bs->pending = 0;
 364
 365         /* Calculate the estimated time in us the transfer runs.  Note that
 366          * there are are 2 idle clocks cycles after each chunk getting
 367          * transferred - in our case the chunk size is 3 bytes, so we
 368          * approximate this by 9 cycles/byte.  This is used to find the number
 369          * of Hz per byte per polling limit.  E.g., we can transfer 1 byte in
 370          * 30 µs per 300,000 Hz of bus clock.
 371          */
 372 #define HZ_PER_BYTE ((9 * 1000000) / BCM2835_AUX_SPI_POLLING_LIMIT_US)
 373         /* run in polling mode for short transfers */
 374         if (tfr->len < spi_used_hz / HZ_PER_BYTE)
 375                 return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);
 376
 377         /* run in interrupt mode for all others */
 378         return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
 379 #undef HZ_PER_BYTE
 380 }
 381
 382 static int bcm2835aux_spi_prepare_message(struct spi_master *master,
 383                                           struct spi_message *msg)
 384 {
 385         struct spi_device *spi = msg->spi;
 386         struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 387
 388         bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
 389                       BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
 390                       BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
 391         bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
 392
 393         /* handle all the modes */
 394         if (spi->mode & SPI_CPOL) {
 395                 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
 396                 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING;
 397         } else {
 398                 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING;
 399         }
 400         bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
 401         bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
 402
 403         return 0;
 404 }
 405
 406 static int bcm2835aux_spi_unprepare_message(struct spi_master *master,
 407                                             struct spi_message *msg)
 408 {
 409         struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 410
 411         bcm2835aux_spi_reset_hw(bs);
 412
 413         return 0;
 414 }
 415
 416 static void bcm2835aux_spi_handle_err(struct spi_master *master,
 417                                       struct spi_message *msg)
 418 {
 419         struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 420
 421         bcm2835aux_spi_reset_hw(bs);
 422 }
 423
 424 static int bcm2835aux_spi_probe(struct platform_device *pdev)
 425 {
 426         struct spi_master *master;
 427         struct bcm2835aux_spi *bs;
 428         struct resource *res;
 429         unsigned long clk_hz;
 430         int err;
 431
 432         master = spi_alloc_master(&pdev->dev, sizeof(*bs));
 433         if (!master) {
 434                 dev_err(&pdev->dev, "spi_alloc_master() failed\n");
 435                 return -ENOMEM;
 436         }
 437
 438         platform_set_drvdata(pdev, master);
 439         master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS);
 440         master->bits_per_word_mask = SPI_BPW_MASK(8);
 441         master->num_chipselect = -1;
 442         master->transfer_one = bcm2835aux_spi_transfer_one;
 443         master->handle_err = bcm2835aux_spi_handle_err;
 444         master->prepare_message = bcm2835aux_spi_prepare_message;
 445         master->unprepare_message = bcm2835aux_spi_unprepare_message;
 446         master->dev.of_node = pdev->dev.of_node;
 447
 448         bs = spi_master_get_devdata(master);
 449
 450         /* the main area */
 451         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 452         bs->regs = devm_ioremap_resource(&pdev->dev, res);
 453         if (IS_ERR(bs->regs)) {
 454                 err = PTR_ERR(bs->regs);
 455                 goto out_master_put;
 456         }
 457
 458         bs->clk = devm_clk_get(&pdev->dev, NULL);
 459         if ((!bs->clk) || (IS_ERR(bs->clk))) {
 460                 err = PTR_ERR(bs->clk);
 461                 dev_err(&pdev->dev, "could not get clk: %d\n", err);
 462                 goto out_master_put;
 463         }
 464
 465         bs->irq = platform_get_irq(pdev, 0);
 466         if (bs->irq <= 0) {
 467                 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
 468                 err = bs->irq ? bs->irq : -ENODEV;
 469                 goto out_master_put;
 470         }
 471
 472         /* this also enables the HW block */
 473         err = clk_prepare_enable(bs->clk);
 474         if (err) {
 475                 dev_err(&pdev->dev, "could not prepare clock: %d\n", err);
 476                 goto out_master_put;
 477         }
 478
 479         /* just checking if the clock returns a sane value */
 480         clk_hz = clk_get_rate(bs->clk);
 481         if (!clk_hz) {
 482                 dev_err(&pdev->dev, "clock returns 0 Hz\n");
 483                 err = -ENODEV;
 484                 goto out_clk_disable;
 485         }
 486
 487         /* reset SPI-HW block */
 488         bcm2835aux_spi_reset_hw(bs);
 489
 490         err = devm_request_irq(&pdev->dev, bs->irq,
 491                                bcm2835aux_spi_interrupt,
 492                                IRQF_SHARED,
 493                                dev_name(&pdev->dev), master);
 494         if (err) {
 495                 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
 496                 goto out_clk_disable;
 497         }
 498
 499         err = devm_spi_register_master(&pdev->dev, master);
 500         if (err) {
 501                 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
 502                 goto out_clk_disable;
 503         }
 504
 505         return 0;
 506
 507 out_clk_disable:
 508         clk_disable_unprepare(bs->clk);
 509 out_master_put:
 510         spi_master_put(master);
 511         return err;
 512 }
 513
 514 static int bcm2835aux_spi_remove(struct platform_device *pdev)
 515 {
 516         struct spi_master *master = platform_get_drvdata(pdev);
 517         struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 518
 519         bcm2835aux_spi_reset_hw(bs);
 520
 521         /* disable the HW block by releasing the clock */
 522         clk_disable_unprepare(bs->clk);
 523
 524         return 0;
 525 }
 526
 527 static const struct of_device_id bcm2835aux_spi_match[] = {
 528         { .compatible = "brcm,bcm2835-aux-spi", },
 529         {}
 530 };
 531 MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);
 532
 533 static struct platform_driver bcm2835aux_spi_driver = {
 534         .driver         = {
 535                 .name           = "spi-bcm2835aux",
 536                 .of_match_table = bcm2835aux_spi_match,
 537         },
 538         .probe          = bcm2835aux_spi_probe,
 539         .remove         = bcm2835aux_spi_remove,
 540 };
 541 module_platform_driver(bcm2835aux_spi_driver);
 542
 543 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
 544 MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
 545 MODULE_LICENSE("GPL");