1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
5 // Refer to drivers/dma/imx-sdma.c
7 #include <linux/init.h>
8 #include <linux/types.h>
10 #include <linux/interrupt.h>
11 #include <linux/clk.h>
12 #include <linux/wait.h>
13 #include <linux/sched.h>
14 #include <linux/semaphore.h>
15 #include <linux/device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/slab.h>
18 #include <linux/platform_device.h>
19 #include <linux/dmaengine.h>
20 #include <linux/delay.h>
21 #include <linux/module.h>
22 #include <linux/stmp_device.h>
24 #include <linux/of_device.h>
25 #include <linux/of_dma.h>
26 #include <linux/list.h>
27 #include <linux/dma/mxs-dma.h>
31 #include "dmaengine.h"
34 * NOTE: The term "PIO" throughout the mxs-dma implementation means
35 * PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
36 * dma can program the controller registers of peripheral devices.
39 #define dma_is_apbh(mxs_dma) ((mxs_dma)->type == MXS_DMA_APBH)
40 #define apbh_is_old(mxs_dma) ((mxs_dma)->dev_id == IMX23_DMA)
42 #define HW_APBHX_CTRL0 0x000
43 #define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
44 #define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
45 #define BP_APBH_CTRL0_RESET_CHANNEL 16
46 #define HW_APBHX_CTRL1 0x010
47 #define HW_APBHX_CTRL2 0x020
48 #define HW_APBHX_CHANNEL_CTRL 0x030
49 #define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
51 * The offset of NXTCMDAR register is different per both dma type and version,
52 * while stride for each channel is all the same 0x70.
54 #define HW_APBHX_CHn_NXTCMDAR(d, n) \
55 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x050 : 0x110) + (n) * 0x70)
56 #define HW_APBHX_CHn_SEMA(d, n) \
57 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x080 : 0x140) + (n) * 0x70)
58 #define HW_APBHX_CHn_BAR(d, n) \
59 (((dma_is_apbh(d) && apbh_is_old(d)) ? 0x070 : 0x130) + (n) * 0x70)
60 #define HW_APBX_CHn_DEBUG1(d, n) (0x150 + (n) * 0x70)
63 * ccw bits definitions
68 * NAND_LOCK: 4 (1) - not implemented
69 * NAND_WAIT4READY: 5 (1) - not implemented
72 * HALT_ON_TERMINATE: 8 (1)
73 * TERMINATE_FLUSH: 9 (1)
74 * RESERVED: 10..11 (2)
77 #define BP_CCW_COMMAND 0
78 #define BM_CCW_COMMAND (3 << 0)
79 #define CCW_CHAIN (1 << 2)
80 #define CCW_IRQ (1 << 3)
81 #define CCW_WAIT4RDY (1 << 5)
82 #define CCW_DEC_SEM (1 << 6)
83 #define CCW_WAIT4END (1 << 7)
84 #define CCW_HALT_ON_TERM (1 << 8)
85 #define CCW_TERM_FLUSH (1 << 9)
86 #define BP_CCW_PIO_NUM 12
87 #define BM_CCW_PIO_NUM (0xf << 12)
89 #define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
91 #define MXS_DMA_CMD_NO_XFER 0
92 #define MXS_DMA_CMD_WRITE 1
93 #define MXS_DMA_CMD_READ 2
94 #define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
100 #define MAX_XFER_BYTES 0xff00
102 #define MXS_PIO_WORDS 16
103 u32 pio_words
[MXS_PIO_WORDS
];
106 #define CCW_BLOCK_SIZE (4 * PAGE_SIZE)
107 #define NUM_CCW (int)(CCW_BLOCK_SIZE / sizeof(struct mxs_dma_ccw))
109 struct mxs_dma_chan
{
110 struct mxs_dma_engine
*mxs_dma
;
111 struct dma_chan chan
;
112 struct dma_async_tx_descriptor desc
;
113 struct tasklet_struct tasklet
;
114 unsigned int chan_irq
;
115 struct mxs_dma_ccw
*ccw
;
118 enum dma_status status
;
121 #define MXS_DMA_SG_LOOP (1 << 0)
122 #define MXS_DMA_USE_SEMAPHORE (1 << 1)
125 #define MXS_DMA_CHANNELS 16
126 #define MXS_DMA_CHANNELS_MASK 0xffff
128 enum mxs_dma_devtype
{
138 struct mxs_dma_engine
{
139 enum mxs_dma_id dev_id
;
140 enum mxs_dma_devtype type
;
143 struct dma_device dma_device
;
144 struct device_dma_parameters dma_parms
;
145 struct mxs_dma_chan mxs_chans
[MXS_DMA_CHANNELS
];
146 struct platform_device
*pdev
;
147 unsigned int nr_channels
;
150 struct mxs_dma_type
{
152 enum mxs_dma_devtype type
;
155 static struct mxs_dma_type mxs_dma_types
[] = {
158 .type
= MXS_DMA_APBH
,
161 .type
= MXS_DMA_APBX
,
164 .type
= MXS_DMA_APBH
,
167 .type
= MXS_DMA_APBX
,
171 static const struct platform_device_id mxs_dma_ids
[] = {
173 .name
= "imx23-dma-apbh",
174 .driver_data
= (kernel_ulong_t
) &mxs_dma_types
[0],
176 .name
= "imx23-dma-apbx",
177 .driver_data
= (kernel_ulong_t
) &mxs_dma_types
[1],
179 .name
= "imx28-dma-apbh",
180 .driver_data
= (kernel_ulong_t
) &mxs_dma_types
[2],
182 .name
= "imx28-dma-apbx",
183 .driver_data
= (kernel_ulong_t
) &mxs_dma_types
[3],
189 static const struct of_device_id mxs_dma_dt_ids
[] = {
190 { .compatible
= "fsl,imx23-dma-apbh", .data
= &mxs_dma_ids
[0], },
191 { .compatible
= "fsl,imx23-dma-apbx", .data
= &mxs_dma_ids
[1], },
192 { .compatible
= "fsl,imx28-dma-apbh", .data
= &mxs_dma_ids
[2], },
193 { .compatible
= "fsl,imx28-dma-apbx", .data
= &mxs_dma_ids
[3], },
196 MODULE_DEVICE_TABLE(of
, mxs_dma_dt_ids
);
198 static struct mxs_dma_chan
*to_mxs_dma_chan(struct dma_chan
*chan
)
200 return container_of(chan
, struct mxs_dma_chan
, chan
);
203 static void mxs_dma_reset_chan(struct dma_chan
*chan
)
205 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
206 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
207 int chan_id
= mxs_chan
->chan
.chan_id
;
210 * mxs dma channel resets can cause a channel stall. To recover from a
211 * channel stall, we have to reset the whole DMA engine. To avoid this,
212 * we use cyclic DMA with semaphores, that are enhanced in
213 * mxs_dma_int_handler. To reset the channel, we can simply stop writing
214 * into the semaphore counter.
216 if (mxs_chan
->flags
& MXS_DMA_USE_SEMAPHORE
&&
217 mxs_chan
->flags
& MXS_DMA_SG_LOOP
) {
218 mxs_chan
->reset
= true;
219 } else if (dma_is_apbh(mxs_dma
) && apbh_is_old(mxs_dma
)) {
220 writel(1 << (chan_id
+ BP_APBH_CTRL0_RESET_CHANNEL
),
221 mxs_dma
->base
+ HW_APBHX_CTRL0
+ STMP_OFFSET_REG_SET
);
223 unsigned long elapsed
= 0;
224 const unsigned long max_wait
= 50000; /* 50ms */
225 void __iomem
*reg_dbg1
= mxs_dma
->base
+
226 HW_APBX_CHn_DEBUG1(mxs_dma
, chan_id
);
229 * On i.MX28 APBX, the DMA channel can stop working if we reset
230 * the channel while it is in READ_FLUSH (0x08) state.
231 * We wait here until we leave the state. Then we trigger the
232 * reset. Waiting a maximum of 50ms, the kernel shouldn't crash
235 while ((readl(reg_dbg1
) & 0xf) == 0x8 && elapsed
< max_wait
) {
240 if (elapsed
>= max_wait
)
241 dev_err(&mxs_chan
->mxs_dma
->pdev
->dev
,
242 "Failed waiting for the DMA channel %d to leave state READ_FLUSH, trying to reset channel in READ_FLUSH state now\n",
245 writel(1 << (chan_id
+ BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL
),
246 mxs_dma
->base
+ HW_APBHX_CHANNEL_CTRL
+ STMP_OFFSET_REG_SET
);
249 mxs_chan
->status
= DMA_COMPLETE
;
252 static void mxs_dma_enable_chan(struct dma_chan
*chan
)
254 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
255 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
256 int chan_id
= mxs_chan
->chan
.chan_id
;
258 /* set cmd_addr up */
259 writel(mxs_chan
->ccw_phys
,
260 mxs_dma
->base
+ HW_APBHX_CHn_NXTCMDAR(mxs_dma
, chan_id
));
262 /* write 1 to SEMA to kick off the channel */
263 if (mxs_chan
->flags
& MXS_DMA_USE_SEMAPHORE
&&
264 mxs_chan
->flags
& MXS_DMA_SG_LOOP
) {
265 /* A cyclic DMA consists of at least 2 segments, so initialize
266 * the semaphore with 2 so we have enough time to add 1 to the
267 * semaphore if we need to */
268 writel(2, mxs_dma
->base
+ HW_APBHX_CHn_SEMA(mxs_dma
, chan_id
));
270 writel(1, mxs_dma
->base
+ HW_APBHX_CHn_SEMA(mxs_dma
, chan_id
));
272 mxs_chan
->reset
= false;
275 static void mxs_dma_disable_chan(struct dma_chan
*chan
)
277 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
279 mxs_chan
->status
= DMA_COMPLETE
;
282 static int mxs_dma_pause_chan(struct dma_chan
*chan
)
284 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
285 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
286 int chan_id
= mxs_chan
->chan
.chan_id
;
288 /* freeze the channel */
289 if (dma_is_apbh(mxs_dma
) && apbh_is_old(mxs_dma
))
291 mxs_dma
->base
+ HW_APBHX_CTRL0
+ STMP_OFFSET_REG_SET
);
294 mxs_dma
->base
+ HW_APBHX_CHANNEL_CTRL
+ STMP_OFFSET_REG_SET
);
296 mxs_chan
->status
= DMA_PAUSED
;
300 static int mxs_dma_resume_chan(struct dma_chan
*chan
)
302 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
303 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
304 int chan_id
= mxs_chan
->chan
.chan_id
;
306 /* unfreeze the channel */
307 if (dma_is_apbh(mxs_dma
) && apbh_is_old(mxs_dma
))
309 mxs_dma
->base
+ HW_APBHX_CTRL0
+ STMP_OFFSET_REG_CLR
);
312 mxs_dma
->base
+ HW_APBHX_CHANNEL_CTRL
+ STMP_OFFSET_REG_CLR
);
314 mxs_chan
->status
= DMA_IN_PROGRESS
;
318 static dma_cookie_t
mxs_dma_tx_submit(struct dma_async_tx_descriptor
*tx
)
320 return dma_cookie_assign(tx
);
323 static void mxs_dma_tasklet(unsigned long data
)
325 struct mxs_dma_chan
*mxs_chan
= (struct mxs_dma_chan
*) data
;
327 dmaengine_desc_get_callback_invoke(&mxs_chan
->desc
, NULL
);
330 static int mxs_dma_irq_to_chan(struct mxs_dma_engine
*mxs_dma
, int irq
)
334 for (i
= 0; i
!= mxs_dma
->nr_channels
; ++i
)
335 if (mxs_dma
->mxs_chans
[i
].chan_irq
== irq
)
341 static irqreturn_t
mxs_dma_int_handler(int irq
, void *dev_id
)
343 struct mxs_dma_engine
*mxs_dma
= dev_id
;
344 struct mxs_dma_chan
*mxs_chan
;
347 int chan
= mxs_dma_irq_to_chan(mxs_dma
, irq
);
352 /* completion status */
353 completed
= readl(mxs_dma
->base
+ HW_APBHX_CTRL1
);
354 completed
= (completed
>> chan
) & 0x1;
356 /* Clear interrupt */
358 mxs_dma
->base
+ HW_APBHX_CTRL1
+ STMP_OFFSET_REG_CLR
);
361 err
= readl(mxs_dma
->base
+ HW_APBHX_CTRL2
);
362 err
&= (1 << (MXS_DMA_CHANNELS
+ chan
)) | (1 << chan
);
365 * error status bit is in the upper 16 bits, error irq bit in the lower
366 * 16 bits. We transform it into a simpler error code:
367 * err: 0x00 = no error, 0x01 = TERMINATION, 0x02 = BUS_ERROR
369 err
= (err
>> (MXS_DMA_CHANNELS
+ chan
)) + (err
>> chan
);
371 /* Clear error irq */
373 mxs_dma
->base
+ HW_APBHX_CTRL2
+ STMP_OFFSET_REG_CLR
);
376 * When both completion and error of termination bits set at the
377 * same time, we do not take it as an error. IOW, it only becomes
378 * an error we need to handle here in case of either it's a bus
379 * error or a termination error with no completion. 0x01 is termination
380 * error, so we can subtract err & completed to get the real error case.
382 err
-= err
& completed
;
384 mxs_chan
= &mxs_dma
->mxs_chans
[chan
];
387 dev_dbg(mxs_dma
->dma_device
.dev
,
388 "%s: error in channel %d\n", __func__
,
390 mxs_chan
->status
= DMA_ERROR
;
391 mxs_dma_reset_chan(&mxs_chan
->chan
);
392 } else if (mxs_chan
->status
!= DMA_COMPLETE
) {
393 if (mxs_chan
->flags
& MXS_DMA_SG_LOOP
) {
394 mxs_chan
->status
= DMA_IN_PROGRESS
;
395 if (mxs_chan
->flags
& MXS_DMA_USE_SEMAPHORE
)
396 writel(1, mxs_dma
->base
+
397 HW_APBHX_CHn_SEMA(mxs_dma
, chan
));
399 mxs_chan
->status
= DMA_COMPLETE
;
403 if (mxs_chan
->status
== DMA_COMPLETE
) {
406 dma_cookie_complete(&mxs_chan
->desc
);
409 /* schedule tasklet on this channel */
410 tasklet_schedule(&mxs_chan
->tasklet
);
415 static int mxs_dma_alloc_chan_resources(struct dma_chan
*chan
)
417 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
418 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
421 mxs_chan
->ccw
= dma_alloc_coherent(mxs_dma
->dma_device
.dev
,
423 &mxs_chan
->ccw_phys
, GFP_KERNEL
);
424 if (!mxs_chan
->ccw
) {
429 ret
= request_irq(mxs_chan
->chan_irq
, mxs_dma_int_handler
,
430 0, "mxs-dma", mxs_dma
);
434 ret
= clk_prepare_enable(mxs_dma
->clk
);
438 mxs_dma_reset_chan(chan
);
440 dma_async_tx_descriptor_init(&mxs_chan
->desc
, chan
);
441 mxs_chan
->desc
.tx_submit
= mxs_dma_tx_submit
;
443 /* the descriptor is ready */
444 async_tx_ack(&mxs_chan
->desc
);
449 free_irq(mxs_chan
->chan_irq
, mxs_dma
);
451 dma_free_coherent(mxs_dma
->dma_device
.dev
, CCW_BLOCK_SIZE
,
452 mxs_chan
->ccw
, mxs_chan
->ccw_phys
);
457 static void mxs_dma_free_chan_resources(struct dma_chan
*chan
)
459 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
460 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
462 mxs_dma_disable_chan(chan
);
464 free_irq(mxs_chan
->chan_irq
, mxs_dma
);
466 dma_free_coherent(mxs_dma
->dma_device
.dev
, CCW_BLOCK_SIZE
,
467 mxs_chan
->ccw
, mxs_chan
->ccw_phys
);
469 clk_disable_unprepare(mxs_dma
->clk
);
473 * How to use the flags for ->device_prep_slave_sg() :
474 * [1] If there is only one DMA command in the DMA chain, the code should be:
476 * ->device_prep_slave_sg(DMA_CTRL_ACK);
478 * [2] If there are two DMA commands in the DMA chain, the code should be
480 * ->device_prep_slave_sg(0);
482 * ->device_prep_slave_sg(DMA_CTRL_ACK);
484 * [3] If there are more than two DMA commands in the DMA chain, the code
487 * ->device_prep_slave_sg(0); // First
489 * ->device_prep_slave_sg(DMA_CTRL_ACK]);
491 * ->device_prep_slave_sg(DMA_CTRL_ACK); // Last
494 static struct dma_async_tx_descriptor
*mxs_dma_prep_slave_sg(
495 struct dma_chan
*chan
, struct scatterlist
*sgl
,
496 unsigned int sg_len
, enum dma_transfer_direction direction
,
497 unsigned long flags
, void *context
)
499 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
500 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
501 struct mxs_dma_ccw
*ccw
;
502 struct scatterlist
*sg
;
507 if (mxs_chan
->status
== DMA_IN_PROGRESS
)
508 idx
= mxs_chan
->desc_count
;
510 if (sg_len
+ idx
> NUM_CCW
) {
511 dev_err(mxs_dma
->dma_device
.dev
,
512 "maximum number of sg exceeded: %d > %d\n",
517 mxs_chan
->status
= DMA_IN_PROGRESS
;
521 * If the sg is prepared with append flag set, the sg
522 * will be appended to the last prepared sg.
526 ccw
= &mxs_chan
->ccw
[idx
- 1];
527 ccw
->next
= mxs_chan
->ccw_phys
+ sizeof(*ccw
) * idx
;
528 ccw
->bits
|= CCW_CHAIN
;
529 ccw
->bits
&= ~CCW_IRQ
;
530 ccw
->bits
&= ~CCW_DEC_SEM
;
535 if (direction
== DMA_TRANS_NONE
) {
536 ccw
= &mxs_chan
->ccw
[idx
++];
539 for (j
= 0; j
< sg_len
;)
540 ccw
->pio_words
[j
++] = *pio
++;
543 ccw
->bits
|= CCW_IRQ
;
544 ccw
->bits
|= CCW_DEC_SEM
;
545 if (flags
& MXS_DMA_CTRL_WAIT4END
)
546 ccw
->bits
|= CCW_WAIT4END
;
547 ccw
->bits
|= CCW_HALT_ON_TERM
;
548 ccw
->bits
|= CCW_TERM_FLUSH
;
549 ccw
->bits
|= BF_CCW(sg_len
, PIO_NUM
);
550 ccw
->bits
|= BF_CCW(MXS_DMA_CMD_NO_XFER
, COMMAND
);
551 if (flags
& MXS_DMA_CTRL_WAIT4RDY
)
552 ccw
->bits
|= CCW_WAIT4RDY
;
554 for_each_sg(sgl
, sg
, sg_len
, i
) {
555 if (sg_dma_len(sg
) > MAX_XFER_BYTES
) {
556 dev_err(mxs_dma
->dma_device
.dev
, "maximum bytes for sg entry exceeded: %d > %d\n",
557 sg_dma_len(sg
), MAX_XFER_BYTES
);
561 ccw
= &mxs_chan
->ccw
[idx
++];
563 ccw
->next
= mxs_chan
->ccw_phys
+ sizeof(*ccw
) * idx
;
564 ccw
->bufaddr
= sg
->dma_address
;
565 ccw
->xfer_bytes
= sg_dma_len(sg
);
568 ccw
->bits
|= CCW_CHAIN
;
569 ccw
->bits
|= CCW_HALT_ON_TERM
;
570 ccw
->bits
|= CCW_TERM_FLUSH
;
571 ccw
->bits
|= BF_CCW(direction
== DMA_DEV_TO_MEM
?
572 MXS_DMA_CMD_WRITE
: MXS_DMA_CMD_READ
,
575 if (i
+ 1 == sg_len
) {
576 ccw
->bits
&= ~CCW_CHAIN
;
577 ccw
->bits
|= CCW_IRQ
;
578 ccw
->bits
|= CCW_DEC_SEM
;
579 if (flags
& MXS_DMA_CTRL_WAIT4END
)
580 ccw
->bits
|= CCW_WAIT4END
;
584 mxs_chan
->desc_count
= idx
;
586 return &mxs_chan
->desc
;
589 mxs_chan
->status
= DMA_ERROR
;
593 static struct dma_async_tx_descriptor
*mxs_dma_prep_dma_cyclic(
594 struct dma_chan
*chan
, dma_addr_t dma_addr
, size_t buf_len
,
595 size_t period_len
, enum dma_transfer_direction direction
,
598 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
599 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
600 u32 num_periods
= buf_len
/ period_len
;
603 if (mxs_chan
->status
== DMA_IN_PROGRESS
)
606 mxs_chan
->status
= DMA_IN_PROGRESS
;
607 mxs_chan
->flags
|= MXS_DMA_SG_LOOP
;
608 mxs_chan
->flags
|= MXS_DMA_USE_SEMAPHORE
;
610 if (num_periods
> NUM_CCW
) {
611 dev_err(mxs_dma
->dma_device
.dev
,
612 "maximum number of sg exceeded: %d > %d\n",
613 num_periods
, NUM_CCW
);
617 if (period_len
> MAX_XFER_BYTES
) {
618 dev_err(mxs_dma
->dma_device
.dev
,
619 "maximum period size exceeded: %zu > %d\n",
620 period_len
, MAX_XFER_BYTES
);
624 while (buf
< buf_len
) {
625 struct mxs_dma_ccw
*ccw
= &mxs_chan
->ccw
[i
];
627 if (i
+ 1 == num_periods
)
628 ccw
->next
= mxs_chan
->ccw_phys
;
630 ccw
->next
= mxs_chan
->ccw_phys
+ sizeof(*ccw
) * (i
+ 1);
632 ccw
->bufaddr
= dma_addr
;
633 ccw
->xfer_bytes
= period_len
;
636 ccw
->bits
|= CCW_CHAIN
;
637 ccw
->bits
|= CCW_IRQ
;
638 ccw
->bits
|= CCW_HALT_ON_TERM
;
639 ccw
->bits
|= CCW_TERM_FLUSH
;
640 ccw
->bits
|= CCW_DEC_SEM
;
641 ccw
->bits
|= BF_CCW(direction
== DMA_DEV_TO_MEM
?
642 MXS_DMA_CMD_WRITE
: MXS_DMA_CMD_READ
, COMMAND
);
644 dma_addr
+= period_len
;
649 mxs_chan
->desc_count
= i
;
651 return &mxs_chan
->desc
;
654 mxs_chan
->status
= DMA_ERROR
;
658 static int mxs_dma_terminate_all(struct dma_chan
*chan
)
660 mxs_dma_reset_chan(chan
);
661 mxs_dma_disable_chan(chan
);
666 static enum dma_status
mxs_dma_tx_status(struct dma_chan
*chan
,
667 dma_cookie_t cookie
, struct dma_tx_state
*txstate
)
669 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
670 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
673 if (mxs_chan
->status
== DMA_IN_PROGRESS
&&
674 mxs_chan
->flags
& MXS_DMA_SG_LOOP
) {
675 struct mxs_dma_ccw
*last_ccw
;
678 last_ccw
= &mxs_chan
->ccw
[mxs_chan
->desc_count
- 1];
679 residue
= last_ccw
->xfer_bytes
+ last_ccw
->bufaddr
;
681 bar
= readl(mxs_dma
->base
+
682 HW_APBHX_CHn_BAR(mxs_dma
, chan
->chan_id
));
686 dma_set_tx_state(txstate
, chan
->completed_cookie
, chan
->cookie
,
689 return mxs_chan
->status
;
692 static int __init
mxs_dma_init(struct mxs_dma_engine
*mxs_dma
)
696 ret
= clk_prepare_enable(mxs_dma
->clk
);
700 ret
= stmp_reset_block(mxs_dma
->base
);
704 /* enable apbh burst */
705 if (dma_is_apbh(mxs_dma
)) {
706 writel(BM_APBH_CTRL0_APB_BURST_EN
,
707 mxs_dma
->base
+ HW_APBHX_CTRL0
+ STMP_OFFSET_REG_SET
);
708 writel(BM_APBH_CTRL0_APB_BURST8_EN
,
709 mxs_dma
->base
+ HW_APBHX_CTRL0
+ STMP_OFFSET_REG_SET
);
712 /* enable irq for all the channels */
713 writel(MXS_DMA_CHANNELS_MASK
<< MXS_DMA_CHANNELS
,
714 mxs_dma
->base
+ HW_APBHX_CTRL1
+ STMP_OFFSET_REG_SET
);
717 clk_disable_unprepare(mxs_dma
->clk
);
721 struct mxs_dma_filter_param
{
722 unsigned int chan_id
;
725 static bool mxs_dma_filter_fn(struct dma_chan
*chan
, void *fn_param
)
727 struct mxs_dma_filter_param
*param
= fn_param
;
728 struct mxs_dma_chan
*mxs_chan
= to_mxs_dma_chan(chan
);
729 struct mxs_dma_engine
*mxs_dma
= mxs_chan
->mxs_dma
;
732 if (chan
->chan_id
!= param
->chan_id
)
735 chan_irq
= platform_get_irq(mxs_dma
->pdev
, param
->chan_id
);
739 mxs_chan
->chan_irq
= chan_irq
;
744 static struct dma_chan
*mxs_dma_xlate(struct of_phandle_args
*dma_spec
,
745 struct of_dma
*ofdma
)
747 struct mxs_dma_engine
*mxs_dma
= ofdma
->of_dma_data
;
748 dma_cap_mask_t mask
= mxs_dma
->dma_device
.cap_mask
;
749 struct mxs_dma_filter_param param
;
751 if (dma_spec
->args_count
!= 1)
754 param
.chan_id
= dma_spec
->args
[0];
756 if (param
.chan_id
>= mxs_dma
->nr_channels
)
759 return __dma_request_channel(&mask
, mxs_dma_filter_fn
, ¶m
,
763 static int __init
mxs_dma_probe(struct platform_device
*pdev
)
765 struct device_node
*np
= pdev
->dev
.of_node
;
766 const struct platform_device_id
*id_entry
;
767 const struct of_device_id
*of_id
;
768 const struct mxs_dma_type
*dma_type
;
769 struct mxs_dma_engine
*mxs_dma
;
770 struct resource
*iores
;
773 mxs_dma
= devm_kzalloc(&pdev
->dev
, sizeof(*mxs_dma
), GFP_KERNEL
);
777 ret
= of_property_read_u32(np
, "dma-channels", &mxs_dma
->nr_channels
);
779 dev_err(&pdev
->dev
, "failed to read dma-channels\n");
783 of_id
= of_match_device(mxs_dma_dt_ids
, &pdev
->dev
);
785 id_entry
= of_id
->data
;
787 id_entry
= platform_get_device_id(pdev
);
789 dma_type
= (struct mxs_dma_type
*)id_entry
->driver_data
;
790 mxs_dma
->type
= dma_type
->type
;
791 mxs_dma
->dev_id
= dma_type
->id
;
793 iores
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
794 mxs_dma
->base
= devm_ioremap_resource(&pdev
->dev
, iores
);
795 if (IS_ERR(mxs_dma
->base
))
796 return PTR_ERR(mxs_dma
->base
);
798 mxs_dma
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
799 if (IS_ERR(mxs_dma
->clk
))
800 return PTR_ERR(mxs_dma
->clk
);
802 dma_cap_set(DMA_SLAVE
, mxs_dma
->dma_device
.cap_mask
);
803 dma_cap_set(DMA_CYCLIC
, mxs_dma
->dma_device
.cap_mask
);
805 INIT_LIST_HEAD(&mxs_dma
->dma_device
.channels
);
807 /* Initialize channel parameters */
808 for (i
= 0; i
< MXS_DMA_CHANNELS
; i
++) {
809 struct mxs_dma_chan
*mxs_chan
= &mxs_dma
->mxs_chans
[i
];
811 mxs_chan
->mxs_dma
= mxs_dma
;
812 mxs_chan
->chan
.device
= &mxs_dma
->dma_device
;
813 dma_cookie_init(&mxs_chan
->chan
);
815 tasklet_init(&mxs_chan
->tasklet
, mxs_dma_tasklet
,
816 (unsigned long) mxs_chan
);
819 /* Add the channel to mxs_chan list */
820 list_add_tail(&mxs_chan
->chan
.device_node
,
821 &mxs_dma
->dma_device
.channels
);
824 ret
= mxs_dma_init(mxs_dma
);
828 mxs_dma
->pdev
= pdev
;
829 mxs_dma
->dma_device
.dev
= &pdev
->dev
;
831 /* mxs_dma gets 65535 bytes maximum sg size */
832 mxs_dma
->dma_device
.dev
->dma_parms
= &mxs_dma
->dma_parms
;
833 dma_set_max_seg_size(mxs_dma
->dma_device
.dev
, MAX_XFER_BYTES
);
835 mxs_dma
->dma_device
.device_alloc_chan_resources
= mxs_dma_alloc_chan_resources
;
836 mxs_dma
->dma_device
.device_free_chan_resources
= mxs_dma_free_chan_resources
;
837 mxs_dma
->dma_device
.device_tx_status
= mxs_dma_tx_status
;
838 mxs_dma
->dma_device
.device_prep_slave_sg
= mxs_dma_prep_slave_sg
;
839 mxs_dma
->dma_device
.device_prep_dma_cyclic
= mxs_dma_prep_dma_cyclic
;
840 mxs_dma
->dma_device
.device_pause
= mxs_dma_pause_chan
;
841 mxs_dma
->dma_device
.device_resume
= mxs_dma_resume_chan
;
842 mxs_dma
->dma_device
.device_terminate_all
= mxs_dma_terminate_all
;
843 mxs_dma
->dma_device
.src_addr_widths
= BIT(DMA_SLAVE_BUSWIDTH_4_BYTES
);
844 mxs_dma
->dma_device
.dst_addr_widths
= BIT(DMA_SLAVE_BUSWIDTH_4_BYTES
);
845 mxs_dma
->dma_device
.directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
846 mxs_dma
->dma_device
.residue_granularity
= DMA_RESIDUE_GRANULARITY_BURST
;
847 mxs_dma
->dma_device
.device_issue_pending
= mxs_dma_enable_chan
;
849 ret
= dmaenginem_async_device_register(&mxs_dma
->dma_device
);
851 dev_err(mxs_dma
->dma_device
.dev
, "unable to register\n");
855 ret
= of_dma_controller_register(np
, mxs_dma_xlate
, mxs_dma
);
857 dev_err(mxs_dma
->dma_device
.dev
,
858 "failed to register controller\n");
861 dev_info(mxs_dma
->dma_device
.dev
, "initialized\n");
866 static struct platform_driver mxs_dma_driver
= {
869 .of_match_table
= mxs_dma_dt_ids
,
871 .id_table
= mxs_dma_ids
,
874 static int __init
mxs_dma_module_init(void)
876 return platform_driver_probe(&mxs_dma_driver
, mxs_dma_probe
);
878 subsys_initcall(mxs_dma_module_init
);