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staging: use pci_zalloc_consistent
[linux/fpc-iii.git] / drivers / staging / rtl8192ee / pci.c
blob0215aef1eacc14004aa75f5d91f91f8f3ab40619
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "core.h"
27 #include "wifi.h"
28 #include "pci.h"
29 #include "base.h"
30 #include "ps.h"
31 #include "efuse.h"
32
33 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
34 INTEL_VENDOR_ID,
35 ATI_VENDOR_ID,
36 AMD_VENDOR_ID,
37 SIS_VENDOR_ID
38 };
39
40 static const u8 ac_to_hwq[] = {
41 VO_QUEUE,
42 VI_QUEUE,
43 BE_QUEUE,
44 BK_QUEUE
45 };
46
47 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
48 struct sk_buff *skb)
49 {
50 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
51 __le16 fc = rtl_get_fc(skb);
52 u8 queue_index = skb_get_queue_mapping(skb);
53
54 if (unlikely(ieee80211_is_beacon(fc)))
55 return BEACON_QUEUE;
56 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
57 return MGNT_QUEUE;
58 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
59 if (ieee80211_is_nullfunc(fc))
60 return HIGH_QUEUE;
61
62 return ac_to_hwq[queue_index];
63 }
64
65 /* Update PCI dependent default settings*/
66 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
67 {
68 struct rtl_priv *rtlpriv = rtl_priv(hw);
69 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
70 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
71 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
72 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
73 u8 init_aspm;
74
75 ppsc->reg_rfps_level = 0;
76 ppsc->b_support_aspm = 0;
77
78 /*Update PCI ASPM setting */
79 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
80 switch (rtlpci->const_pci_aspm) {
81 case 0:
82 /*No ASPM */
83 break;
84
85 case 1:
86 /*ASPM dynamically enabled/disable. */
87 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
88 break;
89
90 case 2:
91 /*ASPM with Clock Req dynamically enabled/disable. */
92 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
93 RT_RF_OFF_LEVL_CLK_REQ);
94 break;
95
96 case 3:
97 /*
98 * Always enable ASPM and Clock Req
99 * from initialization to halt.
100 * */
101 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
102 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
103 RT_RF_OFF_LEVL_CLK_REQ);
104 break;
105
106 case 4:
107 /*
108 * Always enable ASPM without Clock Req
109 * from initialization to halt.
110 * */
111 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
112 RT_RF_OFF_LEVL_CLK_REQ);
113 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
114 break;
115 }
116
117 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
118
119 /*Update Radio OFF setting */
120 switch (rtlpci->const_hwsw_rfoff_d3) {
121 case 1:
122 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
123 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
124 break;
125
126 case 2:
127 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
128 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
129 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
130 break;
131
132 case 3:
133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
134 break;
135 }
136
137 /*Set HW definition to determine if it supports ASPM. */
138 switch (rtlpci->const_support_pciaspm) {
139 case 0:{
140 /*Not support ASPM. */
141 bool b_support_aspm = false;
142 ppsc->b_support_aspm = b_support_aspm;
143 break;
144 }
145 case 1:{
146 /*Support ASPM. */
147 bool b_support_aspm = true;
148 bool b_support_backdoor = true;
149 ppsc->b_support_aspm = b_support_aspm;
150
151 /*if (priv->oem_id == RT_CID_TOSHIBA &&
152 !priv->ndis_adapter.amd_l1_patch)
153 b_support_backdoor = false; */
154
155 ppsc->b_support_backdoor = b_support_backdoor;
156
157 break;
158 }
159 case 2:
160 /*ASPM value set by chipset. */
161 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
162 bool b_support_aspm = true;
163 ppsc->b_support_aspm = b_support_aspm;
164 }
165 break;
166 default:
167 RT_TRACE(COMP_ERR, DBG_EMERG,
168 ("switch case not process\n"));
169 break;
170 }
171
172 /* toshiba aspm issue, toshiba will set aspm selfly
173 * so we should not set aspm in driver */
174 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
175 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
176 init_aspm == 0x43)
177 ppsc->b_support_aspm = false;
178 }
179
180 static bool _rtl_pci_platform_switch_device_pci_aspm(struct ieee80211_hw *hw,
181 u8 value)
182 {
183 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
184 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
185 bool bresult = false;
186
187 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
188 value |= 0x40;
189
190 pci_write_config_byte(rtlpci->pdev, 0x80, value);
191
192 return bresult;
193 }
194
195 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
196 static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
197 {
198 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
199 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
200 bool bresult = false;
201
202 pci_write_config_byte(rtlpci->pdev, 0x81, value);
203 bresult = true;
204
205 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
206 udelay(100);
207
208 return bresult;
209 }
210
211 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
212 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
213 {
214 struct rtl_priv *rtlpriv = rtl_priv(hw);
215 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
216 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
217 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
218 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
219 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
220 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
221 /*Retrieve original configuration settings. */
222 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
223 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
224 pcibridge_linkctrlreg;
225 u16 aspmlevel = 0;
226
227 if (!ppsc->b_support_aspm)
228 return;
229
230 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
231 RT_TRACE(COMP_POWER, DBG_TRACE,
232 ("PCI(Bridge) UNKNOWN.\n"));
233
234 return;
235 }
236
237 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
238 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
239 _rtl_pci_switch_clk_req(hw, 0x0);
240 }
241
242 if (1) {
243 /*for promising device will in L0 state after an I/O. */
244 u8 tmp_u1b;
245 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
246 }
247
248 /*Set corresponding value. */
249 aspmlevel |= BIT(0) | BIT(1);
250 linkctrl_reg &= ~aspmlevel;
251 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
252
253 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
254 udelay(50);
255
256 /*4 Disable Pci Bridge ASPM */
257 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
258 pcicfg_addrport + (num4bytes << 2));
259 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
260
261 udelay(50);
262 }
263
264 /*
265 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
266 *power saving We should follow the sequence to enable
267 *RTL8192SE first then enable Pci Bridge ASPM
268 *or the system will show bluescreen.
269 */
270 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
271 {
272 struct rtl_priv *rtlpriv = rtl_priv(hw);
273 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
274 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
275 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
276 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
277 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
278 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
279 u16 aspmlevel;
280 u8 u_pcibridge_aspmsetting;
281 u8 u_device_aspmsetting;
282
283 if (!ppsc->b_support_aspm)
284 return;
285
286 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
287 RT_TRACE(COMP_POWER, DBG_TRACE,
288 ("PCI(Bridge) UNKNOWN.\n"));
289 return;
290 }
291
292 /*4 Enable Pci Bridge ASPM */
293 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
294 pcicfg_addrport + (num4bytes << 2));
295
296 u_pcibridge_aspmsetting =
297 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
298 rtlpci->const_hostpci_aspm_setting;
299
300 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
301 u_pcibridge_aspmsetting &= ~BIT(0);
302
303 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
304
305 RT_TRACE(COMP_INIT, DBG_LOUD,
306 ("PlatformEnableASPM(): Write reg[%x] = %x\n",
307 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
308 u_pcibridge_aspmsetting));
309
310 udelay(50);
311
312 /*Get ASPM level (with/without Clock Req) */
313 aspmlevel = rtlpci->const_devicepci_aspm_setting;
314 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
315
316 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
317 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
318
319 u_device_aspmsetting |= aspmlevel;
320
321 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
322
323 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
324 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
325 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
326 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
327 }
328 udelay(100);
329 }
330
331 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
332 {
333 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
334 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
335
336 bool status = false;
337 u8 offset_e0;
338 unsigned offset_e4;
339
340 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE0);
341 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
342
343 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE0);
344 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
345
346 if (offset_e0 == 0xA0) {
347 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
348 pcicfg_addrport + 0xE4);
349 rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
350 if (offset_e4 & BIT(23))
351 status = true;
352 }
353
354 return status;
355 }
356
357 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
358 struct rtl_priv **buddy_priv)
359 {
360 struct rtl_priv *rtlpriv = rtl_priv(hw);
361 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
362 bool find_buddy_priv = false;
363 struct rtl_priv *tpriv = NULL;
364 struct rtl_pci_priv *tpcipriv = NULL;
365
366 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
367 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
368 list) {
369 if (tpriv == NULL)
370 break;
371
372 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
373 RT_TRACE(COMP_INIT, DBG_LOUD,
374 ("pcipriv->ndis_adapter.funcnumber %x\n",
375 pcipriv->ndis_adapter.funcnumber));
376 RT_TRACE(COMP_INIT, DBG_LOUD,
377 ("tpcipriv->ndis_adapter.funcnumber %x\n",
378 tpcipriv->ndis_adapter.funcnumber));
379
380 if ((pcipriv->ndis_adapter.busnumber ==
381 tpcipriv->ndis_adapter.busnumber) &&
382 (pcipriv->ndis_adapter.devnumber ==
383 tpcipriv->ndis_adapter.devnumber) &&
384 (pcipriv->ndis_adapter.funcnumber !=
385 tpcipriv->ndis_adapter.funcnumber)) {
386 find_buddy_priv = true;
387 break;
388 }
389 }
390 }
391
392 RT_TRACE(COMP_INIT, DBG_LOUD,
393 ("find_buddy_priv %d\n", find_buddy_priv));
394
395 if (find_buddy_priv)
396 *buddy_priv = tpriv;
397
398 return find_buddy_priv;
399 }
400
401 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
402 {
403 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
404 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
405 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
406 u8 linkctrl_reg;
407 u8 num4bbytes;
408
409 num4bbytes = (capabilityoffset + 0x10) / 4;
410
411 /*Read Link Control Register */
412 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
413 pcicfg_addrport + (num4bbytes << 2));
414 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
415
416 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
417 }
418
419 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
420 struct ieee80211_hw *hw)
421 {
422 struct rtl_priv *rtlpriv = rtl_priv(hw);
423 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
424
425 u8 tmp;
426 int pos;
427 u8 linkctrl_reg;
428
429 /*Link Control Register */
430 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
431 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
432 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
433
434 RT_TRACE(COMP_INIT, DBG_TRACE,
435 ("Link Control Register =%x\n",
436 pcipriv->ndis_adapter.linkctrl_reg));
437
438 pci_read_config_byte(pdev, 0x98, &tmp);
439 tmp |= BIT(4);
440 pci_write_config_byte(pdev, 0x98, tmp);
441
442 tmp = 0x17;
443 pci_write_config_byte(pdev, 0x70f, tmp);
444 }
445
446 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
447 {
448 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
449
450 _rtl_pci_update_default_setting(hw);
451
452 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
453 /*Always enable ASPM & Clock Req. */
454 rtl_pci_enable_aspm(hw);
455 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
456 }
457 }
458
459 static void _rtl_pci_io_handler_init(struct device *dev,
460 struct ieee80211_hw *hw)
461 {
462 struct rtl_priv *rtlpriv = rtl_priv(hw);
463
464 rtlpriv->io.dev = dev;
465
466 rtlpriv->io.write8_async = pci_write8_async;
467 rtlpriv->io.write16_async = pci_write16_async;
468 rtlpriv->io.write32_async = pci_write32_async;
469
470 rtlpriv->io.read8_sync = pci_read8_sync;
471 rtlpriv->io.read16_sync = pci_read16_sync;
472 rtlpriv->io.read32_sync = pci_read32_sync;
473 }
474
475 static bool _rtl_pci_update_earlymode_info(struct ieee80211_hw *hw,
476 struct sk_buff *skb,
477 struct rtl_tcb_desc *tcb_desc,
478 u8 tid)
479 {
480 struct rtl_priv *rtlpriv = rtl_priv(hw);
481 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
482 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
483 struct sk_buff *next_skb;
484 u8 additionlen = FCS_LEN;
485
486 /* here open is 4, wep/tkip is 8, aes is 12*/
487 if (info->control.hw_key)
488 additionlen += info->control.hw_key->icv_len;
489
490 /* The most skb num is 6 */
491 tcb_desc->empkt_num = 0;
492 spin_lock_bh(&rtlpriv->locks.waitq_lock);
493 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
494 struct ieee80211_tx_info *next_info;
495
496 next_info = IEEE80211_SKB_CB(next_skb);
497 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
498 tcb_desc->empkt_len[tcb_desc->empkt_num] =
499 next_skb->len + additionlen;
500 tcb_desc->empkt_num++;
501 } else {
502 break;
503 }
504
505 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
506 next_skb))
507 break;
508
509 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
510 break;
511 }
512 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
513 return true;
514 }
515
516 /* just for early mode now */
517 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
518 {
519 struct rtl_priv *rtlpriv = rtl_priv(hw);
520 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
521 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
522 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
523 struct sk_buff *skb = NULL;
524 struct ieee80211_tx_info *info = NULL;
525 int tid; /* should be int */
526
527 if (!rtlpriv->rtlhal.b_earlymode_enable)
528 return;
529 if (rtlpriv->dm.supp_phymode_switch &&
530 (rtlpriv->easy_concurrent_ctl.bswitch_in_process ||
531 (rtlpriv->buddy_priv &&
532 rtlpriv->buddy_priv->easy_concurrent_ctl.bswitch_in_process)))
533 return;
534 /* we juse use em for BE/BK/VI/VO */
535 for (tid = 7; tid >= 0; tid--) {
536 u8 hw_queue = ac_to_hwq[rtl92e_tid_to_ac(hw, tid)];
537 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
538 while (!mac->act_scanning &&
539 rtlpriv->psc.rfpwr_state == ERFON) {
540 struct rtl_tcb_desc tcb_desc;
541 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
542
543 spin_lock_bh(&rtlpriv->locks.waitq_lock);
544 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
545 (ring->entries - skb_queue_len(&ring->queue) >
546 rtlhal->max_earlymode_num)) {
547 skb = skb_dequeue(&mac->skb_waitq[tid]);
548 } else {
549 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
550 break;
551 }
552 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
553
554 /* Some macaddr can't do early mode. like
555 * multicast/broadcast/no_qos data */
556 info = IEEE80211_SKB_CB(skb);
557 if (info->flags & IEEE80211_TX_CTL_AMPDU)
558 _rtl_pci_update_earlymode_info(hw, skb,
559 &tcb_desc, tid);
560
561 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
562 }
563 }
564 }
565
566 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
567 {
568 struct rtl_priv *rtlpriv = rtl_priv(hw);
569 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
570 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
571
572 while (skb_queue_len(&ring->queue)) {
573 struct sk_buff *skb;
574 struct ieee80211_tx_info *info;
575 __le16 fc;
576 u8 tid;
577 u8 *entry;
578
579
580 if (rtlpriv->use_new_trx_flow)
581 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
582 else
583 entry = (u8 *)(&ring->desc[ring->idx]);
584
585 if (rtlpriv->cfg->ops->is_tx_desc_closed &&
586 !rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
587 return;
588
589 ring->idx = (ring->idx + 1) % ring->entries;
590
591 skb = __skb_dequeue(&ring->queue);
592
593 pci_unmap_single(rtlpci->pdev,
594 rtlpriv->cfg->ops->
595 get_desc((u8 *)entry, true,
596 HW_DESC_TXBUFF_ADDR),
597 skb->len, PCI_DMA_TODEVICE);
598
599 /* remove early mode header */
600 if (rtlpriv->rtlhal.b_earlymode_enable)
601 skb_pull(skb, EM_HDR_LEN);
602
603 RT_TRACE((COMP_INTR | COMP_SEND), DBG_TRACE,
604 ("new ring->idx:%d, free: skb_queue_len:%d, free: seq:%d\n",
605 ring->idx,
606 skb_queue_len(&ring->queue),
607 *(u16 *)(skb->data + 22)));
608
609 if (prio == TXCMD_QUEUE) {
610 dev_kfree_skb(skb);
611 goto tx_status_ok;
612 }
613
614 /* for sw LPS, just after NULL skb send out, we can
615 * sure AP knows that we are sleeping, our we should not let
616 * rf to sleep
617 */
618 fc = rtl_get_fc(skb);
619 if (ieee80211_is_nullfunc(fc)) {
620 if (ieee80211_has_pm(fc)) {
621 rtlpriv->mac80211.offchan_deley = true;
622 rtlpriv->psc.state_inap = 1;
623 } else {
624 rtlpriv->psc.state_inap = 0;
625 }
626 }
627 if (ieee80211_is_action(fc)) {
628 struct ieee80211_mgmt_compat *action_frame =
629 (struct ieee80211_mgmt_compat *)skb->data;
630 if (action_frame->u.action.u.ht_smps.action ==
631 WLAN_HT_ACTION_SMPS) {
632 dev_kfree_skb(skb);
633 goto tx_status_ok;
634 }
635 }
636
637 /* update tid tx pkt num */
638 tid = rtl_get_tid(skb);
639 if (tid <= 7)
640 rtlpriv->link_info.tidtx_inperiod[tid]++;
641
642 info = IEEE80211_SKB_CB(skb);
643 ieee80211_tx_info_clear_status(info);
644
645 info->flags |= IEEE80211_TX_STAT_ACK;
646 /*info->status.rates[0].count = 1; */
647
648 ieee80211_tx_status_irqsafe(hw, skb);
649
650 if ((ring->entries - skb_queue_len(&ring->queue)) == 2) {
651 RT_TRACE(COMP_ERR, DBG_LOUD,
652 ("more desc left, wake skb_queue@%d,ring->idx = %d, skb_queue_len = 0x%d\n",
653 prio, ring->idx,
654 skb_queue_len(&ring->queue)));
655
656 ieee80211_wake_queue(hw, skb_get_queue_mapping
657 (skb));
658 }
659 tx_status_ok:
660 skb = NULL;
661 }
662
663 if (((rtlpriv->link_info.num_rx_inperiod +
664 rtlpriv->link_info.num_tx_inperiod) > 8) ||
665 (rtlpriv->link_info.num_rx_inperiod > 2)) {
666 rtl92e_lps_leave(hw);
667 }
668 }
669
670 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
671 u8 *entry, int rxring_idx, int desc_idx)
672 {
673 struct rtl_priv *rtlpriv = rtl_priv(hw);
674 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
675 struct sk_buff *skb;
676 u32 bufferaddress;
677 u8 tmp_one = 1;
678
679 skb = dev_alloc_skb(rtlpci->rxbuffersize);
680 if (!skb)
681 return 0;
682 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
683
684 /* just set skb->cb to mapping addr
685 * for pci_unmap_single use
686 */
687 *((dma_addr_t *)skb->cb) = pci_map_single(rtlpci->pdev,
688 skb_tail_pointer(skb), rtlpci->rxbuffersize,
689 PCI_DMA_FROMDEVICE);
690 bufferaddress = *((dma_addr_t *)skb->cb);
691 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
692 return 0;
693 if (rtlpriv->use_new_trx_flow) {
694 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
695 HW_DESC_RX_PREPARE,
696 (u8 *)&bufferaddress);
697 } else {
698 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
699 HW_DESC_RXBUFF_ADDR,
700 (u8 *)&bufferaddress);
701 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
702 HW_DESC_RXPKT_LEN,
703 (u8 *)&rtlpci->rxbuffersize);
704 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
705 HW_DESC_RXOWN,
706 (u8 *)&tmp_one);
707 }
708 return 1;
709 }
710
711 /* inorder to receive 8K AMSDU we have set skb to
712 * 9100bytes in init rx ring, but if this packet is
713 * not a AMSDU, this so big packet will be sent to
714 * TCP/IP directly, this cause big packet ping fail
715 * like: "ping -s 65507", so here we will realloc skb
716 * based on the true size of packet, I think mac80211
717 * do it will be better, but now mac80211 haven't */
718
719 /* but some platform will fail when alloc skb sometimes.
720 * in this condition, we will send the old skb to
721 * mac80211 directly, this will not cause any other
722 * issues, but only be losted by TCP/IP */
723 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
724 struct sk_buff *skb,
725 struct ieee80211_rx_status rx_status)
726 {
727 if (unlikely(!rtl92e_action_proc(hw, skb, false))) {
728 dev_kfree_skb_any(skb);
729 } else {
730 struct sk_buff *uskb = NULL;
731 u8 *pdata;
732
733 uskb = dev_alloc_skb(skb->len + 128);
734 if (likely(uskb)) {
735 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
736 sizeof(rx_status));
737 pdata = (u8 *)skb_put(uskb, skb->len);
738 memcpy(pdata, skb->data, skb->len);
739 dev_kfree_skb_any(skb);
740
741 ieee80211_rx_irqsafe(hw, uskb);
742 } else {
743 ieee80211_rx_irqsafe(hw, skb);
744 }
745 }
746 }
747
748 /*hsisr interrupt handler*/
749 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
750 {
751 struct rtl_priv *rtlpriv = rtl_priv(hw);
752 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
753
754 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
755 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
756 rtlpci->sys_irq_mask);
757 }
758
759 static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
760 struct ieee80211_rx_status rx_status)
761 {
762 struct rtl_priv *rtlpriv = rtl_priv(hw);
763 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
764 __le16 fc = rtl_get_fc(skb);
765 bool unicast = false;
766
767 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
768
769 if (is_broadcast_ether_addr(hdr->addr1)) {
770 ;/*TODO*/
771 } else if (is_multicast_ether_addr(hdr->addr1)) {
772 ;/*TODO*/
773 } else {
774 unicast = true;
775 rtlpriv->stats.rxbytesunicast += skb->len;
776 }
777
778 rtl92e_is_special_data(hw, skb, false);
779 if (ieee80211_is_data(fc)) {
780 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
781
782 if (unicast)
783 rtlpriv->link_info.num_rx_inperiod++;
784 }
785
786 /* static bcn for roaming */
787 rtl92e_beacon_statistic(hw, skb);
788 rtl92e_p2p_info(hw, (void *)skb->data, skb->len);
789
790 /* for sw lps */
791 rtl92e_swlps_beacon(hw, (void *)skb->data, skb->len);
792 rtl92e_recognize_peer(hw, (void *)skb->data, skb->len);
793 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
794 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
795 (ieee80211_is_beacon(fc) ||
796 ieee80211_is_probe_resp(fc)))
797 dev_kfree_skb_any(skb);
798 else
799 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
800 }
801
802 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
803 {
804 struct rtl_priv *rtlpriv = rtl_priv(hw);
805 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
806 struct ieee80211_rx_status rx_status = { 0 };
807 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
808 unsigned int count = rtlpci->rxringcount;
809 u8 hw_queue = 0;
810 unsigned int rx_remained_cnt;
811 u8 own;
812 u8 tmp_one;
813 static int err_count;
814 struct rtl_stats stats = {
815 .signal = 0,
816 .rate = 0,
817 };
818
819 /*RX NORMAL PKT */
820 while (count--) {
821 struct ieee80211_hdr *hdr;
822 __le16 fc;
823 u16 len;
824 /*rx buffer descriptor */
825 struct rtl_rx_buffer_desc *buffer_desc = NULL;
826 /*if use new trx flow, it means wifi info */
827 struct rtl_rx_desc *pdesc = NULL;
828 /*rx pkt */
829 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
830 rtlpci->rx_ring[rxring_idx].idx];
831
832 if (rtlpriv->use_new_trx_flow) {
833 rx_remained_cnt =
834 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
835 hw_queue);
836 if (rx_remained_cnt < 1)
837 return;
838
839 } else { /* rx descriptor */
840 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
841 rtlpci->rx_ring[rxring_idx].idx];
842
843 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc,
844 false,
845 HW_DESC_OWN);
846 if (own) /* wait data to be filled by hardware */
847 return;
848 }
849
850 /* If we get here, the data is filled already
851 * Attention !!!
852 * We can NOT access 'skb' before 'pci_unmap_single'
853 */
854 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
855 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
856
857 if (rtlpriv->use_new_trx_flow) {
858 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
859 rtlpci->rx_ring[rxring_idx].idx];
860 /*means rx wifi info*/
861 pdesc = (struct rtl_rx_desc *)skb->data;
862 }
863 memset(&rx_status , 0 , sizeof(rx_status));
864 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
865 &rx_status, (u8 *)pdesc, skb);
866
867 if (rtlpriv->use_new_trx_flow)
868 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
869 (u8 *)buffer_desc,
870 hw_queue);
871 len = rtlpriv->cfg->ops->get_desc((u8 *)pdesc, false,
872 HW_DESC_RXPKT_LEN);
873
874 if (skb->end - skb->tail > len) {
875 skb_put(skb, len);
876 if (rtlpriv->use_new_trx_flow)
877 skb_reserve(skb, stats.rx_drvinfo_size +
878 stats.rx_bufshift + 24);
879 else
880 skb_reserve(skb, stats.rx_drvinfo_size +
881 stats.rx_bufshift);
882
883 } else {
884 if (err_count++ < 10) {
885 pr_info("skb->end (%d) - skb->tail (%d) > len (%d)\n",
886 skb->end, skb->tail, len);
887 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_EMERG,
888 "RX desc\n",
889 (u8 *)pdesc, 32);
890 }
891 break;
892 }
893
894 /* handle command packet here */
895 if (rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) {
896 dev_kfree_skb_any(skb);
897 goto end;
898 }
899
900 /* NOTICE This can not be use for mac80211,
901 *this is done in mac80211 code,
902 *if you done here sec DHCP will fail
903 *skb_trim(skb, skb->len - 4);
904 */
905
906 hdr = rtl_get_hdr(skb);
907 fc = rtl_get_fc(skb);
908
909 if (!stats.b_crc && !stats.b_hwerror)
910 _rtl_receive_one(hw, skb, rx_status);
911 else
912 dev_kfree_skb_any(skb);
913 if (rtlpriv->use_new_trx_flow) {
914 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
915 rtlpci->rx_ring[hw_queue].next_rx_rp %=
916 RTL_PCI_MAX_RX_COUNT;
917
918
919 rx_remained_cnt--;
920 rtl_write_word(rtlpriv, 0x3B4,
921 rtlpci->rx_ring[hw_queue].next_rx_rp);
922 }
923 if (((rtlpriv->link_info.num_rx_inperiod +
924 rtlpriv->link_info.num_tx_inperiod) > 8) ||
925 (rtlpriv->link_info.num_rx_inperiod > 2)) {
926 rtl92e_lps_leave(hw);
927 }
928 end:
929 if (rtlpriv->use_new_trx_flow) {
930 _rtl_pci_init_one_rxdesc(hw, (u8 *)buffer_desc,
931 rxring_idx,
932 rtlpci->rx_ring[rxring_idx].idx);
933 } else {
934 _rtl_pci_init_one_rxdesc(hw, (u8 *)pdesc, rxring_idx,
935 rtlpci->rx_ring[rxring_idx].idx);
936
937 if (rtlpci->rx_ring[rxring_idx].idx ==
938 rtlpci->rxringcount - 1)
939 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
940 false,
941 HW_DESC_RXERO,
942 (u8 *)&tmp_one);
943 }
944 rtlpci->rx_ring[rxring_idx].idx =
945 (rtlpci->rx_ring[rxring_idx].idx + 1) %
946 rtlpci->rxringcount;
947 }
948 }
949
950 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
951 {
952 struct ieee80211_hw *hw = dev_id;
953 struct rtl_priv *rtlpriv = rtl_priv(hw);
954 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
955 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
956 unsigned long flags;
957 u32 inta = 0;
958 u32 intb = 0;
959
960 if (rtlpci->irq_enabled == 0)
961 return IRQ_HANDLED;
962
963 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock , flags);
964 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[MAC_HIMR], 0x0);
965 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[MAC_HIMRE], 0x0);
966
967 /*read ISR: 4/8bytes */
968 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
969
970 /*Shared IRQ or HW disappared */
971 if (!inta || inta == 0xffff)
972 goto done;
973 /*<1> beacon related */
974 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
975 RT_TRACE(COMP_INTR, DBG_TRACE, ("beacon ok interrupt!\n"));
976
977 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
978 RT_TRACE(COMP_INTR, DBG_TRACE, ("beacon err interrupt!\n"));
979
980 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
981 RT_TRACE(COMP_INTR, DBG_TRACE, ("beacon interrupt!\n"));
982
983 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
984 RT_TRACE(COMP_INTR, DBG_TRACE,
985 ("prepare beacon for interrupt!\n"));
986 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
987 }
988
989 /*<2> tx related */
990 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
991 RT_TRACE(COMP_ERR, DBG_TRACE, ("IMR_TXFOVW!\n"));
992
993 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
994 RT_TRACE(COMP_INTR, DBG_TRACE, ("Manage ok interrupt!\n"));
995 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
996 }
997
998 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
999 RT_TRACE(COMP_INTR, DBG_TRACE, ("HIGH_QUEUE ok interrupt!\n"));
1000 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
1001 }
1002
1003 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
1004 rtlpriv->link_info.num_tx_inperiod++;
1005
1006 RT_TRACE(COMP_INTR, DBG_TRACE, ("BK Tx OK interrupt!\n"));
1007 _rtl_pci_tx_isr(hw, BK_QUEUE);
1008 }
1009
1010 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
1011 rtlpriv->link_info.num_tx_inperiod++;
1012
1013 RT_TRACE(COMP_INTR, DBG_TRACE, ("BE TX OK interrupt!\n"));
1014 _rtl_pci_tx_isr(hw, BE_QUEUE);
1015 }
1016
1017 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
1018 rtlpriv->link_info.num_tx_inperiod++;
1019
1020 RT_TRACE(COMP_INTR, DBG_TRACE, ("VI TX OK interrupt!\n"));
1021 _rtl_pci_tx_isr(hw, VI_QUEUE);
1022 }
1023
1024 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
1025 rtlpriv->link_info.num_tx_inperiod++;
1026
1027 RT_TRACE(COMP_INTR, DBG_TRACE, ("Vo TX OK interrupt!\n"));
1028 _rtl_pci_tx_isr(hw, VO_QUEUE);
1029 }
1030
1031 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1032 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1033 rtlpriv->link_info.num_tx_inperiod++;
1034
1035 RT_TRACE(COMP_INTR, DBG_TRACE,
1036 ("CMD TX OK interrupt!\n"));
1037 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1038 }
1039 }
1040
1041 /*<3> rx related */
1042 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1043 RT_TRACE(COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
1044 _rtl_pci_rx_interrupt(hw);
1045 }
1046
1047 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1048 RT_TRACE(COMP_ERR, DBG_WARNING,
1049 ("rx descriptor unavailable!\n"));
1050 _rtl_pci_rx_interrupt(hw);
1051 }
1052
1053 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1054 RT_TRACE(COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
1055 _rtl_pci_rx_interrupt(hw);
1056 }
1057
1058 /*<4> fw related*/
1059 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1060 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1061 RT_TRACE(COMP_INTR, DBG_TRACE,
1062 ("firmware interrupt!\n"));
1063 queue_delayed_work(rtlpriv->works.rtl_wq,
1064 &rtlpriv->works.fwevt_wq, 0);
1065 }
1066 }
1067
1068 /*<5> hsisr related*/
1069 /* Only 8188EE & 8723BE Supported.
1070 * If Other ICs Come in, System will corrupt,
1071 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1072 * are not initialized*/
1073 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1074 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1075 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1076 RT_TRACE(COMP_INTR, DBG_TRACE,
1077 ("hsisr interrupt!\n"));
1078 _rtl_pci_hs_interrupt(hw);
1079 }
1080 }
1081
1082
1083 if (rtlpriv->rtlhal.b_earlymode_enable)
1084 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1085
1086 done:
1087 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[MAC_HIMR],
1088 rtlpci->irq_mask[0]);
1089 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[MAC_HIMRE],
1090 rtlpci->irq_mask[1]);
1091 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1092 return IRQ_HANDLED;
1093 }
1094
1095 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
1096 {
1097 _rtl_pci_tx_chk_waitq(hw);
1098 }
1099
1100 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
1101 {
1102 struct rtl_priv *rtlpriv = rtl_priv(hw);
1103 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1104 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1105 struct rtl8192_tx_ring *ring = NULL;
1106 struct ieee80211_hdr *hdr = NULL;
1107 struct ieee80211_tx_info *info = NULL;
1108 struct sk_buff *pskb = NULL;
1109 struct rtl_tx_desc *pdesc = NULL;
1110 struct rtl_tcb_desc tcb_desc;
1111 /*This is for new trx flow*/
1112 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1113 u8 temp_one = 1;
1114
1115 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1116 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1117 pskb = __skb_dequeue(&ring->queue);
1118 if (pskb)
1119 kfree_skb(pskb);
1120
1121 /*NB: the beacon data buffer must be 32-bit aligned. */
1122 pskb = ieee80211_beacon_get(hw, mac->vif);
1123 if (pskb == NULL)
1124 return;
1125 hdr = rtl_get_hdr(pskb);
1126 info = IEEE80211_SKB_CB(pskb);
1127 pdesc = &ring->desc[0];
1128 if (rtlpriv->use_new_trx_flow)
1129 pbuffer_desc = &ring->buffer_desc[0];
1130
1131 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1132 (u8 *)pbuffer_desc, info, NULL, pskb,
1133 BEACON_QUEUE, &tcb_desc);
1134
1135 __skb_queue_tail(&ring->queue, pskb);
1136
1137 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1138 (u8 *)&temp_one);
1139
1140 return;
1141 }
1142
1143 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1144 {
1145 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1146 struct rtl_priv *rtlpriv = rtl_priv(hw);
1147 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1148 u8 i;
1149 u16 desc_num;
1150
1151 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1152 desc_num = TX_DESC_NUM_92E;
1153 else
1154 desc_num = RT_TXDESC_NUM;
1155
1156 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1157 rtlpci->txringcount[i] = desc_num;
1158 /*
1159 *we just alloc 2 desc for beacon queue,
1160 *because we just need first desc in hw beacon.
1161 */
1162 rtlpci->txringcount[BEACON_QUEUE] = 2;
1163
1164 /*
1165 *BE queue need more descriptor for performance
1166 *consideration or, No more tx desc will happen,
1167 *and may cause mac80211 mem leakage.
1168 */
1169 if (!rtl_priv(hw)->use_new_trx_flow)
1170 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1171
1172 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1173 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1174 }
1175
1176 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1177 struct pci_dev *pdev)
1178 {
1179 struct rtl_priv *rtlpriv = rtl_priv(hw);
1180 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1181 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1182 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1183
1184 rtlpriv->rtlhal.up_first_time = true;
1185 rtlpriv->rtlhal.being_init_adapter = false;
1186
1187 rtlhal->hw = hw;
1188 rtlpci->pdev = pdev;
1189
1190 /*Tx/Rx related var */
1191 _rtl_pci_init_trx_var(hw);
1192
1193 /*IBSS*/ mac->beacon_interval = 100;
1194
1195 /*AMPDU*/
1196 mac->min_space_cfg = 0;
1197 mac->max_mss_density = 0;
1198 /*set sane AMPDU defaults */
1199 mac->current_ampdu_density = 7;
1200 mac->current_ampdu_factor = 3;
1201
1202 /*QOS*/
1203 rtlpci->acm_method = eAcmWay2_SW;
1204
1205 /*task */
1206 tasklet_init(&rtlpriv->works.irq_tasklet,
1207 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1208 (unsigned long)hw);
1209 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1210 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1211 (unsigned long)hw);
1212 }
1213
1214 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1215 unsigned int prio, unsigned int entries)
1216 {
1217 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1218 struct rtl_priv *rtlpriv = rtl_priv(hw);
1219 struct rtl_tx_buffer_desc *buffer_desc;
1220 struct rtl_tx_desc *desc;
1221 dma_addr_t buffer_desc_dma, desc_dma;
1222 u32 nextdescaddress;
1223 int i;
1224
1225 /* alloc tx buffer desc for new trx flow*/
1226 if (rtlpriv->use_new_trx_flow) {
1227 buffer_desc =
1228 pci_zalloc_consistent(rtlpci->pdev,
1229 sizeof(*buffer_desc) * entries,
1230 &buffer_desc_dma);
1231 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1232 RT_TRACE(COMP_ERR, DBG_EMERG,
1233 ("Cannot allocate TX ring (prio = %d)\n",
1234 prio));
1235 return -ENOMEM;
1236 }
1237
1238 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1239 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1240
1241 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1242 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1243 rtlpci->tx_ring[prio].avl_desc = entries;
1244 }
1245
1246 /* alloc dma for this ring */
1247 desc = pci_zalloc_consistent(rtlpci->pdev, sizeof(*desc) * entries,
1248 &desc_dma);
1249 if (!desc || (unsigned long)desc & 0xFF) {
1250 RT_TRACE(COMP_ERR, DBG_EMERG,
1251 ("Cannot allocate TX ring (prio = %d)\n", prio));
1252 return -ENOMEM;
1253 }
1254
1255 rtlpci->tx_ring[prio].desc = desc;
1256 rtlpci->tx_ring[prio].dma = desc_dma;
1257
1258 rtlpci->tx_ring[prio].idx = 0;
1259 rtlpci->tx_ring[prio].entries = entries;
1260 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1261 RT_TRACE(COMP_INIT, DBG_LOUD,
1262 ("queue:%d, ring_addr:%p\n", prio, desc));
1263
1264 /* init every desc in this ring */
1265 if (!rtlpriv->use_new_trx_flow) {
1266 for (i = 0; i < entries; i++) {
1267 nextdescaddress = (u32) desc_dma +
1268 ((i + 1) % entries) *
1269 sizeof(*desc);
1270
1271 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&(desc[i]),
1272 true,
1273 HW_DESC_TX_NEXTDESC_ADDR,
1274 (u8 *)&nextdescaddress);
1275 }
1276 }
1277 return 0;
1278 }
1279
1280 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1281 {
1282 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1283 struct rtl_priv *rtlpriv = rtl_priv(hw);
1284 int i;
1285
1286 if (rtlpriv->use_new_trx_flow) {
1287 struct rtl_rx_buffer_desc *entry = NULL;
1288 /* alloc dma for this ring */
1289 rtlpci->rx_ring[rxring_idx].buffer_desc =
1290 pci_zalloc_consistent(rtlpci->pdev,
1291 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) * rtlpci->rxringcount,
1292 &rtlpci->rx_ring[rxring_idx].dma);
1293 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1294 (unsigned long)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1295 RT_TRACE(COMP_ERR, DBG_EMERG,
1296 ("Cannot allocate RX ring\n"));
1297 return -ENOMEM;
1298 }
1299
1300 /* init every desc in this ring */
1301 rtlpci->rx_ring[rxring_idx].idx = 0;
1302
1303 for (i = 0; i < rtlpci->rxringcount; i++) {
1304 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1305 if (!_rtl_pci_init_one_rxdesc(hw, (u8 *)entry,
1306 rxring_idx, i))
1307 return -ENOMEM;
1308 }
1309 } else {
1310 struct rtl_rx_desc *entry = NULL;
1311 u8 tmp_one = 1;
1312 /* alloc dma for this ring */
1313 rtlpci->rx_ring[rxring_idx].desc =
1314 pci_zalloc_consistent(rtlpci->pdev,
1315 sizeof(*rtlpci->rx_ring[rxring_idx].desc) * rtlpci->rxringcount,
1316 &rtlpci->rx_ring[rxring_idx].dma);
1317 if (!rtlpci->rx_ring[rxring_idx].desc ||
1318 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1319 RT_TRACE(COMP_ERR, DBG_EMERG,
1320 ("Cannot allocate RX ring\n"));
1321 return -ENOMEM;
1322 }
1323
1324 /* init every desc in this ring */
1325 rtlpci->rx_ring[rxring_idx].idx = 0;
1326 for (i = 0; i < rtlpci->rxringcount; i++) {
1327 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1328 if (!_rtl_pci_init_one_rxdesc(hw, (u8 *)entry,
1329 rxring_idx, i))
1330 return -ENOMEM;
1331 }
1332 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1333 HW_DESC_RXERO, (u8 *) &tmp_one);
1334 }
1335 return 0;
1336 }
1337
1338 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1339 unsigned int prio)
1340 {
1341 struct rtl_priv *rtlpriv = rtl_priv(hw);
1342 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1343 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1344
1345 /* free every desc in this ring */
1346 while (skb_queue_len(&ring->queue)) {
1347 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1348 u8 *entry;
1349
1350 if (rtlpriv->use_new_trx_flow)
1351 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1352 else
1353 entry = (u8 *)(&ring->desc[ring->idx]);
1354
1355 pci_unmap_single(rtlpci->pdev,
1356 rtlpriv->cfg->ops->get_desc((u8 *)entry, true,
1357 HW_DESC_TXBUFF_ADDR),
1358 skb->len, PCI_DMA_TODEVICE);
1359 kfree_skb(skb);
1360 ring->idx = (ring->idx + 1) % ring->entries;
1361 }
1362
1363 /* free dma of this ring */
1364 pci_free_consistent(rtlpci->pdev,
1365 sizeof(*ring->desc) * ring->entries,
1366 ring->desc, ring->dma);
1367 ring->desc = NULL;
1368 if (rtlpriv->use_new_trx_flow) {
1369 pci_free_consistent(rtlpci->pdev,
1370 sizeof(*ring->buffer_desc) * ring->entries,
1371 ring->buffer_desc, ring->buffer_desc_dma);
1372 ring->buffer_desc = NULL;
1373 }
1374 }
1375
1376 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1377 {
1378 struct rtl_priv *rtlpriv = rtl_priv(hw);
1379 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1380 int i;
1381
1382 /* free every desc in this ring */
1383 for (i = 0; i < rtlpci->rxringcount; i++) {
1384 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1385
1386 if (!skb)
1387 continue;
1388
1389 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
1390 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
1391 kfree_skb(skb);
1392 }
1393
1394 /* free dma of this ring */
1395 if (rtlpriv->use_new_trx_flow) {
1396 pci_free_consistent(rtlpci->pdev,
1397 sizeof(*rtlpci->rx_ring[rxring_idx].
1398 buffer_desc) * rtlpci->rxringcount,
1399 rtlpci->rx_ring[rxring_idx].buffer_desc,
1400 rtlpci->rx_ring[rxring_idx].dma);
1401 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1402 } else {
1403 pci_free_consistent(rtlpci->pdev,
1404 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1405 rtlpci->rxringcount,
1406 rtlpci->rx_ring[rxring_idx].desc,
1407 rtlpci->rx_ring[rxring_idx].dma);
1408 rtlpci->rx_ring[rxring_idx].desc = NULL;
1409 }
1410 }
1411
1412 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1413 {
1414 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1415 int ret;
1416 int i, rxring_idx;
1417
1418 /* rxring_idx 0:RX_MPDU_QUEUE
1419 * rxring_idx 1:RX_CMD_QUEUE */
1420 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1421 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1422 if (ret)
1423 return ret;
1424 }
1425
1426 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1427 ret = _rtl_pci_init_tx_ring(hw, i,
1428 rtlpci->txringcount[i]);
1429 if (ret)
1430 goto err_free_rings;
1431 }
1432
1433 return 0;
1434
1435 err_free_rings:
1436 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1437 _rtl_pci_free_rx_ring(hw, rxring_idx);
1438
1439 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1440 if (rtlpci->tx_ring[i].desc ||
1441 rtlpci->tx_ring[i].buffer_desc)
1442 _rtl_pci_free_tx_ring(hw, i);
1443
1444 return 1;
1445 }
1446
1447 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1448 {
1449 u32 i, rxring_idx;
1450
1451 /*free rx rings */
1452 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1453 _rtl_pci_free_rx_ring(hw, rxring_idx);
1454
1455 /*free tx rings */
1456 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1457 _rtl_pci_free_tx_ring(hw, i);
1458
1459 return 0;
1460 }
1461
1462 int rtl92e_pci_reset_trx_ring(struct ieee80211_hw *hw)
1463 {
1464 struct rtl_priv *rtlpriv = rtl_priv(hw);
1465 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1466 int i, rxring_idx;
1467 unsigned long flags;
1468 u8 tmp_one = 1;
1469 /* rxring_idx 0:RX_MPDU_QUEUE */
1470 /* rxring_idx 1:RX_CMD_QUEUE */
1471 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1472 /* force the rx_ring[RX_MPDU_QUEUE]
1473 * RX_CMD_QUEUE].idx to the first one
1474 * If using the new trx flow, do nothing
1475 */
1476 if (!rtlpriv->use_new_trx_flow &&
1477 rtlpci->rx_ring[rxring_idx].desc) {
1478 struct rtl_rx_desc *entry = NULL;
1479
1480 for (i = 0; i < rtlpci->rxringcount; i++) {
1481 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1482 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry,
1483 false,
1484 HW_DESC_RXOWN,
1485 &tmp_one);
1486 }
1487 }
1488 rtlpci->rx_ring[rxring_idx].idx = 0;
1489 }
1490
1491 /* after reset, release previous pending packet,
1492 * and force the tx idx to the first one
1493 */
1494 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1495 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1496 if (rtlpci->tx_ring[i].desc ||
1497 rtlpci->tx_ring[i].buffer_desc) {
1498 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1499
1500 while (skb_queue_len(&ring->queue)) {
1501 struct sk_buff *skb =
1502 __skb_dequeue(&ring->queue);
1503 u8 *entry;
1504
1505 if (rtlpriv->use_new_trx_flow)
1506 entry = (u8 *)(&ring->buffer_desc
1507 [ring->idx]);
1508 else
1509 entry = (u8 *)(&ring->desc[ring->idx]);
1510
1511 pci_unmap_single(rtlpci->pdev,
1512 rtlpriv->cfg->ops->get_desc(
1513 (u8 *)entry, true,
1514 HW_DESC_TXBUFF_ADDR),
1515 skb->len, PCI_DMA_TODEVICE);
1516 kfree_skb(skb);
1517 ring->idx = (ring->idx + 1) % ring->entries;
1518 }
1519 ring->idx = 0;
1520 }
1521 }
1522
1523 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1524
1525 return 0;
1526 }
1527
1528 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1529 struct ieee80211_sta *sta,
1530 struct sk_buff *skb)
1531 {
1532 struct rtl_priv *rtlpriv = rtl_priv(hw);
1533 struct rtl_sta_info *sta_entry = NULL;
1534 u8 tid = rtl_get_tid(skb);
1535 __le16 fc = rtl_get_fc(skb);
1536
1537 if (!sta)
1538 return false;
1539 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1540
1541 if (!rtlpriv->rtlhal.b_earlymode_enable)
1542 return false;
1543 if (ieee80211_is_nullfunc(fc))
1544 return false;
1545 if (ieee80211_is_qos_nullfunc(fc))
1546 return false;
1547 if (ieee80211_is_pspoll(fc))
1548 return false;
1549
1550 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1551 return false;
1552 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1553 return false;
1554 if (tid > 7)
1555 return false;
1556 /* maybe every tid should be checked */
1557 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1558 return false;
1559
1560 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1561 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1562 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1563
1564 return true;
1565 }
1566
1567 static int rtl_pci_tx(struct ieee80211_hw *hw,
1568 struct ieee80211_sta *sta,
1569 struct sk_buff *skb,
1570 struct rtl_tcb_desc *ptcb_desc)
1571 {
1572 struct rtl_priv *rtlpriv = rtl_priv(hw);
1573 struct rtl_sta_info *sta_entry = NULL;
1574 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1575 struct rtl8192_tx_ring *ring;
1576 struct rtl_tx_desc *pdesc;
1577 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1578 u16 idx;
1579 u8 own;
1580 u8 temp_one = 1;
1581 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1582 unsigned long flags;
1583 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1584 __le16 fc = rtl_get_fc(skb);
1585 u8 *pda_addr = hdr->addr1;
1586 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1587 /*ssn */
1588 u8 tid = 0;
1589 u16 seq_number = 0;
1590
1591 if (ieee80211_is_mgmt(fc))
1592 rtl92e_tx_mgmt_proc(hw, skb);
1593
1594 if (rtlpriv->psc.sw_ps_enabled) {
1595 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1596 !ieee80211_has_pm(fc))
1597 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1598 }
1599
1600 rtl92e_action_proc(hw, skb, true);
1601
1602 if (is_multicast_ether_addr(pda_addr))
1603 rtlpriv->stats.txbytesmulticast += skb->len;
1604 else if (is_broadcast_ether_addr(pda_addr))
1605 rtlpriv->stats.txbytesbroadcast += skb->len;
1606 else
1607 rtlpriv->stats.txbytesunicast += skb->len;
1608
1609 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1610 ring = &rtlpci->tx_ring[hw_queue];
1611 if (hw_queue != BEACON_QUEUE) {
1612 if (rtlpriv->use_new_trx_flow)
1613 idx = ring->cur_tx_wp;
1614 else
1615 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1616 ring->entries;
1617 } else {
1618 idx = 0;
1619 }
1620
1621 pdesc = &ring->desc[idx];
1622
1623 if (rtlpriv->use_new_trx_flow) {
1624 ptx_bd_desc = &ring->buffer_desc[idx];
1625 } else {
1626 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc,
1627 true, HW_DESC_OWN);
1628
1629 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1630 RT_TRACE(COMP_ERR, DBG_WARNING,
1631 ("No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1632 hw_queue, ring->idx, idx,
1633 skb_queue_len(&ring->queue)));
1634
1635 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1636 flags);
1637 return skb->len;
1638 }
1639 }
1640
1641 if (ieee80211_is_data_qos(fc)) {
1642 tid = rtl_get_tid(skb);
1643 if (sta) {
1644 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1645 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1646 IEEE80211_SCTL_SEQ) >> 4;
1647 seq_number += 1;
1648
1649 if (!ieee80211_has_morefrags(hdr->frame_control))
1650 sta_entry->tids[tid].seq_number = seq_number;
1651 }
1652 }
1653
1654 if (ieee80211_is_data(fc))
1655 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1656
1657 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1658 (u8 *)ptx_bd_desc, info, sta, skb,
1659 hw_queue, ptcb_desc);
1660
1661 __skb_queue_tail(&ring->queue, skb);
1662 if (rtlpriv->use_new_trx_flow) {
1663 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1664 HW_DESC_OWN, (u8 *)&hw_queue);
1665 } else {
1666 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1667 HW_DESC_OWN, (u8 *)&temp_one);
1668 }
1669
1670 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1671 hw_queue != BEACON_QUEUE) {
1672 RT_TRACE(COMP_ERR, DBG_LOUD,
1673 ("less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1674 hw_queue, ring->idx, idx,
1675 skb_queue_len(&ring->queue)));
1676
1677 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1678 }
1679
1680 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1681
1682 if (rtlpriv->cfg->ops->tx_polling)
1683 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1684
1685 return 0;
1686 }
1687 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1688 {
1689 struct rtl_priv *rtlpriv = rtl_priv(hw);
1690 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1691 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1692 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1693 u16 i = 0;
1694 int queue_id;
1695 struct rtl8192_tx_ring *ring;
1696
1697 if (mac->skip_scan)
1698 return;
1699
1700 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1701 u32 queue_len;
1702 if (((queues >> queue_id) & 0x1) == 0) {
1703 queue_id--;
1704 continue;
1705 }
1706 ring = &pcipriv->dev.tx_ring[queue_id];
1707 queue_len = skb_queue_len(&ring->queue);
1708 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1709 queue_id == TXCMD_QUEUE) {
1710 queue_id--;
1711 continue;
1712 } else {
1713 msleep(5);
1714 i++;
1715 }
1716
1717 /* we just wait 1s for all queues */
1718 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1719 is_hal_stop(rtlhal) || i >= 200)
1720 return;
1721 }
1722 }
1723
1724 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1725 {
1726 struct rtl_priv *rtlpriv = rtl_priv(hw);
1727 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1728
1729 _rtl_pci_deinit_trx_ring(hw);
1730
1731 synchronize_irq(rtlpci->pdev->irq);
1732 tasklet_kill(&rtlpriv->works.irq_tasklet);
1733
1734 flush_workqueue(rtlpriv->works.rtl_wq);
1735 destroy_workqueue(rtlpriv->works.rtl_wq);
1736 }
1737
1738 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1739 {
1740 struct rtl_priv *rtlpriv = rtl_priv(hw);
1741 int err;
1742
1743 _rtl_pci_init_struct(hw, pdev);
1744
1745 err = _rtl_pci_init_trx_ring(hw);
1746 if (err) {
1747 RT_TRACE(COMP_ERR, DBG_EMERG,
1748 ("tx ring initialization failed"));
1749 return err;
1750 }
1751
1752 return 1;
1753 }
1754
1755 static int rtl_pci_start(struct ieee80211_hw *hw)
1756 {
1757 struct rtl_priv *rtlpriv = rtl_priv(hw);
1758 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1759 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1760 int err = 0;
1761
1762 RT_TRACE(COMP_INIT, DBG_DMESG, (" rtl_pci_start\n"));
1763 rtl92e_pci_reset_trx_ring(hw);
1764
1765 rtlpriv->rtlhal.driver_is_goingto_unload = false;
1766 if (rtlpriv->cfg->ops->get_btc_status()) {
1767 rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv);
1768 rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv);
1769 }
1770
1771 err = rtlpriv->cfg->ops->hw_init(hw);
1772 if (err) {
1773 RT_TRACE(COMP_INIT, DBG_DMESG,
1774 ("Failed to config hardware err %x!\n" , err));
1775 return err;
1776 }
1777
1778 rtlpriv->cfg->ops->enable_interrupt(hw);
1779 RT_TRACE(COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1780
1781 rtl92e_init_rx_config(hw);
1782
1783 /*should after adapter start and interrupt enable. */
1784 set_hal_start(rtlhal);
1785
1786 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1787
1788 rtlpriv->rtlhal.up_first_time = false;
1789
1790 RT_TRACE(COMP_INIT, DBG_DMESG, ("rtl_pci_start OK\n"));
1791 return 0;
1792 }
1793
1794 static void rtl_pci_stop(struct ieee80211_hw *hw)
1795 {
1796 struct rtl_priv *rtlpriv = rtl_priv(hw);
1797 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1798 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1799 u8 RFInProgressTimeOut = 0;
1800
1801 if (rtlpriv->cfg->ops->get_btc_status())
1802 rtlpriv->btcoexist.btc_ops->btc_halt_notify();
1803
1804 /*
1805 *should before disable interrrupt&adapter
1806 *and will do it immediately.
1807 */
1808 set_hal_stop(rtlhal);
1809
1810 rtlpriv->cfg->ops->disable_interrupt(hw);
1811
1812 spin_lock(&rtlpriv->locks.rf_ps_lock);
1813 while (ppsc->rfchange_inprogress) {
1814 spin_unlock(&rtlpriv->locks.rf_ps_lock);
1815 if (RFInProgressTimeOut > 100) {
1816 spin_lock(&rtlpriv->locks.rf_ps_lock);
1817 break;
1818 }
1819 mdelay(1);
1820 RFInProgressTimeOut++;
1821 spin_lock(&rtlpriv->locks.rf_ps_lock);
1822 }
1823 ppsc->rfchange_inprogress = true;
1824 spin_unlock(&rtlpriv->locks.rf_ps_lock);
1825
1826 rtlpriv->rtlhal.driver_is_goingto_unload = true;
1827 rtlpriv->cfg->ops->hw_disable(hw);
1828 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1829
1830 spin_lock(&rtlpriv->locks.rf_ps_lock);
1831 ppsc->rfchange_inprogress = false;
1832 spin_unlock(&rtlpriv->locks.rf_ps_lock);
1833
1834 rtl_pci_enable_aspm(hw);
1835 }
1836
1837 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1838 struct ieee80211_hw *hw)
1839 {
1840 struct rtl_priv *rtlpriv = rtl_priv(hw);
1841 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1842 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1843 struct pci_dev *bridge_pdev = pdev->bus->self;
1844 u16 venderid;
1845 u16 deviceid;
1846 u8 revisionid;
1847 u16 irqline;
1848 u8 tmp;
1849
1850 venderid = pdev->vendor;
1851 deviceid = pdev->device;
1852 pci_read_config_byte(pdev, 0x8, &revisionid);
1853 pci_read_config_word(pdev, 0x3C, &irqline);
1854
1855 if (deviceid == RTL_PCI_8192_DID ||
1856 deviceid == RTL_PCI_0044_DID ||
1857 deviceid == RTL_PCI_0047_DID ||
1858 deviceid == RTL_PCI_8192SE_DID ||
1859 deviceid == RTL_PCI_8174_DID ||
1860 deviceid == RTL_PCI_8173_DID ||
1861 deviceid == RTL_PCI_8172_DID ||
1862 deviceid == RTL_PCI_8171_DID) {
1863 switch (revisionid) {
1864 case RTL_PCI_REVISION_ID_8192PCIE:
1865 RT_TRACE(COMP_INIT, DBG_DMESG,
1866 ("8192E is found but not supported now-vid/did=%x/%x\n",
1867 venderid, deviceid));
1868 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1869 return false;
1870 break;
1871 case RTL_PCI_REVISION_ID_8192SE:
1872 RT_TRACE(COMP_INIT, DBG_DMESG,
1873 ("8192SE is found - vid/did=%x/%x\n",
1874 venderid, deviceid));
1875 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1876 break;
1877 default:
1878 RT_TRACE(COMP_ERR, DBG_WARNING,
1879 ("Err: Unknown device - vid/did=%x/%x\n",
1880 venderid, deviceid));
1881 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1882 break;
1883 }
1884 } else if (deviceid == RTL_PCI_8723AE_DID) {
1885 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1886 RT_TRACE(COMP_INIT, DBG_DMESG,
1887 ("8723AE PCI-E is found - vid/did=%x/%x\n",
1888 venderid, deviceid));
1889 } else if (deviceid == RTL_PCI_8192CET_DID ||
1890 deviceid == RTL_PCI_8192CE_DID ||
1891 deviceid == RTL_PCI_8191CE_DID ||
1892 deviceid == RTL_PCI_8188CE_DID) {
1893 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1894 RT_TRACE(COMP_INIT, DBG_DMESG,
1895 ("8192C PCI-E is found - vid/did=%x/%x\n",
1896 venderid, deviceid));
1897 } else if (deviceid == RTL_PCI_8192DE_DID ||
1898 deviceid == RTL_PCI_8192DE_DID2) {
1899 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1900 RT_TRACE(COMP_INIT, DBG_DMESG,
1901 ("8192D PCI-E is found - vid/did=%x/%x\n",
1902 venderid, deviceid));
1903 } else if (deviceid == RTL_PCI_8188EE_DID) {
1904 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1905 RT_TRACE(COMP_INIT , DBG_LOUD,
1906 ("Find adapter, Hardware type is 8188EE\n"));
1907 } else if (deviceid == RTL_PCI_8723BE_DID) {
1908 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1909 RT_TRACE(COMP_INIT , DBG_LOUD,
1910 ("Find adapter, Hardware type is 8723BE\n"));
1911 } else if (deviceid == RTL_PCI_8192EE_DID) {
1912 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1913 RT_TRACE(COMP_INIT , DBG_LOUD,
1914 ("Find adapter, Hardware type is 8192EE\n"));
1915 } else if (deviceid == RTL_PCI_8821AE_DID) {
1916 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1917 RT_TRACE(COMP_INIT , DBG_LOUD,
1918 ("Find adapter, Hardware type is 8821AE\n"));
1919 } else if (deviceid == RTL_PCI_8812AE_DID) {
1920 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1921 RT_TRACE(COMP_INIT , DBG_LOUD,
1922 ("Find adapter, Hardware type is 8812AE\n"));
1923 } else {
1924 RT_TRACE(COMP_ERR, DBG_WARNING,
1925 ("Err: Unknown device - vid/did=%x/%x\n",
1926 venderid, deviceid));
1927
1928 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1929 }
1930
1931 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1932 if (revisionid == 0 || revisionid == 1) {
1933 if (revisionid == 0) {
1934 RT_TRACE(COMP_INIT, DBG_LOUD,
1935 ("Find 92DE MAC0.\n"));
1936 rtlhal->interfaceindex = 0;
1937 } else if (revisionid == 1) {
1938 RT_TRACE(COMP_INIT, DBG_LOUD,
1939 ("Find 92DE MAC1.\n"));
1940 rtlhal->interfaceindex = 1;
1941 }
1942 } else {
1943 RT_TRACE(COMP_INIT, DBG_LOUD,
1944 ("Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1945 venderid, deviceid, revisionid));
1946 rtlhal->interfaceindex = 0;
1947 }
1948 }
1949
1950 /* 92ee use new trx flow */
1951 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1952 rtlpriv->use_new_trx_flow = true;
1953 else
1954 rtlpriv->use_new_trx_flow = false;
1955
1956 /*find bus info */
1957 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1958 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1959 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1960
1961 /*find bridge info */
1962 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1963 /* some ARM have no bridge_pdev and will crash here
1964 * so we should check if bridge_pdev is NULL */
1965 if (bridge_pdev) {
1966 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1967 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1968 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1969 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1970 RT_TRACE(COMP_INIT, DBG_DMESG,
1971 ("Pci Bridge Vendor is found index: %d\n",
1972 tmp));
1973 break;
1974 }
1975 }
1976 }
1977
1978 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1979 PCI_BRIDGE_VENDOR_UNKNOWN) {
1980 pcipriv->ndis_adapter.pcibridge_busnum =
1981 bridge_pdev->bus->number;
1982 pcipriv->ndis_adapter.pcibridge_devnum =
1983 PCI_SLOT(bridge_pdev->devfn);
1984 pcipriv->ndis_adapter.pcibridge_funcnum =
1985 PCI_FUNC(bridge_pdev->devfn);
1986 pcipriv->ndis_adapter.pcicfg_addrport =
1987 (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
1988 (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
1989 (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
1990 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1991 pci_pcie_cap(bridge_pdev);
1992 pcipriv->ndis_adapter.num4bytes =
1993 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1994
1995 rtl_pci_get_linkcontrol_field(hw);
1996
1997 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1998 PCI_BRIDGE_VENDOR_AMD) {
1999 pcipriv->ndis_adapter.amd_l1_patch =
2000 rtl_pci_get_amd_l1_patch(hw);
2001 }
2002 }
2003
2004 RT_TRACE(COMP_INIT, DBG_DMESG,
2005 ("pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2006 pcipriv->ndis_adapter.busnumber,
2007 pcipriv->ndis_adapter.devnumber,
2008 pcipriv->ndis_adapter.funcnumber,
2009 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
2010
2011 RT_TRACE(COMP_INIT, DBG_DMESG,
2012 ("pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2013 pcipriv->ndis_adapter.pcibridge_busnum,
2014 pcipriv->ndis_adapter.pcibridge_devnum,
2015 pcipriv->ndis_adapter.pcibridge_funcnum,
2016 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2017 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2018 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2019 pcipriv->ndis_adapter.amd_l1_patch));
2020
2021 rtl_pci_parse_configuration(pdev, hw);
2022 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2023 return true;
2024 }
2025
2026 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2027 {
2028 struct rtl_priv *rtlpriv = rtl_priv(hw);
2029 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2030 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2031 int ret;
2032 ret = pci_enable_msi(rtlpci->pdev);
2033 if (ret < 0)
2034 return ret;
2035
2036 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2037 IRQF_SHARED, KBUILD_MODNAME, hw);
2038 if (ret < 0) {
2039 pci_disable_msi(rtlpci->pdev);
2040 return ret;
2041 }
2042
2043 rtlpci->using_msi = true;
2044
2045 RT_TRACE(COMP_INIT|COMP_INTR, DBG_DMESG, ("MSI Interrupt Mode!\n"));
2046 return 0;
2047 }
2048
2049 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2050 {
2051 struct rtl_priv *rtlpriv = rtl_priv(hw);
2052 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2053 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2054 int ret;
2055
2056 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2057 IRQF_SHARED, KBUILD_MODNAME, hw);
2058 if (ret < 0)
2059 return ret;
2060
2061 rtlpci->using_msi = false;
2062 RT_TRACE(COMP_INIT|COMP_INTR, DBG_DMESG,
2063 ("Pin-based Interrupt Mode!\n"));
2064 return 0;
2065 }
2066
2067 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2068 {
2069 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2070 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2071 int ret;
2072 if (rtlpci->msi_support) {
2073 ret = rtl_pci_intr_mode_msi(hw);
2074 if (ret < 0)
2075 ret = rtl_pci_intr_mode_legacy(hw);
2076 } else {
2077 ret = rtl_pci_intr_mode_legacy(hw);
2078 }
2079 return ret;
2080 }
2081
2082 /* this is used for other modules get
2083 * hw pointer in rtl_pci_get_hw_pointer */
2084 static struct ieee80211_hw *hw_export;
2085
2086 int stg_rtl_pci_probe(struct pci_dev *pdev,
2087 const struct pci_device_id *id)
2088 {
2089 struct ieee80211_hw *hw = NULL;
2090 struct rtl_priv *rtlpriv = NULL;
2091 struct rtl_pci_priv *pcipriv = NULL;
2092 struct rtl_pci *rtlpci;
2093 unsigned long pmem_start, pmem_len, pmem_flags;
2094 int err;
2095
2096 err = pci_enable_device(pdev);
2097 if (err) {
2098 RT_ASSERT(false,
2099 ("%s : Cannot enable new PCI device\n",
2100 pci_name(pdev)));
2101 return err;
2102 }
2103
2104 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2105 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2106 RT_ASSERT(false,
2107 ("Unable to obtain 32bit DMA for consistent allocations\n"));
2108 pci_disable_device(pdev);
2109 return -ENOMEM;
2110 }
2111 }
2112
2113 pci_set_master(pdev);
2114
2115 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2116 sizeof(struct rtl_priv), &rtl92e_ops);
2117 if (!hw) {
2118 RT_ASSERT(false,
2119 ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
2120 err = -ENOMEM;
2121 goto fail1;
2122 }
2123 hw_export = hw;
2124
2125 SET_IEEE80211_DEV(hw, &pdev->dev);
2126 pci_set_drvdata(pdev, hw);
2127
2128 rtlpriv = hw->priv;
2129 pcipriv = (void *)rtlpriv->priv;
2130 pcipriv->dev.pdev = pdev;
2131
2132 /* init cfg & intf_ops */
2133 rtlpriv->rtlhal.interface = INTF_PCI;
2134 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2135 rtlpriv->intf_ops = &rtl92e_pci_ops;
2136 rtlpriv->glb_var = &global_var;
2137
2138 /*
2139 *init dbgp flags before all
2140 *other functions, because we will
2141 *use it in other funtions like
2142 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
2143 *you can not use these macro
2144 *before this
2145 */
2146 rtl92e_dbgp_flag_init(hw);
2147
2148 /* MEM map */
2149 err = pci_request_regions(pdev, KBUILD_MODNAME);
2150 if (err) {
2151 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
2152 return err;
2153 }
2154
2155 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2156 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2157 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2158
2159 /*shared mem start */
2160 rtlpriv->io.pci_mem_start =
2161 (unsigned long)pci_iomap(pdev,
2162 rtlpriv->cfg->bar_id, pmem_len);
2163 if (rtlpriv->io.pci_mem_start == 0) {
2164 RT_ASSERT(false, ("Can't map PCI mem\n"));
2165 goto fail2;
2166 }
2167
2168 RT_TRACE(COMP_INIT, DBG_DMESG,
2169 ("mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2170 pmem_start, pmem_len, pmem_flags,
2171 rtlpriv->io.pci_mem_start));
2172
2173 /* Disable Clk Request */
2174 pci_write_config_byte(pdev, 0x81, 0);
2175 /* leave D3 mode */
2176 pci_write_config_byte(pdev, 0x44, 0);
2177 pci_write_config_byte(pdev, 0x04, 0x06);
2178 pci_write_config_byte(pdev, 0x04, 0x07);
2179
2180 /* The next statement is needed when built as single module */
2181 rtl_core_module_init();
2182
2183 /* find adapter */
2184 /* if chip not support, will return false */
2185 if (!_rtl_pci_find_adapter(pdev, hw))
2186 goto fail3;
2187
2188 /* Init IO handler */
2189 _rtl_pci_io_handler_init(&pdev->dev, hw);
2190
2191 /*like read eeprom and so on */
2192 rtlpriv->cfg->ops->read_eeprom_info(hw);
2193
2194 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2195 RT_TRACE(COMP_ERR, DBG_EMERG, ("Can't init_sw_vars.\n"));
2196 goto fail3;
2197 }
2198
2199 rtlpriv->cfg->ops->init_sw_leds(hw);
2200
2201 /*aspm */
2202 rtl_pci_init_aspm(hw);
2203
2204 /* Init mac80211 sw */
2205 err = rtl92e_init_core(hw);
2206 if (err) {
2207 RT_TRACE(COMP_ERR, DBG_EMERG,
2208 ("Can't allocate sw for mac80211.\n"));
2209 goto fail3;
2210 }
2211
2212 /* Init PCI sw */
2213 err = !rtl_pci_init(hw, pdev);
2214 if (err) {
2215 RT_TRACE(COMP_ERR, DBG_EMERG, ("Failed to init PCI.\n"));
2216 goto fail3;
2217 }
2218
2219 err = ieee80211_register_hw(hw);
2220 if (err) {
2221 RT_TRACE(COMP_ERR, DBG_EMERG,
2222 ("Can't register mac80211 hw.\n"));
2223 goto fail3;
2224 } else {
2225 rtlpriv->mac80211.mac80211_registered = 1;
2226 }
2227 /* the wiphy must have been registed to
2228 * cfg80211 prior to regulatory_hint */
2229 if (regulatory_hint(hw->wiphy, rtlpriv->regd.alpha2))
2230 RT_TRACE(COMP_ERR, DBG_WARNING, ("regulatory_hint fail\n"));
2231
2232 /* add for prov */
2233 rtl_proc_add_one(hw);
2234
2235 /*init rfkill */
2236 rtl92e_init_rfkill(hw);
2237
2238 rtlpci = rtl_pcidev(pcipriv);
2239 err = rtl_pci_intr_mode_decide(hw);
2240 if (err) {
2241 RT_TRACE(COMP_INIT, DBG_DMESG,
2242 ("%s: failed to register IRQ handler\n",
2243 wiphy_name(hw->wiphy)));
2244 goto fail3;
2245 } else {
2246 rtlpci->irq_alloc = 1;
2247 }
2248
2249 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2250 return 0;
2251
2252 fail3:
2253 pci_set_drvdata(pdev, NULL);
2254 rtl92e_deinit_core(hw);
2255 ieee80211_free_hw(hw);
2256
2257 if (rtlpriv->io.pci_mem_start != 0)
2258 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2259
2260 fail2:
2261 pci_release_regions(pdev);
2262
2263 fail1:
2264
2265 pci_disable_device(pdev);
2266
2267 return -ENODEV;
2268 }
2269 EXPORT_SYMBOL(stg_rtl_pci_probe);
2270
2271 struct ieee80211_hw *rtl_pci_get_hw_pointer(void)
2272 {
2273 return hw_export;
2274 }
2275 EXPORT_SYMBOL(rtl_pci_get_hw_pointer);
2276
2277 void stg_rtl_pci_disconnect(struct pci_dev *pdev)
2278 {
2279 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2280 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2281 struct rtl_priv *rtlpriv = rtl_priv(hw);
2282 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2283 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2284
2285 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2286
2287 /* add for prov */
2288 rtl_proc_remove_one(hw);
2289
2290 /*ieee80211_unregister_hw will call ops_stop */
2291 if (rtlmac->mac80211_registered == 1) {
2292 ieee80211_unregister_hw(hw);
2293 rtlmac->mac80211_registered = 0;
2294 } else {
2295 rtl92e_deinit_deferred_work(hw);
2296 rtlpriv->intf_ops->adapter_stop(hw);
2297 }
2298
2299 /*deinit rfkill */
2300 rtl92e_deinit_rfkill(hw);
2301
2302 rtl_pci_deinit(hw);
2303 rtl92e_deinit_core(hw);
2304 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2305
2306 if (rtlpci->irq_alloc) {
2307 synchronize_irq(rtlpci->pdev->irq);
2308 free_irq(rtlpci->pdev->irq, hw);
2309 rtlpci->irq_alloc = 0;
2310 }
2311
2312 if (rtlpci->using_msi)
2313 pci_disable_msi(rtlpci->pdev);
2314
2315 list_del(&rtlpriv->list);
2316 if (rtlpriv->io.pci_mem_start != 0) {
2317 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2318 pci_release_regions(pdev);
2319 }
2320
2321 pci_disable_device(pdev);
2322
2323 rtl_pci_disable_aspm(hw);
2324
2325 pci_set_drvdata(pdev, NULL);
2326
2327 ieee80211_free_hw(hw);
2328 }
2329 EXPORT_SYMBOL(stg_rtl_pci_disconnect);
2330
2331 /***************************************
2332 kernel pci power state define:
2333 PCI_D0 ((pci_power_t __force) 0)
2334 PCI_D1 ((pci_power_t __force) 1)
2335 PCI_D2 ((pci_power_t __force) 2)
2336 PCI_D3hot ((pci_power_t __force) 3)
2337 PCI_D3cold ((pci_power_t __force) 4)
2338 PCI_UNKNOWN ((pci_power_t __force) 5)
2339
2340 This function is called when system
2341 goes into suspend state mac80211 will
2342 call rtl_mac_stop() from the mac80211
2343 suspend function first, So there is
2344 no need to call hw_disable here.
2345 ****************************************/
2346 int stg_rtl_pci_suspend(struct device *dev)
2347 {
2348 struct pci_dev *pdev = to_pci_dev(dev);
2349 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2350 struct rtl_priv *rtlpriv = rtl_priv(hw);
2351
2352 rtlpriv->cfg->ops->hw_suspend(hw);
2353 rtl92e_deinit_rfkill(hw);
2354
2355 return 0;
2356 }
2357 EXPORT_SYMBOL(stg_rtl_pci_suspend);
2358
2359 int stg_rtl_pci_resume(struct device *dev)
2360 {
2361 struct pci_dev *pdev = to_pci_dev(dev);
2362 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2363 struct rtl_priv *rtlpriv = rtl_priv(hw);
2364
2365 rtlpriv->cfg->ops->hw_resume(hw);
2366 rtl92e_init_rfkill(hw);
2367
2368 return 0;
2369 }
2370 EXPORT_SYMBOL(stg_rtl_pci_resume);
2371
2372 struct rtl_intf_ops rtl92e_pci_ops = {
2373 .read92e_efuse_byte = read92e_efuse_byte,
2374 .adapter_start = rtl_pci_start,
2375 .adapter_stop = rtl_pci_stop,
2376 .check_buddy_priv = rtl_pci_check_buddy_priv,
2377 .adapter_tx = rtl_pci_tx,
2378 .flush = rtl_pci_flush,
2379 .reset_trx_ring = rtl92e_pci_reset_trx_ring,
2380 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2381
2382 .disable_aspm = rtl_pci_disable_aspm,
2383 .enable_aspm = rtl_pci_enable_aspm,
2384 };
Linux with added FPC-III support