arch/mips/include/asm/txx9/tx4938.h

   1 /*
   2  * Definitions for TX4937/TX4938
   3  * Copyright (C) 2000-2001 Toshiba Corporation
   4  *
   5  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
   6  * terms of the GNU General Public License version 2. This program is
   7  * licensed "as is" without any warranty of any kind, whether express
   8  * or implied.
   9  *
  10  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  11  */
  12 #ifndef __ASM_TXX9_TX4938_H
  13 #define __ASM_TXX9_TX4938_H
  14
  15 /* some controllers are compatible with 4927 */
  16 #include <asm/txx9/tx4927.h>
  17
  18 #ifdef CONFIG_64BIT
  19 #define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
  20 #else
  21 #define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
  22 #endif
  23 #define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
  24
  25 /* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
  26 #define TX4938_NDFMC_REG        (TX4938_REG_BASE + 0x5000)
  27 #define TX4938_SRAMC_REG        (TX4938_REG_BASE + 0x6000)
  28 #define TX4938_PCIC1_REG        (TX4938_REG_BASE + 0x7000)
  29 #define TX4938_SDRAMC_REG       (TX4938_REG_BASE + 0x8000)
  30 #define TX4938_EBUSC_REG        (TX4938_REG_BASE + 0x9000)
  31 #define TX4938_DMA_REG(ch)      (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
  32 #define TX4938_PCIC_REG         (TX4938_REG_BASE + 0xd000)
  33 #define TX4938_CCFG_REG         (TX4938_REG_BASE + 0xe000)
  34 #define TX4938_NR_TMR   3
  35 #define TX4938_TMR_REG(ch)      ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
  36 #define TX4938_NR_SIO   2
  37 #define TX4938_SIO_REG(ch)      ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
  38 #define TX4938_PIO_REG          (TX4938_REG_BASE + 0xf500)
  39 #define TX4938_IRC_REG          (TX4938_REG_BASE + 0xf600)
  40 #define TX4938_ACLC_REG         (TX4938_REG_BASE + 0xf700)
  41 #define TX4938_SPI_REG          (TX4938_REG_BASE + 0xf800)
  42
  43 struct tx4938_sramc_reg {
  44         u64 cr;
  45 };
  46
  47 struct tx4938_ccfg_reg {
  48         u64 ccfg;
  49         u64 crir;
  50         u64 pcfg;
  51         u64 toea;
  52         u64 clkctr;
  53         u64 unused0;
  54         u64 garbc;
  55         u64 unused1;
  56         u64 unused2;
  57         u64 ramp;
  58         u64 unused3;
  59         u64 jmpadr;
  60 };
  61
  62 /*
  63  * IRC
  64  */
  65
  66 #define TX4938_IR_ECCERR        0
  67 #define TX4938_IR_WTOERR        1
  68 #define TX4938_NUM_IR_INT       6
  69 #define TX4938_IR_INT(n)        (2 + (n))
  70 #define TX4938_NUM_IR_SIO       2
  71 #define TX4938_IR_SIO(n)        (8 + (n))
  72 #define TX4938_NUM_IR_DMA       4
  73 #define TX4938_IR_DMA(ch, n)    ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
  74 #define TX4938_IR_PIO   14
  75 #define TX4938_IR_PDMAC 15
  76 #define TX4938_IR_PCIC  16
  77 #define TX4938_NUM_IR_TMR       3
  78 #define TX4938_IR_TMR(n)        (17 + (n))
  79 #define TX4938_IR_NDFMC 21
  80 #define TX4938_IR_PCIERR        22
  81 #define TX4938_IR_PCIPME        23
  82 #define TX4938_IR_ACLC  24
  83 #define TX4938_IR_ACLCPME       25
  84 #define TX4938_IR_PCIC1 26
  85 #define TX4938_IR_SPI   31
  86 #define TX4938_NUM_IR   32
  87 /* multiplex */
  88 #define TX4938_IR_ETH0  TX4938_IR_INT(4)
  89 #define TX4938_IR_ETH1  TX4938_IR_INT(3)
  90
  91 #define TX4938_IRC_INT  2       /* IP[2] in Status register */
  92
  93 #define TX4938_NUM_PIO  16
  94
  95 /*
  96  * CCFG
  97  */
  98 /* CCFG : Chip Configuration */
  99 #define TX4938_CCFG_WDRST       0x0000020000000000ULL
 100 #define TX4938_CCFG_WDREXEN     0x0000010000000000ULL
 101 #define TX4938_CCFG_BCFG_MASK   0x000000ff00000000ULL
 102 #define TX4938_CCFG_TINTDIS     0x01000000
 103 #define TX4938_CCFG_PCI66       0x00800000
 104 #define TX4938_CCFG_PCIMODE     0x00400000
 105 #define TX4938_CCFG_PCI1_66     0x00200000
 106 #define TX4938_CCFG_DIVMODE_MASK        0x001e0000
 107 #define TX4938_CCFG_DIVMODE_2   (0x4 << 17)
 108 #define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
 109 #define TX4938_CCFG_DIVMODE_3   (0x5 << 17)
 110 #define TX4938_CCFG_DIVMODE_4   (0x6 << 17)
 111 #define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
 112 #define TX4938_CCFG_DIVMODE_8   (0x0 << 17)
 113 #define TX4938_CCFG_DIVMODE_10  (0xb << 17)
 114 #define TX4938_CCFG_DIVMODE_12  (0x1 << 17)
 115 #define TX4938_CCFG_DIVMODE_16  (0x2 << 17)
 116 #define TX4938_CCFG_DIVMODE_18  (0x9 << 17)
 117 #define TX4938_CCFG_BEOW        0x00010000
 118 #define TX4938_CCFG_WR  0x00008000
 119 #define TX4938_CCFG_TOE 0x00004000
 120 #define TX4938_CCFG_PCIARB      0x00002000
 121 #define TX4938_CCFG_PCIDIVMODE_MASK     0x00001c00
 122 #define TX4938_CCFG_PCIDIVMODE_4        (0x1 << 10)
 123 #define TX4938_CCFG_PCIDIVMODE_4_5      (0x3 << 10)
 124 #define TX4938_CCFG_PCIDIVMODE_5        (0x5 << 10)
 125 #define TX4938_CCFG_PCIDIVMODE_5_5      (0x7 << 10)
 126 #define TX4938_CCFG_PCIDIVMODE_8        (0x0 << 10)
 127 #define TX4938_CCFG_PCIDIVMODE_9        (0x2 << 10)
 128 #define TX4938_CCFG_PCIDIVMODE_10       (0x4 << 10)
 129 #define TX4938_CCFG_PCIDIVMODE_11       (0x6 << 10)
 130 #define TX4938_CCFG_PCI1DMD     0x00000100
 131 #define TX4938_CCFG_SYSSP_MASK  0x000000c0
 132 #define TX4938_CCFG_ENDIAN      0x00000004
 133 #define TX4938_CCFG_HALT        0x00000002
 134 #define TX4938_CCFG_ACEHOLD     0x00000001
 135
 136 /* PCFG : Pin Configuration */
 137 #define TX4938_PCFG_ETH0_SEL    0x8000000000000000ULL
 138 #define TX4938_PCFG_ETH1_SEL    0x4000000000000000ULL
 139 #define TX4938_PCFG_ATA_SEL     0x2000000000000000ULL
 140 #define TX4938_PCFG_ISA_SEL     0x1000000000000000ULL
 141 #define TX4938_PCFG_SPI_SEL     0x0800000000000000ULL
 142 #define TX4938_PCFG_NDF_SEL     0x0400000000000000ULL
 143 #define TX4938_PCFG_SDCLKDLY_MASK       0x30000000
 144 #define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
 145 #define TX4938_PCFG_SYSCLKEN    0x08000000
 146 #define TX4938_PCFG_SDCLKEN_ALL 0x07800000
 147 #define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
 148 #define TX4938_PCFG_PCICLKEN_ALL        0x003f0000
 149 #define TX4938_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
 150 #define TX4938_PCFG_SEL2        0x00000200
 151 #define TX4938_PCFG_SEL1        0x00000100
 152 #define TX4938_PCFG_DMASEL_ALL  0x0000000f
 153 #define TX4938_PCFG_DMASEL0_DRQ0        0x00000000
 154 #define TX4938_PCFG_DMASEL0_SIO1        0x00000001
 155 #define TX4938_PCFG_DMASEL1_DRQ1        0x00000000
 156 #define TX4938_PCFG_DMASEL1_SIO1        0x00000002
 157 #define TX4938_PCFG_DMASEL2_DRQ2        0x00000000
 158 #define TX4938_PCFG_DMASEL2_SIO0        0x00000004
 159 #define TX4938_PCFG_DMASEL3_DRQ3        0x00000000
 160 #define TX4938_PCFG_DMASEL3_SIO0        0x00000008
 161
 162 /* CLKCTR : Clock Control */
 163 #define TX4938_CLKCTR_NDFCKD    0x0001000000000000ULL
 164 #define TX4938_CLKCTR_NDFRST    0x0000000100000000ULL
 165 #define TX4938_CLKCTR_ETH1CKD   0x80000000
 166 #define TX4938_CLKCTR_ETH0CKD   0x40000000
 167 #define TX4938_CLKCTR_SPICKD    0x20000000
 168 #define TX4938_CLKCTR_SRAMCKD   0x10000000
 169 #define TX4938_CLKCTR_PCIC1CKD  0x08000000
 170 #define TX4938_CLKCTR_DMA1CKD   0x04000000
 171 #define TX4938_CLKCTR_ACLCKD    0x02000000
 172 #define TX4938_CLKCTR_PIOCKD    0x01000000
 173 #define TX4938_CLKCTR_DMACKD    0x00800000
 174 #define TX4938_CLKCTR_PCICKD    0x00400000
 175 #define TX4938_CLKCTR_TM0CKD    0x00100000
 176 #define TX4938_CLKCTR_TM1CKD    0x00080000
 177 #define TX4938_CLKCTR_TM2CKD    0x00040000
 178 #define TX4938_CLKCTR_SIO0CKD   0x00020000
 179 #define TX4938_CLKCTR_SIO1CKD   0x00010000
 180 #define TX4938_CLKCTR_ETH1RST   0x00008000
 181 #define TX4938_CLKCTR_ETH0RST   0x00004000
 182 #define TX4938_CLKCTR_SPIRST    0x00002000
 183 #define TX4938_CLKCTR_SRAMRST   0x00001000
 184 #define TX4938_CLKCTR_PCIC1RST  0x00000800
 185 #define TX4938_CLKCTR_DMA1RST   0x00000400
 186 #define TX4938_CLKCTR_ACLRST    0x00000200
 187 #define TX4938_CLKCTR_PIORST    0x00000100
 188 #define TX4938_CLKCTR_DMARST    0x00000080
 189 #define TX4938_CLKCTR_PCIRST    0x00000040
 190 #define TX4938_CLKCTR_TM0RST    0x00000010
 191 #define TX4938_CLKCTR_TM1RST    0x00000008
 192 #define TX4938_CLKCTR_TM2RST    0x00000004
 193 #define TX4938_CLKCTR_SIO0RST   0x00000002
 194 #define TX4938_CLKCTR_SIO1RST   0x00000001
 195
 196 /*
 197  * DMA
 198  */
 199 /* bits for MCR */
 200 #define TX4938_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
 201 #define TX4938_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
 202 #define TX4938_DMA_MCR_RSFIF    0x00000080
 203 #define TX4938_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
 204 #define TX4938_DMA_MCR_RPRT     0x00000002
 205 #define TX4938_DMA_MCR_MSTEN    0x00000001
 206
 207 /* bits for CCRn */
 208 #define TX4938_DMA_CCR_IMMCHN   0x20000000
 209 #define TX4938_DMA_CCR_USEXFSZ  0x10000000
 210 #define TX4938_DMA_CCR_LE       0x08000000
 211 #define TX4938_DMA_CCR_DBINH    0x04000000
 212 #define TX4938_DMA_CCR_SBINH    0x02000000
 213 #define TX4938_DMA_CCR_CHRST    0x01000000
 214 #define TX4938_DMA_CCR_RVBYTE   0x00800000
 215 #define TX4938_DMA_CCR_ACKPOL   0x00400000
 216 #define TX4938_DMA_CCR_REQPL    0x00200000
 217 #define TX4938_DMA_CCR_EGREQ    0x00100000
 218 #define TX4938_DMA_CCR_CHDN     0x00080000
 219 #define TX4938_DMA_CCR_DNCTL    0x00060000
 220 #define TX4938_DMA_CCR_EXTRQ    0x00010000
 221 #define TX4938_DMA_CCR_INTRQD   0x0000e000
 222 #define TX4938_DMA_CCR_INTENE   0x00001000
 223 #define TX4938_DMA_CCR_INTENC   0x00000800
 224 #define TX4938_DMA_CCR_INTENT   0x00000400
 225 #define TX4938_DMA_CCR_CHNEN    0x00000200
 226 #define TX4938_DMA_CCR_XFACT    0x00000100
 227 #define TX4938_DMA_CCR_SMPCHN   0x00000020
 228 #define TX4938_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
 229 #define TX4938_DMA_CCR_XFSZ_1W  TX4938_DMA_CCR_XFSZ(2)
 230 #define TX4938_DMA_CCR_XFSZ_2W  TX4938_DMA_CCR_XFSZ(3)
 231 #define TX4938_DMA_CCR_XFSZ_4W  TX4938_DMA_CCR_XFSZ(4)
 232 #define TX4938_DMA_CCR_XFSZ_8W  TX4938_DMA_CCR_XFSZ(5)
 233 #define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
 234 #define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
 235 #define TX4938_DMA_CCR_MEMIO    0x00000002
 236 #define TX4938_DMA_CCR_SNGAD    0x00000001
 237
 238 /* bits for CSRn */
 239 #define TX4938_DMA_CSR_CHNEN    0x00000400
 240 #define TX4938_DMA_CSR_STLXFER  0x00000200
 241 #define TX4938_DMA_CSR_CHNACT   0x00000100
 242 #define TX4938_DMA_CSR_ABCHC    0x00000080
 243 #define TX4938_DMA_CSR_NCHNC    0x00000040
 244 #define TX4938_DMA_CSR_NTRNFC   0x00000020
 245 #define TX4938_DMA_CSR_EXTDN    0x00000010
 246 #define TX4938_DMA_CSR_CFERR    0x00000008
 247 #define TX4938_DMA_CSR_CHERR    0x00000004
 248 #define TX4938_DMA_CSR_DESERR   0x00000002
 249 #define TX4938_DMA_CSR_SORERR   0x00000001
 250
 251 #define tx4938_sdramcptr        tx4927_sdramcptr
 252 #define tx4938_ebuscptr         tx4927_ebuscptr
 253 #define tx4938_pcicptr          tx4927_pcicptr
 254 #define tx4938_pcic1ptr \
 255                 ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
 256 #define tx4938_ccfgptr \
 257                 ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
 258 #define tx4938_pioptr           ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
 259 #define tx4938_sramcptr \
 260                 ((struct tx4938_sramc_reg __iomem *)TX4938_SRAMC_REG)
 261
 262
 263 #define TX4938_REV_PCODE()      \
 264         ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
 265
 266 #define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
 267 #define tx4938_ccfg_set(bits)   tx4927_ccfg_set(bits)
 268 #define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
 269
 270 #define TX4938_SDRAMC_CR(ch)    TX4927_SDRAMC_CR(ch)
 271 #define TX4938_SDRAMC_BA(ch)    TX4927_SDRAMC_BA(ch)
 272 #define TX4938_SDRAMC_SIZE(ch)  TX4927_SDRAMC_SIZE(ch)
 273
 274 #define TX4938_EBUSC_CR(ch)     TX4927_EBUSC_CR(ch)
 275 #define TX4938_EBUSC_BA(ch)     TX4927_EBUSC_BA(ch)
 276 #define TX4938_EBUSC_SIZE(ch)   TX4927_EBUSC_SIZE(ch)
 277 #define TX4938_EBUSC_WIDTH(ch)  TX4927_EBUSC_WIDTH(ch)
 278
 279 #define tx4938_get_mem_size() tx4927_get_mem_size()
 280 void tx4938_wdt_init(void);
 281 void tx4938_setup(void);
 282 void tx4938_time_init(unsigned int tmrnr);
 283 void tx4938_sio_init(unsigned int sclk, unsigned int cts_mask);
 284 void tx4938_spi_init(int busid);
 285 void tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
 286 int tx4938_report_pciclk(void);
 287 void tx4938_report_pci1clk(void);
 288 int tx4938_pciclk66_setup(void);
 289 struct pci_dev;
 290 int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
 291 void tx4938_setup_pcierr_irq(void);
 292 void tx4938_irq_init(void);
 293 void tx4938_mtd_init(int ch);
 294
 295 struct tx4938ide_platform_info {
 296         /*
 297          * I/O port shift, for platforms with ports that are
 298          * constantly spaced and need larger than the 1-byte
 299          * spacing used by ata_std_ports().
 300          */
 301         unsigned int ioport_shift;
 302         unsigned int gbus_clock;        /*  0 means no PIO mode tuning. */
 303         unsigned int ebus_ch;
 304 };
 305
 306 void tx4938_ata_init(unsigned int irq, unsigned int shift, int tune);
 307
 308 #endif