drivers/net/fddi/skfp/h/skfbi.h

   1 /******************************************************************************
   2  *
   3  *      (C)Copyright 1998,1999 SysKonnect,
   4  *      a business unit of Schneider & Koch & Co. Datensysteme GmbH.
   5  *
   6  *      This program is free software; you can redistribute it and/or modify
   7  *      it under the terms of the GNU General Public License as published by
   8  *      the Free Software Foundation; either version 2 of the License, or
   9  *      (at your option) any later version.
  10  *
  11  *      The information in this file is provided "AS IS" without warranty.
  12  *
  13  ******************************************************************************/
  14
  15 #ifndef _SKFBI_H_
  16 #define _SKFBI_H_
  17
  18 /*
  19  * FDDI-Fx (x := {I(SA), P(CI)})
  20  *      address calculation & function defines
  21  */
  22
  23 /*--------------------------------------------------------------------------*/
  24 #ifdef  PCI
  25
  26 /*
  27  *      (DV)    = only defined for Da Vinci
  28  *      (ML)    = only defined for Monalisa
  29  */
  30
  31 /*
  32  * Configuration Space header
  33  */
  34 #define PCI_VENDOR_ID   0x00    /* 16 bit       Vendor ID */
  35 #define PCI_DEVICE_ID   0x02    /* 16 bit       Device ID */
  36 #define PCI_COMMAND     0x04    /* 16 bit       Command */
  37 #define PCI_STATUS      0x06    /* 16 bit       Status */
  38 #define PCI_REV_ID      0x08    /*  8 bit       Revision ID */
  39 #define PCI_CLASS_CODE  0x09    /* 24 bit       Class Code */
  40 #define PCI_CACHE_LSZ   0x0c    /*  8 bit       Cache Line Size */
  41 #define PCI_LAT_TIM     0x0d    /*  8 bit       Latency Timer */
  42 #define PCI_HEADER_T    0x0e    /*  8 bit       Header Type */
  43 #define PCI_BIST        0x0f    /*  8 bit       Built-in selftest */
  44 #define PCI_BASE_1ST    0x10    /* 32 bit       1st Base address */
  45 #define PCI_BASE_2ND    0x14    /* 32 bit       2nd Base address */
  46 /* Byte 18..2b: Reserved */
  47 #define PCI_SUB_VID     0x2c    /* 16 bit       Subsystem Vendor ID */
  48 #define PCI_SUB_ID      0x2e    /* 16 bit       Subsystem ID */
  49 #define PCI_BASE_ROM    0x30    /* 32 bit       Expansion ROM Base Address */
  50 /* Byte 34..33: Reserved */
  51 #define PCI_CAP_PTR     0x34    /*  8 bit (ML)  Capabilities Ptr */
  52 /* Byte 35..3b: Reserved */
  53 #define PCI_IRQ_LINE    0x3c    /*  8 bit       Interrupt Line */
  54 #define PCI_IRQ_PIN     0x3d    /*  8 bit       Interrupt Pin */
  55 #define PCI_MIN_GNT     0x3e    /*  8 bit       Min_Gnt */
  56 #define PCI_MAX_LAT     0x3f    /*  8 bit       Max_Lat */
  57 /* Device Dependent Region */
  58 #define PCI_OUR_REG     0x40    /* 32 bit (DV)  Our Register */
  59 #define PCI_OUR_REG_1   0x40    /* 32 bit (ML)  Our Register 1 */
  60 #define PCI_OUR_REG_2   0x44    /* 32 bit (ML)  Our Register 2 */
  61 /* Power Management Region */
  62 #define PCI_PM_CAP_ID   0x48    /*  8 bit (ML)  Power Management Cap. ID */
  63 #define PCI_PM_NITEM    0x49    /*  8 bit (ML)  Next Item Ptr */
  64 #define PCI_PM_CAP_REG  0x4a    /* 16 bit (ML)  Power Management Capabilities */
  65 #define PCI_PM_CTL_STS  0x4c    /* 16 bit (ML)  Power Manag. Control/Status */
  66 /* Byte 0x4e:   Reserved */
  67 #define PCI_PM_DAT_REG  0x4f    /*  8 bit (ML)  Power Manag. Data Register */
  68 /* VPD Region */
  69 #define PCI_VPD_CAP_ID  0x50    /*  8 bit (ML)  VPD Cap. ID */
  70 #define PCI_VPD_NITEM   0x51    /*  8 bit (ML)  Next Item Ptr */
  71 #define PCI_VPD_ADR_REG 0x52    /* 16 bit (ML)  VPD Address Register */
  72 #define PCI_VPD_DAT_REG 0x54    /* 32 bit (ML)  VPD Data Register */
  73 /* Byte 58..ff: Reserved */
  74
  75 /*
  76  * I2C Address (PCI Config)
  77  *
  78  * Note: The temperature and voltage sensors are relocated on a different
  79  *       I2C bus.
  80  */
  81 #define I2C_ADDR_VPD    0xA0    /* I2C address for the VPD EEPROM */
  82
  83 /*
  84  * Define Bits and Values of the registers
  85  */
  86 /*      PCI_VENDOR_ID   16 bit  Vendor ID */
  87 /*      PCI_DEVICE_ID   16 bit  Device ID */
  88 /* Values for Vendor ID and Device ID shall be patched into the code */
  89 /*      PCI_COMMAND     16 bit  Command */
  90 #define PCI_FBTEN       0x0200  /* Bit 9:       Fast Back-To-Back enable */
  91 #define PCI_SERREN      0x0100  /* Bit 8:       SERR enable */
  92 #define PCI_ADSTEP      0x0080  /* Bit 7:       Address Stepping */
  93 #define PCI_PERREN      0x0040  /* Bit 6:       Parity Report Response enable */
  94 #define PCI_VGA_SNOOP   0x0020  /* Bit 5:       VGA palette snoop */
  95 #define PCI_MWIEN       0x0010  /* Bit 4:       Memory write an inv cycl ena */
  96 #define PCI_SCYCEN      0x0008  /* Bit 3:       Special Cycle enable */
  97 #define PCI_BMEN        0x0004  /* Bit 2:       Bus Master enable */
  98 #define PCI_MEMEN       0x0002  /* Bit 1:       Memory Space Access enable */
  99 #define PCI_IOEN        0x0001  /* Bit 0:       IO Space Access enable */
 100
 101 /*      PCI_STATUS      16 bit  Status */
 102 #define PCI_PERR        0x8000  /* Bit 15:      Parity Error */
 103 #define PCI_SERR        0x4000  /* Bit 14:      Signaled SERR */
 104 #define PCI_RMABORT     0x2000  /* Bit 13:      Received Master Abort */
 105 #define PCI_RTABORT     0x1000  /* Bit 12:      Received Target Abort */
 106 #define PCI_STABORT     0x0800  /* Bit 11:      Sent Target Abort */
 107 #define PCI_DEVSEL      0x0600  /* Bit 10..9:   DEVSEL Timing */
 108 #define PCI_DEV_FAST    (0<<9)  /*              fast */
 109 #define PCI_DEV_MEDIUM  (1<<9)  /*              medium */
 110 #define PCI_DEV_SLOW    (2<<9)  /*              slow */
 111 #define PCI_DATAPERR    0x0100  /* Bit 8:       DATA Parity error detected */
 112 #define PCI_FB2BCAP     0x0080  /* Bit 7:       Fast Back-to-Back Capability */
 113 #define PCI_UDF         0x0040  /* Bit 6:       User Defined Features */
 114 #define PCI_66MHZCAP    0x0020  /* Bit 5:       66 MHz PCI bus clock capable */
 115 #define PCI_NEWCAP      0x0010  /* Bit 4:       New cap. list implemented */
 116
 117 #define PCI_ERRBITS     (PCI_PERR|PCI_SERR|PCI_RMABORT|PCI_STABORT|PCI_DATAPERR)
 118
 119 /*      PCI_REV_ID      8 bit   Revision ID */
 120 /*      PCI_CLASS_CODE  24 bit  Class Code */
 121 /*      Byte 2:         Base Class              (02) */
 122 /*      Byte 1:         SubClass                (02) */
 123 /*      Byte 0:         Programming Interface   (00) */
 124
 125 /*      PCI_CACHE_LSZ   8 bit   Cache Line Size */
 126 /*      Possible values: 0,2,4,8,16     */
 127
 128 /*      PCI_LAT_TIM     8 bit   Latency Timer */
 129
 130 /*      PCI_HEADER_T    8 bit   Header Type */
 131 #define PCI_HD_MF_DEV   0x80    /* Bit 7:       0= single, 1= multi-func dev */
 132 #define PCI_HD_TYPE     0x7f    /* Bit 6..0:    Header Layout 0= normal */
 133
 134 /*      PCI_BIST        8 bit   Built-in selftest */
 135 #define PCI_BIST_CAP    0x80    /* Bit 7:       BIST Capable */
 136 #define PCI_BIST_ST     0x40    /* Bit 6:       Start BIST */
 137 #define PCI_BIST_RET    0x0f    /* Bit 3..0:    Completion Code */
 138
 139 /*      PCI_BASE_1ST    32 bit  1st Base address */
 140 #define PCI_MEMSIZE     0x800L       /* use 2 kB Memory Base */
 141 #define PCI_MEMBASE_BITS 0xfffff800L /* Bit 31..11:     Memory Base Address */
 142 #define PCI_MEMSIZE_BIIS 0x000007f0L /* Bit 10..4:      Memory Size Req. */
 143 #define PCI_PREFEN      0x00000008L  /* Bit 3:          Prefetchable */
 144 #define PCI_MEM_TYP     0x00000006L  /* Bit 2..1:       Memory Type */
 145 #define PCI_MEM32BIT    (0<<1)       /* Base addr anywhere in 32 Bit range */
 146 #define PCI_MEM1M       (1<<1)       /* Base addr below 1 MegaByte */
 147 #define PCI_MEM64BIT    (2<<1)       /* Base addr anywhere in 64 Bit range */
 148 #define PCI_MEMSPACE    0x00000001L  /* Bit 0:  Memory Space Indic. */
 149
 150 /*      PCI_BASE_2ND    32 bit  2nd Base address */
 151 #define PCI_IOBASE      0xffffff00L  /* Bit 31..8:  I/O Base address */
 152 #define PCI_IOSIZE      0x000000fcL  /* Bit 7..2:   I/O Size Requirements */
 153 #define PCI_IOSPACE     0x00000001L  /* Bit 0:      I/O Space Indicator */
 154
 155 /*      PCI_SUB_VID     16 bit  Subsystem Vendor ID */
 156 /*      PCI_SUB_ID      16 bit  Subsystem ID */
 157
 158 /*      PCI_BASE_ROM    32 bit  Expansion ROM Base Address */
 159 #define PCI_ROMBASE     0xfffe0000L  /* Bit 31..17: ROM BASE address (1st) */
 160 #define PCI_ROMBASZ     0x0001c000L  /* Bit 16..14: Treat as BASE or SIZE */
 161 #define PCI_ROMSIZE     0x00003800L  /* Bit 13..11: ROM Size Requirements */
 162 #define PCI_ROMEN       0x00000001L  /* Bit 0:      Address Decode enable */
 163
 164 /*      PCI_CAP_PTR     8 bit   New Capabilities Pointers */
 165 /*      PCI_IRQ_LINE    8 bit   Interrupt Line */
 166 /*      PCI_IRQ_PIN     8 bit   Interrupt Pin */
 167 /*      PCI_MIN_GNT     8 bit   Min_Gnt */
 168 /*      PCI_MAX_LAT     8 bit   Max_Lat */
 169 /* Device Dependent Region */
 170 /*      PCI_OUR_REG     (DV)    32 bit  Our Register */
 171 /*      PCI_OUR_REG_1   (ML)    32 bit  Our Register 1 */
 172                                   /*     Bit 31..29:    reserved */
 173 #define PCI_PATCH_DIR   (3L<<27)  /*(DV) Bit 28..27:    Ext Patchs direction */
 174 #define PCI_PATCH_DIR_0 (1L<<27)  /*(DV) Type of the pins EXT_PATCHS<1..0>   */
 175 #define PCI_PATCH_DIR_1 (1L<<28)  /*       0 = input                         */
 176                                   /*       1 = output                        */
 177 #define PCI_EXT_PATCHS  (3L<<25)  /*(DV) Bit 26..25:    Extended Patches     */
 178 #define PCI_EXT_PATCH_0 (1L<<25)  /*(DV)                                     */
 179 #define PCI_EXT_PATCH_1 (1L<<26)  /*     CLK for MicroWire (ML)              */
 180 #define PCI_VIO         (1L<<25)  /*(ML)                                     */
 181 #define PCI_EN_BOOT     (1L<<24)  /*     Bit 24:        Enable BOOT via ROM  */
 182                                   /*       1 = Don't boot with ROM           */
 183                                   /*       0 = Boot with ROM                 */
 184 #define PCI_EN_IO       (1L<<23)  /*     Bit 23:        Mapping to IO space  */
 185 #define PCI_EN_FPROM    (1L<<22)  /*     Bit 22:        FLASH mapped to mem? */
 186                                   /*       1 = Map Flash to Memory           */
 187                                   /*       0 = Disable all addr. decoding    */
 188 #define PCI_PAGESIZE    (3L<<20)  /*     Bit 21..20:    FLASH Page Size      */
 189 #define PCI_PAGE_16     (0L<<20)  /*            16 k pages                   */
 190 #define PCI_PAGE_32K    (1L<<20)  /*            32 k pages                   */
 191 #define PCI_PAGE_64K    (2L<<20)  /*            64 k pages                   */
 192 #define PCI_PAGE_128K   (3L<<20)  /*            128 k pages                  */
 193                                   /*     Bit 19: reserved (ML) and (DV)      */
 194 #define PCI_PAGEREG     (7L<<16)  /*     Bit 18..16:    Page Register        */
 195                                   /*     Bit 15:        reserved             */
 196 #define PCI_FORCE_BE    (1L<<14)  /*     Bit 14:        Assert all BEs on MR */
 197 #define PCI_DIS_MRL     (1L<<13)  /*     Bit 13:        Disable Mem R Line   */
 198 #define PCI_DIS_MRM     (1L<<12)  /*     Bit 12:        Disable Mem R multip */
 199 #define PCI_DIS_MWI     (1L<<11)  /*     Bit 11:        Disable Mem W & inv  */
 200 #define PCI_DISC_CLS    (1L<<10)  /*     Bit 10:        Disc: cacheLsz bound */
 201 #define PCI_BURST_DIS   (1L<<9)   /*     Bit  9:        Burst Disable        */
 202 #define PCI_BYTE_SWAP   (1L<<8)   /*(DV) Bit  8:        Byte Swap in DATA    */
 203 #define PCI_SKEW_DAS    (0xfL<<4) /*     Bit 7..4:      Skew Ctrl, DAS Ext   */
 204 #define PCI_SKEW_BASE   (0xfL<<0) /*     Bit 3..0:      Skew Ctrl, Base      */
 205
 206 /*      PCI_OUR_REG_2   (ML)    32 bit  Our Register 2 (Monalisa only) */
 207 #define PCI_VPD_WR_TH   (0xffL<<24)     /* Bit 24..31   VPD Write Threshold  */
 208 #define PCI_DEV_SEL     (0x7fL<<17)     /* Bit 17..23   EEPROM Device Select */
 209 #define PCI_VPD_ROM_SZ  (7L<<14)        /* Bit 14..16   VPD ROM Size         */
 210                                         /* Bit 12..13   reserved             */
 211 #define PCI_PATCH_DIR2  (0xfL<<8)       /* Bit  8..11   Ext Patchs dir 2..5  */
 212 #define PCI_PATCH_DIR_2 (1L<<8)         /* Bit  8       CS for MicroWire     */
 213 #define PCI_PATCH_DIR_3 (1L<<9)
 214 #define PCI_PATCH_DIR_4 (1L<<10)
 215 #define PCI_PATCH_DIR_5 (1L<<11)
 216 #define PCI_EXT_PATCHS2 (0xfL<<4)       /* Bit  4..7    Extended Patches     */
 217 #define PCI_EXT_PATCH_2 (1L<<4)         /* Bit  4       CS for MicroWire     */
 218 #define PCI_EXT_PATCH_3 (1L<<5)
 219 #define PCI_EXT_PATCH_4 (1L<<6)
 220 #define PCI_EXT_PATCH_5 (1L<<7)
 221 #define PCI_EN_DUMMY_RD (1L<<3)         /* Bit  3       Enable Dummy Read    */
 222 #define PCI_REV_DESC    (1L<<2)         /* Bit  2       Reverse Desc. Bytes  */
 223 #define PCI_USEADDR64   (1L<<1)         /* Bit  1       Use 64 Bit Addresse  */
 224 #define PCI_USEDATA64   (1L<<0)         /* Bit  0       Use 64 Bit Data bus ext*/
 225
 226 /* Power Management Region */
 227 /*      PCI_PM_CAP_ID            8 bit (ML)     Power Management Cap. ID */
 228 /*      PCI_PM_NITEM             8 bit (ML)     Next Item Ptr */
 229 /*      PCI_PM_CAP_REG          16 bit (ML)     Power Management Capabilities*/
 230 #define PCI_PME_SUP     (0x1f<<11)      /* Bit 11..15   PM Manag. Event Support*/
 231 #define PCI_PM_D2_SUB   (1<<10)         /* Bit 10       D2 Support Bit       */
 232 #define PCI_PM_D1_SUB   (1<<9)          /* Bit 9        D1 Support Bit       */
 233                                         /* Bit 6..8 reserved                 */
 234 #define PCI_PM_DSI      (1<<5)          /* Bit 5        Device Specific Init.*/
 235 #define PCI_PM_APS      (1<<4)          /* Bit 4        Auxialiary Power Src */
 236 #define PCI_PME_CLOCK   (1<<3)          /* Bit 3        PM Event Clock       */
 237 #define PCI_PM_VER      (7<<0)          /* Bit 0..2     PM PCI Spec. version */
 238
 239 /*      PCI_PM_CTL_STS          16 bit (ML)     Power Manag. Control/Status  */
 240 #define PCI_PME_STATUS  (1<<15)         /* Bit 15       PFA doesn't sup. PME#*/
 241 #define PCI_PM_DAT_SCL  (3<<13)         /* Bit 13..14   dat reg Scaling factor */
 242 #define PCI_PM_DAT_SEL  (0xf<<9)        /* Bit  9..12   PM data selector field */
 243                                         /* Bit  7.. 2   reserved             */
 244 #define PCI_PM_STATE    (3<<0)          /* Bit  0.. 1   Power Management State */
 245 #define PCI_PM_STATE_D0 (0<<0)          /* D0:  Operational (default) */
 246 #define PCI_PM_STATE_D1 (1<<0)          /* D1:  not supported */
 247 #define PCI_PM_STATE_D2 (2<<0)          /* D2:  not supported */
 248 #define PCI_PM_STATE_D3 (3<<0)          /* D3:  HOT, Power Down and Reset */
 249
 250 /*      PCI_PM_DAT_REG           8 bit (ML)     Power Manag. Data Register */
 251 /* VPD Region */
 252 /*      PCI_VPD_CAP_ID           8 bit (ML)     VPD Cap. ID */
 253 /*      PCI_VPD_NITEM            8 bit (ML)     Next Item Ptr */
 254 /*      PCI_VPD_ADR_REG         16 bit (ML)     VPD Address Register */
 255 #define PCI_VPD_FLAG    (1<<15)         /* Bit 15       starts VPD rd/wd cycle*/
 256
 257 /*      PCI_VPD_DAT_REG         32 bit (ML)     VPD Data Register */
 258
 259 /*
 260  *      Control Register File:
 261  *      Bank 0
 262  */
 263 #define B0_RAP          0x0000  /*  8 bit register address port */
 264         /* 0x0001 - 0x0003:     reserved */
 265 #define B0_CTRL         0x0004  /*  8 bit control register */
 266 #define B0_DAS          0x0005  /*  8 Bit control register (DAS) */
 267 #define B0_LED          0x0006  /*  8 Bit LED register */
 268 #define B0_TST_CTRL     0x0007  /*  8 bit test control register */
 269 #define B0_ISRC         0x0008  /* 32 bit Interrupt source register */
 270 #define B0_IMSK         0x000c  /* 32 bit Interrupt mask register */
 271
 272 /* 0x0010 - 0x006b:     formac+ (supernet_3) fequently used registers */
 273 #define B0_CMDREG1      0x0010  /* write command reg 1 instruction */
 274 #define B0_CMDREG2      0x0014  /* write command reg 2 instruction */
 275 #define B0_ST1U         0x0010  /* read upper 16-bit of status reg 1 */
 276 #define B0_ST1L         0x0014  /* read lower 16-bit of status reg 1 */
 277 #define B0_ST2U         0x0018  /* read upper 16-bit of status reg 2 */
 278 #define B0_ST2L         0x001c  /* read lower 16-bit of status reg 2 */
 279
 280 #define B0_MARR         0x0020  /* r/w the memory read addr register */
 281 #define B0_MARW         0x0024  /* r/w the memory write addr register*/
 282 #define B0_MDRU         0x0028  /* r/w upper 16-bit of mem. data reg */
 283 #define B0_MDRL         0x002c  /* r/w lower 16-bit of mem. data reg */
 284
 285 #define B0_MDREG3       0x0030  /* r/w Mode Register 3 */
 286 #define B0_ST3U         0x0034  /* read upper 16-bit of status reg 3 */
 287 #define B0_ST3L         0x0038  /* read lower 16-bit of status reg 3 */
 288 #define B0_IMSK3U       0x003c  /* r/w upper 16-bit of IMSK reg 3 */
 289 #define B0_IMSK3L       0x0040  /* r/w lower 16-bit of IMSK reg 3 */
 290 #define B0_IVR          0x0044  /* read Interrupt Vector register */
 291 #define B0_IMR          0x0048  /* r/w Interrupt mask register */
 292 /* 0x4c Hidden */
 293
 294 #define B0_CNTRL_A      0x0050  /* control register A (r/w) */
 295 #define B0_CNTRL_B      0x0054  /* control register B (r/w) */
 296 #define B0_INTR_MASK    0x0058  /* interrupt mask (r/w) */
 297 #define B0_XMIT_VECTOR  0x005c  /* transmit vector register (r/w) */
 298
 299 #define B0_STATUS_A     0x0060  /* status register A (read only) */
 300 #define B0_STATUS_B     0x0064  /* status register B (read only) */
 301 #define B0_CNTRL_C      0x0068  /* control register C (r/w) */
 302 #define B0_MDREG1       0x006c  /* r/w Mode Register 1 */
 303
 304 #define B0_R1_CSR       0x0070  /* 32 bit BMU control/status reg (rec q 1) */
 305 #define B0_R2_CSR       0x0074  /* 32 bit BMU control/status reg (rec q 2)(DV)*/
 306 #define B0_XA_CSR       0x0078  /* 32 bit BMU control/status reg (a xmit q) */
 307 #define B0_XS_CSR       0x007c  /* 32 bit BMU control/status reg (s xmit q) */
 308
 309 /*
 310  *      Bank 1
 311  *      - completely empty (this is the RAP Block window)
 312  *      Note: if RAP = 1 this page is reserved
 313  */
 314
 315 /*
 316  *      Bank 2
 317  */
 318 #define B2_MAC_0        0x0100  /*  8 bit MAC address Byte 0 */
 319 #define B2_MAC_1        0x0101  /*  8 bit MAC address Byte 1 */
 320 #define B2_MAC_2        0x0102  /*  8 bit MAC address Byte 2 */
 321 #define B2_MAC_3        0x0103  /*  8 bit MAC address Byte 3 */
 322 #define B2_MAC_4        0x0104  /*  8 bit MAC address Byte 4 */
 323 #define B2_MAC_5        0x0105  /*  8 bit MAC address Byte 5 */
 324 #define B2_MAC_6        0x0106  /*  8 bit MAC address Byte 6 (== 0) (DV) */
 325 #define B2_MAC_7        0x0107  /*  8 bit MAC address Byte 7 (== 0) (DV) */
 326
 327 #define B2_CONN_TYP     0x0108  /*  8 bit Connector type */
 328 #define B2_PMD_TYP      0x0109  /*  8 bit PMD type */
 329                                 /* 0x010a - 0x010b:     reserved */
 330         /* Eprom registers are currently of no use */
 331 #define B2_E_0          0x010c  /*  8 bit EPROM Byte 0 */
 332 #define B2_E_1          0x010d  /*  8 bit EPROM Byte 1 */
 333 #define B2_E_2          0x010e  /*  8 bit EPROM Byte 2 */
 334 #define B2_E_3          0x010f  /*  8 bit EPROM Byte 3 */
 335 #define B2_FAR          0x0110  /* 32 bit Flash-Prom Address Register/Counter */
 336 #define B2_FDP          0x0114  /*  8 bit Flash-Prom Data Port */
 337                                 /* 0x0115 - 0x0117:     reserved */
 338 #define B2_LD_CRTL      0x0118  /*  8 bit loader control */
 339 #define B2_LD_TEST      0x0119  /*  8 bit loader test */
 340                                 /* 0x011a - 0x011f:     reserved */
 341 #define B2_TI_INI       0x0120  /* 32 bit Timer init value */
 342 #define B2_TI_VAL       0x0124  /* 32 bit Timer value */
 343 #define B2_TI_CRTL      0x0128  /*  8 bit Timer control */
 344 #define B2_TI_TEST      0x0129  /*  8 Bit Timer Test */
 345                                 /* 0x012a - 0x012f:     reserved */
 346 #define B2_WDOG_INI     0x0130  /* 32 bit Watchdog init value */
 347 #define B2_WDOG_VAL     0x0134  /* 32 bit Watchdog value */
 348 #define B2_WDOG_CRTL    0x0138  /*  8 bit Watchdog control */
 349 #define B2_WDOG_TEST    0x0139  /*  8 Bit Watchdog Test */
 350                                 /* 0x013a - 0x013f:     reserved */
 351 #define B2_RTM_INI      0x0140  /* 32 bit RTM init value */
 352 #define B2_RTM_VAL      0x0144  /* 32 bit RTM value */
 353 #define B2_RTM_CRTL     0x0148  /*  8 bit RTM control */
 354 #define B2_RTM_TEST     0x0149  /*  8 Bit RTM Test */
 355
 356 #define B2_TOK_COUNT    0x014c  /* (ML) 32 bit  Token Counter */
 357 #define B2_DESC_ADDR_H  0x0150  /* (ML) 32 bit  Desciptor Base Addr Reg High */
 358 #define B2_CTRL_2       0x0154  /* (ML)  8 bit  Control Register 2 */
 359 #define B2_IFACE_REG    0x0155  /* (ML)  8 bit  Interface Register */
 360                                 /* 0x0156:              reserved */
 361 #define B2_TST_CTRL_2   0x0157  /* (ML)  8 bit  Test Control Register 2 */
 362 #define B2_I2C_CTRL     0x0158  /* (ML) 32 bit  I2C Control Register */
 363 #define B2_I2C_DATA     0x015c  /* (ML) 32 bit  I2C Data Register */
 364
 365 #define B2_IRQ_MOD_INI  0x0160  /* (ML) 32 bit  IRQ Moderation Timer Init Reg. */
 366 #define B2_IRQ_MOD_VAL  0x0164  /* (ML) 32 bit  IRQ Moderation Timer Value */
 367 #define B2_IRQ_MOD_CTRL 0x0168  /* (ML)  8 bit  IRQ Moderation Timer Control */
 368 #define B2_IRQ_MOD_TEST 0x0169  /* (ML)  8 bit  IRQ Moderation Timer Test */
 369                                 /* 0x016a - 0x017f:     reserved */
 370
 371 /*
 372  *      Bank 3
 373  */
 374 /*
 375  * This is a copy of the Configuration register file (lower half)
 376  */
 377 #define B3_CFG_SPC      0x180
 378
 379 /*
 380  *      Bank 4
 381  */
 382 #define B4_R1_D         0x0200  /*      4*32 bit current receive Descriptor  */
 383 #define B4_R1_DA        0x0210  /*      32 bit current rec desc address      */
 384 #define B4_R1_AC        0x0214  /*      32 bit current receive Address Count */
 385 #define B4_R1_BC        0x0218  /*      32 bit current receive Byte Counter  */
 386 #define B4_R1_CSR       0x021c  /*      32 bit BMU Control/Status Register   */
 387 #define B4_R1_F         0x0220  /*      32 bit flag register                 */
 388 #define B4_R1_T1        0x0224  /*      32 bit Test Register 1               */
 389 #define B4_R1_T1_TR     0x0224  /*      8 bit Test Register 1 TR             */
 390 #define B4_R1_T1_WR     0x0225  /*      8 bit Test Register 1 WR             */
 391 #define B4_R1_T1_RD     0x0226  /*      8 bit Test Register 1 RD             */
 392 #define B4_R1_T1_SV     0x0227  /*      8 bit Test Register 1 SV             */
 393 #define B4_R1_T2        0x0228  /*      32 bit Test Register 2               */
 394 #define B4_R1_T3        0x022c  /*      32 bit Test Register 3               */
 395 #define B4_R1_DA_H      0x0230  /* (ML) 32 bit Curr Rx Desc Address High     */
 396 #define B4_R1_AC_H      0x0234  /* (ML) 32 bit Curr Addr Counter High dword  */
 397                                 /* 0x0238 - 0x023f:     reserved          */
 398                                 /* Receive queue 2 is removed on Monalisa */
 399 #define B4_R2_D         0x0240  /* 4*32 bit current receive Descriptor  (q2) */
 400 #define B4_R2_DA        0x0250  /* 32 bit current rec desc address      (q2) */
 401 #define B4_R2_AC        0x0254  /* 32 bit current receive Address Count (q2) */
 402 #define B4_R2_BC        0x0258  /* 32 bit current receive Byte Counter  (q2) */
 403 #define B4_R2_CSR       0x025c  /* 32 bit BMU Control/Status Register   (q2) */
 404 #define B4_R2_F         0x0260  /* 32 bit flag register                 (q2) */
 405 #define B4_R2_T1        0x0264  /* 32 bit Test Register 1               (q2) */
 406 #define B4_R2_T1_TR     0x0264  /* 8 bit Test Register 1 TR             (q2) */
 407 #define B4_R2_T1_WR     0x0265  /* 8 bit Test Register 1 WR             (q2) */
 408 #define B4_R2_T1_RD     0x0266  /* 8 bit Test Register 1 RD             (q2) */
 409 #define B4_R2_T1_SV     0x0267  /* 8 bit Test Register 1 SV             (q2) */
 410 #define B4_R2_T2        0x0268  /* 32 bit Test Register 2               (q2) */
 411 #define B4_R2_T3        0x026c  /* 32 bit Test Register 3               (q2) */
 412                                 /* 0x0270 - 0x027c:     reserved */
 413
 414 /*
 415  *      Bank 5
 416  */
 417 #define B5_XA_D         0x0280  /* 4*32 bit current transmit Descriptor (xa) */
 418 #define B5_XA_DA        0x0290  /* 32 bit current tx desc address       (xa) */
 419 #define B5_XA_AC        0x0294  /* 32 bit current tx Address Count      (xa) */
 420 #define B5_XA_BC        0x0298  /* 32 bit current tx Byte Counter       (xa) */
 421 #define B5_XA_CSR       0x029c  /* 32 bit BMU Control/Status Register   (xa) */
 422 #define B5_XA_F         0x02a0  /* 32 bit flag register                 (xa) */
 423 #define B5_XA_T1        0x02a4  /* 32 bit Test Register 1               (xa) */
 424 #define B5_XA_T1_TR     0x02a4  /* 8 bit Test Register 1 TR             (xa) */
 425 #define B5_XA_T1_WR     0x02a5  /* 8 bit Test Register 1 WR             (xa) */
 426 #define B5_XA_T1_RD     0x02a6  /* 8 bit Test Register 1 RD             (xa) */
 427 #define B5_XA_T1_SV     0x02a7  /* 8 bit Test Register 1 SV             (xa) */
 428 #define B5_XA_T2        0x02a8  /* 32 bit Test Register 2               (xa) */
 429 #define B5_XA_T3        0x02ac  /* 32 bit Test Register 3               (xa) */
 430 #define B5_XA_DA_H      0x02b0  /* (ML) 32 bit Curr Tx Desc Address High     */
 431 #define B5_XA_AC_H      0x02b4  /* (ML) 32 bit Curr Addr Counter High dword  */
 432                                 /* 0x02b8 - 0x02bc:     reserved */
 433 #define B5_XS_D         0x02c0  /* 4*32 bit current transmit Descriptor (xs) */
 434 #define B5_XS_DA        0x02d0  /* 32 bit current tx desc address       (xs) */
 435 #define B5_XS_AC        0x02d4  /* 32 bit current transmit Address Count(xs) */
 436 #define B5_XS_BC        0x02d8  /* 32 bit current transmit Byte Counter (xs) */
 437 #define B5_XS_CSR       0x02dc  /* 32 bit BMU Control/Status Register   (xs) */
 438 #define B5_XS_F         0x02e0  /* 32 bit flag register                 (xs) */
 439 #define B5_XS_T1        0x02e4  /* 32 bit Test Register 1               (xs) */
 440 #define B5_XS_T1_TR     0x02e4  /* 8 bit Test Register 1 TR             (xs) */
 441 #define B5_XS_T1_WR     0x02e5  /* 8 bit Test Register 1 WR             (xs) */
 442 #define B5_XS_T1_RD     0x02e6  /* 8 bit Test Register 1 RD             (xs) */
 443 #define B5_XS_T1_SV     0x02e7  /* 8 bit Test Register 1 SV             (xs) */
 444 #define B5_XS_T2        0x02e8  /* 32 bit Test Register 2               (xs) */
 445 #define B5_XS_T3        0x02ec  /* 32 bit Test Register 3               (xs) */
 446 #define B5_XS_DA_H      0x02f0  /* (ML) 32 bit Curr Tx Desc Address High     */
 447 #define B5_XS_AC_H      0x02f4  /* (ML) 32 bit Curr Addr Counter High dword  */
 448                                 /* 0x02f8 - 0x02fc:     reserved */
 449
 450 /*
 451  *      Bank 6
 452  */
 453 /* External PLC-S registers (SN2 compatibility for DV) */
 454 /* External registers (ML) */
 455 #define B6_EXT_REG      0x300
 456
 457 /*
 458  *      Bank 7
 459  */
 460 /* DAS PLC-S Registers */
 461
 462 /*
 463  *      Bank 8 - 15
 464  */
 465 /* IFCP registers */
 466
 467 /*---------------------------------------------------------------------------*/
 468 /* Definitions of the Bits in the registers */
 469
 470 /*      B0_RAP          16 bit register address port */
 471 #define RAP_RAP         0x0f    /* Bit 3..0:    0 = block0, .., f = block15 */
 472
 473 /*      B0_CTRL         8 bit control register */
 474 #define CTRL_FDDI_CLR   (1<<7)  /* Bit 7: (ML)  Clear FDDI Reset */
 475 #define CTRL_FDDI_SET   (1<<6)  /* Bit 6: (ML)  Set FDDI Reset */
 476 #define CTRL_HPI_CLR    (1<<5)  /* Bit 5:       Clear HPI SM reset */
 477 #define CTRL_HPI_SET    (1<<4)  /* Bit 4:       Set HPI SM reset */
 478 #define CTRL_MRST_CLR   (1<<3)  /* Bit 3:       Clear Master reset */
 479 #define CTRL_MRST_SET   (1<<2)  /* Bit 2:       Set Master reset */
 480 #define CTRL_RST_CLR    (1<<1)  /* Bit 1:       Clear Software reset */
 481 #define CTRL_RST_SET    (1<<0)  /* Bit 0:       Set Software reset */
 482
 483 /*      B0_DAS          8 Bit control register (DAS) */
 484 #define BUS_CLOCK       (1<<7)  /* Bit 7: (ML)  Bus Clock 0/1 = 33/66MHz */
 485 #define BUS_SLOT_SZ     (1<<6)  /* Bit 6: (ML)  Slot Size 0/1 = 32/64 bit slot*/
 486                                 /* Bit 5..4:    reserved */
 487 #define DAS_AVAIL       (1<<3)  /* Bit 3:       1 = DAS, 0 = SAS */
 488 #define DAS_BYP_ST      (1<<2)  /* Bit 2:       1 = avail,SAS, 0 = not avail */
 489 #define DAS_BYP_INS     (1<<1)  /* Bit 1:       1 = insert Bypass */
 490 #define DAS_BYP_RMV     (1<<0)  /* Bit 0:       1 = remove Bypass */
 491
 492 /*      B0_LED          8 Bit LED register */
 493                                 /* Bit 7..6:    reserved */
 494 #define LED_2_ON        (1<<5)  /* Bit 5:       1 = switch LED_2 on (left,gn)*/
 495 #define LED_2_OFF       (1<<4)  /* Bit 4:       1 = switch LED_2 off */
 496 #define LED_1_ON        (1<<3)  /* Bit 3:       1 = switch LED_1 on (mid,yel)*/
 497 #define LED_1_OFF       (1<<2)  /* Bit 2:       1 = switch LED_1 off */
 498 #define LED_0_ON        (1<<1)  /* Bit 1:       1 = switch LED_0 on (rght,gn)*/
 499 #define LED_0_OFF       (1<<0)  /* Bit 0:       1 = switch LED_0 off */
 500 /* This hardware defines are very ugly therefore we define some others */
 501
 502 #define LED_GA_ON       LED_2_ON        /* S port = A port */
 503 #define LED_GA_OFF      LED_2_OFF       /* S port = A port */
 504 #define LED_MY_ON       LED_1_ON
 505 #define LED_MY_OFF      LED_1_OFF
 506 #define LED_GB_ON       LED_0_ON
 507 #define LED_GB_OFF      LED_0_OFF
 508
 509 /*      B0_TST_CTRL     8 bit test control register */
 510 #define TST_FRC_DPERR_MR        (1<<7)  /* Bit 7:  force DATAPERR on MST RE. */
 511 #define TST_FRC_DPERR_MW        (1<<6)  /* Bit 6:  force DATAPERR on MST WR. */
 512 #define TST_FRC_DPERR_TR        (1<<5)  /* Bit 5:  force DATAPERR on TRG RE. */
 513 #define TST_FRC_DPERR_TW        (1<<4)  /* Bit 4:  force DATAPERR on TRG WR. */
 514 #define TST_FRC_APERR_M         (1<<3)  /* Bit 3:  force ADDRPERR on MST     */
 515 #define TST_FRC_APERR_T         (1<<2)  /* Bit 2:  force ADDRPERR on TRG     */
 516 #define TST_CFG_WRITE_ON        (1<<1)  /* Bit 1:  ena configuration reg. WR */
 517 #define TST_CFG_WRITE_OFF       (1<<0)  /* Bit 0:  dis configuration reg. WR */
 518
 519 /*      B0_ISRC         32 bit Interrupt source register */
 520                                         /* Bit 31..28:  reserved             */
 521 #define IS_I2C_READY    (1L<<27)        /* Bit 27: (ML) IRQ on end of I2C tx */
 522 #define IS_IRQ_SW       (1L<<26)        /* Bit 26: (ML) SW forced IRQ        */
 523 #define IS_EXT_REG      (1L<<25)        /* Bit 25: (ML) IRQ from external reg*/
 524 #define IS_IRQ_STAT     (1L<<24)        /* Bit 24:      IRQ status exception */
 525                                         /*   PERR, RMABORT, RTABORT DATAPERR */
 526 #define IS_IRQ_MST_ERR  (1L<<23)        /* Bit 23:      IRQ master error     */
 527                                         /*   RMABORT, RTABORT, DATAPERR      */
 528 #define IS_TIMINT       (1L<<22)        /* Bit 22:      IRQ_TIMER       */
 529 #define IS_TOKEN        (1L<<21)        /* Bit 21:      IRQ_RTM         */
 530 /*
 531  * Note: The DAS is our First Port (!=PA)
 532  */
 533 #define IS_PLINT1       (1L<<20)        /* Bit 20:      IRQ_PHY_DAS     */
 534 #define IS_PLINT2       (1L<<19)        /* Bit 19:      IRQ_IFCP_4      */
 535 #define IS_MINTR3       (1L<<18)        /* Bit 18:      IRQ_IFCP_3/IRQ_PHY */
 536 #define IS_MINTR2       (1L<<17)        /* Bit 17:      IRQ_IFCP_2/IRQ_MAC_2 */
 537 #define IS_MINTR1       (1L<<16)        /* Bit 16:      IRQ_IFCP_1/IRQ_MAC_1 */
 538 /* Receive Queue 1 */
 539 #define IS_R1_P         (1L<<15)        /* Bit 15:      Parity Error (q1) */
 540 #define IS_R1_B         (1L<<14)        /* Bit 14:      End of Buffer (q1) */
 541 #define IS_R1_F         (1L<<13)        /* Bit 13:      End of Frame (q1) */
 542 #define IS_R1_C         (1L<<12)        /* Bit 12:      Encoding Error (q1) */
 543 /* Receive Queue 2 */
 544 #define IS_R2_P         (1L<<11)        /* Bit 11: (DV) Parity Error (q2) */
 545 #define IS_R2_B         (1L<<10)        /* Bit 10: (DV) End of Buffer (q2) */
 546 #define IS_R2_F         (1L<<9)         /* Bit  9: (DV) End of Frame (q2) */
 547 #define IS_R2_C         (1L<<8)         /* Bit  8: (DV) Encoding Error (q2) */
 548 /* Asynchronous Transmit queue */
 549                                         /* Bit  7:      reserved */
 550 #define IS_XA_B         (1L<<6)         /* Bit  6:      End of Buffer (xa) */
 551 #define IS_XA_F         (1L<<5)         /* Bit  5:      End of Frame (xa) */
 552 #define IS_XA_C         (1L<<4)         /* Bit  4:      Encoding Error (xa) */
 553 /* Synchronous Transmit queue */
 554                                         /* Bit  3:      reserved */
 555 #define IS_XS_B         (1L<<2)         /* Bit  2:      End of Buffer (xs) */
 556 #define IS_XS_F         (1L<<1)         /* Bit  1:      End of Frame (xs) */
 557 #define IS_XS_C         (1L<<0)         /* Bit  0:      Encoding Error (xs) */
 558
 559 /*
 560  * Define all valid interrupt source Bits from GET_ISR ()
 561  */
 562 #define ALL_IRSR        0x01ffff77L     /* (DV) */
 563 #define ALL_IRSR_ML     0x0ffff077L     /* (ML) */
 564
 565
 566 /*      B0_IMSK         32 bit Interrupt mask register */
 567 /*
 568  * The Bit definnition of this register are the same as of the interrupt
 569  * source register. These definition are directly derived from the Hardware
 570  * spec.
 571  */
 572                                         /* Bit 31..28:  reserved             */
 573 #define IRQ_I2C_READY   (1L<<27)        /* Bit 27: (ML) IRQ on end of I2C tx */
 574 #define IRQ_SW          (1L<<26)        /* Bit 26: (ML) SW forced IRQ        */
 575 #define IRQ_EXT_REG     (1L<<25)        /* Bit 25: (ML) IRQ from external reg*/
 576 #define IRQ_STAT        (1L<<24)        /* Bit 24:      IRQ status exception */
 577                                         /*   PERR, RMABORT, RTABORT DATAPERR */
 578 #define IRQ_MST_ERR     (1L<<23)        /* Bit 23:      IRQ master error     */
 579                                         /*   RMABORT, RTABORT, DATAPERR      */
 580 #define IRQ_TIMER       (1L<<22)        /* Bit 22:      IRQ_TIMER       */
 581 #define IRQ_RTM         (1L<<21)        /* Bit 21:      IRQ_RTM         */
 582 #define IRQ_DAS         (1L<<20)        /* Bit 20:      IRQ_PHY_DAS     */
 583 #define IRQ_IFCP_4      (1L<<19)        /* Bit 19:      IRQ_IFCP_4      */
 584 #define IRQ_IFCP_3      (1L<<18)        /* Bit 18:      IRQ_IFCP_3/IRQ_PHY */
 585 #define IRQ_IFCP_2      (1L<<17)        /* Bit 17:      IRQ_IFCP_2/IRQ_MAC_2 */
 586 #define IRQ_IFCP_1      (1L<<16)        /* Bit 16:      IRQ_IFCP_1/IRQ_MAC_1 */
 587 /* Receive Queue 1 */
 588 #define IRQ_R1_P        (1L<<15)        /* Bit 15:      Parity Error (q1) */
 589 #define IRQ_R1_B        (1L<<14)        /* Bit 14:      End of Buffer (q1) */
 590 #define IRQ_R1_F        (1L<<13)        /* Bit 13:      End of Frame (q1) */
 591 #define IRQ_R1_C        (1L<<12)        /* Bit 12:      Encoding Error (q1) */
 592 /* Receive Queue 2 */
 593 #define IRQ_R2_P        (1L<<11)        /* Bit 11: (DV) Parity Error (q2) */
 594 #define IRQ_R2_B        (1L<<10)        /* Bit 10: (DV) End of Buffer (q2) */
 595 #define IRQ_R2_F        (1L<<9)         /* Bit  9: (DV) End of Frame (q2) */
 596 #define IRQ_R2_C        (1L<<8)         /* Bit  8: (DV) Encoding Error (q2) */
 597 /* Asynchronous Transmit queue */
 598                                         /* Bit  7:      reserved */
 599 #define IRQ_XA_B        (1L<<6)         /* Bit  6:      End of Buffer (xa) */
 600 #define IRQ_XA_F        (1L<<5)         /* Bit  5:      End of Frame (xa) */
 601 #define IRQ_XA_C        (1L<<4)         /* Bit  4:      Encoding Error (xa) */
 602 /* Synchronous Transmit queue */
 603                                         /* Bit  3:      reserved */
 604 #define IRQ_XS_B        (1L<<2)         /* Bit  2:      End of Buffer (xs) */
 605 #define IRQ_XS_F        (1L<<1)         /* Bit  1:      End of Frame (xs) */
 606 #define IRQ_XS_C        (1L<<0)         /* Bit  0:      Encoding Error (xs) */
 607
 608 /* 0x0010 - 0x006b:     formac+ (supernet_3) fequently used registers */
 609 /*      B0_R1_CSR       32 bit BMU control/status reg (rec q 1 ) */
 610 /*      B0_R2_CSR       32 bit BMU control/status reg (rec q 2 ) */
 611 /*      B0_XA_CSR       32 bit BMU control/status reg (a xmit q ) */
 612 /*      B0_XS_CSR       32 bit BMU control/status reg (s xmit q ) */
 613 /* The registers are the same as B4_R1_CSR, B4_R2_CSR, B5_Xa_CSR, B5_XS_CSR */
 614
 615 /*      B2_MAC_0        8 bit MAC address Byte 0 */
 616 /*      B2_MAC_1        8 bit MAC address Byte 1 */
 617 /*      B2_MAC_2        8 bit MAC address Byte 2 */
 618 /*      B2_MAC_3        8 bit MAC address Byte 3 */
 619 /*      B2_MAC_4        8 bit MAC address Byte 4 */
 620 /*      B2_MAC_5        8 bit MAC address Byte 5 */
 621 /*      B2_MAC_6        8 bit MAC address Byte 6 (== 0) (DV) */
 622 /*      B2_MAC_7        8 bit MAC address Byte 7 (== 0) (DV) */
 623
 624 /*      B2_CONN_TYP     8 bit Connector type */
 625 /*      B2_PMD_TYP      8 bit PMD type */
 626 /*      Values of connector and PMD type comply to SysKonnect internal std */
 627
 628 /*      The EPROM register are currently of no use */
 629 /*      B2_E_0          8 bit EPROM Byte 0 */
 630 /*      B2_E_1          8 bit EPROM Byte 1 */
 631 /*      B2_E_2          8 bit EPROM Byte 2 */
 632 /*      B2_E_3          8 bit EPROM Byte 3 */
 633
 634 /*      B2_FAR          32 bit Flash-Prom Address Register/Counter */
 635 #define FAR_ADDR        0x1ffffL        /* Bit 16..0:   FPROM Address mask */
 636
 637 /*      B2_FDP          8 bit Flash-Prom Data Port */
 638
 639 /*      B2_LD_CRTL      8 bit loader control */
 640 /*      Bits are currently reserved */
 641
 642 /*      B2_LD_TEST      8 bit loader test */
 643 #define LD_T_ON         (1<<3)  /* Bit 3:    Loader Testmode on */
 644 #define LD_T_OFF        (1<<2)  /* Bit 2:    Loader Testmode off */
 645 #define LD_T_STEP       (1<<1)  /* Bit 1:    Decrement FPROM addr. Counter */
 646 #define LD_START        (1<<0)  /* Bit 0:    Start loading FPROM */
 647
 648 /*      B2_TI_INI       32 bit Timer init value */
 649 /*      B2_TI_VAL       32 bit Timer value */
 650 /*      B2_TI_CRTL      8 bit Timer control */
 651 /*      B2_TI_TEST      8 Bit Timer Test */
 652 /*      B2_WDOG_INI     32 bit Watchdog init value */
 653 /*      B2_WDOG_VAL     32 bit Watchdog value */
 654 /*      B2_WDOG_CRTL    8 bit Watchdog control */
 655 /*      B2_WDOG_TEST    8 Bit Watchdog Test */
 656 /*      B2_RTM_INI      32 bit RTM init value */
 657 /*      B2_RTM_VAL      32 bit RTM value */
 658 /*      B2_RTM_CRTL     8 bit RTM control */
 659 /*      B2_RTM_TEST     8 Bit RTM Test */
 660 /*      B2_<TIM>_CRTL   8 bit <TIM> control */
 661 /*      B2_IRQ_MOD_INI  32 bit IRQ Moderation Timer Init Reg.   (ML) */
 662 /*      B2_IRQ_MOD_VAL  32 bit IRQ Moderation Timer Value       (ML) */
 663 /*      B2_IRQ_MOD_CTRL 8 bit IRQ Moderation Timer Control      (ML) */
 664 /*      B2_IRQ_MOD_TEST 8 bit IRQ Moderation Timer Test         (ML) */
 665 #define GET_TOK_CT      (1<<4)  /* Bit 4: Get the Token Counter (RTM) */
 666 #define TIM_RES_TOK     (1<<3)  /* Bit 3: RTM Status: 1 == restricted */
 667 #define TIM_ALARM       (1<<3)  /* Bit 3: Timer Alarm (WDOG) */
 668 #define TIM_START       (1<<2)  /* Bit 2: Start Timer (TI,WDOG,RTM,IRQ_MOD)*/
 669 #define TIM_STOP        (1<<1)  /* Bit 1: Stop Timer (TI,WDOG,RTM,IRQ_MOD) */
 670 #define TIM_CL_IRQ      (1<<0)  /* Bit 0: Clear Timer IRQ (TI,WDOG,RTM) */
 671 /*      B2_<TIM>_TEST   8 Bit <TIM> Test */
 672 #define TIM_T_ON        (1<<2)  /* Bit 2: Test mode on (TI,WDOG,RTM,IRQ_MOD) */
 673 #define TIM_T_OFF       (1<<1)  /* Bit 1: Test mode off (TI,WDOG,RTM,IRQ_MOD) */
 674 #define TIM_T_STEP      (1<<0)  /* Bit 0: Test step (TI,WDOG,RTM,IRQ_MOD) */
 675
 676 /*      B2_TOK_COUNT    0x014c  (ML)    32 bit  Token Counter */
 677 /*      B2_DESC_ADDR_H  0x0150  (ML)    32 bit  Desciptor Base Addr Reg High */
 678 /*      B2_CTRL_2       0x0154  (ML)     8 bit  Control Register 2 */
 679                                 /* Bit 7..5:    reserved                */
 680 #define CTRL_CL_I2C_IRQ (1<<4)  /* Bit 4:       Clear I2C IRQ           */
 681 #define CTRL_ST_SW_IRQ  (1<<3)  /* Bit 3:       Set IRQ SW Request      */
 682 #define CTRL_CL_SW_IRQ  (1<<2)  /* Bit 2:       Clear IRQ SW Request    */
 683 #define CTRL_STOP_DONE  (1<<1)  /* Bit 1:       Stop Master is finished */
 684 #define CTRL_STOP_MAST  (1<<0)  /* Bit 0:       Command Bit to stop the master*/
 685
 686 /*      B2_IFACE_REG    0x0155  (ML)     8 bit  Interface Register */
 687                                 /* Bit 7..3:    reserved                */
 688 #define IF_I2C_DATA_DIR (1<<2)  /* Bit 2:       direction of IF_I2C_DATA*/
 689 #define IF_I2C_DATA     (1<<1)  /* Bit 1:       I2C Data Port           */
 690 #define IF_I2C_CLK      (1<<0)  /* Bit 0:       I2C Clock Port          */
 691
 692                                 /* 0x0156:              reserved */
 693 /*      B2_TST_CTRL_2   0x0157  (ML)     8 bit  Test Control Register 2 */
 694                                         /* Bit 7..4:    reserved */
 695                                         /* force the following error on */
 696                                         /* the next master read/write   */
 697 #define TST_FRC_DPERR_MR64      (1<<3)  /* Bit 3:       DataPERR RD 64  */
 698 #define TST_FRC_DPERR_MW64      (1<<2)  /* Bit 2:       DataPERR WR 64  */
 699 #define TST_FRC_APERR_1M64      (1<<1)  /* Bit 1:       AddrPERR on 1. phase */
 700 #define TST_FRC_APERR_2M64      (1<<0)  /* Bit 0:       AddrPERR on 2. phase */
 701
 702 /*      B2_I2C_CTRL     0x0158  (ML)    32 bit  I2C Control Register           */
 703 #define I2C_FLAG        (1L<<31)        /* Bit 31:      Start read/write if WR */
 704 #define I2C_ADDR        (0x7fffL<<16)   /* Bit 30..16:  Addr to be read/written*/
 705 #define I2C_DEV_SEL     (0x7fL<<9)      /* Bit  9..15:  I2C Device Select      */
 706                                         /* Bit  5.. 8:  reserved               */
 707 #define I2C_BURST_LEN   (1L<<4)         /* Bit  4       Burst Len, 1/4 bytes   */
 708 #define I2C_DEV_SIZE    (7L<<1)         /* Bit  1.. 3:  I2C Device Size        */
 709 #define I2C_025K_DEV    (0L<<1)         /*              0: 256 Bytes or smaller*/
 710 #define I2C_05K_DEV     (1L<<1)         /*              1: 512  Bytes          */
 711 #define I2C_1K_DEV      (2L<<1)         /*              2: 1024 Bytes          */
 712 #define I2C_2K_DEV      (3L<<1)         /*              3: 2048 Bytes          */
 713 #define I2C_4K_DEV      (4L<<1)         /*              4: 4096 Bytes          */
 714 #define I2C_8K_DEV      (5L<<1)         /*              5: 8192 Bytes          */
 715 #define I2C_16K_DEV     (6L<<1)         /*              6: 16384 Bytes         */
 716 #define I2C_32K_DEV     (7L<<1)         /*              7: 32768 Bytes         */
 717 #define I2C_STOP_BIT    (1<<0)          /* Bit  0:      Interrupt I2C transfer */
 718
 719 /*
 720  * I2C Addresses
 721  *
 722  * The temperature sensor and the voltage sensor are on the same I2C bus.
 723  * Note: The voltage sensor (Micorwire) will be selected by PCI_EXT_PATCH_1
 724  *       in PCI_OUR_REG 1.
 725  */
 726 #define I2C_ADDR_TEMP   0x90    /* I2C Address Temperature Sensor */
 727
 728 /*      B2_I2C_DATA     0x015c  (ML)    32 bit  I2C Data Register */
 729
 730 /*      B4_R1_D         4*32 bit current receive Descriptor     (q1) */
 731 /*      B4_R1_DA        32 bit current rec desc address         (q1) */
 732 /*      B4_R1_AC        32 bit current receive Address Count    (q1) */
 733 /*      B4_R1_BC        32 bit current receive Byte Counter     (q1) */
 734 /*      B4_R1_CSR       32 bit BMU Control/Status Register      (q1) */
 735 /*      B4_R1_F         32 bit flag register                    (q1) */
 736 /*      B4_R1_T1        32 bit Test Register 1                  (q1) */
 737 /*      B4_R1_T2        32 bit Test Register 2                  (q1) */
 738 /*      B4_R1_T3        32 bit Test Register 3                  (q1) */
 739 /*      B4_R2_D         4*32 bit current receive Descriptor     (q2) */
 740 /*      B4_R2_DA        32 bit current rec desc address         (q2) */
 741 /*      B4_R2_AC        32 bit current receive Address Count    (q2) */
 742 /*      B4_R2_BC        32 bit current receive Byte Counter     (q2) */
 743 /*      B4_R2_CSR       32 bit BMU Control/Status Register      (q2) */
 744 /*      B4_R2_F         32 bit flag register                    (q2) */
 745 /*      B4_R2_T1        32 bit Test Register 1                  (q2) */
 746 /*      B4_R2_T2        32 bit Test Register 2                  (q2) */
 747 /*      B4_R2_T3        32 bit Test Register 3                  (q2) */
 748 /*      B5_XA_D         4*32 bit current receive Descriptor     (xa) */
 749 /*      B5_XA_DA        32 bit current rec desc address         (xa) */
 750 /*      B5_XA_AC        32 bit current receive Address Count    (xa) */
 751 /*      B5_XA_BC        32 bit current receive Byte Counter     (xa) */
 752 /*      B5_XA_CSR       32 bit BMU Control/Status Register      (xa) */
 753 /*      B5_XA_F         32 bit flag register                    (xa) */
 754 /*      B5_XA_T1        32 bit Test Register 1                  (xa) */
 755 /*      B5_XA_T2        32 bit Test Register 2                  (xa) */
 756 /*      B5_XA_T3        32 bit Test Register 3                  (xa) */
 757 /*      B5_XS_D         4*32 bit current receive Descriptor     (xs) */
 758 /*      B5_XS_DA        32 bit current rec desc address         (xs) */
 759 /*      B5_XS_AC        32 bit current receive Address Count    (xs) */
 760 /*      B5_XS_BC        32 bit current receive Byte Counter     (xs) */
 761 /*      B5_XS_CSR       32 bit BMU Control/Status Register      (xs) */
 762 /*      B5_XS_F         32 bit flag register                    (xs) */
 763 /*      B5_XS_T1        32 bit Test Register 1                  (xs) */
 764 /*      B5_XS_T2        32 bit Test Register 2                  (xs) */
 765 /*      B5_XS_T3        32 bit Test Register 3                  (xs) */
 766 /*      B5_<xx>_CSR     32 bit BMU Control/Status Register      (xx) */
 767 #define CSR_DESC_CLEAR  (1L<<21)    /* Bit 21:  Clear Reset for Descr */
 768 #define CSR_DESC_SET    (1L<<20)    /* Bit 20:  Set Reset for Descr */
 769 #define CSR_FIFO_CLEAR  (1L<<19)    /* Bit 19:  Clear Reset for FIFO */
 770 #define CSR_FIFO_SET    (1L<<18)    /* Bit 18:  Set Reset for FIFO */
 771 #define CSR_HPI_RUN     (1L<<17)    /* Bit 17:  Release HPI SM */
 772 #define CSR_HPI_RST     (1L<<16)    /* Bit 16:  Reset HPI SM to Idle */
 773 #define CSR_SV_RUN      (1L<<15)    /* Bit 15:  Release Supervisor SM */
 774 #define CSR_SV_RST      (1L<<14)    /* Bit 14:  Reset Supervisor SM */
 775 #define CSR_DREAD_RUN   (1L<<13)    /* Bit 13:  Release Descr Read SM */
 776 #define CSR_DREAD_RST   (1L<<12)    /* Bit 12:  Reset Descr Read SM */
 777 #define CSR_DWRITE_RUN  (1L<<11)    /* Bit 11:  Rel. Descr Write SM */
 778 #define CSR_DWRITE_RST  (1L<<10)    /* Bit 10:  Reset Descr Write SM */
 779 #define CSR_TRANS_RUN   (1L<<9)     /* Bit 9:   Release Transfer SM */
 780 #define CSR_TRANS_RST   (1L<<8)     /* Bit 8:   Reset Transfer SM */
 781                                     /* Bit 7..5: reserved */
 782 #define CSR_START       (1L<<4)     /* Bit 4:   Start Rec/Xmit Queue */
 783 #define CSR_IRQ_CL_P    (1L<<3)     /* Bit 3:   Clear Parity IRQ, Rcv */
 784 #define CSR_IRQ_CL_B    (1L<<2)     /* Bit 2:   Clear EOB IRQ */
 785 #define CSR_IRQ_CL_F    (1L<<1)     /* Bit 1:   Clear EOF IRQ */
 786 #define CSR_IRQ_CL_C    (1L<<0)     /* Bit 0:   Clear ERR IRQ */
 787
 788 #define CSR_SET_RESET   (CSR_DESC_SET|CSR_FIFO_SET|CSR_HPI_RST|CSR_SV_RST|\
 789                         CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST)
 790 #define CSR_CLR_RESET   (CSR_DESC_CLEAR|CSR_FIFO_CLEAR|CSR_HPI_RUN|CSR_SV_RUN|\
 791                         CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN)
 792
 793
 794 /*      B5_<xx>_F       32 bit flag register             (xx) */
 795                                         /* Bit 28..31:  reserved              */
 796 #define F_ALM_FULL      (1L<<27)        /* Bit 27: (ML) FIFO almost full      */
 797 #define F_FIFO_EOF      (1L<<26)        /* Bit 26: (ML) Fag bit in FIFO       */
 798 #define F_WM_REACHED    (1L<<25)        /* Bit 25: (ML) Watermark reached     */
 799 #define F_UP_DW_USED    (1L<<24)        /* Bit 24: (ML) Upper Dword used (bug)*/
 800                                         /* Bit 23:      reserved              */
 801 #define F_FIFO_LEVEL    (0x1fL<<16)     /* Bit 16..22:(ML) # of Qwords in FIFO*/
 802                                         /* Bit  8..15:  reserved              */
 803 #define F_ML_WATER_M    0x0000ffL       /* Bit  0.. 7:(ML) Watermark          */
 804 #define FLAG_WATER      0x00001fL       /* Bit 4..0:(DV) Level of req data tr.*/
 805
 806 /*      B5_<xx>_T1      32 bit Test Register 1           (xx) */
 807 /*              Holds four State Machine control Bytes */
 808 #define SM_CRTL_SV      (0xffL<<24) /* Bit 31..24:  Control Supervisor SM */
 809 #define SM_CRTL_RD      (0xffL<<16) /* Bit 23..16:  Control Read Desc SM */
 810 #define SM_CRTL_WR      (0xffL<<8)  /* Bit 15..8:   Control Write Desc SM */
 811 #define SM_CRTL_TR      (0xffL<<0)  /* Bit 7..0:    Control Transfer SM */
 812
 813 /*      B4_<xx>_T1_TR   8 bit Test Register 1 TR                (xx) */
 814 /*      B4_<xx>_T1_WR   8 bit Test Register 1 WR                (xx) */
 815 /*      B4_<xx>_T1_RD   8 bit Test Register 1 RD                (xx) */
 816 /*      B4_<xx>_T1_SV   8 bit Test Register 1 SV                (xx) */
 817 /* The control status byte of each machine looks like ... */
 818 #define SM_STATE        0xf0    /* Bit 7..4:    State which shall be loaded */
 819 #define SM_LOAD         0x08    /* Bit 3:       Load the SM with SM_STATE */
 820 #define SM_TEST_ON      0x04    /* Bit 2:       Switch on SM Test Mode */
 821 #define SM_TEST_OFF     0x02    /* Bit 1:       Go off the Test Mode */
 822 #define SM_STEP         0x01    /* Bit 0:       Step the State Machine */
 823
 824 /* The coding of the states */
 825 #define SM_SV_IDLE      0x0     /* Supervisor   Idle            Tr/Re        */
 826 #define SM_SV_RES_START 0x1     /* Supervisor   Res_Start       Tr/Re        */
 827 #define SM_SV_GET_DESC  0x3     /* Supervisor   Get_Desc        Tr/Re        */
 828 #define SM_SV_CHECK     0x2     /* Supervisor   Check           Tr/Re        */
 829 #define SM_SV_MOV_DATA  0x6     /* Supervisor   Move_Data       Tr/Re        */
 830 #define SM_SV_PUT_DESC  0x7     /* Supervisor   Put_Desc        Tr/Re        */
 831 #define SM_SV_SET_IRQ   0x5     /* Supervisor   Set_Irq         Tr/Re        */
 832
 833 #define SM_RD_IDLE      0x0     /* Read Desc.   Idle            Tr/Re        */
 834 #define SM_RD_LOAD      0x1     /* Read Desc.   Load            Tr/Re        */
 835 #define SM_RD_WAIT_TC   0x3     /* Read Desc.   Wait_TC         Tr/Re        */
 836 #define SM_RD_RST_EOF   0x6     /* Read Desc.   Reset_EOF          Re        */
 837 #define SM_RD_WDONE_R   0x2     /* Read Desc.   Wait_Done          Re        */
 838 #define SM_RD_WDONE_T   0x4     /* Read Desc.   Wait_Done       Tr           */
 839
 840 #define SM_TR_IDLE      0x0     /* Trans. Data  Idle            Tr/Re        */
 841 #define SM_TR_LOAD      0x3     /* Trans. Data  Load            Tr/Re        */
 842 #define SM_TR_LOAD_R_ML 0x1     /* Trans. Data  Load              /Re   (ML) */
 843 #define SM_TR_WAIT_TC   0x2     /* Trans. Data  Wait_TC         Tr/Re        */
 844 #define SM_TR_WDONE     0x4     /* Trans. Data  Wait_Done       Tr/Re        */
 845
 846 #define SM_WR_IDLE      0x0     /* Write Desc.  Idle            Tr/Re        */
 847 #define SM_WR_ABLEN     0x1     /* Write Desc.  Act_Buf_Length  Tr/Re        */
 848 #define SM_WR_LD_A4     0x2     /* Write Desc.  Load_A4            Re        */
 849 #define SM_WR_RES_OWN   0x2     /* Write Desc.  Res_OWN         Tr           */
 850 #define SM_WR_WAIT_EOF  0x3     /* Write Desc.  Wait_EOF           Re        */
 851 #define SM_WR_LD_N2C_R  0x4     /* Write Desc.  Load_N2C           Re        */
 852 #define SM_WR_WAIT_TC_R 0x5     /* Write Desc.  Wait_TC            Re        */
 853 #define SM_WR_WAIT_TC4  0x6     /* Write Desc.  Wait_TC4           Re        */
 854 #define SM_WR_LD_A_T    0x6     /* Write Desc.  Load_A          Tr           */
 855 #define SM_WR_LD_A_R    0x7     /* Write Desc.  Load_A             Re        */
 856 #define SM_WR_WAIT_TC_T 0x7     /* Write Desc.  Wait_TC         Tr           */
 857 #define SM_WR_LD_N2C_T  0xc     /* Write Desc.  Load_N2C        Tr           */
 858 #define SM_WR_WDONE_T   0x9     /* Write Desc.  Wait_Done       Tr           */
 859 #define SM_WR_WDONE_R   0xc     /* Write Desc.  Wait_Done          Re        */
 860 #define SM_WR_LD_D_AD   0xe     /* Write Desc.  Load_Dumr_A        Re   (ML) */
 861 #define SM_WR_WAIT_D_TC 0xf     /* Write Desc.  Wait_Dumr_TC       Re   (ML) */
 862
 863 /*      B5_<xx>_T2      32 bit Test Register 2           (xx) */
 864 /* Note: This register is only defined for the transmit queues */
 865                                 /* Bit 31..8:   reserved */
 866 #define AC_TEST_ON      (1<<7)  /* Bit 7:       Address Counter Test Mode on */
 867 #define AC_TEST_OFF     (1<<6)  /* Bit 6:       Address Counter Test Mode off*/
 868 #define BC_TEST_ON      (1<<5)  /* Bit 5:       Byte Counter Test Mode on */
 869 #define BC_TEST_OFF     (1<<4)  /* Bit 4:       Byte Counter Test Mode off */
 870 #define TEST_STEP04     (1<<3)  /* Bit 3:       Inc AC/Dec BC by 4 */
 871 #define TEST_STEP03     (1<<2)  /* Bit 2:       Inc AC/Dec BC by 3 */
 872 #define TEST_STEP02     (1<<1)  /* Bit 1:       Inc AC/Dec BC by 2 */
 873 #define TEST_STEP01     (1<<0)  /* Bit 0:       Inc AC/Dec BC by 1 */
 874
 875 /*      B5_<xx>_T3      32 bit Test Register 3           (xx) */
 876 /* Note: This register is only defined for the transmit queues */
 877                                 /* Bit 31..8:   reserved */
 878 #define T3_MUX_2        (1<<7)  /* Bit 7: (ML)  Mux position MSB */
 879 #define T3_VRAM_2       (1<<6)  /* Bit 6: (ML)  Virtual RAM buffer addr MSB */
 880 #define T3_LOOP         (1<<5)  /* Bit 5:       Set Loopback (Xmit) */
 881 #define T3_UNLOOP       (1<<4)  /* Bit 4:       Unset Loopback (Xmit) */
 882 #define T3_MUX          (3<<2)  /* Bit 3..2:    Mux position */
 883 #define T3_VRAM         (3<<0)  /* Bit 1..0:    Virtual RAM buffer Address */
 884
 885 /* PCI card IDs */
 886 /*
 887  * Note: The following 4 byte definitions shall not be used! Use OEM Concept!
 888  */
 889 #define PCI_VEND_ID0    0x48            /* PCI vendor ID (SysKonnect) */
 890 #define PCI_VEND_ID1    0x11            /* PCI vendor ID (SysKonnect) */
 891                                         /*               (High byte) */
 892 #define PCI_DEV_ID0     0x00            /* PCI device ID */
 893 #define PCI_DEV_ID1     0x40            /* PCI device ID (High byte) */
 894
 895 /*#define PCI_CLASS     0x02*/          /* PCI class code: network device */
 896 #define PCI_NW_CLASS    0x02            /* PCI class code: network device */
 897 #define PCI_SUB_CLASS   0x02            /* PCI subclass ID: FDDI device */
 898 #define PCI_PROG_INTFC  0x00            /* PCI programming Interface (=0) */
 899
 900 /*
 901  * address transmission from logical to physical offset address on board
 902  */
 903 #define FMA(a)  (0x0400|((a)<<2))       /* FORMAC+ (r/w) (SN3) */
 904 #define P1(a)   (0x0380|((a)<<2))       /* PLC1 (r/w) (DAS) */
 905 #define P2(a)   (0x0600|((a)<<2))       /* PLC2 (r/w) (covered by the SN3) */
 906 #define PRA(a)  (B2_MAC_0 + (a))        /* configuration PROM (MAC address) */
 907
 908 /*
 909  * FlashProm specification
 910  */
 911 #define MAX_PAGES       0x20000L        /* Every byte has a single page */
 912 #define MAX_FADDR       1               /* 1 byte per page */
 913
 914 /*
 915  * Receive / Transmit Buffer Control word
 916  */
 917 #define BMU_OWN         (1UL<<31)       /* OWN bit: 0 == host, 1 == adapter */
 918 #define BMU_STF         (1L<<30)        /* Start of Frame ?             */
 919 #define BMU_EOF         (1L<<29)        /* End of Frame ?               */
 920 #define BMU_EN_IRQ_EOB  (1L<<28)        /* Enable "End of Buffer" IRQ   */
 921 #define BMU_EN_IRQ_EOF  (1L<<27)        /* Enable "End of Frame" IRQ    */
 922 #define BMU_DEV_0       (1L<<26)        /* RX: don't transfer to system mem */
 923 #define BMU_SMT_TX      (1L<<25)        /* TX: if set, buffer type SMT_MBuf */
 924 #define BMU_ST_BUF      (1L<<25)        /* RX: copy of start of frame */
 925 #define BMU_UNUSED      (1L<<24)        /* Set if the Descr is curr unused */
 926 #define BMU_SW          (3L<<24)        /* 2 Bits reserved for SW usage */
 927 #define BMU_CHECK       0x00550000L     /* To identify the control word */
 928 #define BMU_BBC         0x0000FFFFL     /* R/T Buffer Byte Count        */
 929
 930 /*
 931  * physical address offset + IO-Port base address
 932  */
 933 #ifdef MEM_MAPPED_IO
 934 #define ADDR(a)         (char far *) smc->hw.iop+(a)
 935 #define ADDRS(smc,a)    (char far *) (smc)->hw.iop+(a)
 936 #else
 937 #define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \
 938         (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
 939         (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
 940 #define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \
 941         ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
 942         ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
 943 #endif
 944
 945 /*
 946  * Define a macro to access the configuration space
 947  */
 948 #define PCI_C(a)        ADDR(B3_CFG_SPC + (a))  /* PCI Config Space */
 949
 950 #define EXT_R(a)        ADDR(B6_EXT_REG + (a))  /* External Registers */
 951
 952 /*
 953  * Define some values needed for the MAC address (PROM)
 954  */
 955 #define SA_MAC          (0)     /* start addr. MAC_AD within the PROM */
 956 #define PRA_OFF         (0)     /* offset correction when 4th byte reading */
 957
 958 #define SKFDDI_PSZ      8       /* address PROM size */
 959
 960 #define FM_A(a) ADDR(FMA(a))    /* FORMAC Plus physical addr */
 961 #define P1_A(a) ADDR(P1(a))     /* PLC1 (r/w) */
 962 #define P2_A(a) ADDR(P2(a))     /* PLC2 (r/w) (DAS) */
 963 #define PR_A(a) ADDR(PRA(a))    /* config. PROM (MAC address) */
 964
 965 /*
 966  * Macro to read the PROM
 967  */
 968 #define READ_PROM(a)    ((u_char)inp(a))
 969
 970 #define GET_PAGE(bank)  outpd(ADDR(B2_FAR),bank)
 971 #define VPP_ON()
 972 #define VPP_OFF()
 973
 974 /*
 975  * Note: Values of the Interrupt Source Register are defined above
 976  */
 977 #define ISR_A           ADDR(B0_ISRC)
 978 #define GET_ISR()               inpd(ISR_A)
 979 #define GET_ISR_SMP(iop)        inpd((iop)+B0_ISRC)
 980 #define CHECK_ISR()             (inpd(ISR_A) & inpd(ADDR(B0_IMSK)))
 981 #define CHECK_ISR_SMP(iop)      (inpd((iop)+B0_ISRC) & inpd((iop)+B0_IMSK))
 982
 983 #define BUS_CHECK()
 984
 985 /*
 986  * CLI_FBI:     Disable Board Interrupts
 987  * STI_FBI:     Enable Board Interrupts
 988  */
 989 #ifndef UNIX
 990 #define CLI_FBI()       outpd(ADDR(B0_IMSK),0)
 991 #else
 992 #define CLI_FBI(smc)    outpd(ADDRS((smc),B0_IMSK),0)
 993 #endif
 994
 995 #ifndef UNIX
 996 #define STI_FBI()       outpd(ADDR(B0_IMSK),smc->hw.is_imask)
 997 #else
 998 #define STI_FBI(smc)    outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask)
 999 #endif
1000
1001 #define CLI_FBI_SMP(iop)        outpd((iop)+B0_IMSK,0)
1002 #define STI_FBI_SMP(smc,iop)    outpd((iop)+B0_IMSK,(smc)->hw.is_imask)
1003
1004 #endif  /* PCI */
1005 /*--------------------------------------------------------------------------*/
1006
1007 /*
1008  * 12 bit transfer (dword) counter:
1009  *      (ISA:   2*trc = number of byte)
1010  *      (EISA:  4*trc = number of byte)
1011  *      (MCA:   4*trc = number of byte)
1012  */
1013 #define MAX_TRANS       (0x0fff)
1014
1015 /*
1016  * PC PIC
1017  */
1018 #define MST_8259 (0x20)
1019 #define SLV_8259 (0xA0)
1020
1021 #define TPS             (18)            /* ticks per second */
1022
1023 /*
1024  * error timer defs
1025  */
1026 #define TN              (4)     /* number of supported timer = TN+1 */
1027 #define SNPPND_TIME     (5)     /* buffer memory access over mem. data reg. */
1028
1029 #define MAC_AD  0x405a0000
1030
1031 #define MODR1   FM_A(FM_MDREG1) /* mode register 1 */
1032 #define MODR2   FM_A(FM_MDREG2) /* mode register 2 */
1033
1034 #define CMDR1   FM_A(FM_CMDREG1)        /* command register 1 */
1035 #define CMDR2   FM_A(FM_CMDREG2)        /* command register 2 */
1036
1037
1038 /*
1039  * function defines
1040  */
1041 #define CLEAR(io,mask)          outpw((io),inpw(io)&(~(mask)))
1042 #define SET(io,mask)            outpw((io),inpw(io)|(mask))
1043 #define GET(io,mask)            (inpw(io)&(mask))
1044 #define SETMASK(io,val,mask)    outpw((io),(inpw(io) & ~(mask)) | (val))
1045
1046 /*
1047  * PHY Port A (PA) = PLC 1
1048  * With SuperNet 3 PHY-A and PHY S are identical.
1049  */
1050 #define PLC(np,reg)     (((np) == PA) ? P2_A(reg) : P1_A(reg))
1051
1052 /*
1053  * set memory address register for write and read
1054  */
1055 #define MARW(ma)        outpw(FM_A(FM_MARW),(unsigned int)(ma))
1056 #define MARR(ma)        outpw(FM_A(FM_MARR),(unsigned int)(ma))
1057
1058 /*
1059  * read/write from/to memory data register
1060  */
1061 /* write double word */
1062 #define MDRW(dd)        outpw(FM_A(FM_MDRU),(unsigned int)((dd)>>16)) ;\
1063                         outpw(FM_A(FM_MDRL),(unsigned int)(dd))
1064
1065 #ifndef WINNT
1066 /* read double word */
1067 #define MDRR()          (((long)inpw(FM_A(FM_MDRU))<<16) + inpw(FM_A(FM_MDRL)))
1068
1069 /* read FORMAC+ 32-bit status register */
1070 #define GET_ST1()       (((long)inpw(FM_A(FM_ST1U))<<16) + inpw(FM_A(FM_ST1L)))
1071 #define GET_ST2()       (((long)inpw(FM_A(FM_ST2U))<<16) + inpw(FM_A(FM_ST2L)))
1072 #ifdef  SUPERNET_3
1073 #define GET_ST3()       (((long)inpw(FM_A(FM_ST3U))<<16) + inpw(FM_A(FM_ST3L)))
1074 #endif
1075 #else
1076 /* read double word */
1077 #define MDRR()          inp2w((FM_A(FM_MDRU)),(FM_A(FM_MDRL)))
1078
1079 /* read FORMAC+ 32-bit status register */
1080 #define GET_ST1()       inp2w((FM_A(FM_ST1U)),(FM_A(FM_ST1L)))
1081 #define GET_ST2()       inp2w((FM_A(FM_ST2U)),(FM_A(FM_ST2L)))
1082 #ifdef  SUPERNET_3
1083 #define GET_ST3()       inp2w((FM_A(FM_ST3U)),(FM_A(FM_ST3L)))
1084 #endif
1085 #endif
1086
1087 /* Special timer macro for 82c54 */
1088                                 /* timer access over data bus bit 8..15 */
1089 #define OUT_82c54_TIMER(port,val)       outpw(TI_A(port),(val)<<8)
1090 #define IN_82c54_TIMER(port)            ((inpw(TI_A(port))>>8) & 0xff)
1091
1092
1093 #ifdef  DEBUG
1094 #define DB_MAC(mac,st) {if (debug_mac & 0x1)\
1095                                 printf("M") ;\
1096                         if (debug_mac & 0x2)\
1097                                 printf("\tMAC %d status 0x%08lx\n",mac,st) ;\
1098                         if (debug_mac & 0x4)\
1099                                 dp_mac(mac,st) ;\
1100 }
1101
1102 #define DB_PLC(p,iev) { if (debug_plc & 0x1)\
1103                                 printf("P") ;\
1104                         if (debug_plc & 0x2)\
1105                                 printf("\tPLC %s Int 0x%04x\n", \
1106                                         (p == PA) ? "A" : "B", iev) ;\
1107                         if (debug_plc & 0x4)\
1108                                 dp_plc(p,iev) ;\
1109 }
1110
1111 #define DB_TIMER() {    if (debug_timer & 0x1)\
1112                                 printf("T") ;\
1113                         if (debug_timer & 0x2)\
1114                                 printf("\tTimer ISR\n") ;\
1115 }
1116
1117 #else   /* no DEBUG */
1118
1119 #define DB_MAC(mac,st)
1120 #define DB_PLC(p,iev)
1121 #define DB_TIMER()
1122
1123 #endif  /* no DEBUG */
1124
1125 #define INC_PTR(sp,cp,ep)       if (++cp == ep) cp = sp
1126 /*
1127  * timer defs
1128  */
1129 #define COUNT(t)        ((t)<<6)        /* counter */
1130 #define RW_OP(o)        ((o)<<4)        /* read/write operation */
1131 #define TMODE(m)        ((m)<<1)        /* timer mode */
1132
1133 #endif