?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
xenbus_client.c: correct exit path for xenbus_map_ring_valloc_hvm
[linux/fpc-iii.git] / drivers / staging / cxt1e1 / musycc.c
blobb2cc68a1fe879ab155106b271e2671fb564cab09
1 unsigned int max_intcnt = 0;
2 unsigned int max_bh = 0;
3
4 /*-----------------------------------------------------------------------------
5 * musycc.c -
6 *
7 * Copyright (C) 2007 One Stop Systems, Inc.
8 * Copyright (C) 2003-2006 SBE, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * For further information, contact via email: support@onestopsystems.com
21 * One Stop Systems, Inc. Escondido, California U.S.A.
22 *-----------------------------------------------------------------------------
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/types.h>
28 #include "pmcc4_sysdep.h"
29 #include <linux/kernel.h>
30 #include <linux/errno.h>
31 #include <linux/init.h>
32 #include "sbecom_inline_linux.h"
33 #include "libsbew.h"
34 #include "pmcc4_private.h"
35 #include "pmcc4.h"
36 #include "musycc.h"
37
38 #ifdef SBE_INCLUDE_SYMBOLS
39 #define STATIC
40 #else
41 #define STATIC static
42 #endif
43
44 #define sd_find_chan(ci,ch) c4_find_chan(ch)
45
46
47 /*******************************************************************/
48 /* global driver variables */
49 extern ci_t *c4_list;
50 extern int drvr_state;
51 extern int cxt1e1_log_level;
52
53 extern int cxt1e1_max_mru;
54 extern int cxt1e1_max_mtu;
55 extern int max_rxdesc_used;
56 extern int max_txdesc_used;
57 extern ci_t *CI; /* dummy pointr to board ZEROE's data - DEBUG
58 * USAGE */
59
60
61 /*******************************************************************/
62 /* forward references */
63 void c4_fifo_free(mpi_t *, int);
64 void c4_wk_chan_restart(mch_t *);
65 void musycc_bh_tx_eom(mpi_t *, int);
66 int musycc_chan_up(ci_t *, int);
67 status_t __init musycc_init(ci_t *);
68 STATIC void __init musycc_init_port(mpi_t *);
69 void musycc_intr_bh_tasklet(ci_t *);
70 void musycc_serv_req(mpi_t *, u_int32_t);
71 void musycc_update_timeslots(mpi_t *);
72
73 /*******************************************************************/
74
75 #if 1
76 STATIC int
77 musycc_dump_rxbuffer_ring(mch_t * ch, int lockit)
78 {
79 struct mdesc *m;
80 unsigned long flags = 0;
81
82 u_int32_t status;
83 int n;
84
85 if (lockit)
86 spin_lock_irqsave(&ch->ch_rxlock, flags);
87 if (ch->rxd_num == 0)
88 pr_info(" ZERO receive buffers allocated for this channel.");
89 else {
90 FLUSH_MEM_READ();
91 m = &ch->mdr[ch->rxix_irq_srv];
92 for (n = ch->rxd_num; n; n--) {
93 status = le32_to_cpu(m->status);
94 {
95 pr_info("%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
96 (m == &ch->mdr[ch->rxix_irq_srv]) ? 'F' : ' ',
97 (unsigned long) m, n,
98 status,
99 m->data ? (status & HOST_RX_OWNED ? 'H' : 'M') : '-',
100 status & POLL_DISABLED ? 'P' : '-',
101 status & EOBIRQ_ENABLE ? 'b' : '-',
102 status & EOMIRQ_ENABLE ? 'm' : '-',
103 status & LENGTH_MASK,
104 le32_to_cpu(m->data), le32_to_cpu(m->next));
105 #ifdef RLD_DUMP_BUFDATA
106 {
107 u_int32_t *dp;
108 int len = status & LENGTH_MASK;
109
110 #if 1
111 if (m->data && (status & HOST_RX_OWNED))
112 #else
113 if (m->data) /* always dump regardless of valid RX
114 * data */
115 #endif
116 {
117 dp = (u_int32_t *) OS_phystov((void *) (le32_to_cpu(m->data)));
118 if (len >= 0x10)
119 pr_info(" %x[%x]: %08X %08X %08X %08x\n", (u_int32_t) dp, len,
120 *dp, *(dp + 1), *(dp + 2), *(dp + 3));
121 else if (len >= 0x08)
122 pr_info(" %x[%x]: %08X %08X\n", (u_int32_t) dp, len,
123 *dp, *(dp + 1));
124 else
125 pr_info(" %x[%x]: %08X\n", (u_int32_t) dp, len, *dp);
126 }
127 }
128 #endif
129 }
130 m = m->snext;
131 }
132 } /* -for- */
133 pr_info("\n");
134
135 if (lockit)
136 spin_unlock_irqrestore(&ch->ch_rxlock, flags);
137 return 0;
138 }
139 #endif
140
141 #if 1
142 STATIC int
143 musycc_dump_txbuffer_ring(mch_t * ch, int lockit)
144 {
145 struct mdesc *m;
146 unsigned long flags = 0;
147 u_int32_t status;
148 int n;
149
150 if (lockit)
151 spin_lock_irqsave(&ch->ch_txlock, flags);
152 if (ch->txd_num == 0)
153 pr_info(" ZERO transmit buffers allocated for this channel.");
154 else {
155 FLUSH_MEM_READ();
156 m = ch->txd_irq_srv;
157 for (n = ch->txd_num; n; n--) {
158 status = le32_to_cpu(m->status);
159 {
160 pr_info("%c%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
161 (m == ch->txd_usr_add) ? 'F' : ' ',
162 (m == ch->txd_irq_srv) ? 'L' : ' ',
163 (unsigned long) m, n,
164 status,
165 m->data ? (status & MUSYCC_TX_OWNED ? 'M' : 'H') : '-',
166 status & POLL_DISABLED ? 'P' : '-',
167 status & EOBIRQ_ENABLE ? 'b' : '-',
168 status & EOMIRQ_ENABLE ? 'm' : '-',
169 status & LENGTH_MASK,
170 le32_to_cpu(m->data), le32_to_cpu(m->next));
171 #ifdef RLD_DUMP_BUFDATA
172 {
173 u_int32_t *dp;
174 int len = status & LENGTH_MASK;
175
176 if (m->data) {
177 dp = (u_int32_t *) OS_phystov((void *) (le32_to_cpu(m->data)));
178 if (len >= 0x10)
179 pr_info(" %x[%x]: %08X %08X %08X %08x\n", (u_int32_t) dp, len,
180 *dp, *(dp + 1), *(dp + 2), *(dp + 3));
181 else if (len >= 0x08)
182 pr_info(" %x[%x]: %08X %08X\n", (u_int32_t) dp, len,
183 *dp, *(dp + 1));
184 else
185 pr_info(" %x[%x]: %08X\n", (u_int32_t) dp, len, *dp);
186 }
187 }
188 #endif
189 }
190 m = m->snext;
191 }
192 } /* -for- */
193 pr_info("\n");
194
195 if (lockit)
196 spin_unlock_irqrestore(&ch->ch_txlock, flags);
197 return 0;
198 }
199 #endif
200
201
202 /*
203 * The following supports a backdoor debug facility which can be used to
204 * display the state of a board's channel.
205 */
206
207 status_t
208 musycc_dump_ring(ci_t * ci, unsigned int chan)
209 {
210 mch_t *ch;
211
212 if (chan >= MAX_CHANS_USED)
213 return SBE_DRVR_FAIL; /* E2BIG */
214 {
215 int bh;
216
217 bh = atomic_read(&ci->bh_pending);
218 pr_info(">> bh_pend %d [%d] ihead %d itail %d [%d] th_cnt %d bh_cnt %d wdcnt %d note %d\n",
219 bh, max_bh, ci->iqp_headx, ci->iqp_tailx, max_intcnt,
220 ci->intlog.drvr_intr_thcount,
221 ci->intlog.drvr_intr_bhcount,
222 ci->wdcount, ci->wd_notify);
223 max_bh = 0; /* reset counter */
224 max_intcnt = 0; /* reset counter */
225 }
226
227 if (!(ch = sd_find_chan(dummy, chan))) {
228 pr_info(">> musycc_dump_ring: channel %d not up.\n", chan);
229 return ENOENT;
230 }
231 pr_info(">> CI %p CHANNEL %3d @ %p: state %x status/p %x/%x\n", ci, chan, ch, ch->state,
232 ch->status, ch->p.status);
233 pr_info("--------------------------------\nTX Buffer Ring - Channel %d, txd_num %d. (bd/ch pend %d %d), TXD required %d, txpkt %lu\n",
234 chan, ch->txd_num,
235 (u_int32_t) atomic_read(&ci->tx_pending), (u_int32_t) atomic_read(&ch->tx_pending), ch->txd_required, ch->s.tx_packets);
236 pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
237 ch->user, ch->txd_irq_srv, ch->txd_usr_add,
238 sd_queue_stopped(ch->user),
239 ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
240 musycc_dump_txbuffer_ring(ch, 1);
241 pr_info("RX Buffer Ring - Channel %d, rxd_num %d. IRQ_SRV[%d] 0x%p, start_rx %x rxpkt %lu\n",
242 chan, ch->rxd_num, ch->rxix_irq_srv,
243 &ch->mdr[ch->rxix_irq_srv], ch->ch_start_rx, ch->s.rx_packets);
244 musycc_dump_rxbuffer_ring(ch, 1);
245
246 return SBE_DRVR_SUCCESS;
247 }
248
249
250 status_t
251 musycc_dump_rings(ci_t * ci, unsigned int start_chan)
252 {
253 unsigned int chan;
254
255 for (chan = start_chan; chan < (start_chan + 5); chan++)
256 musycc_dump_ring(ci, chan);
257 return SBE_DRVR_SUCCESS;
258 }
259
260
261 /*
262 * NOTE on musycc_init_mdt(): These MUSYCC writes are only operational after
263 * a MUSYCC GROUP_INIT command has been issued.
264 */
265
266 void
267 musycc_init_mdt(mpi_t * pi)
268 {
269 u_int32_t *addr, cfg;
270 int i;
271
272 /*
273 * This Idle Code insertion takes effect prior to channel's first
274 * transmitted message. After that, each message contains its own Idle
275 * Code information which is to be issued after the message is
276 * transmitted (Ref.MUSYCC 5.2.2.3: MCENBL bit in Group Configuration
277 * Descriptor).
278 */
279
280 addr = (u_int32_t *) ((u_long) pi->reg + MUSYCC_MDT_BASE03_ADDR);
281 cfg = CFG_CH_FLAG_7E << IDLE_CODE;
282
283 for (i = 0; i < 32; addr++, i++)
284 pci_write_32(addr, cfg);
285 }
286
287
288 /* Set TX thp to the next unprocessed md */
289
290 void
291 musycc_update_tx_thp(mch_t * ch)
292 {
293 struct mdesc *md;
294 unsigned long flags;
295
296 spin_lock_irqsave(&ch->ch_txlock, flags);
297 while (1) {
298 md = ch->txd_irq_srv;
299 FLUSH_MEM_READ();
300 if (!md->data) {
301 /* No MDs with buffers to process */
302 spin_unlock_irqrestore(&ch->ch_txlock, flags);
303 return;
304 }
305 if ((le32_to_cpu(md->status)) & MUSYCC_TX_OWNED) {
306 /* this is the MD to restart TX with */
307 break;
308 }
309 /*
310 * Otherwise, we have a valid, host-owned message descriptor which
311 * has been successfully transmitted and whose buffer can be freed,
312 * so... process this MD, it's owned by the host. (This might give
313 * as a new, updated txd_irq_srv.)
314 */
315 musycc_bh_tx_eom(ch->up, ch->gchan);
316 }
317 md = ch->txd_irq_srv;
318 ch->up->regram->thp[ch->gchan] = cpu_to_le32(OS_vtophys(md));
319 FLUSH_MEM_WRITE();
320
321 if (ch->tx_full) {
322 ch->tx_full = 0;
323 ch->txd_required = 0;
324 sd_enable_xmit(ch->user); /* re-enable to catch flow controlled
325 * channel */
326 }
327 spin_unlock_irqrestore(&ch->ch_txlock, flags);
328
329 #ifdef RLD_TRANS_DEBUG
330 pr_info("++ musycc_update_tx_thp[%d]: setting thp = %p, sts %x\n", ch->channum, md, md->status);
331 #endif
332 }
333
334
335 /*
336 * This is the workq task executed by the OS when our queue_work() is
337 * scheduled and run. It can fire off either RX or TX ACTIVATION depending
338 * upon the channel's ch_start_tx and ch_start_rx variables. This routine
339 * is implemented as a work queue so that the call to the service request is
340 * able to sleep, awaiting an interrupt acknowledgment response (SACK) from
341 * the hardware.
342 */
343
344 void
345 musycc_wq_chan_restart(void *arg) /* channel private structure */
346 {
347 mch_t *ch;
348 mpi_t *pi;
349 struct mdesc *md;
350 #if 0
351 unsigned long flags;
352 #endif
353
354 ch = container_of(arg, struct c4_chan_info, ch_work);
355 pi = ch->up;
356
357 #ifdef RLD_TRANS_DEBUG
358 pr_info("wq_chan_restart[%d]: start_RT[%d/%d] status %x\n",
359 ch->channum, ch->ch_start_rx, ch->ch_start_tx, ch->status);
360
361 #endif
362
363 /**********************************/
364 /** check for RX restart request **/
365 /**********************************/
366
367 if ((ch->ch_start_rx) && (ch->status & RX_ENABLED)) {
368
369 ch->ch_start_rx = 0;
370 #if defined(RLD_TRANS_DEBUG) || defined(RLD_RXACT_DEBUG)
371 {
372 static int hereb4 = 7;
373
374 if (hereb4) { /* RLD DEBUG */
375 hereb4--;
376 #ifdef RLD_TRANS_DEBUG
377 md = &ch->mdr[ch->rxix_irq_srv];
378 pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
379 ch->channum, ch->rxix_irq_srv, md, le32_to_cpu(md->status),
380 ch->s.rx_packets);
381 #elif defined(RLD_RXACT_DEBUG)
382 md = &ch->mdr[ch->rxix_irq_srv];
383 pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
384 ch->channum, ch->rxix_irq_srv, md, le32_to_cpu(md->status),
385 ch->s.rx_packets);
386 musycc_dump_rxbuffer_ring(ch, 1); /* RLD DEBUG */
387 #endif
388 }
389 }
390 #endif
391 musycc_serv_req(pi, SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION | ch->gchan);
392 }
393 /**********************************/
394 /** check for TX restart request **/
395 /**********************************/
396
397 if ((ch->ch_start_tx) && (ch->status & TX_ENABLED)) {
398 /* find next unprocessed message, then set TX thp to it */
399 musycc_update_tx_thp(ch);
400
401 #if 0
402 spin_lock_irqsave(&ch->ch_txlock, flags);
403 #endif
404 md = ch->txd_irq_srv;
405 if (!md) {
406 #ifdef RLD_TRANS_DEBUG
407 pr_info("-- musycc_wq_chan_restart[%d]: WARNING, starting NULL md\n", ch->channum);
408 #endif
409 #if 0
410 spin_unlock_irqrestore(&ch->ch_txlock, flags);
411 #endif
412 } else if (md->data && ((le32_to_cpu(md->status)) & MUSYCC_TX_OWNED)) {
413 ch->ch_start_tx = 0;
414 #if 0
415 spin_unlock_irqrestore(&ch->ch_txlock, flags); /* allow interrupts for service request */
416 #endif
417 #ifdef RLD_TRANS_DEBUG
418 pr_info("++ musycc_wq_chan_restart() CHAN TX ACTIVATE: chan %d txd_irq_srv %p = sts %x, txpkt %lu\n",
419 ch->channum, ch->txd_irq_srv, ch->txd_irq_srv->status, ch->s.tx_packets);
420 #endif
421 musycc_serv_req(pi, SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION | ch->gchan);
422 }
423 #ifdef RLD_RESTART_DEBUG
424 else {
425 /* retain request to start until retried and we have data to xmit */
426 pr_info("-- musycc_wq_chan_restart[%d]: DELAYED due to md %p sts %x data %x, start_tx %x\n",
427 ch->channum, md,
428 le32_to_cpu(md->status),
429 le32_to_cpu(md->data), ch->ch_start_tx);
430 musycc_dump_txbuffer_ring(ch, 0);
431 #if 0
432 spin_unlock_irqrestore(&ch->ch_txlock, flags); /* allow interrupts for service request */
433 #endif
434 }
435 #endif
436 }
437 }
438
439
440 /*
441 * Channel restart either fires of a workqueue request (2.6) or lodges a
442 * watchdog activation sequence (2.4).
443 */
444
445 void
446 musycc_chan_restart(mch_t * ch)
447 {
448 #ifdef RLD_RESTART_DEBUG
449 pr_info("++ musycc_chan_restart[%d]: txd_irq_srv @ %p = sts %x\n",
450 ch->channum, ch->txd_irq_srv, ch->txd_irq_srv->status);
451 #endif
452
453 /* 2.6 - find next unprocessed message, then set TX thp to it */
454 #ifdef RLD_RESTART_DEBUG
455 pr_info(">> musycc_chan_restart: scheduling Chan %x workQ @ %p\n", ch->channum, &ch->ch_work);
456 #endif
457 c4_wk_chan_restart(ch); /* work queue mechanism fires off: Ref:
458 * musycc_wq_chan_restart () */
459
460 }
461
462
463 void
464 rld_put_led(mpi_t * pi, u_int32_t ledval)
465 {
466 static u_int32_t led = 0;
467
468 if (ledval == 0)
469 led = 0;
470 else
471 led |= ledval;
472
473 pci_write_32((u_int32_t *) &pi->up->cpldbase->leds, led); /* RLD DEBUG TRANHANG */
474 }
475
476
477 #define MUSYCC_SR_RETRY_CNT 9
478
479 void
480 musycc_serv_req(mpi_t * pi, u_int32_t req)
481 {
482 volatile u_int32_t r;
483 int rcnt;
484
485 /*
486 * PORT NOTE: Semaphore protect service loop guarantees only a single
487 * operation at a time. Per MUSYCC Manual - "Issuing service requests to
488 * the same channel group without first receiving ACK from each request
489 * may cause the host to lose track of which service request has been
490 * acknowledged."
491 */
492
493 SD_SEM_TAKE(&pi->sr_sem_busy, "serv"); /* only 1 thru here, per
494 * group */
495
496 if (pi->sr_last == req) {
497 #ifdef RLD_TRANS_DEBUG
498 pr_info(">> same SR, Port %d Req %x\n", pi->portnum, req);
499 #endif
500
501 /*
502 * The most likely repeated request is the channel activation command
503 * which follows the occurrence of a Transparent mode TX ONR or a
504 * BUFF error. If the previous command was a CHANNEL ACTIVATE,
505 * precede it with a NOOP command in order maintain coherent control
506 * of this current (re)ACTIVATE.
507 */
508
509 r = (pi->sr_last & ~SR_GCHANNEL_MASK);
510 if ((r == (SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION)) ||
511 (r == (SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION))) {
512 #ifdef RLD_TRANS_DEBUG
513 pr_info(">> same CHAN ACT SR, Port %d Req %x => issue SR_NOOP CMD\n", pi->portnum, req);
514 #endif
515 SD_SEM_GIVE(&pi->sr_sem_busy); /* allow this next request */
516 musycc_serv_req(pi, SR_NOOP);
517 SD_SEM_TAKE(&pi->sr_sem_busy, "serv"); /* relock & continue w/
518 * original req */
519 } else if (req == SR_NOOP) {
520 /* no need to issue back-to-back SR_NOOP commands at this time */
521 #ifdef RLD_TRANS_DEBUG
522 pr_info(">> same Port SR_NOOP skipped, Port %d\n", pi->portnum);
523 #endif
524 SD_SEM_GIVE(&pi->sr_sem_busy); /* allow this next request */
525 return;
526 }
527 }
528 rcnt = 0;
529 pi->sr_last = req;
530 rewrite:
531 pci_write_32((u_int32_t *) &pi->reg->srd, req);
532 FLUSH_MEM_WRITE();
533
534 /*
535 * Per MUSYCC Manual, Section 6.1,2 - "When writing an SCR service
536 * request, the host must ensure at least one PCI bus clock cycle has
537 * elapsed before writing another service request. To meet this minimum
538 * elapsed service request write timing interval, it is recommended that
539 * the host follow any SCR write with another operation which reads from
540 * the same address."
541 */
542 r = pci_read_32((u_int32_t *) &pi->reg->srd); /* adhere to write
543 * timing imposition */
544
545
546 if ((r != req) && (req != SR_CHIP_RESET) && (++rcnt <= MUSYCC_SR_RETRY_CNT)) {
547 if (cxt1e1_log_level >= LOG_MONITOR)
548 pr_info("%s: %d - reissue srv req/last %x/%x (hdw reads %x), Chan %d.\n",
549 pi->up->devname, rcnt, req, pi->sr_last, r,
550 (pi->portnum * MUSYCC_NCHANS) + (req & 0x1f));
551 OS_uwait_dummy(); /* this delay helps reduce reissue counts
552 * (reason not yet researched) */
553 goto rewrite;
554 }
555 if (rcnt > MUSYCC_SR_RETRY_CNT) {
556 pr_warning("%s: failed service request (#%d)= %x, group %d.\n",
557 pi->up->devname, MUSYCC_SR_RETRY_CNT, req, pi->portnum);
558 SD_SEM_GIVE(&pi->sr_sem_busy); /* allow any next request */
559 return;
560 }
561 if (req == SR_CHIP_RESET) {
562 /*
563 * PORT NOTE: the CHIP_RESET command is NOT ack'd by the MUSYCC, thus
564 * the upcoming delay is used. Though the MUSYCC documentation
565 * suggests a read-after-write would supply the required delay, it's
566 * unclear what CPU/BUS clock speeds might have been assumed when
567 * suggesting this 'lack of ACK' workaround. Thus the use of uwait.
568 */
569 OS_uwait(100000, "icard"); /* 100ms */
570 } else {
571 FLUSH_MEM_READ();
572 SD_SEM_TAKE(&pi->sr_sem_wait, "sakack"); /* sleep until SACK
573 * interrupt occurs */
574 }
575 SD_SEM_GIVE(&pi->sr_sem_busy); /* allow any next request */
576 }
577
578
579 #ifdef SBE_PMCC4_ENABLE
580 void
581 musycc_update_timeslots(mpi_t * pi)
582 {
583 int i, ch;
584 char e1mode = IS_FRAME_ANY_E1(pi->p.port_mode);
585
586 for (i = 0; i < 32; i++) {
587 int usedby = 0, last = 0, ts, j, bits[8];
588
589 u_int8_t lastval = 0;
590
591 if (((i == 0) && e1mode) || /* disable if E1 mode */
592 ((i == 16) && ((pi->p.port_mode == CFG_FRAME_E1CRC_CAS) || (pi->p.port_mode == CFG_FRAME_E1CRC_CAS_AMI)))
593 || ((i > 23) && (!e1mode))) /* disable if T1 mode */
594 pi->tsm[i] = 0xff; /* make tslot unavailable for this mode */
595 else
596 pi->tsm[i] = 0x00; /* make tslot available for assignment */
597 for (j = 0; j < 8; j++)
598 bits[j] = -1;
599 for (ch = 0; ch < MUSYCC_NCHANS; ch++) {
600 if ((pi->chan[ch]->state == UP) && (pi->chan[ch]->p.bitmask[i])) {
601 usedby++;
602 last = ch;
603 lastval = pi->chan[ch]->p.bitmask[i];
604 for (j = 0; j < 8; j++)
605 if (lastval & (1 << j))
606 bits[j] = ch;
607 pi->tsm[i] |= lastval;
608 }
609 }
610 if (!usedby)
611 ts = 0;
612 else if ((usedby == 1) && (lastval == 0xff))
613 ts = (4 << 5) | last;
614 else if ((usedby == 1) && (lastval == 0x7f))
615 ts = (5 << 5) | last;
616 else {
617 int idx;
618
619 if (bits[0] < 0)
620 ts = (6 << 5) | (idx = last);
621 else
622 ts = (7 << 5) | (idx = bits[0]);
623 for (j = 1; j < 8; j++) {
624 pi->regram->rscm[idx * 8 + j] = (bits[j] < 0) ? 0 : (0x80 | bits[j]);
625 pi->regram->tscm[idx * 8 + j] = (bits[j] < 0) ? 0 : (0x80 | bits[j]);
626 }
627 }
628 pi->regram->rtsm[i] = ts;
629 pi->regram->ttsm[i] = ts;
630 }
631 FLUSH_MEM_WRITE();
632
633 musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
634 musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_TX_DIRECTION);
635 musycc_serv_req(pi, SR_SUBCHANNEL_MAP | SR_RX_DIRECTION);
636 musycc_serv_req(pi, SR_SUBCHANNEL_MAP | SR_TX_DIRECTION);
637 }
638 #endif
639
640
641 #ifdef SBE_WAN256T3_ENABLE
642 void
643 musycc_update_timeslots(mpi_t * pi)
644 {
645 mch_t *ch;
646
647 u_int8_t ts, hmask, tsen;
648 int gchan;
649 int i;
650
651 #ifdef SBE_PMCC4_ENABLE
652 hmask = (0x1f << pi->up->p.hypersize) & 0x1f;
653 #endif
654 #ifdef SBE_WAN256T3_ENABLE
655 hmask = (0x1f << hyperdummy) & 0x1f;
656 #endif
657 for (i = 0; i < 128; i++) {
658 gchan = ((pi->portnum * MUSYCC_NCHANS) + (i & hmask)) % MUSYCC_NCHANS;
659 ch = pi->chan[gchan];
660 if (ch->p.mode_56k)
661 tsen = MODE_56KBPS;
662 else
663 tsen = MODE_64KBPS; /* also the default */
664 ts = ((pi->portnum % 4) == (i / 32)) ? (tsen << 5) | (i & hmask) : 0;
665 pi->regram->rtsm[i] = ts;
666 pi->regram->ttsm[i] = ts;
667 }
668 FLUSH_MEM_WRITE();
669 musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
670 musycc_serv_req(pi, SR_TIMESLOT_MAP | SR_TX_DIRECTION);
671 }
672 #endif
673
674
675 /*
676 * This routine converts a generic library channel configuration parameter
677 * into a hardware specific register value (IE. MUSYCC CCD Register).
678 */
679 u_int32_t
680 musycc_chan_proto(int proto)
681 {
682 int reg;
683
684 switch (proto) {
685 case CFG_CH_PROTO_TRANS: /* 0 */
686 reg = MUSYCC_CCD_TRANS;
687 break;
688 case CFG_CH_PROTO_SS7: /* 1 */
689 reg = MUSYCC_CCD_SS7;
690 break;
691 default:
692 case CFG_CH_PROTO_ISLP_MODE: /* 4 */
693 case CFG_CH_PROTO_HDLC_FCS16: /* 2 */
694 reg = MUSYCC_CCD_HDLC_FCS16;
695 break;
696 case CFG_CH_PROTO_HDLC_FCS32: /* 3 */
697 reg = MUSYCC_CCD_HDLC_FCS32;
698 break;
699 }
700
701 return reg;
702 }
703
704 #ifdef SBE_WAN256T3_ENABLE
705 STATIC void __init
706 musycc_init_port(mpi_t * pi)
707 {
708 pci_write_32((u_int32_t *) &pi->reg->gbp, OS_vtophys(pi->regram));
709
710 pi->regram->grcd =
711 __constant_cpu_to_le32(MUSYCC_GRCD_RX_ENABLE |
712 MUSYCC_GRCD_TX_ENABLE |
713 MUSYCC_GRCD_SF_ALIGN |
714 MUSYCC_GRCD_SUBCHAN_DISABLE |
715 MUSYCC_GRCD_OOFMP_DISABLE |
716 MUSYCC_GRCD_COFAIRQ_DISABLE |
717 MUSYCC_GRCD_MC_ENABLE |
718 (MUSYCC_GRCD_POLLTH_32 << MUSYCC_GRCD_POLLTH_SHIFT));
719
720 pi->regram->pcd =
721 __constant_cpu_to_le32(MUSYCC_PCD_E1X4_MODE |
722 MUSYCC_PCD_TXDATA_RISING |
723 MUSYCC_PCD_TX_DRIVEN);
724
725 /* Message length descriptor */
726 pi->regram->mld = __constant_cpu_to_le32(cxt1e1_max_mru | (cxt1e1_max_mru << 16));
727 FLUSH_MEM_WRITE();
728
729 musycc_serv_req(pi, SR_GROUP_INIT | SR_RX_DIRECTION);
730 musycc_serv_req(pi, SR_GROUP_INIT | SR_TX_DIRECTION);
731
732 musycc_init_mdt(pi);
733
734 musycc_update_timeslots(pi);
735 }
736 #endif
737
738
739 status_t __init
740 musycc_init(ci_t * ci)
741 {
742 char *regaddr; /* temp for address boundary calculations */
743 int i, gchan;
744
745 OS_sem_init(&ci->sem_wdbusy, SEM_AVAILABLE); /* watchdog exclusion */
746
747 /*
748 * Per MUSYCC manual, Section 6.3.4 - "The host must allocate a dword
749 * aligned memory segment for interrupt queue pointers."
750 */
751
752 #define INT_QUEUE_BOUNDARY 4
753
754 regaddr = OS_kmalloc((INT_QUEUE_SIZE + 1) * sizeof(u_int32_t));
755 if (regaddr == 0)
756 return ENOMEM;
757 ci->iqd_p_saved = regaddr; /* save orig value for free's usage */
758 ci->iqd_p = (u_int32_t *) ((unsigned long) (regaddr + INT_QUEUE_BOUNDARY - 1) &
759 (~(INT_QUEUE_BOUNDARY - 1))); /* this calculates
760 * closest boundary */
761
762 for (i = 0; i < INT_QUEUE_SIZE; i++)
763 ci->iqd_p[i] = __constant_cpu_to_le32(INT_EMPTY_ENTRY);
764
765 for (i = 0; i < ci->max_port; i++) {
766 mpi_t *pi = &ci->port[i];
767
768 /*
769 * Per MUSYCC manual, Section 6.3.2 - "The host must allocate a 2KB
770 * bound memory segment for Channel Group 0."
771 */
772
773 #define GROUP_BOUNDARY 0x800
774
775 regaddr = OS_kmalloc(sizeof(struct musycc_groupr) + GROUP_BOUNDARY);
776 if (regaddr == 0) {
777 for (gchan = 0; gchan < i; gchan++) {
778 pi = &ci->port[gchan];
779 OS_kfree(pi->reg);
780 pi->reg = 0;
781 }
782 return ENOMEM;
783 }
784 pi->regram_saved = regaddr; /* save orig value for free's usage */
785 pi->regram = (struct musycc_groupr *) ((unsigned long) (regaddr + GROUP_BOUNDARY - 1) &
786 (~(GROUP_BOUNDARY - 1))); /* this calculates
787 * closest boundary */
788 }
789
790 /* any board centric MUSYCC commands will use group ZERO as its "home" */
791 ci->regram = ci->port[0].regram;
792 musycc_serv_req(&ci->port[0], SR_CHIP_RESET);
793
794 pci_write_32((u_int32_t *) &ci->reg->gbp, OS_vtophys(ci->regram));
795 pci_flush_write(ci);
796 #ifdef CONFIG_SBE_PMCC4_NCOMM
797 ci->regram->__glcd = __constant_cpu_to_le32(GCD_MAGIC);
798 #else
799 /* standard driver POLLS for INTB via CPLD register */
800 ci->regram->__glcd = __constant_cpu_to_le32(GCD_MAGIC | MUSYCC_GCD_INTB_DISABLE);
801 #endif
802
803 ci->regram->__iqp = cpu_to_le32(OS_vtophys(&ci->iqd_p[0]));
804 ci->regram->__iql = __constant_cpu_to_le32(INT_QUEUE_SIZE - 1);
805 pci_write_32((u_int32_t *) &ci->reg->dacbp, 0);
806 FLUSH_MEM_WRITE();
807
808 ci->state = C_RUNNING; /* mark as full interrupt processing
809 * available */
810
811 musycc_serv_req(&ci->port[0], SR_GLOBAL_INIT); /* FIRST INTERRUPT ! */
812
813 /* sanity check settable parameters */
814
815 if (cxt1e1_max_mru > 0xffe) {
816 pr_warning("Maximum allowed MRU exceeded, resetting %d to %d.\n",
817 cxt1e1_max_mru, 0xffe);
818 cxt1e1_max_mru = 0xffe;
819 }
820 if (cxt1e1_max_mtu > 0xffe) {
821 pr_warning("Maximum allowed MTU exceeded, resetting %d to %d.\n",
822 cxt1e1_max_mtu, 0xffe);
823 cxt1e1_max_mtu = 0xffe;
824 }
825 #ifdef SBE_WAN256T3_ENABLE
826 for (i = 0; i < MUSYCC_NPORTS; i++)
827 musycc_init_port(&ci->port[i]);
828 #endif
829
830 return SBE_DRVR_SUCCESS; /* no error */
831 }
832
833
834 void
835 musycc_bh_tx_eom(mpi_t * pi, int gchan)
836 {
837 mch_t *ch;
838 struct mdesc *md;
839
840 #if 0
841 #ifndef SBE_ISR_INLINE
842 unsigned long flags;
843
844 #endif
845 #endif
846 volatile u_int32_t status;
847
848 ch = pi->chan[gchan];
849 if (ch == 0 || ch->state != UP) {
850 if (cxt1e1_log_level >= LOG_ERROR)
851 pr_info("%s: intr: xmit EOM on uninitialized channel %d\n",
852 pi->up->devname, gchan);
853 }
854 if (ch == 0 || ch->mdt == 0)
855 return; /* note: mdt==0 implies a malloc()
856 * failure w/in chan_up() routine */
857
858 #if 0
859 #ifdef SBE_ISR_INLINE
860 spin_lock_irq(&ch->ch_txlock);
861 #else
862 spin_lock_irqsave(&ch->ch_txlock, flags);
863 #endif
864 #endif
865 do {
866 FLUSH_MEM_READ();
867 md = ch->txd_irq_srv;
868 status = le32_to_cpu(md->status);
869
870 /*
871 * Note: Per MUSYCC Ref 6.4.9, the host does not poll a host-owned
872 * Transmit Buffer Descriptor during Transparent Mode.
873 */
874 if (status & MUSYCC_TX_OWNED) {
875 int readCount, loopCount;
876
877 /***********************************************************/
878 /* HW Bug Fix */
879 /* ---------- */
880 /* Under certain PCI Bus loading conditions, the data */
881 /* associated with an update of Shared Memory is delayed */
882 /* relative to its PCI Interrupt. This is caught when */
883 /* the host determines it does not yet OWN the descriptor. */
884 /***********************************************************/
885
886 readCount = 0;
887 while (status & MUSYCC_TX_OWNED) {
888 for (loopCount = 0; loopCount < 0x30; loopCount++)
889 OS_uwait_dummy(); /* use call to avoid optimization
890 * removal of dummy delay */
891 FLUSH_MEM_READ();
892 status = le32_to_cpu(md->status);
893 if (readCount++ > 40)
894 break; /* don't wait any longer */
895 }
896 if (status & MUSYCC_TX_OWNED) {
897 if (cxt1e1_log_level >= LOG_MONITOR) {
898 pr_info("%s: Port %d Chan %2d - unexpected TX msg ownership intr (md %p sts %x)\n",
899 pi->up->devname, pi->portnum, ch->channum,
900 md, status);
901 pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
902 ch->user, ch->txd_irq_srv, ch->txd_usr_add,
903 sd_queue_stopped(ch->user),
904 ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
905 musycc_dump_txbuffer_ring(ch, 0);
906 }
907 break; /* Not our mdesc, done */
908 } else {
909 if (cxt1e1_log_level >= LOG_MONITOR)
910 pr_info("%s: Port %d Chan %2d - recovered TX msg ownership [%d] (md %p sts %x)\n",
911 pi->up->devname, pi->portnum, ch->channum, readCount, md, status);
912 }
913 }
914 ch->txd_irq_srv = md->snext;
915
916 md->data = 0;
917 if (md->mem_token != 0) {
918 /* upcount channel */
919 atomic_sub(OS_mem_token_tlen(md->mem_token), &ch->tx_pending);
920 /* upcount card */
921 atomic_sub(OS_mem_token_tlen(md->mem_token), &pi->up->tx_pending);
922 #ifdef SBE_WAN256T3_ENABLE
923 if (!atomic_read(&pi->up->tx_pending))
924 wan256t3_led(pi->up, LED_TX, 0);
925 #endif
926
927 #ifdef CONFIG_SBE_WAN256T3_NCOMM
928 /* callback that our packet was sent */
929 {
930 int hdlcnum = (pi->portnum * 32 + gchan);
931
932 if (hdlcnum >= 228) {
933 if (nciProcess_TX_complete)
934 (*nciProcess_TX_complete) (hdlcnum,
935 getuserbychan(gchan));
936 }
937 }
938 #endif /*** CONFIG_SBE_WAN256T3_NCOMM ***/
939
940 OS_mem_token_free_irq(md->mem_token);
941 md->mem_token = 0;
942 }
943 md->status = 0;
944 #ifdef RLD_TXFULL_DEBUG
945 if (cxt1e1_log_level >= LOG_MONITOR2)
946 pr_info("~~ tx_eom: tx_full %x txd_free %d -> %d\n",
947 ch->tx_full, ch->txd_free, ch->txd_free + 1);
948 #endif
949 ++ch->txd_free;
950 FLUSH_MEM_WRITE();
951
952 if ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) && (status & EOBIRQ_ENABLE)) {
953 if (cxt1e1_log_level >= LOG_MONITOR)
954 pr_info("%s: Mode (%x) incorrect EOB status (%x)\n",
955 pi->up->devname, ch->p.chan_mode, status);
956 if ((status & EOMIRQ_ENABLE) == 0)
957 break;
958 }
959 } while ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) && ((status & EOMIRQ_ENABLE) == 0));
960 /*
961 * NOTE: (The above 'while' is coupled w/ previous 'do', way above.) Each
962 * Transparent data buffer has the EOB bit, and NOT the EOM bit, set and
963 * will furthermore have a separate IQD associated with each messages
964 * buffer.
965 */
966
967 FLUSH_MEM_READ();
968 /*
969 * Smooth flow control hysterisis by maintaining task stoppage until half
970 * the available write buffers are available.
971 */
972 if (ch->tx_full && (ch->txd_free >= (ch->txd_num / 2))) {
973 /*
974 * Then, only releave task stoppage if we actually have enough
975 * buffers to service the last requested packet. It may require MORE
976 * than half the available!
977 */
978 if (ch->txd_free >= ch->txd_required) {
979
980 #ifdef RLD_TXFULL_DEBUG
981 if (cxt1e1_log_level >= LOG_MONITOR2)
982 pr_info("tx_eom[%d]: enable xmit tx_full no more, txd_free %d txd_num/2 %d\n",
983 ch->channum,
984 ch->txd_free, ch->txd_num / 2);
985 #endif
986 ch->tx_full = 0;
987 ch->txd_required = 0;
988 sd_enable_xmit(ch->user); /* re-enable to catch flow controlled
989 * channel */
990 }
991 }
992 #ifdef RLD_TXFULL_DEBUG
993 else if (ch->tx_full) {
994 if (cxt1e1_log_level >= LOG_MONITOR2)
995 pr_info("tx_eom[%d]: bypass TX enable though room available? (txd_free %d txd_num/2 %d)\n",
996 ch->channum,
997 ch->txd_free, ch->txd_num / 2);
998 }
999 #endif
1000
1001 FLUSH_MEM_WRITE();
1002 #if 0
1003 #ifdef SBE_ISR_INLINE
1004 spin_unlock_irq(&ch->ch_txlock);
1005 #else
1006 spin_unlock_irqrestore(&ch->ch_txlock, flags);
1007 #endif
1008 #endif
1009 }
1010
1011
1012 STATIC void
1013 musycc_bh_rx_eom(mpi_t * pi, int gchan)
1014 {
1015 mch_t *ch;
1016 void *m, *m2;
1017 struct mdesc *md;
1018 volatile u_int32_t status;
1019 u_int32_t error;
1020
1021 ch = pi->chan[gchan];
1022 if (ch == 0 || ch->state != UP) {
1023 if (cxt1e1_log_level > LOG_ERROR)
1024 pr_info("%s: intr: receive EOM on uninitialized channel %d\n",
1025 pi->up->devname, gchan);
1026 return;
1027 }
1028 if (ch->mdr == 0)
1029 return; /* can this happen ? */
1030
1031 for (;;) {
1032 FLUSH_MEM_READ();
1033 md = &ch->mdr[ch->rxix_irq_srv];
1034 status = le32_to_cpu(md->status);
1035 if (!(status & HOST_RX_OWNED))
1036 break; /* Not our mdesc, done */
1037 m = md->mem_token;
1038 error = (status >> 16) & 0xf;
1039 if (error == 0) {
1040 #ifdef CONFIG_SBE_WAN256T3_NCOMM
1041 int hdlcnum = (pi->portnum * 32 + gchan);
1042
1043 /*
1044 * if the packet number belongs to NCOMM, then send it to the TMS
1045 * driver
1046 */
1047 if (hdlcnum >= 228) {
1048 if (nciProcess_RX_packet)
1049 (*nciProcess_RX_packet) (hdlcnum, status & 0x3fff, m, ch->user);
1050 } else
1051 #endif /*** CONFIG_SBE_WAN256T3_NCOMM ***/
1052
1053 {
1054 if ((m2 = OS_mem_token_alloc(cxt1e1_max_mru))) {
1055 /* substitute the mbuf+cluster */
1056 md->mem_token = m2;
1057 md->data = cpu_to_le32(OS_vtophys(OS_mem_token_data(m2)));
1058
1059 /* pass the received mbuf upward */
1060 sd_recv_consume(m, status & LENGTH_MASK, ch->user);
1061 ch->s.rx_packets++;
1062 ch->s.rx_bytes += status & LENGTH_MASK;
1063 } else
1064 ch->s.rx_dropped++;
1065 }
1066 } else if (error == ERR_FCS)
1067 ch->s.rx_crc_errors++;
1068 else if (error == ERR_ALIGN)
1069 ch->s.rx_missed_errors++;
1070 else if (error == ERR_ABT)
1071 ch->s.rx_missed_errors++;
1072 else if (error == ERR_LNG)
1073 ch->s.rx_length_errors++;
1074 else if (error == ERR_SHT)
1075 ch->s.rx_length_errors++;
1076 FLUSH_MEM_WRITE();
1077 status = cxt1e1_max_mru;
1078 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1079 status |= EOBIRQ_ENABLE;
1080 md->status = cpu_to_le32(status);
1081
1082 /* Check next mdesc in the ring */
1083 if (++ch->rxix_irq_srv >= ch->rxd_num)
1084 ch->rxix_irq_srv = 0;
1085 FLUSH_MEM_WRITE();
1086 }
1087 }
1088
1089
1090 irqreturn_t
1091 musycc_intr_th_handler(void *devp)
1092 {
1093 ci_t *ci = (ci_t *) devp;
1094 volatile u_int32_t status, currInt = 0;
1095 u_int32_t nextInt, intCnt;
1096
1097 /*
1098 * Hardware not available, potential interrupt hang. But since interrupt
1099 * might be shared, just return.
1100 */
1101 if (ci->state == C_INIT)
1102 return IRQ_NONE;
1103 /*
1104 * Marked as hardware available. Don't service interrupts, just clear the
1105 * event.
1106 */
1107
1108 if (ci->state == C_IDLE) {
1109 status = pci_read_32((u_int32_t *) &ci->reg->isd);
1110
1111 /* clear the interrupt but process nothing else */
1112 pci_write_32((u_int32_t *) &ci->reg->isd, status);
1113 return IRQ_HANDLED;
1114 }
1115 FLUSH_PCI_READ();
1116 FLUSH_MEM_READ();
1117
1118 status = pci_read_32((u_int32_t *) &ci->reg->isd);
1119 nextInt = INTRPTS_NEXTINT(status);
1120 intCnt = INTRPTS_INTCNT(status);
1121 ci->intlog.drvr_intr_thcount++;
1122
1123 /*********************************************************/
1124 /* HW Bug Fix */
1125 /* ---------- */
1126 /* Under certain PCI Bus loading conditions, the */
1127 /* MUSYCC looses the data associated with an update */
1128 /* of its ISD and erroneously returns the immediately */
1129 /* preceding 'nextInt' value. However, the 'intCnt' */
1130 /* value appears to be correct. By not starting service */
1131 /* where the 'missing' 'nextInt' SHOULD point causes */
1132 /* the IQD not to be serviced - the 'not serviced' */
1133 /* entries then remain and continue to increase as more */
1134 /* incorrect ISD's are encountered. */
1135 /*********************************************************/
1136
1137 if (nextInt != INTRPTS_NEXTINT(ci->intlog.this_status_new)) {
1138 if (cxt1e1_log_level >= LOG_MONITOR) {
1139 pr_info("%s: note - updated ISD from %08x to %08x\n",
1140 ci->devname, status,
1141 (status & (~INTRPTS_NEXTINT_M)) | ci->intlog.this_status_new);
1142 }
1143 /*
1144 * Replace bogus status with software corrected value.
1145 *
1146 * It's not known whether, during this problem occurrence, if the
1147 * INTFULL bit is correctly reported or not.
1148 */
1149 status = (status & (~INTRPTS_NEXTINT_M)) | (ci->intlog.this_status_new);
1150 nextInt = INTRPTS_NEXTINT(status);
1151 }
1152 /**********************************************/
1153 /* Cn847x Bug Fix */
1154 /* -------------- */
1155 /* Fix for inability to write back same index */
1156 /* as read for a full interrupt queue. */
1157 /**********************************************/
1158
1159 if (intCnt == INT_QUEUE_SIZE)
1160 currInt = ((intCnt - 1) + nextInt) & (INT_QUEUE_SIZE - 1);
1161 else
1162 /************************************************/
1163 /* Interrupt Write Location Issues */
1164 /* ------------------------------- */
1165 /* When the interrupt status descriptor is */
1166 /* written, the interrupt line is de-asserted */
1167 /* by the Cn847x. In the case of MIPS */
1168 /* microprocessors, this must occur at the */
1169 /* beginning of the interrupt handler so that */
1170 /* the interrupt handle is not re-entered due */
1171 /* to interrupt dis-assertion latency. */
1172 /* In the case of all other processors, this */
1173 /* action should occur at the end of the */
1174 /* interrupt handler to avoid overwriting the */
1175 /* interrupt queue. */
1176 /************************************************/
1177
1178 if (intCnt)
1179 currInt = (intCnt + nextInt) & (INT_QUEUE_SIZE - 1);
1180 else {
1181 /*
1182 * NOTE: Servicing an interrupt whose ISD contains a count of ZERO
1183 * can be indicative of a Shared Interrupt chain. Our driver can be
1184 * called from the system's interrupt handler as a matter of the OS
1185 * walking the chain. As the chain is walked, the interrupt will
1186 * eventually be serviced by the correct driver/handler.
1187 */
1188 #if 0
1189 /* chained interrupt = not ours */
1190 pr_info(">> %s: intCnt NULL, sts %x, possibly a chained interrupt!\n",
1191 ci->devname, status);
1192 #endif
1193 return IRQ_NONE;
1194 }
1195
1196 ci->iqp_tailx = currInt;
1197
1198 currInt <<= INTRPTS_NEXTINT_S;
1199 ci->intlog.last_status_new = ci->intlog.this_status_new;
1200 ci->intlog.this_status_new = currInt;
1201
1202 if ((cxt1e1_log_level >= LOG_WARN) && (status & INTRPTS_INTFULL_M))
1203 pr_info("%s: Interrupt queue full condition occurred\n", ci->devname);
1204 if (cxt1e1_log_level >= LOG_DEBUG)
1205 pr_info("%s: interrupts pending, isd @ 0x%p: %x curr %d cnt %d NEXT %d\n",
1206 ci->devname, &ci->reg->isd,
1207 status, nextInt, intCnt, (intCnt + nextInt) & (INT_QUEUE_SIZE - 1));
1208
1209 FLUSH_MEM_WRITE();
1210 #if defined(SBE_ISR_TASKLET)
1211 pci_write_32((u_int32_t *) &ci->reg->isd, currInt);
1212 atomic_inc(&ci->bh_pending);
1213 tasklet_schedule(&ci->ci_musycc_isr_tasklet);
1214 #elif defined(SBE_ISR_IMMEDIATE)
1215 pci_write_32((u_int32_t *) &ci->reg->isd, currInt);
1216 atomic_inc(&ci->bh_pending);
1217 queue_task(&ci->ci_musycc_isr_tq, &tq_immediate);
1218 mark_bh(IMMEDIATE_BH);
1219 #elif defined(SBE_ISR_INLINE)
1220 (void) musycc_intr_bh_tasklet(ci);
1221 pci_write_32((u_int32_t *) &ci->reg->isd, currInt);
1222 #endif
1223 return IRQ_HANDLED;
1224 }
1225
1226
1227 #if defined(SBE_ISR_IMMEDIATE)
1228 unsigned long
1229 #else
1230 void
1231 #endif
1232 musycc_intr_bh_tasklet(ci_t * ci)
1233 {
1234 mpi_t *pi;
1235 mch_t *ch;
1236 unsigned int intCnt;
1237 volatile u_int32_t currInt = 0;
1238 volatile unsigned int headx, tailx;
1239 int readCount, loopCount;
1240 int group, gchan, event, err, tx;
1241 u_int32_t badInt = INT_EMPTY_ENTRY;
1242 u_int32_t badInt2 = INT_EMPTY_ENTRY2;
1243
1244 /*
1245 * Hardware not available, potential interrupt hang. But since interrupt
1246 * might be shared, just return.
1247 */
1248 if ((drvr_state != SBE_DRVR_AVAILABLE) || (ci->state == C_INIT)) {
1249 #if defined(SBE_ISR_IMMEDIATE)
1250 return 0L;
1251 #else
1252 return;
1253 #endif
1254 }
1255 #if defined(SBE_ISR_TASKLET) || defined(SBE_ISR_IMMEDIATE)
1256 if (drvr_state != SBE_DRVR_AVAILABLE) {
1257 #if defined(SBE_ISR_TASKLET)
1258 return;
1259 #elif defined(SBE_ISR_IMMEDIATE)
1260 return 0L;
1261 #endif
1262 }
1263 #elif defined(SBE_ISR_INLINE)
1264 /* no semaphore taken, no double checks */
1265 #endif
1266
1267 ci->intlog.drvr_intr_bhcount++;
1268 FLUSH_MEM_READ();
1269 {
1270 unsigned int bh = atomic_read(&ci->bh_pending);
1271
1272 max_bh = max(bh, max_bh);
1273 }
1274 atomic_set(&ci->bh_pending, 0);/* if here, no longer pending */
1275 while ((headx = ci->iqp_headx) != (tailx = ci->iqp_tailx)) {
1276 intCnt = (tailx >= headx) ? (tailx - headx) : (tailx - headx + INT_QUEUE_SIZE);
1277 currInt = le32_to_cpu(ci->iqd_p[headx]);
1278
1279 max_intcnt = max(intCnt, max_intcnt); /* RLD DEBUG */
1280
1281 /**************************************************/
1282 /* HW Bug Fix */
1283 /* ---------- */
1284 /* The following code checks for the condition */
1285 /* of interrupt assertion before interrupt */
1286 /* queue update. This is a problem on several */
1287 /* PCI-Local bridge chips found on some products. */
1288 /**************************************************/
1289
1290 readCount = 0;
1291 if ((currInt == badInt) || (currInt == badInt2))
1292 ci->intlog.drvr_int_failure++;
1293
1294 while ((currInt == badInt) || (currInt == badInt2)) {
1295 for (loopCount = 0; loopCount < 0x30; loopCount++)
1296 OS_uwait_dummy(); /* use call to avoid optimization removal
1297 * of dummy delay */
1298 FLUSH_MEM_READ();
1299 currInt = le32_to_cpu(ci->iqd_p[headx]);
1300 if (readCount++ > 20)
1301 break;
1302 }
1303
1304 if ((currInt == badInt) || (currInt == badInt2)) { /* catch failure of Bug
1305 * Fix checking */
1306 if (cxt1e1_log_level >= LOG_WARN)
1307 pr_info("%s: Illegal Interrupt Detected @ 0x%p, mod %d.)\n",
1308 ci->devname, &ci->iqd_p[headx], headx);
1309
1310 /*
1311 * If the descriptor has not recovered, then leaving the EMPTY
1312 * entry set will not signal to the MUSYCC that this descriptor
1313 * has been serviced. The Interrupt Queue can then start losing
1314 * available descriptors and MUSYCC eventually encounters and
1315 * reports the INTFULL condition. Per manual, changing any bit
1316 * marks descriptor as available, thus the use of different
1317 * EMPTY_ENTRY values.
1318 */
1319
1320 if (currInt == badInt)
1321 ci->iqd_p[headx] = __constant_cpu_to_le32(INT_EMPTY_ENTRY2);
1322 else
1323 ci->iqd_p[headx] = __constant_cpu_to_le32(INT_EMPTY_ENTRY);
1324 ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1); /* insure wrapness */
1325 FLUSH_MEM_WRITE();
1326 FLUSH_MEM_READ();
1327 continue;
1328 }
1329 group = INTRPT_GRP(currInt);
1330 gchan = INTRPT_CH(currInt);
1331 event = INTRPT_EVENT(currInt);
1332 err = INTRPT_ERROR(currInt);
1333 tx = currInt & INTRPT_DIR_M;
1334
1335 ci->iqd_p[headx] = __constant_cpu_to_le32(INT_EMPTY_ENTRY);
1336 FLUSH_MEM_WRITE();
1337
1338 if (cxt1e1_log_level >= LOG_DEBUG) {
1339 if (err != 0)
1340 pr_info(" %08x -> err: %2d,", currInt, err);
1341
1342 pr_info("+ interrupt event: %d, grp: %d, chan: %2d, side: %cX\n",
1343 event, group, gchan, tx ? 'T' : 'R');
1344 }
1345 pi = &ci->port[group]; /* notice that here we assume 1-1 group -
1346 * port mapping */
1347 ch = pi->chan[gchan];
1348 switch (event) {
1349 case EVE_SACK: /* Service Request Acknowledge */
1350 if (cxt1e1_log_level >= LOG_DEBUG) {
1351 volatile u_int32_t r;
1352
1353 r = pci_read_32((u_int32_t *) &pi->reg->srd);
1354 pr_info("- SACK cmd: %08x (hdw= %08x)\n", pi->sr_last, r);
1355 }
1356 SD_SEM_GIVE(&pi->sr_sem_wait); /* wake up waiting process */
1357 break;
1358 case EVE_CHABT: /* Change To Abort Code (0x7e -> 0xff) */
1359 case EVE_CHIC: /* Change To Idle Code (0xff -> 0x7e) */
1360 break;
1361 case EVE_EOM: /* End Of Message */
1362 case EVE_EOB: /* End Of Buffer (Transparent mode) */
1363 if (tx)
1364 musycc_bh_tx_eom(pi, gchan);
1365 else
1366 musycc_bh_rx_eom(pi, gchan);
1367 #if 0
1368 break;
1369 #else
1370 /*
1371 * MUSYCC Interrupt Descriptor section states that EOB and EOM
1372 * can be combined with the NONE error (as well as others). So
1373 * drop thru to catch this...
1374 */
1375 #endif
1376 case EVE_NONE:
1377 if (err == ERR_SHT)
1378 ch->s.rx_length_errors++;
1379 break;
1380 default:
1381 if (cxt1e1_log_level >= LOG_WARN)
1382 pr_info("%s: unexpected interrupt event: %d, iqd[%d]: %08x, port: %d\n", ci->devname,
1383 event, headx, currInt, group);
1384 break;
1385 } /* switch on event */
1386
1387
1388 /*
1389 * Per MUSYCC Manual, Section 6.4.8.3 [Transmit Errors], TX errors
1390 * are service-affecting and require action to resume normal
1391 * bit-level processing.
1392 */
1393
1394 switch (err) {
1395 case ERR_ONR:
1396 /*
1397 * Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors], this
1398 * error requires Transmit channel reactivation.
1399 *
1400 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], this error
1401 * requires Receive channel reactivation.
1402 */
1403 if (tx) {
1404
1405 /*
1406 * TX ONR Error only occurs when channel is configured for
1407 * Transparent Mode. However, this code will catch and
1408 * re-activate on ANY TX ONR error.
1409 */
1410
1411 /*
1412 * Set flag to re-enable on any next transmit attempt.
1413 */
1414 ch->ch_start_tx = CH_START_TX_ONR;
1415
1416 {
1417 #ifdef RLD_TRANS_DEBUG
1418 if (1 || cxt1e1_log_level >= LOG_MONITOR)
1419 #else
1420 if (cxt1e1_log_level >= LOG_MONITOR)
1421 #endif
1422 {
1423 pr_info("%s: TX buffer underflow [ONR] on channel %d, mode %x QStopped %x free %d\n",
1424 ci->devname, ch->channum, ch->p.chan_mode, sd_queue_stopped(ch->user), ch->txd_free);
1425 #ifdef RLD_DEBUG
1426 if (ch->p.chan_mode == 2) { /* problem = ONR on HDLC
1427 * mode */
1428 pr_info("++ Failed Last %x Next %x QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
1429 (u_int32_t) ch->txd_irq_srv, (u_int32_t) ch->txd_usr_add,
1430 sd_queue_stopped(ch->user),
1431 ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
1432 musycc_dump_txbuffer_ring(ch, 0);
1433 }
1434 #endif
1435 }
1436 }
1437 } else { /* RX buffer overrun */
1438 /*
1439 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors],
1440 * channel recovery for this RX ONR error IS required. It is
1441 * also suggested to increase the number of receive buffers
1442 * for this channel. Receive channel reactivation IS
1443 * required, and data has been lost.
1444 */
1445 ch->s.rx_over_errors++;
1446 ch->ch_start_rx = CH_START_RX_ONR;
1447
1448 if (cxt1e1_log_level >= LOG_WARN) {
1449 pr_info("%s: RX buffer overflow [ONR] on channel %d, mode %x\n",
1450 ci->devname, ch->channum, ch->p.chan_mode);
1451 //musycc_dump_rxbuffer_ring (ch, 0); /* RLD DEBUG */
1452 }
1453 }
1454 musycc_chan_restart(ch);
1455 break;
1456 case ERR_BUF:
1457 if (tx) {
1458 ch->s.tx_fifo_errors++;
1459 ch->ch_start_tx = CH_START_TX_BUF;
1460 /*
1461 * Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors],
1462 * this BUFF error requires Transmit channel reactivation.
1463 */
1464 if (cxt1e1_log_level >= LOG_MONITOR)
1465 pr_info("%s: TX buffer underrun [BUFF] on channel %d, mode %x\n",
1466 ci->devname, ch->channum, ch->p.chan_mode);
1467 } else { /* RX buffer overrun */
1468 ch->s.rx_over_errors++;
1469 /*
1470 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], HDLC
1471 * mode requires NO recovery for this RX BUFF error is
1472 * required. It is suggested to increase the FIFO buffer
1473 * space for this channel. Receive channel reactivation is
1474 * not required, but data has been lost.
1475 */
1476 if (cxt1e1_log_level >= LOG_WARN)
1477 pr_info("%s: RX buffer overrun [BUFF] on channel %d, mode %x\n",
1478 ci->devname, ch->channum, ch->p.chan_mode);
1479 /*
1480 * Per MUSYCC manual, Section 6.4.9.4 [Receive Errors],
1481 * Transparent mode DOES require recovery for the RX BUFF
1482 * error. It is suggested to increase the FIFO buffer space
1483 * for this channel. Receive channel reactivation IS
1484 * required and data has been lost.
1485 */
1486 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1487 ch->ch_start_rx = CH_START_RX_BUF;
1488 }
1489
1490 if (tx || (ch->p.chan_mode == CFG_CH_PROTO_TRANS))
1491 musycc_chan_restart(ch);
1492 break;
1493 default:
1494 break;
1495 } /* switch on err */
1496
1497 /* Check for interrupt lost condition */
1498 if ((currInt & INTRPT_ILOST_M) && (cxt1e1_log_level >= LOG_ERROR))
1499 pr_info("%s: Interrupt queue overflow - ILOST asserted\n",
1500 ci->devname);
1501 ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1); /* insure wrapness */
1502 FLUSH_MEM_WRITE();
1503 FLUSH_MEM_READ();
1504 } /* while */
1505 if ((cxt1e1_log_level >= LOG_MONITOR2) && (ci->iqp_headx != ci->iqp_tailx)) {
1506 int bh;
1507
1508 bh = atomic_read(&CI->bh_pending);
1509 pr_info("_bh_: late arrivals, head %d != tail %d, pending %d\n",
1510 ci->iqp_headx, ci->iqp_tailx, bh);
1511 }
1512 #if defined(SBE_ISR_IMMEDIATE)
1513 return 0L;
1514 #endif
1515 /* else, nothing returned */
1516 }
1517
1518 #if 0
1519 int __init
1520 musycc_new_chan(ci_t * ci, int channum, void *user)
1521 {
1522 mch_t *ch;
1523
1524 ch = ci->port[channum / MUSYCC_NCHANS].chan[channum % MUSYCC_NCHANS];
1525
1526 if (ch->state != UNASSIGNED)
1527 return EEXIST;
1528 /* NOTE: mch_t already cleared during OS_kmalloc() */
1529 ch->state = DOWN;
1530 ch->user = user;
1531 #if 0
1532 ch->status = 0;
1533 ch->p.status = 0;
1534 ch->p.intr_mask = 0;
1535 #endif
1536 ch->p.chan_mode = CFG_CH_PROTO_HDLC_FCS16;
1537 ch->p.idlecode = CFG_CH_FLAG_7E;
1538 ch->p.pad_fill_count = 2;
1539 spin_lock_init(&ch->ch_rxlock);
1540 spin_lock_init(&ch->ch_txlock);
1541
1542 return 0;
1543 }
1544 #endif
1545
1546
1547 #ifdef SBE_PMCC4_ENABLE
1548 status_t
1549 musycc_chan_down(ci_t * dummy, int channum)
1550 {
1551 mpi_t *pi;
1552 mch_t *ch;
1553 int i, gchan;
1554
1555 if (!(ch = sd_find_chan(dummy, channum)))
1556 return EINVAL;
1557 pi = ch->up;
1558 gchan = ch->gchan;
1559
1560 /* Deactivate the channel */
1561 musycc_serv_req(pi, SR_CHANNEL_DEACTIVATE | SR_RX_DIRECTION | gchan);
1562 ch->ch_start_rx = 0;
1563 musycc_serv_req(pi, SR_CHANNEL_DEACTIVATE | SR_TX_DIRECTION | gchan);
1564 ch->ch_start_tx = 0;
1565
1566 if (ch->state == DOWN)
1567 return 0;
1568 ch->state = DOWN;
1569
1570 pi->regram->thp[gchan] = 0;
1571 pi->regram->tmp[gchan] = 0;
1572 pi->regram->rhp[gchan] = 0;
1573 pi->regram->rmp[gchan] = 0;
1574 FLUSH_MEM_WRITE();
1575 for (i = 0; i < ch->txd_num; i++)
1576 if (ch->mdt[i].mem_token != 0)
1577 OS_mem_token_free(ch->mdt[i].mem_token);
1578
1579 for (i = 0; i < ch->rxd_num; i++)
1580 if (ch->mdr[i].mem_token != 0)
1581 OS_mem_token_free(ch->mdr[i].mem_token);
1582
1583 OS_kfree(ch->mdr);
1584 ch->mdr = 0;
1585 ch->rxd_num = 0;
1586 OS_kfree(ch->mdt);
1587 ch->mdt = 0;
1588 ch->txd_num = 0;
1589
1590 musycc_update_timeslots(pi);
1591 c4_fifo_free(pi, ch->gchan);
1592
1593 pi->openchans--;
1594 return 0;
1595 }
1596 #endif
1597
1598
1599 int
1600 musycc_del_chan(ci_t * ci, int channum)
1601 {
1602 mch_t *ch;
1603
1604 if ((channum < 0) || (channum >= (MUSYCC_NPORTS * MUSYCC_NCHANS))) /* sanity chk param */
1605 return ECHRNG;
1606 if (!(ch = sd_find_chan(ci, channum)))
1607 return ENOENT;
1608 if (ch->state == UP)
1609 musycc_chan_down(ci, channum);
1610 ch->state = UNASSIGNED;
1611 return 0;
1612 }
1613
1614
1615 int
1616 musycc_del_chan_stats(ci_t * ci, int channum)
1617 {
1618 mch_t *ch;
1619
1620 if (channum < 0 || channum >= (MUSYCC_NPORTS * MUSYCC_NCHANS)) /* sanity chk param */
1621 return ECHRNG;
1622 if (!(ch = sd_find_chan(ci, channum)))
1623 return ENOENT;
1624
1625 memset(&ch->s, 0, sizeof(struct sbecom_chan_stats));
1626 return 0;
1627 }
1628
1629
1630 int
1631 musycc_start_xmit(ci_t * ci, int channum, void *mem_token)
1632 {
1633 mch_t *ch;
1634 struct mdesc *md;
1635 void *m2;
1636 #if 0
1637 unsigned long flags;
1638 #endif
1639 int txd_need_cnt;
1640 u_int32_t len;
1641
1642 if (!(ch = sd_find_chan(ci, channum)))
1643 return -ENOENT;
1644
1645 if (ci->state != C_RUNNING) /* full interrupt processing available */
1646 return -EINVAL;
1647 if (ch->state != UP)
1648 return -EINVAL;
1649
1650 if (!(ch->status & TX_ENABLED))
1651 return -EROFS; /* how else to flag unwritable state ? */
1652
1653 #ifdef RLD_TRANS_DEBUGx
1654 if (1 || cxt1e1_log_level >= LOG_MONITOR2)
1655 #else
1656 if (cxt1e1_log_level >= LOG_MONITOR2)
1657 #endif
1658 {
1659 pr_info("++ start_xmt[%d]: state %x start %x full %d free %d required %d stopped %x\n",
1660 channum, ch->state, ch->ch_start_tx, ch->tx_full,
1661 ch->txd_free, ch->txd_required, sd_queue_stopped(ch->user));
1662 }
1663 /***********************************************/
1664 /** Determine total amount of data to be sent **/
1665 /***********************************************/
1666 m2 = mem_token;
1667 txd_need_cnt = 0;
1668 for (len = OS_mem_token_tlen(m2); len > 0;
1669 m2 = (void *) OS_mem_token_next(m2)) {
1670 if (!OS_mem_token_len(m2))
1671 continue;
1672 txd_need_cnt++;
1673 len -= OS_mem_token_len(m2);
1674 }
1675
1676 if (txd_need_cnt == 0) {
1677 if (cxt1e1_log_level >= LOG_MONITOR2)
1678 pr_info("%s channel %d: no TX data in User buffer\n", ci->devname, channum);
1679 OS_mem_token_free(mem_token);
1680 return 0; /* no data to send */
1681 }
1682 /*************************************************/
1683 /** Are there sufficient descriptors available? **/
1684 /*************************************************/
1685 if (txd_need_cnt > ch->txd_num) { /* never enough descriptors for this
1686 * large a buffer */
1687 if (cxt1e1_log_level >= LOG_DEBUG)
1688 pr_info("start_xmit: discarding buffer, insufficient descriptor cnt %d, need %d.\n",
1689 ch->txd_num, txd_need_cnt + 1);
1690 ch->s.tx_dropped++;
1691 OS_mem_token_free(mem_token);
1692 return 0;
1693 }
1694 #if 0
1695 spin_lock_irqsave(&ch->ch_txlock, flags);
1696 #endif
1697 /************************************************************/
1698 /** flow control the line if not enough descriptors remain **/
1699 /************************************************************/
1700 if (txd_need_cnt > ch->txd_free) {
1701 if (cxt1e1_log_level >= LOG_MONITOR2)
1702 pr_info("start_xmit[%d]: EBUSY - need more descriptors, have %d of %d need %d\n",
1703 channum, ch->txd_free, ch->txd_num, txd_need_cnt);
1704 ch->tx_full = 1;
1705 ch->txd_required = txd_need_cnt;
1706 sd_disable_xmit(ch->user);
1707 #if 0
1708 spin_unlock_irqrestore(&ch->ch_txlock, flags);
1709 #endif
1710 return -EBUSY; /* tell user to try again later */
1711 }
1712 /**************************************************/
1713 /** Put the user data into MUSYCC data buffer(s) **/
1714 /**************************************************/
1715 m2 = mem_token;
1716 md = ch->txd_usr_add; /* get current available descriptor */
1717
1718 for (len = OS_mem_token_tlen(m2); len > 0; m2 = OS_mem_token_next(m2)) {
1719 int u = OS_mem_token_len(m2);
1720
1721 if (!u)
1722 continue;
1723 len -= u;
1724
1725 /*
1726 * Enable following chunks, yet wait to enable the FIRST chunk until
1727 * after ALL subsequent chunks are setup.
1728 */
1729 if (md != ch->txd_usr_add) /* not first chunk */
1730 u |= MUSYCC_TX_OWNED; /* transfer ownership from HOST to MUSYCC */
1731
1732 if (len) /* not last chunk */
1733 u |= EOBIRQ_ENABLE;
1734 else if (ch->p.chan_mode == CFG_CH_PROTO_TRANS) {
1735 /*
1736 * Per MUSYCC Ref 6.4.9 for Transparent Mode, the host must
1737 * always clear EOMIRQ_ENABLE in every Transmit Buffer Descriptor
1738 * (IE. don't set herein).
1739 */
1740 u |= EOBIRQ_ENABLE;
1741 } else
1742 u |= EOMIRQ_ENABLE; /* EOM, last HDLC chunk */
1743
1744
1745 /* last chunk in hdlc mode */
1746 u |= (ch->p.idlecode << IDLE_CODE);
1747 if (ch->p.pad_fill_count) {
1748 #if 0
1749 /* NOOP NOTE: u_int8_t cannot be > 0xFF */
1750 /* sanitize pad_fill_count for maximums allowed by hardware */
1751 if (ch->p.pad_fill_count > EXTRA_FLAGS_MASK)
1752 ch->p.pad_fill_count = EXTRA_FLAGS_MASK;
1753 #endif
1754 u |= (PADFILL_ENABLE | (ch->p.pad_fill_count << EXTRA_FLAGS));
1755 }
1756 md->mem_token = len ? 0 : mem_token; /* Fill in mds on last
1757 * segment, others set ZERO
1758 * so that entire token is
1759 * removed ONLY when ALL
1760 * segments have been
1761 * transmitted. */
1762
1763 md->data = cpu_to_le32(OS_vtophys(OS_mem_token_data(m2)));
1764 FLUSH_MEM_WRITE();
1765 md->status = cpu_to_le32(u);
1766 --ch->txd_free;
1767 md = md->snext;
1768 }
1769 FLUSH_MEM_WRITE();
1770
1771
1772 /*
1773 * Now transfer ownership of first chunk from HOST to MUSYCC in order to
1774 * fire-off this XMIT.
1775 */
1776 ch->txd_usr_add->status |= __constant_cpu_to_le32(MUSYCC_TX_OWNED);
1777 FLUSH_MEM_WRITE();
1778 ch->txd_usr_add = md;
1779
1780 len = OS_mem_token_tlen(mem_token);
1781 atomic_add(len, &ch->tx_pending);
1782 atomic_add(len, &ci->tx_pending);
1783 ch->s.tx_packets++;
1784 ch->s.tx_bytes += len;
1785 /*
1786 * If an ONR was seen, then channel requires poking to restart
1787 * transmission.
1788 */
1789 if (ch->ch_start_tx)
1790 musycc_chan_restart(ch);
1791 #ifdef SBE_WAN256T3_ENABLE
1792 wan256t3_led(ci, LED_TX, LEDV_G);
1793 #endif
1794 return 0;
1795 }
1796
1797
1798 /*** End-of-File ***/
Linux with added FPC-III support