drivers/net/cxgb3/common.h

   1 /*
   2  * Copyright (c) 2005-2007 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef __CHELSIO_COMMON_H
  33 #define __CHELSIO_COMMON_H
  34
  35 #include <linux/kernel.h>
  36 #include <linux/types.h>
  37 #include <linux/ctype.h>
  38 #include <linux/delay.h>
  39 #include <linux/init.h>
  40 #include <linux/netdevice.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/mii.h>
  43 #include "version.h"
  44
  45 #define CH_ERR(adap, fmt, ...)   dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__)
  46 #define CH_WARN(adap, fmt, ...)  dev_warn(&adap->pdev->dev, fmt, ## __VA_ARGS__)
  47 #define CH_ALERT(adap, fmt, ...) \
  48         dev_printk(KERN_ALERT, &adap->pdev->dev, fmt, ## __VA_ARGS__)
  49
  50 /*
  51  * More powerful macro that selectively prints messages based on msg_enable.
  52  * For info and debugging messages.
  53  */
  54 #define CH_MSG(adapter, level, category, fmt, ...) do { \
  55         if ((adapter)->msg_enable & NETIF_MSG_##category) \
  56                 dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \
  57                            ## __VA_ARGS__); \
  58 } while (0)
  59
  60 #ifdef DEBUG
  61 # define CH_DBG(adapter, category, fmt, ...) \
  62         CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
  63 #else
  64 # define CH_DBG(adapter, category, fmt, ...)
  65 #endif
  66
  67 /* Additional NETIF_MSG_* categories */
  68 #define NETIF_MSG_MMIO 0x8000000
  69
  70 struct t3_rx_mode {
  71         struct net_device *dev;
  72         struct dev_mc_list *mclist;
  73         unsigned int idx;
  74 };
  75
  76 static inline void init_rx_mode(struct t3_rx_mode *p, struct net_device *dev,
  77                                 struct dev_mc_list *mclist)
  78 {
  79         p->dev = dev;
  80         p->mclist = mclist;
  81         p->idx = 0;
  82 }
  83
  84 static inline u8 *t3_get_next_mcaddr(struct t3_rx_mode *rm)
  85 {
  86         u8 *addr = NULL;
  87
  88         if (rm->mclist && rm->idx < rm->dev->mc_count) {
  89                 addr = rm->mclist->dmi_addr;
  90                 rm->mclist = rm->mclist->next;
  91                 rm->idx++;
  92         }
  93         return addr;
  94 }
  95
  96 enum {
  97         MAX_NPORTS = 2,         /* max # of ports */
  98         MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */
  99         EEPROMSIZE = 8192,      /* Serial EEPROM size */
 100         RSS_TABLE_SIZE = 64,    /* size of RSS lookup and mapping tables */
 101         TCB_SIZE = 128,         /* TCB size */
 102         NMTUS = 16,             /* size of MTU table */
 103         NCCTRL_WIN = 32,        /* # of congestion control windows */
 104 };
 105
 106 #define MAX_RX_COALESCING_LEN 16224U
 107
 108 enum {
 109         PAUSE_RX = 1 << 0,
 110         PAUSE_TX = 1 << 1,
 111         PAUSE_AUTONEG = 1 << 2
 112 };
 113
 114 enum {
 115         SUPPORTED_IRQ      = 1 << 24
 116 };
 117
 118 enum {                          /* adapter interrupt-maintained statistics */
 119         STAT_ULP_CH0_PBL_OOB,
 120         STAT_ULP_CH1_PBL_OOB,
 121         STAT_PCI_CORR_ECC,
 122
 123         IRQ_NUM_STATS           /* keep last */
 124 };
 125
 126 enum {
 127         SGE_QSETS = 8,          /* # of SGE Tx/Rx/RspQ sets */
 128         SGE_RXQ_PER_SET = 2,    /* # of Rx queues per set */
 129         SGE_TXQ_PER_SET = 3     /* # of Tx queues per set */
 130 };
 131
 132 enum sge_context_type {         /* SGE egress context types */
 133         SGE_CNTXT_RDMA = 0,
 134         SGE_CNTXT_ETH = 2,
 135         SGE_CNTXT_OFLD = 4,
 136         SGE_CNTXT_CTRL = 5
 137 };
 138
 139 enum {
 140         AN_PKT_SIZE = 32,       /* async notification packet size */
 141         IMMED_PKT_SIZE = 48     /* packet size for immediate data */
 142 };
 143
 144 struct sg_ent {                 /* SGE scatter/gather entry */
 145         u32 len[2];
 146         u64 addr[2];
 147 };
 148
 149 #ifndef SGE_NUM_GENBITS
 150 /* Must be 1 or 2 */
 151 # define SGE_NUM_GENBITS 2
 152 #endif
 153
 154 #define TX_DESC_FLITS 16U
 155 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
 156
 157 struct cphy;
 158 struct adapter;
 159
 160 struct mdio_ops {
 161         int (*read)(struct adapter *adapter, int phy_addr, int mmd_addr,
 162                     int reg_addr, unsigned int *val);
 163         int (*write)(struct adapter *adapter, int phy_addr, int mmd_addr,
 164                      int reg_addr, unsigned int val);
 165 };
 166
 167 struct adapter_info {
 168         unsigned char nports;   /* # of ports */
 169         unsigned char phy_base_addr;    /* MDIO PHY base address */
 170         unsigned char mdien;
 171         unsigned char mdiinv;
 172         unsigned int gpio_out;  /* GPIO output settings */
 173         unsigned int gpio_intr; /* GPIO IRQ enable mask */
 174         unsigned long caps;     /* adapter capabilities */
 175         const struct mdio_ops *mdio_ops;        /* MDIO operations */
 176         const char *desc;       /* product description */
 177 };
 178
 179 struct port_type_info {
 180         void (*phy_prep)(struct cphy *phy, struct adapter *adapter,
 181                          int phy_addr, const struct mdio_ops *ops);
 182         unsigned int caps;
 183         const char *desc;
 184 };
 185
 186 struct mc5_stats {
 187         unsigned long parity_err;
 188         unsigned long active_rgn_full;
 189         unsigned long nfa_srch_err;
 190         unsigned long unknown_cmd;
 191         unsigned long reqq_parity_err;
 192         unsigned long dispq_parity_err;
 193         unsigned long del_act_empty;
 194 };
 195
 196 struct mc7_stats {
 197         unsigned long corr_err;
 198         unsigned long uncorr_err;
 199         unsigned long parity_err;
 200         unsigned long addr_err;
 201 };
 202
 203 struct mac_stats {
 204         u64 tx_octets;          /* total # of octets in good frames */
 205         u64 tx_octets_bad;      /* total # of octets in error frames */
 206         u64 tx_frames;          /* all good frames */
 207         u64 tx_mcast_frames;    /* good multicast frames */
 208         u64 tx_bcast_frames;    /* good broadcast frames */
 209         u64 tx_pause;           /* # of transmitted pause frames */
 210         u64 tx_deferred;        /* frames with deferred transmissions */
 211         u64 tx_late_collisions; /* # of late collisions */
 212         u64 tx_total_collisions;        /* # of total collisions */
 213         u64 tx_excess_collisions;       /* frame errors from excessive collissions */
 214         u64 tx_underrun;        /* # of Tx FIFO underruns */
 215         u64 tx_len_errs;        /* # of Tx length errors */
 216         u64 tx_mac_internal_errs;       /* # of internal MAC errors on Tx */
 217         u64 tx_excess_deferral; /* # of frames with excessive deferral */
 218         u64 tx_fcs_errs;        /* # of frames with bad FCS */
 219
 220         u64 tx_frames_64;       /* # of Tx frames in a particular range */
 221         u64 tx_frames_65_127;
 222         u64 tx_frames_128_255;
 223         u64 tx_frames_256_511;
 224         u64 tx_frames_512_1023;
 225         u64 tx_frames_1024_1518;
 226         u64 tx_frames_1519_max;
 227
 228         u64 rx_octets;          /* total # of octets in good frames */
 229         u64 rx_octets_bad;      /* total # of octets in error frames */
 230         u64 rx_frames;          /* all good frames */
 231         u64 rx_mcast_frames;    /* good multicast frames */
 232         u64 rx_bcast_frames;    /* good broadcast frames */
 233         u64 rx_pause;           /* # of received pause frames */
 234         u64 rx_fcs_errs;        /* # of received frames with bad FCS */
 235         u64 rx_align_errs;      /* alignment errors */
 236         u64 rx_symbol_errs;     /* symbol errors */
 237         u64 rx_data_errs;       /* data errors */
 238         u64 rx_sequence_errs;   /* sequence errors */
 239         u64 rx_runt;            /* # of runt frames */
 240         u64 rx_jabber;          /* # of jabber frames */
 241         u64 rx_short;           /* # of short frames */
 242         u64 rx_too_long;        /* # of oversized frames */
 243         u64 rx_mac_internal_errs;       /* # of internal MAC errors on Rx */
 244
 245         u64 rx_frames_64;       /* # of Rx frames in a particular range */
 246         u64 rx_frames_65_127;
 247         u64 rx_frames_128_255;
 248         u64 rx_frames_256_511;
 249         u64 rx_frames_512_1023;
 250         u64 rx_frames_1024_1518;
 251         u64 rx_frames_1519_max;
 252
 253         u64 rx_cong_drops;      /* # of Rx drops due to SGE congestion */
 254
 255         unsigned long tx_fifo_parity_err;
 256         unsigned long rx_fifo_parity_err;
 257         unsigned long tx_fifo_urun;
 258         unsigned long rx_fifo_ovfl;
 259         unsigned long serdes_signal_loss;
 260         unsigned long xaui_pcs_ctc_err;
 261         unsigned long xaui_pcs_align_change;
 262
 263         unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
 264         unsigned long num_resets;  /* # times reset due to stuck TX */
 265
 266 };
 267
 268 struct tp_mib_stats {
 269         u32 ipInReceive_hi;
 270         u32 ipInReceive_lo;
 271         u32 ipInHdrErrors_hi;
 272         u32 ipInHdrErrors_lo;
 273         u32 ipInAddrErrors_hi;
 274         u32 ipInAddrErrors_lo;
 275         u32 ipInUnknownProtos_hi;
 276         u32 ipInUnknownProtos_lo;
 277         u32 ipInDiscards_hi;
 278         u32 ipInDiscards_lo;
 279         u32 ipInDelivers_hi;
 280         u32 ipInDelivers_lo;
 281         u32 ipOutRequests_hi;
 282         u32 ipOutRequests_lo;
 283         u32 ipOutDiscards_hi;
 284         u32 ipOutDiscards_lo;
 285         u32 ipOutNoRoutes_hi;
 286         u32 ipOutNoRoutes_lo;
 287         u32 ipReasmTimeout;
 288         u32 ipReasmReqds;
 289         u32 ipReasmOKs;
 290         u32 ipReasmFails;
 291
 292         u32 reserved[8];
 293
 294         u32 tcpActiveOpens;
 295         u32 tcpPassiveOpens;
 296         u32 tcpAttemptFails;
 297         u32 tcpEstabResets;
 298         u32 tcpOutRsts;
 299         u32 tcpCurrEstab;
 300         u32 tcpInSegs_hi;
 301         u32 tcpInSegs_lo;
 302         u32 tcpOutSegs_hi;
 303         u32 tcpOutSegs_lo;
 304         u32 tcpRetransSeg_hi;
 305         u32 tcpRetransSeg_lo;
 306         u32 tcpInErrs_hi;
 307         u32 tcpInErrs_lo;
 308         u32 tcpRtoMin;
 309         u32 tcpRtoMax;
 310 };
 311
 312 struct tp_params {
 313         unsigned int nchan;     /* # of channels */
 314         unsigned int pmrx_size; /* total PMRX capacity */
 315         unsigned int pmtx_size; /* total PMTX capacity */
 316         unsigned int cm_size;   /* total CM capacity */
 317         unsigned int chan_rx_size;      /* per channel Rx size */
 318         unsigned int chan_tx_size;      /* per channel Tx size */
 319         unsigned int rx_pg_size;        /* Rx page size */
 320         unsigned int tx_pg_size;        /* Tx page size */
 321         unsigned int rx_num_pgs;        /* # of Rx pages */
 322         unsigned int tx_num_pgs;        /* # of Tx pages */
 323         unsigned int ntimer_qs; /* # of timer queues */
 324 };
 325
 326 struct qset_params {            /* SGE queue set parameters */
 327         unsigned int polling;   /* polling/interrupt service for rspq */
 328         unsigned int coalesce_usecs;    /* irq coalescing timer */
 329         unsigned int rspq_size; /* # of entries in response queue */
 330         unsigned int fl_size;   /* # of entries in regular free list */
 331         unsigned int jumbo_size;        /* # of entries in jumbo free list */
 332         unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
 333         unsigned int cong_thres;        /* FL congestion threshold */
 334 };
 335
 336 struct sge_params {
 337         unsigned int max_pkt_size;      /* max offload pkt size */
 338         struct qset_params qset[SGE_QSETS];
 339 };
 340
 341 struct mc5_params {
 342         unsigned int mode;      /* selects MC5 width */
 343         unsigned int nservers;  /* size of server region */
 344         unsigned int nfilters;  /* size of filter region */
 345         unsigned int nroutes;   /* size of routing region */
 346 };
 347
 348 /* Default MC5 region sizes */
 349 enum {
 350         DEFAULT_NSERVERS = 512,
 351         DEFAULT_NFILTERS = 128
 352 };
 353
 354 /* MC5 modes, these must be non-0 */
 355 enum {
 356         MC5_MODE_144_BIT = 1,
 357         MC5_MODE_72_BIT = 2
 358 };
 359
 360 /* MC5 min active region size */
 361 enum { MC5_MIN_TIDS = 16 };
 362
 363 struct vpd_params {
 364         unsigned int cclk;
 365         unsigned int mclk;
 366         unsigned int uclk;
 367         unsigned int mdc;
 368         unsigned int mem_timing;
 369         u8 eth_base[6];
 370         u8 port_type[MAX_NPORTS];
 371         unsigned short xauicfg[2];
 372 };
 373
 374 struct pci_params {
 375         unsigned int vpd_cap_addr;
 376         unsigned int pcie_cap_addr;
 377         unsigned short speed;
 378         unsigned char width;
 379         unsigned char variant;
 380 };
 381
 382 enum {
 383         PCI_VARIANT_PCI,
 384         PCI_VARIANT_PCIX_MODE1_PARITY,
 385         PCI_VARIANT_PCIX_MODE1_ECC,
 386         PCI_VARIANT_PCIX_266_MODE2,
 387         PCI_VARIANT_PCIE
 388 };
 389
 390 struct adapter_params {
 391         struct sge_params sge;
 392         struct mc5_params mc5;
 393         struct tp_params tp;
 394         struct vpd_params vpd;
 395         struct pci_params pci;
 396
 397         const struct adapter_info *info;
 398
 399         unsigned short mtus[NMTUS];
 400         unsigned short a_wnd[NCCTRL_WIN];
 401         unsigned short b_wnd[NCCTRL_WIN];
 402
 403         unsigned int nports;    /* # of ethernet ports */
 404         unsigned int stats_update_period;       /* MAC stats accumulation period */
 405         unsigned int linkpoll_period;   /* link poll period in 0.1s */
 406         unsigned int rev;       /* chip revision */
 407         unsigned int offload;
 408 };
 409
 410 enum {                                      /* chip revisions */
 411         T3_REV_A  = 0,
 412         T3_REV_B  = 2,
 413         T3_REV_B2 = 3,
 414 };
 415
 416 struct trace_params {
 417         u32 sip;
 418         u32 sip_mask;
 419         u32 dip;
 420         u32 dip_mask;
 421         u16 sport;
 422         u16 sport_mask;
 423         u16 dport;
 424         u16 dport_mask;
 425         u32 vlan:12;
 426         u32 vlan_mask:12;
 427         u32 intf:4;
 428         u32 intf_mask:4;
 429         u8 proto;
 430         u8 proto_mask;
 431 };
 432
 433 struct link_config {
 434         unsigned int supported; /* link capabilities */
 435         unsigned int advertising;       /* advertised capabilities */
 436         unsigned short requested_speed; /* speed user has requested */
 437         unsigned short speed;   /* actual link speed */
 438         unsigned char requested_duplex; /* duplex user has requested */
 439         unsigned char duplex;   /* actual link duplex */
 440         unsigned char requested_fc;     /* flow control user has requested */
 441         unsigned char fc;       /* actual link flow control */
 442         unsigned char autoneg;  /* autonegotiating? */
 443         unsigned int link_ok;   /* link up? */
 444 };
 445
 446 #define SPEED_INVALID   0xffff
 447 #define DUPLEX_INVALID  0xff
 448
 449 struct mc5 {
 450         struct adapter *adapter;
 451         unsigned int tcam_size;
 452         unsigned char part_type;
 453         unsigned char parity_enabled;
 454         unsigned char mode;
 455         struct mc5_stats stats;
 456 };
 457
 458 static inline unsigned int t3_mc5_size(const struct mc5 *p)
 459 {
 460         return p->tcam_size;
 461 }
 462
 463 struct mc7 {
 464         struct adapter *adapter;        /* backpointer to adapter */
 465         unsigned int size;      /* memory size in bytes */
 466         unsigned int width;     /* MC7 interface width */
 467         unsigned int offset;    /* register address offset for MC7 instance */
 468         const char *name;       /* name of MC7 instance */
 469         struct mc7_stats stats; /* MC7 statistics */
 470 };
 471
 472 static inline unsigned int t3_mc7_size(const struct mc7 *p)
 473 {
 474         return p->size;
 475 }
 476
 477 struct cmac {
 478         struct adapter *adapter;
 479         unsigned int offset;
 480         unsigned int nucast;    /* # of address filters for unicast MACs */
 481         unsigned int tx_tcnt;
 482         unsigned int tx_xcnt;
 483         u64 tx_mcnt;
 484         unsigned int rx_xcnt;
 485         u64 rx_mcnt;
 486         unsigned int toggle_cnt;
 487         unsigned int txen;
 488         struct mac_stats stats;
 489 };
 490
 491 enum {
 492         MAC_DIRECTION_RX = 1,
 493         MAC_DIRECTION_TX = 2,
 494         MAC_RXFIFO_SIZE = 32768
 495 };
 496
 497 /* IEEE 802.3ae specified MDIO devices */
 498 enum {
 499         MDIO_DEV_PMA_PMD = 1,
 500         MDIO_DEV_WIS = 2,
 501         MDIO_DEV_PCS = 3,
 502         MDIO_DEV_XGXS = 4
 503 };
 504
 505 /* PHY loopback direction */
 506 enum {
 507         PHY_LOOPBACK_TX = 1,
 508         PHY_LOOPBACK_RX = 2
 509 };
 510
 511 /* PHY interrupt types */
 512 enum {
 513         cphy_cause_link_change = 1,
 514         cphy_cause_fifo_error = 2
 515 };
 516
 517 /* PHY operations */
 518 struct cphy_ops {
 519         void (*destroy)(struct cphy *phy);
 520         int (*reset)(struct cphy *phy, int wait);
 521
 522         int (*intr_enable)(struct cphy *phy);
 523         int (*intr_disable)(struct cphy *phy);
 524         int (*intr_clear)(struct cphy *phy);
 525         int (*intr_handler)(struct cphy *phy);
 526
 527         int (*autoneg_enable)(struct cphy *phy);
 528         int (*autoneg_restart)(struct cphy *phy);
 529
 530         int (*advertise)(struct cphy *phy, unsigned int advertise_map);
 531         int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
 532         int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
 533         int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
 534                                int *duplex, int *fc);
 535         int (*power_down)(struct cphy *phy, int enable);
 536 };
 537
 538 /* A PHY instance */
 539 struct cphy {
 540         int addr;               /* PHY address */
 541         struct adapter *adapter;        /* associated adapter */
 542         unsigned long fifo_errors;      /* FIFO over/under-flows */
 543         const struct cphy_ops *ops;     /* PHY operations */
 544         int (*mdio_read)(struct adapter *adapter, int phy_addr, int mmd_addr,
 545                          int reg_addr, unsigned int *val);
 546         int (*mdio_write)(struct adapter *adapter, int phy_addr, int mmd_addr,
 547                           int reg_addr, unsigned int val);
 548 };
 549
 550 /* Convenience MDIO read/write wrappers */
 551 static inline int mdio_read(struct cphy *phy, int mmd, int reg,
 552                             unsigned int *valp)
 553 {
 554         return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);
 555 }
 556
 557 static inline int mdio_write(struct cphy *phy, int mmd, int reg,
 558                              unsigned int val)
 559 {
 560         return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
 561 }
 562
 563 /* Convenience initializer */
 564 static inline void cphy_init(struct cphy *phy, struct adapter *adapter,
 565                              int phy_addr, struct cphy_ops *phy_ops,
 566                              const struct mdio_ops *mdio_ops)
 567 {
 568         phy->adapter = adapter;
 569         phy->addr = phy_addr;
 570         phy->ops = phy_ops;
 571         if (mdio_ops) {
 572                 phy->mdio_read = mdio_ops->read;
 573                 phy->mdio_write = mdio_ops->write;
 574         }
 575 }
 576
 577 /* Accumulate MAC statistics every 180 seconds.  For 1G we multiply by 10. */
 578 #define MAC_STATS_ACCUM_SECS 180
 579
 580 #define XGM_REG(reg_addr, idx) \
 581         ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
 582
 583 struct addr_val_pair {
 584         unsigned int reg_addr;
 585         unsigned int val;
 586 };
 587
 588 #include "adapter.h"
 589
 590 #ifndef PCI_VENDOR_ID_CHELSIO
 591 # define PCI_VENDOR_ID_CHELSIO 0x1425
 592 #endif
 593
 594 #define for_each_port(adapter, iter) \
 595         for (iter = 0; iter < (adapter)->params.nports; ++iter)
 596
 597 #define adapter_info(adap) ((adap)->params.info)
 598
 599 static inline int uses_xaui(const struct adapter *adap)
 600 {
 601         return adapter_info(adap)->caps & SUPPORTED_AUI;
 602 }
 603
 604 static inline int is_10G(const struct adapter *adap)
 605 {
 606         return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
 607 }
 608
 609 static inline int is_offload(const struct adapter *adap)
 610 {
 611         return adap->params.offload;
 612 }
 613
 614 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
 615 {
 616         return adap->params.vpd.cclk / 1000;
 617 }
 618
 619 static inline unsigned int is_pcie(const struct adapter *adap)
 620 {
 621         return adap->params.pci.variant == PCI_VARIANT_PCIE;
 622 }
 623
 624 void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
 625                       u32 val);
 626 void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p,
 627                    int n, unsigned int offset);
 628 int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
 629                         int polarity, int attempts, int delay, u32 *valp);
 630 static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask,
 631                                   int polarity, int attempts, int delay)
 632 {
 633         return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
 634                                    delay, NULL);
 635 }
 636 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
 637                         unsigned int set);
 638 int t3_phy_reset(struct cphy *phy, int mmd, int wait);
 639 int t3_phy_advertise(struct cphy *phy, unsigned int advert);
 640 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
 641
 642 void t3_intr_enable(struct adapter *adapter);
 643 void t3_intr_disable(struct adapter *adapter);
 644 void t3_intr_clear(struct adapter *adapter);
 645 void t3_port_intr_enable(struct adapter *adapter, int idx);
 646 void t3_port_intr_disable(struct adapter *adapter, int idx);
 647 void t3_port_intr_clear(struct adapter *adapter, int idx);
 648 int t3_slow_intr_handler(struct adapter *adapter);
 649 int t3_phy_intr_handler(struct adapter *adapter);
 650
 651 void t3_link_changed(struct adapter *adapter, int port_id);
 652 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
 653 const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
 654 int t3_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
 655 int t3_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
 656 int t3_seeprom_wp(struct adapter *adapter, int enable);
 657 int t3_read_flash(struct adapter *adapter, unsigned int addr,
 658                   unsigned int nwords, u32 *data, int byte_oriented);
 659 int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size);
 660 int t3_get_fw_version(struct adapter *adapter, u32 *vers);
 661 int t3_check_fw_version(struct adapter *adapter);
 662 int t3_init_hw(struct adapter *adapter, u32 fw_params);
 663 void mac_prep(struct cmac *mac, struct adapter *adapter, int index);
 664 void early_hw_init(struct adapter *adapter, const struct adapter_info *ai);
 665 int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
 666                     int reset);
 667 void t3_led_ready(struct adapter *adapter);
 668 void t3_fatal_err(struct adapter *adapter);
 669 void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on);
 670 void t3_config_rss(struct adapter *adapter, unsigned int rss_config,
 671                    const u8 * cpus, const u16 *rspq);
 672 int t3_read_rss(struct adapter *adapter, u8 * lkup, u16 *map);
 673 int t3_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
 674 int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,
 675                         unsigned int n, unsigned int *valp);
 676 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
 677                    u64 *buf);
 678
 679 int t3_mac_reset(struct cmac *mac);
 680 void t3b_pcs_reset(struct cmac *mac);
 681 int t3_mac_enable(struct cmac *mac, int which);
 682 int t3_mac_disable(struct cmac *mac, int which);
 683 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
 684 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm);
 685 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
 686 int t3_mac_set_num_ucast(struct cmac *mac, int n);
 687 const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
 688 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc);
 689 int t3b2_mac_watchdog_task(struct cmac *mac);
 690
 691 void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode);
 692 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
 693                 unsigned int nroutes);
 694 void t3_mc5_intr_handler(struct mc5 *mc5);
 695 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
 696                       u32 *buf);
 697
 698 int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh);
 699 void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size);
 700 void t3_tp_set_offload_mode(struct adapter *adap, int enable);
 701 void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps);
 702 void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],
 703                   unsigned short alpha[NCCTRL_WIN],
 704                   unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
 705 void t3_read_hw_mtus(struct adapter *adap, unsigned short mtus[NMTUS]);
 706 void t3_get_cong_cntl_tab(struct adapter *adap,
 707                           unsigned short incr[NMTUS][NCCTRL_WIN]);
 708 void t3_config_trace_filter(struct adapter *adapter,
 709                             const struct trace_params *tp, int filter_index,
 710                             int invert, int enable);
 711 int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched);
 712
 713 void t3_sge_prep(struct adapter *adap, struct sge_params *p);
 714 void t3_sge_init(struct adapter *adap, struct sge_params *p);
 715 int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable,
 716                        enum sge_context_type type, int respq, u64 base_addr,
 717                        unsigned int size, unsigned int token, int gen,
 718                        unsigned int cidx);
 719 int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id,
 720                         int gts_enable, u64 base_addr, unsigned int size,
 721                         unsigned int esize, unsigned int cong_thres, int gen,
 722                         unsigned int cidx);
 723 int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id,
 724                          int irq_vec_idx, u64 base_addr, unsigned int size,
 725                          unsigned int fl_thres, int gen, unsigned int cidx);
 726 int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
 727                         unsigned int size, int rspq, int ovfl_mode,
 728                         unsigned int credits, unsigned int credit_thres);
 729 int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable);
 730 int t3_sge_disable_fl(struct adapter *adapter, unsigned int id);
 731 int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id);
 732 int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id);
 733 int t3_sge_read_ecntxt(struct adapter *adapter, unsigned int id, u32 data[4]);
 734 int t3_sge_read_fl(struct adapter *adapter, unsigned int id, u32 data[4]);
 735 int t3_sge_read_cq(struct adapter *adapter, unsigned int id, u32 data[4]);
 736 int t3_sge_read_rspq(struct adapter *adapter, unsigned int id, u32 data[4]);
 737 int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op,
 738                       unsigned int credits);
 739
 740 void t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter,
 741                          int phy_addr, const struct mdio_ops *mdio_ops);
 742 void t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
 743                          int phy_addr, const struct mdio_ops *mdio_ops);
 744 void t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
 745                          int phy_addr, const struct mdio_ops *mdio_ops);
 746 void t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
 747                         const struct mdio_ops *mdio_ops);
 748 void t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
 749                              int phy_addr, const struct mdio_ops *mdio_ops);
 750 #endif                          /* __CHELSIO_COMMON_H */