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Linux 2.6.21.1
[linux/fpc-iii.git] / include / asm-mips / mipsregs.h
blob9985cb7c16e726e22f90ef58f50692920c73ced6
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
15
16 #include <linux/linkage.h>
17 #include <asm/hazards.h>
18
19 /*
20 * The following macros are especially useful for __asm__
21 * inline assembler.
22 */
23 #ifndef __STR
24 #define __STR(x) #x
25 #endif
26 #ifndef STR
27 #define STR(x) __STR(x)
28 #endif
29
30 /*
31 * Configure language
32 */
33 #ifdef __ASSEMBLY__
34 #define _ULCAST_
35 #else
36 #define _ULCAST_ (unsigned long)
37 #endif
38
39 /*
40 * Coprocessor 0 register names
41 */
42 #define CP0_INDEX $0
43 #define CP0_RANDOM $1
44 #define CP0_ENTRYLO0 $2
45 #define CP0_ENTRYLO1 $3
46 #define CP0_CONF $3
47 #define CP0_CONTEXT $4
48 #define CP0_PAGEMASK $5
49 #define CP0_WIRED $6
50 #define CP0_INFO $7
51 #define CP0_BADVADDR $8
52 #define CP0_COUNT $9
53 #define CP0_ENTRYHI $10
54 #define CP0_COMPARE $11
55 #define CP0_STATUS $12
56 #define CP0_CAUSE $13
57 #define CP0_EPC $14
58 #define CP0_PRID $15
59 #define CP0_CONFIG $16
60 #define CP0_LLADDR $17
61 #define CP0_WATCHLO $18
62 #define CP0_WATCHHI $19
63 #define CP0_XCONTEXT $20
64 #define CP0_FRAMEMASK $21
65 #define CP0_DIAGNOSTIC $22
66 #define CP0_DEBUG $23
67 #define CP0_DEPC $24
68 #define CP0_PERFORMANCE $25
69 #define CP0_ECC $26
70 #define CP0_CACHEERR $27
71 #define CP0_TAGLO $28
72 #define CP0_TAGHI $29
73 #define CP0_ERROREPC $30
74 #define CP0_DESAVE $31
75
76 /*
77 * R4640/R4650 cp0 register names. These registers are listed
78 * here only for completeness; without MMU these CPUs are not useable
79 * by Linux. A future ELKS port might take make Linux run on them
80 * though ...
81 */
82 #define CP0_IBASE $0
83 #define CP0_IBOUND $1
84 #define CP0_DBASE $2
85 #define CP0_DBOUND $3
86 #define CP0_CALG $17
87 #define CP0_IWATCH $18
88 #define CP0_DWATCH $19
89
90 /*
91 * Coprocessor 0 Set 1 register names
92 */
93 #define CP0_S1_DERRADDR0 $26
94 #define CP0_S1_DERRADDR1 $27
95 #define CP0_S1_INTCONTROL $20
96
97 /*
98 * Coprocessor 0 Set 2 register names
99 */
100 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
101
102 /*
103 * Coprocessor 0 Set 3 register names
104 */
105 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
106
107 /*
108 * TX39 Series
109 */
110 #define CP0_TX39_CACHE $7
111
112 /*
113 * Coprocessor 1 (FPU) register names
114 */
115 #define CP1_REVISION $0
116 #define CP1_STATUS $31
117
118 /*
119 * FPU Status Register Values
120 */
121 /*
122 * Status Register Values
123 */
124
125 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
126 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
127 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
128 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
129 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
130 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
131 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
132 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
133 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
134 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
135
136 /*
137 * X the exception cause indicator
138 * E the exception enable
139 * S the sticky/flag bit
140 */
141 #define FPU_CSR_ALL_X 0x0003f000
142 #define FPU_CSR_UNI_X 0x00020000
143 #define FPU_CSR_INV_X 0x00010000
144 #define FPU_CSR_DIV_X 0x00008000
145 #define FPU_CSR_OVF_X 0x00004000
146 #define FPU_CSR_UDF_X 0x00002000
147 #define FPU_CSR_INE_X 0x00001000
148
149 #define FPU_CSR_ALL_E 0x00000f80
150 #define FPU_CSR_INV_E 0x00000800
151 #define FPU_CSR_DIV_E 0x00000400
152 #define FPU_CSR_OVF_E 0x00000200
153 #define FPU_CSR_UDF_E 0x00000100
154 #define FPU_CSR_INE_E 0x00000080
155
156 #define FPU_CSR_ALL_S 0x0000007c
157 #define FPU_CSR_INV_S 0x00000040
158 #define FPU_CSR_DIV_S 0x00000020
159 #define FPU_CSR_OVF_S 0x00000010
160 #define FPU_CSR_UDF_S 0x00000008
161 #define FPU_CSR_INE_S 0x00000004
162
163 /* rounding mode */
164 #define FPU_CSR_RN 0x0 /* nearest */
165 #define FPU_CSR_RZ 0x1 /* towards zero */
166 #define FPU_CSR_RU 0x2 /* towards +Infinity */
167 #define FPU_CSR_RD 0x3 /* towards -Infinity */
168
169
170 /*
171 * Values for PageMask register
172 */
173 #ifdef CONFIG_CPU_VR41XX
174
175 /* Why doesn't stupidity hurt ... */
176
177 #define PM_1K 0x00000000
178 #define PM_4K 0x00001800
179 #define PM_16K 0x00007800
180 #define PM_64K 0x0001f800
181 #define PM_256K 0x0007f800
182
183 #else
184
185 #define PM_4K 0x00000000
186 #define PM_16K 0x00006000
187 #define PM_64K 0x0001e000
188 #define PM_256K 0x0007e000
189 #define PM_1M 0x001fe000
190 #define PM_4M 0x007fe000
191 #define PM_16M 0x01ffe000
192 #define PM_64M 0x07ffe000
193 #define PM_256M 0x1fffe000
194
195 #endif
196
197 /*
198 * Default page size for a given kernel configuration
199 */
200 #ifdef CONFIG_PAGE_SIZE_4KB
201 #define PM_DEFAULT_MASK PM_4K
202 #elif defined(CONFIG_PAGE_SIZE_16KB)
203 #define PM_DEFAULT_MASK PM_16K
204 #elif defined(CONFIG_PAGE_SIZE_64KB)
205 #define PM_DEFAULT_MASK PM_64K
206 #else
207 #error Bad page size configuration!
208 #endif
209
210
211 /*
212 * Values used for computation of new tlb entries
213 */
214 #define PL_4K 12
215 #define PL_16K 14
216 #define PL_64K 16
217 #define PL_256K 18
218 #define PL_1M 20
219 #define PL_4M 22
220 #define PL_16M 24
221 #define PL_64M 26
222 #define PL_256M 28
223
224 /*
225 * R4x00 interrupt enable / cause bits
226 */
227 #define IE_SW0 (_ULCAST_(1) << 8)
228 #define IE_SW1 (_ULCAST_(1) << 9)
229 #define IE_IRQ0 (_ULCAST_(1) << 10)
230 #define IE_IRQ1 (_ULCAST_(1) << 11)
231 #define IE_IRQ2 (_ULCAST_(1) << 12)
232 #define IE_IRQ3 (_ULCAST_(1) << 13)
233 #define IE_IRQ4 (_ULCAST_(1) << 14)
234 #define IE_IRQ5 (_ULCAST_(1) << 15)
235
236 /*
237 * R4x00 interrupt cause bits
238 */
239 #define C_SW0 (_ULCAST_(1) << 8)
240 #define C_SW1 (_ULCAST_(1) << 9)
241 #define C_IRQ0 (_ULCAST_(1) << 10)
242 #define C_IRQ1 (_ULCAST_(1) << 11)
243 #define C_IRQ2 (_ULCAST_(1) << 12)
244 #define C_IRQ3 (_ULCAST_(1) << 13)
245 #define C_IRQ4 (_ULCAST_(1) << 14)
246 #define C_IRQ5 (_ULCAST_(1) << 15)
247
248 /*
249 * Bitfields in the R4xx0 cp0 status register
250 */
251 #define ST0_IE 0x00000001
252 #define ST0_EXL 0x00000002
253 #define ST0_ERL 0x00000004
254 #define ST0_KSU 0x00000018
255 # define KSU_USER 0x00000010
256 # define KSU_SUPERVISOR 0x00000008
257 # define KSU_KERNEL 0x00000000
258 #define ST0_UX 0x00000020
259 #define ST0_SX 0x00000040
260 #define ST0_KX 0x00000080
261 #define ST0_DE 0x00010000
262 #define ST0_CE 0x00020000
263
264 /*
265 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
266 * cacheops in userspace. This bit exists only on RM7000 and RM9000
267 * processors.
268 */
269 #define ST0_CO 0x08000000
270
271 /*
272 * Bitfields in the R[23]000 cp0 status register.
273 */
274 #define ST0_IEC 0x00000001
275 #define ST0_KUC 0x00000002
276 #define ST0_IEP 0x00000004
277 #define ST0_KUP 0x00000008
278 #define ST0_IEO 0x00000010
279 #define ST0_KUO 0x00000020
280 /* bits 6 & 7 are reserved on R[23]000 */
281 #define ST0_ISC 0x00010000
282 #define ST0_SWC 0x00020000
283 #define ST0_CM 0x00080000
284
285 /*
286 * Bits specific to the R4640/R4650
287 */
288 #define ST0_UM (_ULCAST_(1) << 4)
289 #define ST0_IL (_ULCAST_(1) << 23)
290 #define ST0_DL (_ULCAST_(1) << 24)
291
292 /*
293 * Enable the MIPS MDMX and DSP ASEs
294 */
295 #define ST0_MX 0x01000000
296
297 /*
298 * Bitfields in the TX39 family CP0 Configuration Register 3
299 */
300 #define TX39_CONF_ICS_SHIFT 19
301 #define TX39_CONF_ICS_MASK 0x00380000
302 #define TX39_CONF_ICS_1KB 0x00000000
303 #define TX39_CONF_ICS_2KB 0x00080000
304 #define TX39_CONF_ICS_4KB 0x00100000
305 #define TX39_CONF_ICS_8KB 0x00180000
306 #define TX39_CONF_ICS_16KB 0x00200000
307
308 #define TX39_CONF_DCS_SHIFT 16
309 #define TX39_CONF_DCS_MASK 0x00070000
310 #define TX39_CONF_DCS_1KB 0x00000000
311 #define TX39_CONF_DCS_2KB 0x00010000
312 #define TX39_CONF_DCS_4KB 0x00020000
313 #define TX39_CONF_DCS_8KB 0x00030000
314 #define TX39_CONF_DCS_16KB 0x00040000
315
316 #define TX39_CONF_CWFON 0x00004000
317 #define TX39_CONF_WBON 0x00002000
318 #define TX39_CONF_RF_SHIFT 10
319 #define TX39_CONF_RF_MASK 0x00000c00
320 #define TX39_CONF_DOZE 0x00000200
321 #define TX39_CONF_HALT 0x00000100
322 #define TX39_CONF_LOCK 0x00000080
323 #define TX39_CONF_ICE 0x00000020
324 #define TX39_CONF_DCE 0x00000010
325 #define TX39_CONF_IRSIZE_SHIFT 2
326 #define TX39_CONF_IRSIZE_MASK 0x0000000c
327 #define TX39_CONF_DRSIZE_SHIFT 0
328 #define TX39_CONF_DRSIZE_MASK 0x00000003
329
330 /*
331 * Status register bits available in all MIPS CPUs.
332 */
333 #define ST0_IM 0x0000ff00
334 #define STATUSB_IP0 8
335 #define STATUSF_IP0 (_ULCAST_(1) << 8)
336 #define STATUSB_IP1 9
337 #define STATUSF_IP1 (_ULCAST_(1) << 9)
338 #define STATUSB_IP2 10
339 #define STATUSF_IP2 (_ULCAST_(1) << 10)
340 #define STATUSB_IP3 11
341 #define STATUSF_IP3 (_ULCAST_(1) << 11)
342 #define STATUSB_IP4 12
343 #define STATUSF_IP4 (_ULCAST_(1) << 12)
344 #define STATUSB_IP5 13
345 #define STATUSF_IP5 (_ULCAST_(1) << 13)
346 #define STATUSB_IP6 14
347 #define STATUSF_IP6 (_ULCAST_(1) << 14)
348 #define STATUSB_IP7 15
349 #define STATUSF_IP7 (_ULCAST_(1) << 15)
350 #define STATUSB_IP8 0
351 #define STATUSF_IP8 (_ULCAST_(1) << 0)
352 #define STATUSB_IP9 1
353 #define STATUSF_IP9 (_ULCAST_(1) << 1)
354 #define STATUSB_IP10 2
355 #define STATUSF_IP10 (_ULCAST_(1) << 2)
356 #define STATUSB_IP11 3
357 #define STATUSF_IP11 (_ULCAST_(1) << 3)
358 #define STATUSB_IP12 4
359 #define STATUSF_IP12 (_ULCAST_(1) << 4)
360 #define STATUSB_IP13 5
361 #define STATUSF_IP13 (_ULCAST_(1) << 5)
362 #define STATUSB_IP14 6
363 #define STATUSF_IP14 (_ULCAST_(1) << 6)
364 #define STATUSB_IP15 7
365 #define STATUSF_IP15 (_ULCAST_(1) << 7)
366 #define ST0_CH 0x00040000
367 #define ST0_SR 0x00100000
368 #define ST0_TS 0x00200000
369 #define ST0_BEV 0x00400000
370 #define ST0_RE 0x02000000
371 #define ST0_FR 0x04000000
372 #define ST0_CU 0xf0000000
373 #define ST0_CU0 0x10000000
374 #define ST0_CU1 0x20000000
375 #define ST0_CU2 0x40000000
376 #define ST0_CU3 0x80000000
377 #define ST0_XX 0x80000000 /* MIPS IV naming */
378
379 /*
380 * Bitfields and bit numbers in the coprocessor 0 cause register.
381 *
382 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
383 */
384 #define CAUSEB_EXCCODE 2
385 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
386 #define CAUSEB_IP 8
387 #define CAUSEF_IP (_ULCAST_(255) << 8)
388 #define CAUSEB_IP0 8
389 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
390 #define CAUSEB_IP1 9
391 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
392 #define CAUSEB_IP2 10
393 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
394 #define CAUSEB_IP3 11
395 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
396 #define CAUSEB_IP4 12
397 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
398 #define CAUSEB_IP5 13
399 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
400 #define CAUSEB_IP6 14
401 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
402 #define CAUSEB_IP7 15
403 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
404 #define CAUSEB_IV 23
405 #define CAUSEF_IV (_ULCAST_(1) << 23)
406 #define CAUSEB_CE 28
407 #define CAUSEF_CE (_ULCAST_(3) << 28)
408 #define CAUSEB_BD 31
409 #define CAUSEF_BD (_ULCAST_(1) << 31)
410
411 /*
412 * Bits in the coprocessor 0 config register.
413 */
414 /* Generic bits. */
415 #define CONF_CM_CACHABLE_NO_WA 0
416 #define CONF_CM_CACHABLE_WA 1
417 #define CONF_CM_UNCACHED 2
418 #define CONF_CM_CACHABLE_NONCOHERENT 3
419 #define CONF_CM_CACHABLE_CE 4
420 #define CONF_CM_CACHABLE_COW 5
421 #define CONF_CM_CACHABLE_CUW 6
422 #define CONF_CM_CACHABLE_ACCELERATED 7
423 #define CONF_CM_CMASK 7
424 #define CONF_BE (_ULCAST_(1) << 15)
425
426 /* Bits common to various processors. */
427 #define CONF_CU (_ULCAST_(1) << 3)
428 #define CONF_DB (_ULCAST_(1) << 4)
429 #define CONF_IB (_ULCAST_(1) << 5)
430 #define CONF_DC (_ULCAST_(7) << 6)
431 #define CONF_IC (_ULCAST_(7) << 9)
432 #define CONF_EB (_ULCAST_(1) << 13)
433 #define CONF_EM (_ULCAST_(1) << 14)
434 #define CONF_SM (_ULCAST_(1) << 16)
435 #define CONF_SC (_ULCAST_(1) << 17)
436 #define CONF_EW (_ULCAST_(3) << 18)
437 #define CONF_EP (_ULCAST_(15)<< 24)
438 #define CONF_EC (_ULCAST_(7) << 28)
439 #define CONF_CM (_ULCAST_(1) << 31)
440
441 /* Bits specific to the R4xx0. */
442 #define R4K_CONF_SW (_ULCAST_(1) << 20)
443 #define R4K_CONF_SS (_ULCAST_(1) << 21)
444 #define R4K_CONF_SB (_ULCAST_(3) << 22)
445
446 /* Bits specific to the R5000. */
447 #define R5K_CONF_SE (_ULCAST_(1) << 12)
448 #define R5K_CONF_SS (_ULCAST_(3) << 20)
449
450 /* Bits specific to the RM7000. */
451 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
452 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
453 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
454 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
455 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
456 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
457
458 /* Bits specific to the R10000. */
459 #define R10K_CONF_DN (_ULCAST_(3) << 3)
460 #define R10K_CONF_CT (_ULCAST_(1) << 5)
461 #define R10K_CONF_PE (_ULCAST_(1) << 6)
462 #define R10K_CONF_PM (_ULCAST_(3) << 7)
463 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
464 #define R10K_CONF_SB (_ULCAST_(1) << 13)
465 #define R10K_CONF_SK (_ULCAST_(1) << 14)
466 #define R10K_CONF_SS (_ULCAST_(7) << 16)
467 #define R10K_CONF_SC (_ULCAST_(7) << 19)
468 #define R10K_CONF_DC (_ULCAST_(7) << 26)
469 #define R10K_CONF_IC (_ULCAST_(7) << 29)
470
471 /* Bits specific to the VR41xx. */
472 #define VR41_CONF_CS (_ULCAST_(1) << 12)
473 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
474 #define VR41_CONF_BP (_ULCAST_(1) << 16)
475 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
476 #define VR41_CONF_AD (_ULCAST_(1) << 23)
477
478 /* Bits specific to the R30xx. */
479 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
480 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
481 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
482 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
483 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
484 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
485 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
486 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
487 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
488
489 /* Bits specific to the TX49. */
490 #define TX49_CONF_DC (_ULCAST_(1) << 16)
491 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
492 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
493 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
494
495 /* Bits specific to the MIPS32/64 PRA. */
496 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
497 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
498 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
499 #define MIPS_CONF_M (_ULCAST_(1) << 31)
500
501 /*
502 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
503 */
504 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
505 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
506 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
507 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
508 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
509 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
510 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
511 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
512 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
513 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
514 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
515 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
516 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
517 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
518
519 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
520 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
521 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
522 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
523 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
524 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
525 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
526 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
527
528 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
529 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
530 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
531 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
532 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
533 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
534 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
535 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
536
537 /*
538 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
539 */
540 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
541 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
542 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
543 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
544 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
545 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
546 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
547
548 #ifndef __ASSEMBLY__
549
550 /*
551 * Functions to access the R10000 performance counters. These are basically
552 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
553 * performance counter number encoded into bits 1 ... 5 of the instruction.
554 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
555 * disassembler these will look like an access to sel 0 or 1.
556 */
557 #define read_r10k_perf_cntr(counter) \
558 ({ \
559 unsigned int __res; \
560 __asm__ __volatile__( \
561 "mfpc\t%0, %1" \
562 : "=r" (__res) \
563 : "i" (counter)); \
564 \
565 __res; \
566 })
567
568 #define write_r10k_perf_cntr(counter,val) \
569 do { \
570 __asm__ __volatile__( \
571 "mtpc\t%0, %1" \
572 : \
573 : "r" (val), "i" (counter)); \
574 } while (0)
575
576 #define read_r10k_perf_event(counter) \
577 ({ \
578 unsigned int __res; \
579 __asm__ __volatile__( \
580 "mfps\t%0, %1" \
581 : "=r" (__res) \
582 : "i" (counter)); \
583 \
584 __res; \
585 })
586
587 #define write_r10k_perf_cntl(counter,val) \
588 do { \
589 __asm__ __volatile__( \
590 "mtps\t%0, %1" \
591 : \
592 : "r" (val), "i" (counter)); \
593 } while (0)
594
595
596 /*
597 * Macros to access the system control coprocessor
598 */
599
600 #define __read_32bit_c0_register(source, sel) \
601 ({ int __res; \
602 if (sel == 0) \
603 __asm__ __volatile__( \
604 "mfc0\t%0, " #source "\n\t" \
605 : "=r" (__res)); \
606 else \
607 __asm__ __volatile__( \
608 ".set\tmips32\n\t" \
609 "mfc0\t%0, " #source ", " #sel "\n\t" \
610 ".set\tmips0\n\t" \
611 : "=r" (__res)); \
612 __res; \
613 })
614
615 #define __read_64bit_c0_register(source, sel) \
616 ({ unsigned long long __res; \
617 if (sizeof(unsigned long) == 4) \
618 __res = __read_64bit_c0_split(source, sel); \
619 else if (sel == 0) \
620 __asm__ __volatile__( \
621 ".set\tmips3\n\t" \
622 "dmfc0\t%0, " #source "\n\t" \
623 ".set\tmips0" \
624 : "=r" (__res)); \
625 else \
626 __asm__ __volatile__( \
627 ".set\tmips64\n\t" \
628 "dmfc0\t%0, " #source ", " #sel "\n\t" \
629 ".set\tmips0" \
630 : "=r" (__res)); \
631 __res; \
632 })
633
634 #define __write_32bit_c0_register(register, sel, value) \
635 do { \
636 if (sel == 0) \
637 __asm__ __volatile__( \
638 "mtc0\t%z0, " #register "\n\t" \
639 : : "Jr" ((unsigned int)(value))); \
640 else \
641 __asm__ __volatile__( \
642 ".set\tmips32\n\t" \
643 "mtc0\t%z0, " #register ", " #sel "\n\t" \
644 ".set\tmips0" \
645 : : "Jr" ((unsigned int)(value))); \
646 } while (0)
647
648 #define __write_64bit_c0_register(register, sel, value) \
649 do { \
650 if (sizeof(unsigned long) == 4) \
651 __write_64bit_c0_split(register, sel, value); \
652 else if (sel == 0) \
653 __asm__ __volatile__( \
654 ".set\tmips3\n\t" \
655 "dmtc0\t%z0, " #register "\n\t" \
656 ".set\tmips0" \
657 : : "Jr" (value)); \
658 else \
659 __asm__ __volatile__( \
660 ".set\tmips64\n\t" \
661 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
662 ".set\tmips0" \
663 : : "Jr" (value)); \
664 } while (0)
665
666 #define __read_ulong_c0_register(reg, sel) \
667 ((sizeof(unsigned long) == 4) ? \
668 (unsigned long) __read_32bit_c0_register(reg, sel) : \
669 (unsigned long) __read_64bit_c0_register(reg, sel))
670
671 #define __write_ulong_c0_register(reg, sel, val) \
672 do { \
673 if (sizeof(unsigned long) == 4) \
674 __write_32bit_c0_register(reg, sel, val); \
675 else \
676 __write_64bit_c0_register(reg, sel, val); \
677 } while (0)
678
679 /*
680 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
681 */
682 #define __read_32bit_c0_ctrl_register(source) \
683 ({ int __res; \
684 __asm__ __volatile__( \
685 "cfc0\t%0, " #source "\n\t" \
686 : "=r" (__res)); \
687 __res; \
688 })
689
690 #define __write_32bit_c0_ctrl_register(register, value) \
691 do { \
692 __asm__ __volatile__( \
693 "ctc0\t%z0, " #register "\n\t" \
694 : : "Jr" ((unsigned int)(value))); \
695 } while (0)
696
697 /*
698 * These versions are only needed for systems with more than 38 bits of
699 * physical address space running the 32-bit kernel. That's none atm :-)
700 */
701 #define __read_64bit_c0_split(source, sel) \
702 ({ \
703 unsigned long long val; \
704 unsigned long flags; \
705 \
706 local_irq_save(flags); \
707 if (sel == 0) \
708 __asm__ __volatile__( \
709 ".set\tmips64\n\t" \
710 "dmfc0\t%M0, " #source "\n\t" \
711 "dsll\t%L0, %M0, 32\n\t" \
712 "dsrl\t%M0, %M0, 32\n\t" \
713 "dsrl\t%L0, %L0, 32\n\t" \
714 ".set\tmips0" \
715 : "=r" (val)); \
716 else \
717 __asm__ __volatile__( \
718 ".set\tmips64\n\t" \
719 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
720 "dsll\t%L0, %M0, 32\n\t" \
721 "dsrl\t%M0, %M0, 32\n\t" \
722 "dsrl\t%L0, %L0, 32\n\t" \
723 ".set\tmips0" \
724 : "=r" (val)); \
725 local_irq_restore(flags); \
726 \
727 val; \
728 })
729
730 #define __write_64bit_c0_split(source, sel, val) \
731 do { \
732 unsigned long flags; \
733 \
734 local_irq_save(flags); \
735 if (sel == 0) \
736 __asm__ __volatile__( \
737 ".set\tmips64\n\t" \
738 "dsll\t%L0, %L0, 32\n\t" \
739 "dsrl\t%L0, %L0, 32\n\t" \
740 "dsll\t%M0, %M0, 32\n\t" \
741 "or\t%L0, %L0, %M0\n\t" \
742 "dmtc0\t%L0, " #source "\n\t" \
743 ".set\tmips0" \
744 : : "r" (val)); \
745 else \
746 __asm__ __volatile__( \
747 ".set\tmips64\n\t" \
748 "dsll\t%L0, %L0, 32\n\t" \
749 "dsrl\t%L0, %L0, 32\n\t" \
750 "dsll\t%M0, %M0, 32\n\t" \
751 "or\t%L0, %L0, %M0\n\t" \
752 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
753 ".set\tmips0" \
754 : : "r" (val)); \
755 local_irq_restore(flags); \
756 } while (0)
757
758 #define read_c0_index() __read_32bit_c0_register($0, 0)
759 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
760
761 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
762 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
763
764 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
765 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
766
767 #define read_c0_conf() __read_32bit_c0_register($3, 0)
768 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
769
770 #define read_c0_context() __read_ulong_c0_register($4, 0)
771 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
772
773 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
774 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
775
776 #define read_c0_wired() __read_32bit_c0_register($6, 0)
777 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
778
779 #define read_c0_info() __read_32bit_c0_register($7, 0)
780
781 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
782 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
783
784 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
785 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
786
787 #define read_c0_count() __read_32bit_c0_register($9, 0)
788 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
789
790 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
791 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
792
793 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
794 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
795
796 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
797 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
798
799 #define read_c0_compare() __read_32bit_c0_register($11, 0)
800 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
801
802 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
803 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
804
805 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
806 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
807
808 #define read_c0_status() __read_32bit_c0_register($12, 0)
809 #ifdef CONFIG_MIPS_MT_SMTC
810 #define write_c0_status(val) \
811 do { \
812 __write_32bit_c0_register($12, 0, val); \
813 __ehb(); \
814 } while (0)
815 #else
816 /*
817 * Legacy non-SMTC code, which may be hazardous
818 * but which might not support EHB
819 */
820 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
821 #endif /* CONFIG_MIPS_MT_SMTC */
822
823 #define read_c0_cause() __read_32bit_c0_register($13, 0)
824 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
825
826 #define read_c0_epc() __read_ulong_c0_register($14, 0)
827 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
828
829 #define read_c0_prid() __read_32bit_c0_register($15, 0)
830
831 #define read_c0_config() __read_32bit_c0_register($16, 0)
832 #define read_c0_config1() __read_32bit_c0_register($16, 1)
833 #define read_c0_config2() __read_32bit_c0_register($16, 2)
834 #define read_c0_config3() __read_32bit_c0_register($16, 3)
835 #define read_c0_config4() __read_32bit_c0_register($16, 4)
836 #define read_c0_config5() __read_32bit_c0_register($16, 5)
837 #define read_c0_config6() __read_32bit_c0_register($16, 6)
838 #define read_c0_config7() __read_32bit_c0_register($16, 7)
839 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
840 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
841 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
842 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
843 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
844 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
845 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
846 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
847
848 /*
849 * The WatchLo register. There may be upto 8 of them.
850 */
851 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
852 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
853 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
854 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
855 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
856 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
857 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
858 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
859 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
860 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
861 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
862 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
863 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
864 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
865 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
866 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
867
868 /*
869 * The WatchHi register. There may be upto 8 of them.
870 */
871 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
872 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
873 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
874 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
875 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
876 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
877 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
878 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
879
880 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
881 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
882 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
883 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
884 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
885 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
886 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
887 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
888
889 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
890 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
891
892 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
893 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
894
895 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
896 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
897
898 /* RM9000 PerfControl performance counter control register */
899 #define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
900 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
901
902 #define read_c0_diag() __read_32bit_c0_register($22, 0)
903 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
904
905 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
906 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
907
908 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
909 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
910
911 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
912 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
913
914 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
915 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
916
917 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
918 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
919
920 #define read_c0_debug() __read_32bit_c0_register($23, 0)
921 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
922
923 #define read_c0_depc() __read_ulong_c0_register($24, 0)
924 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
925
926 /*
927 * MIPS32 / MIPS64 performance counters
928 */
929 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
930 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
931 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
932 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
933 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
934 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
935 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
936 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
937 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
938 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
939 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
940 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
941 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
942 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
943 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
944 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
945
946 /* RM9000 PerfCount performance counter register */
947 #define read_c0_perfcount() __read_64bit_c0_register($25, 0)
948 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
949
950 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
951 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
952
953 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
954 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
955
956 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
957
958 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
959 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
960
961 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
962 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
963
964 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
965 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
966
967 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
968 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
969
970 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
971 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
972
973 /* MIPSR2 */
974 #define read_c0_hwrena() __read_32bit_c0_register($7,0)
975 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
976
977 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
978 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
979
980 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
981 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
982
983 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
984 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
985
986 #define read_c0_ebase() __read_32bit_c0_register($15,1)
987 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
988
989 /*
990 * Macros to access the floating point coprocessor control registers
991 */
992 #define read_32bit_cp1_register(source) \
993 ({ int __res; \
994 __asm__ __volatile__( \
995 ".set\tpush\n\t" \
996 ".set\treorder\n\t" \
997 "cfc1\t%0,"STR(source)"\n\t" \
998 ".set\tpop" \
999 : "=r" (__res)); \
1000 __res;})
1001
1002 #define rddsp(mask) \
1003 ({ \
1004 unsigned int __res; \
1005 \
1006 __asm__ __volatile__( \
1007 " .set push \n" \
1008 " .set noat \n" \
1009 " # rddsp $1, %x1 \n" \
1010 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1011 " move %0, $1 \n" \
1012 " .set pop \n" \
1013 : "=r" (__res) \
1014 : "i" (mask)); \
1015 __res; \
1016 })
1017
1018 #define wrdsp(val, mask) \
1019 do { \
1020 __asm__ __volatile__( \
1021 " .set push \n" \
1022 " .set noat \n" \
1023 " move $1, %0 \n" \
1024 " # wrdsp $1, %x1 \n" \
1025 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1026 " .set pop \n" \
1027 : \
1028 : "r" (val), "i" (mask)); \
1029 } while (0)
1030
1031 #if 0 /* Need DSP ASE capable assembler ... */
1032 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1033 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1034 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1035 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1036
1037 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1038 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1039 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1040 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1041
1042 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1043 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1044 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1045 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1046
1047 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1048 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1049 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1050 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1051
1052 #else
1053
1054 #define mfhi0() \
1055 ({ \
1056 unsigned long __treg; \
1057 \
1058 __asm__ __volatile__( \
1059 " .set push \n" \
1060 " .set noat \n" \
1061 " # mfhi %0, $ac0 \n" \
1062 " .word 0x00000810 \n" \
1063 " move %0, $1 \n" \
1064 " .set pop \n" \
1065 : "=r" (__treg)); \
1066 __treg; \
1067 })
1068
1069 #define mfhi1() \
1070 ({ \
1071 unsigned long __treg; \
1072 \
1073 __asm__ __volatile__( \
1074 " .set push \n" \
1075 " .set noat \n" \
1076 " # mfhi %0, $ac1 \n" \
1077 " .word 0x00200810 \n" \
1078 " move %0, $1 \n" \
1079 " .set pop \n" \
1080 : "=r" (__treg)); \
1081 __treg; \
1082 })
1083
1084 #define mfhi2() \
1085 ({ \
1086 unsigned long __treg; \
1087 \
1088 __asm__ __volatile__( \
1089 " .set push \n" \
1090 " .set noat \n" \
1091 " # mfhi %0, $ac2 \n" \
1092 " .word 0x00400810 \n" \
1093 " move %0, $1 \n" \
1094 " .set pop \n" \
1095 : "=r" (__treg)); \
1096 __treg; \
1097 })
1098
1099 #define mfhi3() \
1100 ({ \
1101 unsigned long __treg; \
1102 \
1103 __asm__ __volatile__( \
1104 " .set push \n" \
1105 " .set noat \n" \
1106 " # mfhi %0, $ac3 \n" \
1107 " .word 0x00600810 \n" \
1108 " move %0, $1 \n" \
1109 " .set pop \n" \
1110 : "=r" (__treg)); \
1111 __treg; \
1112 })
1113
1114 #define mflo0() \
1115 ({ \
1116 unsigned long __treg; \
1117 \
1118 __asm__ __volatile__( \
1119 " .set push \n" \
1120 " .set noat \n" \
1121 " # mflo %0, $ac0 \n" \
1122 " .word 0x00000812 \n" \
1123 " move %0, $1 \n" \
1124 " .set pop \n" \
1125 : "=r" (__treg)); \
1126 __treg; \
1127 })
1128
1129 #define mflo1() \
1130 ({ \
1131 unsigned long __treg; \
1132 \
1133 __asm__ __volatile__( \
1134 " .set push \n" \
1135 " .set noat \n" \
1136 " # mflo %0, $ac1 \n" \
1137 " .word 0x00200812 \n" \
1138 " move %0, $1 \n" \
1139 " .set pop \n" \
1140 : "=r" (__treg)); \
1141 __treg; \
1142 })
1143
1144 #define mflo2() \
1145 ({ \
1146 unsigned long __treg; \
1147 \
1148 __asm__ __volatile__( \
1149 " .set push \n" \
1150 " .set noat \n" \
1151 " # mflo %0, $ac2 \n" \
1152 " .word 0x00400812 \n" \
1153 " move %0, $1 \n" \
1154 " .set pop \n" \
1155 : "=r" (__treg)); \
1156 __treg; \
1157 })
1158
1159 #define mflo3() \
1160 ({ \
1161 unsigned long __treg; \
1162 \
1163 __asm__ __volatile__( \
1164 " .set push \n" \
1165 " .set noat \n" \
1166 " # mflo %0, $ac3 \n" \
1167 " .word 0x00600812 \n" \
1168 " move %0, $1 \n" \
1169 " .set pop \n" \
1170 : "=r" (__treg)); \
1171 __treg; \
1172 })
1173
1174 #define mthi0(x) \
1175 do { \
1176 __asm__ __volatile__( \
1177 " .set push \n" \
1178 " .set noat \n" \
1179 " move $1, %0 \n" \
1180 " # mthi $1, $ac0 \n" \
1181 " .word 0x00200011 \n" \
1182 " .set pop \n" \
1183 : \
1184 : "r" (x)); \
1185 } while (0)
1186
1187 #define mthi1(x) \
1188 do { \
1189 __asm__ __volatile__( \
1190 " .set push \n" \
1191 " .set noat \n" \
1192 " move $1, %0 \n" \
1193 " # mthi $1, $ac1 \n" \
1194 " .word 0x00200811 \n" \
1195 " .set pop \n" \
1196 : \
1197 : "r" (x)); \
1198 } while (0)
1199
1200 #define mthi2(x) \
1201 do { \
1202 __asm__ __volatile__( \
1203 " .set push \n" \
1204 " .set noat \n" \
1205 " move $1, %0 \n" \
1206 " # mthi $1, $ac2 \n" \
1207 " .word 0x00201011 \n" \
1208 " .set pop \n" \
1209 : \
1210 : "r" (x)); \
1211 } while (0)
1212
1213 #define mthi3(x) \
1214 do { \
1215 __asm__ __volatile__( \
1216 " .set push \n" \
1217 " .set noat \n" \
1218 " move $1, %0 \n" \
1219 " # mthi $1, $ac3 \n" \
1220 " .word 0x00201811 \n" \
1221 " .set pop \n" \
1222 : \
1223 : "r" (x)); \
1224 } while (0)
1225
1226 #define mtlo0(x) \
1227 do { \
1228 __asm__ __volatile__( \
1229 " .set push \n" \
1230 " .set noat \n" \
1231 " move $1, %0 \n" \
1232 " # mtlo $1, $ac0 \n" \
1233 " .word 0x00200013 \n" \
1234 " .set pop \n" \
1235 : \
1236 : "r" (x)); \
1237 } while (0)
1238
1239 #define mtlo1(x) \
1240 do { \
1241 __asm__ __volatile__( \
1242 " .set push \n" \
1243 " .set noat \n" \
1244 " move $1, %0 \n" \
1245 " # mtlo $1, $ac1 \n" \
1246 " .word 0x00200813 \n" \
1247 " .set pop \n" \
1248 : \
1249 : "r" (x)); \
1250 } while (0)
1251
1252 #define mtlo2(x) \
1253 do { \
1254 __asm__ __volatile__( \
1255 " .set push \n" \
1256 " .set noat \n" \
1257 " move $1, %0 \n" \
1258 " # mtlo $1, $ac2 \n" \
1259 " .word 0x00201013 \n" \
1260 " .set pop \n" \
1261 : \
1262 : "r" (x)); \
1263 } while (0)
1264
1265 #define mtlo3(x) \
1266 do { \
1267 __asm__ __volatile__( \
1268 " .set push \n" \
1269 " .set noat \n" \
1270 " move $1, %0 \n" \
1271 " # mtlo $1, $ac3 \n" \
1272 " .word 0x00201813 \n" \
1273 " .set pop \n" \
1274 : \
1275 : "r" (x)); \
1276 } while (0)
1277
1278 #endif
1279
1280 /*
1281 * TLB operations.
1282 *
1283 * It is responsibility of the caller to take care of any TLB hazards.
1284 */
1285 static inline void tlb_probe(void)
1286 {
1287 __asm__ __volatile__(
1288 ".set noreorder\n\t"
1289 "tlbp\n\t"
1290 ".set reorder");
1291 }
1292
1293 static inline void tlb_read(void)
1294 {
1295 __asm__ __volatile__(
1296 ".set noreorder\n\t"
1297 "tlbr\n\t"
1298 ".set reorder");
1299 }
1300
1301 static inline void tlb_write_indexed(void)
1302 {
1303 __asm__ __volatile__(
1304 ".set noreorder\n\t"
1305 "tlbwi\n\t"
1306 ".set reorder");
1307 }
1308
1309 static inline void tlb_write_random(void)
1310 {
1311 __asm__ __volatile__(
1312 ".set noreorder\n\t"
1313 "tlbwr\n\t"
1314 ".set reorder");
1315 }
1316
1317 /*
1318 * Manipulate bits in a c0 register.
1319 */
1320 #ifndef CONFIG_MIPS_MT_SMTC
1321 /*
1322 * SMTC Linux requires shutting-down microthread scheduling
1323 * during CP0 register read-modify-write sequences.
1324 */
1325 #define __BUILD_SET_C0(name) \
1326 static inline unsigned int \
1327 set_c0_##name(unsigned int set) \
1328 { \
1329 unsigned int res; \
1330 \
1331 res = read_c0_##name(); \
1332 res |= set; \
1333 write_c0_##name(res); \
1334 \
1335 return res; \
1336 } \
1337 \
1338 static inline unsigned int \
1339 clear_c0_##name(unsigned int clear) \
1340 { \
1341 unsigned int res; \
1342 \
1343 res = read_c0_##name(); \
1344 res &= ~clear; \
1345 write_c0_##name(res); \
1346 \
1347 return res; \
1348 } \
1349 \
1350 static inline unsigned int \
1351 change_c0_##name(unsigned int change, unsigned int new) \
1352 { \
1353 unsigned int res; \
1354 \
1355 res = read_c0_##name(); \
1356 res &= ~change; \
1357 res |= (new & change); \
1358 write_c0_##name(res); \
1359 \
1360 return res; \
1361 }
1362
1363 #else /* SMTC versions that manage MT scheduling */
1364
1365 #include <linux/irqflags.h>
1366
1367 /*
1368 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1369 * header file recursion.
1370 */
1371 static inline unsigned int __dmt(void)
1372 {
1373 int res;
1374
1375 __asm__ __volatile__(
1376 " .set push \n"
1377 " .set mips32r2 \n"
1378 " .set noat \n"
1379 " .word 0x41610BC1 # dmt $1 \n"
1380 " ehb \n"
1381 " move %0, $1 \n"
1382 " .set pop \n"
1383 : "=r" (res));
1384
1385 instruction_hazard();
1386
1387 return res;
1388 }
1389
1390 #define __VPECONTROL_TE_SHIFT 15
1391 #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT)
1392
1393 #define __EMT_ENABLE __VPECONTROL_TE
1394
1395 static inline void __emt(unsigned int previous)
1396 {
1397 if ((previous & __EMT_ENABLE))
1398 __asm__ __volatile__(
1399 " .set mips32r2 \n"
1400 " .word 0x41600be1 # emt \n"
1401 " ehb \n"
1402 " .set mips0 \n");
1403 }
1404
1405 static inline void __ehb(void)
1406 {
1407 __asm__ __volatile__(
1408 " .set mips32r2 \n"
1409 " ehb \n" " .set mips0 \n");
1410 }
1411
1412 /*
1413 * Note that local_irq_save/restore affect TC-specific IXMT state,
1414 * not Status.IE as in non-SMTC kernel.
1415 */
1416
1417 #define __BUILD_SET_C0(name) \
1418 static inline unsigned int \
1419 set_c0_##name(unsigned int set) \
1420 { \
1421 unsigned int res; \
1422 unsigned int omt; \
1423 unsigned int flags; \
1424 \
1425 local_irq_save(flags); \
1426 omt = __dmt(); \
1427 res = read_c0_##name(); \
1428 res |= set; \
1429 write_c0_##name(res); \
1430 __emt(omt); \
1431 local_irq_restore(flags); \
1432 \
1433 return res; \
1434 } \
1435 \
1436 static inline unsigned int \
1437 clear_c0_##name(unsigned int clear) \
1438 { \
1439 unsigned int res; \
1440 unsigned int omt; \
1441 unsigned int flags; \
1442 \
1443 local_irq_save(flags); \
1444 omt = __dmt(); \
1445 res = read_c0_##name(); \
1446 res &= ~clear; \
1447 write_c0_##name(res); \
1448 __emt(omt); \
1449 local_irq_restore(flags); \
1450 \
1451 return res; \
1452 } \
1453 \
1454 static inline unsigned int \
1455 change_c0_##name(unsigned int change, unsigned int new) \
1456 { \
1457 unsigned int res; \
1458 unsigned int omt; \
1459 unsigned int flags; \
1460 \
1461 local_irq_save(flags); \
1462 \
1463 omt = __dmt(); \
1464 res = read_c0_##name(); \
1465 res &= ~change; \
1466 res |= (new & change); \
1467 write_c0_##name(res); \
1468 __emt(omt); \
1469 local_irq_restore(flags); \
1470 \
1471 return res; \
1472 }
1473 #endif
1474
1475 __BUILD_SET_C0(status)
1476 __BUILD_SET_C0(cause)
1477 __BUILD_SET_C0(config)
1478 __BUILD_SET_C0(intcontrol)
1479 __BUILD_SET_C0(intctl)
1480 __BUILD_SET_C0(srsmap)
1481
1482 #endif /* !__ASSEMBLY__ */
1483
1484 #endif /* _ASM_MIPSREGS_H */
Linux with added FPC-III support