include/asm-mips/tx4938/tx4938.h

   1 /*
   2  * linux/include/asm-mips/tx4938/tx4938.h
   3  * Definitions for TX4937/TX4938
   4  * Copyright (C) 2000-2001 Toshiba Corporation
   5  *
   6  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
   7  * terms of the GNU General Public License version 2. This program is
   8  * licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  *
  11  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  12  */
  13 #ifndef __ASM_TX_BOARDS_TX4938_H
  14 #define __ASM_TX_BOARDS_TX4938_H
  15
  16 #include <asm/tx4938/tx4938_mips.h>
  17
  18 #define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
  19 #define tx4938_write_nfmc(b,addr) (*(volatile unsigned int *)(addr)) = (b)
  20
  21 #define TX4938_NR_IRQ_LOCAL     TX4938_IRQ_PIC_BEG
  22
  23 #define TX4938_IRQ_IRC_PCIC     (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC)
  24 #define TX4938_IRQ_IRC_PCIERR   (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR)
  25
  26 #define TX4938_PCIIO_0 0x10000000
  27 #define TX4938_PCIIO_1 0x01010000
  28 #define TX4938_PCIMEM_0 0x08000000
  29 #define TX4938_PCIMEM_1 0x11000000
  30
  31 #define TX4938_PCIIO_SIZE_0 0x01000000
  32 #define TX4938_PCIIO_SIZE_1 0x00010000
  33 #define TX4938_PCIMEM_SIZE_0 0x08000000
  34 #define TX4938_PCIMEM_SIZE_1 0x00010000
  35
  36 #define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
  37 #define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
  38
  39 /* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
  40 #define TX4938_NDFMC_REG        (TX4938_REG_BASE + 0x5000)
  41 #define TX4938_SRAMC_REG        (TX4938_REG_BASE + 0x6000)
  42 #define TX4938_PCIC1_REG        (TX4938_REG_BASE + 0x7000)
  43 #define TX4938_SDRAMC_REG       (TX4938_REG_BASE + 0x8000)
  44 #define TX4938_EBUSC_REG        (TX4938_REG_BASE + 0x9000)
  45 #define TX4938_DMA_REG(ch)      (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
  46 #define TX4938_PCIC_REG         (TX4938_REG_BASE + 0xd000)
  47 #define TX4938_CCFG_REG         (TX4938_REG_BASE + 0xe000)
  48 #define TX4938_NR_TMR   3
  49 #define TX4938_TMR_REG(ch)      ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
  50 #define TX4938_NR_SIO   2
  51 #define TX4938_SIO_REG(ch)      ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
  52 #define TX4938_PIO_REG          (TX4938_REG_BASE + 0xf500)
  53 #define TX4938_IRC_REG          (TX4938_REG_BASE + 0xf600)
  54 #define TX4938_ACLC_REG         (TX4938_REG_BASE + 0xf700)
  55 #define TX4938_SPI_REG          (TX4938_REG_BASE + 0xf800)
  56
  57 #ifndef _LANGUAGE_ASSEMBLY
  58 #include <asm/byteorder.h>
  59
  60 #define TX4938_MKA(x) ((u32)( ((u32)(TX4938_REG_BASE)) | ((u32)(x)) ))
  61
  62 #define TX4938_RD08( reg      )   (*(vu08*)(reg))
  63 #define TX4938_WR08( reg, val )  ((*(vu08*)(reg))=(val))
  64
  65 #define TX4938_RD16( reg      )   (*(vu16*)(reg))
  66 #define TX4938_WR16( reg, val )  ((*(vu16*)(reg))=(val))
  67
  68 #define TX4938_RD32( reg      )   (*(vu32*)(reg))
  69 #define TX4938_WR32( reg, val )  ((*(vu32*)(reg))=(val))
  70
  71 #define TX4938_RD64( reg      )   (*(vu64*)(reg))
  72 #define TX4938_WR64( reg, val )  ((*(vu64*)(reg))=(val))
  73
  74 #define TX4938_RD( reg      ) TX4938_RD32( reg )
  75 #define TX4938_WR( reg, val ) TX4938_WR32( reg, val )
  76
  77 #endif /* !__ASSEMBLY__ */
  78
  79 #ifdef __ASSEMBLY__
  80 #define _CONST64(c)     c
  81 #else
  82 #define _CONST64(c)     c##ull
  83
  84 #include <asm/byteorder.h>
  85
  86 #ifdef __BIG_ENDIAN
  87 #define endian_def_l2(e1,e2)    \
  88         volatile unsigned long e1,e2
  89 #define endian_def_s2(e1,e2)    \
  90         volatile unsigned short e1,e2
  91 #define endian_def_sb2(e1,e2,e3)        \
  92         volatile unsigned short e1;volatile unsigned char e2,e3
  93 #define endian_def_b2s(e1,e2,e3)        \
  94         volatile unsigned char e1,e2;volatile unsigned short e3
  95 #define endian_def_b4(e1,e2,e3,e4)      \
  96         volatile unsigned char e1,e2,e3,e4
  97 #else
  98 #define endian_def_l2(e1,e2)    \
  99         volatile unsigned long e2,e1
 100 #define endian_def_s2(e1,e2)    \
 101         volatile unsigned short e2,e1
 102 #define endian_def_sb2(e1,e2,e3)        \
 103         volatile unsigned char e3,e2;volatile unsigned short e1
 104 #define endian_def_b2s(e1,e2,e3)        \
 105         volatile unsigned short e3;volatile unsigned char e2,e1
 106 #define endian_def_b4(e1,e2,e3,e4)      \
 107         volatile unsigned char e4,e3,e2,e1
 108 #endif
 109
 110
 111 struct tx4938_sdramc_reg {
 112         volatile unsigned long long cr[4];
 113         volatile unsigned long long unused0[4];
 114         volatile unsigned long long tr;
 115         volatile unsigned long long unused1[2];
 116         volatile unsigned long long cmd;
 117         volatile unsigned long long sfcmd;
 118 };
 119
 120 struct tx4938_ebusc_reg {
 121         volatile unsigned long long cr[8];
 122 };
 123
 124 struct tx4938_dma_reg {
 125         struct tx4938_dma_ch_reg {
 126                 volatile unsigned long long cha;
 127                 volatile unsigned long long sar;
 128                 volatile unsigned long long dar;
 129                 endian_def_l2(unused0, cntr);
 130                 endian_def_l2(unused1, sair);
 131                 endian_def_l2(unused2, dair);
 132                 endian_def_l2(unused3, ccr);
 133                 endian_def_l2(unused4, csr);
 134         } ch[4];
 135         volatile unsigned long long dbr[8];
 136         volatile unsigned long long tdhr;
 137         volatile unsigned long long midr;
 138         endian_def_l2(unused0, mcr);
 139 };
 140
 141 struct tx4938_pcic_reg {
 142         volatile unsigned long pciid;
 143         volatile unsigned long pcistatus;
 144         volatile unsigned long pciccrev;
 145         volatile unsigned long pcicfg1;
 146         volatile unsigned long p2gm0plbase;             /* +10 */
 147         volatile unsigned long p2gm0pubase;
 148         volatile unsigned long p2gm1plbase;
 149         volatile unsigned long p2gm1pubase;
 150         volatile unsigned long p2gm2pbase;              /* +20 */
 151         volatile unsigned long p2giopbase;
 152         volatile unsigned long unused0;
 153         volatile unsigned long pcisid;
 154         volatile unsigned long unused1;         /* +30 */
 155         volatile unsigned long pcicapptr;
 156         volatile unsigned long unused2;
 157         volatile unsigned long pcicfg2;
 158         volatile unsigned long g2ptocnt;                /* +40 */
 159         volatile unsigned long unused3[15];
 160         volatile unsigned long g2pstatus;               /* +80 */
 161         volatile unsigned long g2pmask;
 162         volatile unsigned long pcisstatus;
 163         volatile unsigned long pcimask;
 164         volatile unsigned long p2gcfg;          /* +90 */
 165         volatile unsigned long p2gstatus;
 166         volatile unsigned long p2gmask;
 167         volatile unsigned long p2gccmd;
 168         volatile unsigned long unused4[24];             /* +a0 */
 169         volatile unsigned long pbareqport;              /* +100 */
 170         volatile unsigned long pbacfg;
 171         volatile unsigned long pbastatus;
 172         volatile unsigned long pbamask;
 173         volatile unsigned long pbabm;           /* +110 */
 174         volatile unsigned long pbacreq;
 175         volatile unsigned long pbacgnt;
 176         volatile unsigned long pbacstate;
 177         volatile unsigned long long g2pmgbase[3];               /* +120 */
 178         volatile unsigned long long g2piogbase;
 179         volatile unsigned long g2pmmask[3];             /* +140 */
 180         volatile unsigned long g2piomask;
 181         volatile unsigned long long g2pmpbase[3];               /* +150 */
 182         volatile unsigned long long g2piopbase;
 183         volatile unsigned long pciccfg;         /* +170 */
 184         volatile unsigned long pcicstatus;
 185         volatile unsigned long pcicmask;
 186         volatile unsigned long unused5;
 187         volatile unsigned long long p2gmgbase[3];               /* +180 */
 188         volatile unsigned long long p2giogbase;
 189         volatile unsigned long g2pcfgadrs;              /* +1a0 */
 190         volatile unsigned long g2pcfgdata;
 191         volatile unsigned long unused6[8];
 192         volatile unsigned long g2pintack;
 193         volatile unsigned long g2pspc;
 194         volatile unsigned long unused7[12];             /* +1d0 */
 195         volatile unsigned long long pdmca;              /* +200 */
 196         volatile unsigned long long pdmga;
 197         volatile unsigned long long pdmpa;
 198         volatile unsigned long long pdmctr;
 199         volatile unsigned long long pdmcfg;             /* +220 */
 200         volatile unsigned long long pdmsts;
 201 };
 202
 203 struct tx4938_aclc_reg {
 204         volatile unsigned long acctlen;
 205         volatile unsigned long acctldis;
 206         volatile unsigned long acregacc;
 207         volatile unsigned long unused0;
 208         volatile unsigned long acintsts;
 209         volatile unsigned long acintmsts;
 210         volatile unsigned long acinten;
 211         volatile unsigned long acintdis;
 212         volatile unsigned long acsemaph;
 213         volatile unsigned long unused1[7];
 214         volatile unsigned long acgpidat;
 215         volatile unsigned long acgpodat;
 216         volatile unsigned long acslten;
 217         volatile unsigned long acsltdis;
 218         volatile unsigned long acfifosts;
 219         volatile unsigned long unused2[11];
 220         volatile unsigned long acdmasts;
 221         volatile unsigned long acdmasel;
 222         volatile unsigned long unused3[6];
 223         volatile unsigned long acaudodat;
 224         volatile unsigned long acsurrdat;
 225         volatile unsigned long accentdat;
 226         volatile unsigned long aclfedat;
 227         volatile unsigned long acaudiat;
 228         volatile unsigned long unused4;
 229         volatile unsigned long acmodoat;
 230         volatile unsigned long acmodidat;
 231         volatile unsigned long unused5[15];
 232         volatile unsigned long acrevid;
 233 };
 234
 235
 236 struct tx4938_tmr_reg {
 237         volatile unsigned long tcr;
 238         volatile unsigned long tisr;
 239         volatile unsigned long cpra;
 240         volatile unsigned long cprb;
 241         volatile unsigned long itmr;
 242         volatile unsigned long unused0[3];
 243         volatile unsigned long ccdr;
 244         volatile unsigned long unused1[3];
 245         volatile unsigned long pgmr;
 246         volatile unsigned long unused2[3];
 247         volatile unsigned long wtmr;
 248         volatile unsigned long unused3[43];
 249         volatile unsigned long trr;
 250 };
 251
 252 struct tx4938_sio_reg {
 253         volatile unsigned long lcr;
 254         volatile unsigned long dicr;
 255         volatile unsigned long disr;
 256         volatile unsigned long cisr;
 257         volatile unsigned long fcr;
 258         volatile unsigned long flcr;
 259         volatile unsigned long bgr;
 260         volatile unsigned long tfifo;
 261         volatile unsigned long rfifo;
 262 };
 263
 264 struct tx4938_pio_reg {
 265         volatile unsigned long dout;
 266         volatile unsigned long din;
 267         volatile unsigned long dir;
 268         volatile unsigned long od;
 269         volatile unsigned long flag[2];
 270         volatile unsigned long pol;
 271         volatile unsigned long intc;
 272         volatile unsigned long maskcpu;
 273         volatile unsigned long maskext;
 274 };
 275 struct tx4938_irc_reg {
 276         volatile unsigned long cer;
 277         volatile unsigned long cr[2];
 278         volatile unsigned long unused0;
 279         volatile unsigned long ilr[8];
 280         volatile unsigned long unused1[4];
 281         volatile unsigned long imr;
 282         volatile unsigned long unused2[7];
 283         volatile unsigned long scr;
 284         volatile unsigned long unused3[7];
 285         volatile unsigned long ssr;
 286         volatile unsigned long unused4[7];
 287         volatile unsigned long csr;
 288 };
 289
 290 struct tx4938_ndfmc_reg {
 291         endian_def_l2(unused0, dtr);
 292         endian_def_l2(unused1, mcr);
 293         endian_def_l2(unused2, sr);
 294         endian_def_l2(unused3, isr);
 295         endian_def_l2(unused4, imr);
 296         endian_def_l2(unused5, spr);
 297         endian_def_l2(unused6, rstr);
 298 };
 299
 300 struct tx4938_spi_reg {
 301         volatile unsigned long mcr;
 302         volatile unsigned long cr0;
 303         volatile unsigned long cr1;
 304         volatile unsigned long fs;
 305         volatile unsigned long unused1;
 306         volatile unsigned long sr;
 307         volatile unsigned long dr;
 308         volatile unsigned long unused2;
 309 };
 310
 311 struct tx4938_sramc_reg {
 312         volatile unsigned long long cr;
 313 };
 314
 315 struct tx4938_ccfg_reg {
 316         volatile unsigned long long ccfg;
 317         volatile unsigned long long crir;
 318         volatile unsigned long long pcfg;
 319         volatile unsigned long long tear;
 320         volatile unsigned long long clkctr;
 321         volatile unsigned long long unused0;
 322         volatile unsigned long long garbc;
 323         volatile unsigned long long unused1;
 324         volatile unsigned long long unused2;
 325         volatile unsigned long long ramp;
 326         volatile unsigned long long unused3;
 327         volatile unsigned long long jmpadr;
 328 };
 329
 330 #undef endian_def_l2
 331 #undef endian_def_s2
 332 #undef endian_def_sb2
 333 #undef endian_def_b2s
 334 #undef endian_def_b4
 335
 336 #endif /* __ASSEMBLY__ */
 337
 338 /*
 339  * NDFMC
 340  */
 341
 342 /* NDFMCR : NDFMC Mode Control */
 343 #define TX4938_NDFMCR_WE        0x80
 344 #define TX4938_NDFMCR_ECC_ALL   0x60
 345 #define TX4938_NDFMCR_ECC_RESET 0x60
 346 #define TX4938_NDFMCR_ECC_READ  0x40
 347 #define TX4938_NDFMCR_ECC_ON    0x20
 348 #define TX4938_NDFMCR_ECC_OFF   0x00
 349 #define TX4938_NDFMCR_CE        0x10
 350 #define TX4938_NDFMCR_BSPRT     0x04
 351 #define TX4938_NDFMCR_ALE       0x02
 352 #define TX4938_NDFMCR_CLE       0x01
 353
 354 /* NDFMCR : NDFMC Status */
 355 #define TX4938_NDFSR_BUSY       0x80
 356
 357 /* NDFMCR : NDFMC Reset */
 358 #define TX4938_NDFRSTR_RST      0x01
 359
 360 /*
 361  * IRC
 362  */
 363
 364 #define TX4938_IR_ECCERR        0
 365 #define TX4938_IR_WTOERR        1
 366 #define TX4938_NUM_IR_INT       6
 367 #define TX4938_IR_INT(n)        (2 + (n))
 368 #define TX4938_NUM_IR_SIO       2
 369 #define TX4938_IR_SIO(n)        (8 + (n))
 370 #define TX4938_NUM_IR_DMA       4
 371 #define TX4938_IR_DMA(ch,n)     ((ch ? 27 : 10) + (n)) /* 10-13,27-30 */
 372 #define TX4938_IR_PIO   14
 373 #define TX4938_IR_PDMAC 15
 374 #define TX4938_IR_PCIC  16
 375 #define TX4938_NUM_IR_TMR       3
 376 #define TX4938_IR_TMR(n)        (17 + (n))
 377 #define TX4938_IR_NDFMC 21
 378 #define TX4938_IR_PCIERR        22
 379 #define TX4938_IR_PCIPME        23
 380 #define TX4938_IR_ACLC  24
 381 #define TX4938_IR_ACLCPME       25
 382 #define TX4938_IR_PCIC1 26
 383 #define TX4938_IR_SPI   31
 384 #define TX4938_NUM_IR   32
 385 /* multiplex */
 386 #define TX4938_IR_ETH0  TX4938_IR_INT(4)
 387 #define TX4938_IR_ETH1  TX4938_IR_INT(3)
 388
 389 /*
 390  * CCFG
 391  */
 392 /* CCFG : Chip Configuration */
 393 #define TX4938_CCFG_WDRST       _CONST64(0x0000020000000000)
 394 #define TX4938_CCFG_WDREXEN     _CONST64(0x0000010000000000)
 395 #define TX4938_CCFG_BCFG_MASK   _CONST64(0x000000ff00000000)
 396 #define TX4938_CCFG_TINTDIS     0x01000000
 397 #define TX4938_CCFG_PCI66       0x00800000
 398 #define TX4938_CCFG_PCIMODE     0x00400000
 399 #define TX4938_CCFG_PCI1_66     0x00200000
 400 #define TX4938_CCFG_DIVMODE_MASK        0x001e0000
 401 #define TX4938_CCFG_DIVMODE_2   (0x4 << 17)
 402 #define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
 403 #define TX4938_CCFG_DIVMODE_3   (0x5 << 17)
 404 #define TX4938_CCFG_DIVMODE_4   (0x6 << 17)
 405 #define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
 406 #define TX4938_CCFG_DIVMODE_8   (0x0 << 17)
 407 #define TX4938_CCFG_DIVMODE_10  (0xb << 17)
 408 #define TX4938_CCFG_DIVMODE_12  (0x1 << 17)
 409 #define TX4938_CCFG_DIVMODE_16  (0x2 << 17)
 410 #define TX4938_CCFG_DIVMODE_18  (0x9 << 17)
 411 #define TX4938_CCFG_BEOW        0x00010000
 412 #define TX4938_CCFG_WR  0x00008000
 413 #define TX4938_CCFG_TOE 0x00004000
 414 #define TX4938_CCFG_PCIXARB     0x00002000
 415 #define TX4938_CCFG_PCIDIVMODE_MASK     0x00001c00
 416 #define TX4938_CCFG_PCIDIVMODE_4        (0x1 << 10)
 417 #define TX4938_CCFG_PCIDIVMODE_4_5      (0x3 << 10)
 418 #define TX4938_CCFG_PCIDIVMODE_5        (0x5 << 10)
 419 #define TX4938_CCFG_PCIDIVMODE_5_5      (0x7 << 10)
 420 #define TX4938_CCFG_PCIDIVMODE_8        (0x0 << 10)
 421 #define TX4938_CCFG_PCIDIVMODE_9        (0x2 << 10)
 422 #define TX4938_CCFG_PCIDIVMODE_10       (0x4 << 10)
 423 #define TX4938_CCFG_PCIDIVMODE_11       (0x6 << 10)
 424 #define TX4938_CCFG_PCI1DMD     0x00000100
 425 #define TX4938_CCFG_SYSSP_MASK  0x000000c0
 426 #define TX4938_CCFG_ENDIAN      0x00000004
 427 #define TX4938_CCFG_HALT        0x00000002
 428 #define TX4938_CCFG_ACEHOLD     0x00000001
 429
 430 /* PCFG : Pin Configuration */
 431 #define TX4938_PCFG_ETH0_SEL    _CONST64(0x8000000000000000)
 432 #define TX4938_PCFG_ETH1_SEL    _CONST64(0x4000000000000000)
 433 #define TX4938_PCFG_ATA_SEL     _CONST64(0x2000000000000000)
 434 #define TX4938_PCFG_ISA_SEL     _CONST64(0x1000000000000000)
 435 #define TX4938_PCFG_SPI_SEL     _CONST64(0x0800000000000000)
 436 #define TX4938_PCFG_NDF_SEL     _CONST64(0x0400000000000000)
 437 #define TX4938_PCFG_SDCLKDLY_MASK       0x30000000
 438 #define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
 439 #define TX4938_PCFG_SYSCLKEN    0x08000000
 440 #define TX4938_PCFG_SDCLKEN_ALL 0x07800000
 441 #define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
 442 #define TX4938_PCFG_PCICLKEN_ALL        0x003f0000
 443 #define TX4938_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
 444 #define TX4938_PCFG_SEL2        0x00000200
 445 #define TX4938_PCFG_SEL1        0x00000100
 446 #define TX4938_PCFG_DMASEL_ALL  0x0000000f
 447 #define TX4938_PCFG_DMASEL0_DRQ0        0x00000000
 448 #define TX4938_PCFG_DMASEL0_SIO1        0x00000001
 449 #define TX4938_PCFG_DMASEL1_DRQ1        0x00000000
 450 #define TX4938_PCFG_DMASEL1_SIO1        0x00000002
 451 #define TX4938_PCFG_DMASEL2_DRQ2        0x00000000
 452 #define TX4938_PCFG_DMASEL2_SIO0        0x00000004
 453 #define TX4938_PCFG_DMASEL3_DRQ3        0x00000000
 454 #define TX4938_PCFG_DMASEL3_SIO0        0x00000008
 455
 456 /* CLKCTR : Clock Control */
 457 #define TX4938_CLKCTR_NDFCKD    _CONST64(0x0001000000000000)
 458 #define TX4938_CLKCTR_NDFRST    _CONST64(0x0000000100000000)
 459 #define TX4938_CLKCTR_ETH1CKD   0x80000000
 460 #define TX4938_CLKCTR_ETH0CKD   0x40000000
 461 #define TX4938_CLKCTR_SPICKD    0x20000000
 462 #define TX4938_CLKCTR_SRAMCKD   0x10000000
 463 #define TX4938_CLKCTR_PCIC1CKD  0x08000000
 464 #define TX4938_CLKCTR_DMA1CKD   0x04000000
 465 #define TX4938_CLKCTR_ACLCKD    0x02000000
 466 #define TX4938_CLKCTR_PIOCKD    0x01000000
 467 #define TX4938_CLKCTR_DMACKD    0x00800000
 468 #define TX4938_CLKCTR_PCICKD    0x00400000
 469 #define TX4938_CLKCTR_TM0CKD    0x00100000
 470 #define TX4938_CLKCTR_TM1CKD    0x00080000
 471 #define TX4938_CLKCTR_TM2CKD    0x00040000
 472 #define TX4938_CLKCTR_SIO0CKD   0x00020000
 473 #define TX4938_CLKCTR_SIO1CKD   0x00010000
 474 #define TX4938_CLKCTR_ETH1RST   0x00008000
 475 #define TX4938_CLKCTR_ETH0RST   0x00004000
 476 #define TX4938_CLKCTR_SPIRST    0x00002000
 477 #define TX4938_CLKCTR_SRAMRST   0x00001000
 478 #define TX4938_CLKCTR_PCIC1RST  0x00000800
 479 #define TX4938_CLKCTR_DMA1RST   0x00000400
 480 #define TX4938_CLKCTR_ACLRST    0x00000200
 481 #define TX4938_CLKCTR_PIORST    0x00000100
 482 #define TX4938_CLKCTR_DMARST    0x00000080
 483 #define TX4938_CLKCTR_PCIRST    0x00000040
 484 #define TX4938_CLKCTR_TM0RST    0x00000010
 485 #define TX4938_CLKCTR_TM1RST    0x00000008
 486 #define TX4938_CLKCTR_TM2RST    0x00000004
 487 #define TX4938_CLKCTR_SIO0RST   0x00000002
 488 #define TX4938_CLKCTR_SIO1RST   0x00000001
 489
 490 /* bits for G2PSTATUS/G2PMASK */
 491 #define TX4938_PCIC_G2PSTATUS_ALL       0x00000003
 492 #define TX4938_PCIC_G2PSTATUS_TTOE      0x00000002
 493 #define TX4938_PCIC_G2PSTATUS_RTOE      0x00000001
 494
 495 /* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
 496 #define TX4938_PCIC_PCISTATUS_ALL       0x0000f900
 497
 498 /* bits for PBACFG */
 499 #define TX4938_PCIC_PBACFG_FIXPA        0x00000008
 500 #define TX4938_PCIC_PBACFG_RPBA 0x00000004
 501 #define TX4938_PCIC_PBACFG_PBAEN        0x00000002
 502 #define TX4938_PCIC_PBACFG_BMCEN        0x00000001
 503
 504 /* bits for G2PMnGBASE */
 505 #define TX4938_PCIC_G2PMnGBASE_BSDIS    _CONST64(0x0000002000000000)
 506 #define TX4938_PCIC_G2PMnGBASE_ECHG     _CONST64(0x0000001000000000)
 507
 508 /* bits for G2PIOGBASE */
 509 #define TX4938_PCIC_G2PIOGBASE_BSDIS    _CONST64(0x0000002000000000)
 510 #define TX4938_PCIC_G2PIOGBASE_ECHG     _CONST64(0x0000001000000000)
 511
 512 /* bits for PCICSTATUS/PCICMASK */
 513 #define TX4938_PCIC_PCICSTATUS_ALL      0x000007b8
 514 #define TX4938_PCIC_PCICSTATUS_PME      0x00000400
 515 #define TX4938_PCIC_PCICSTATUS_TLB      0x00000200
 516 #define TX4938_PCIC_PCICSTATUS_NIB      0x00000100
 517 #define TX4938_PCIC_PCICSTATUS_ZIB      0x00000080
 518 #define TX4938_PCIC_PCICSTATUS_PERR     0x00000020
 519 #define TX4938_PCIC_PCICSTATUS_SERR     0x00000010
 520 #define TX4938_PCIC_PCICSTATUS_GBE      0x00000008
 521 #define TX4938_PCIC_PCICSTATUS_IWB      0x00000002
 522 #define TX4938_PCIC_PCICSTATUS_E2PDONE  0x00000001
 523
 524 /* bits for PCICCFG */
 525 #define TX4938_PCIC_PCICCFG_GBWC_MASK   0x0fff0000
 526 #define TX4938_PCIC_PCICCFG_HRST        0x00000800
 527 #define TX4938_PCIC_PCICCFG_SRST        0x00000400
 528 #define TX4938_PCIC_PCICCFG_IRBER       0x00000200
 529 #define TX4938_PCIC_PCICCFG_G2PMEN(ch)  (0x00000100>>(ch))
 530 #define TX4938_PCIC_PCICCFG_G2PM0EN     0x00000100
 531 #define TX4938_PCIC_PCICCFG_G2PM1EN     0x00000080
 532 #define TX4938_PCIC_PCICCFG_G2PM2EN     0x00000040
 533 #define TX4938_PCIC_PCICCFG_G2PIOEN     0x00000020
 534 #define TX4938_PCIC_PCICCFG_TCAR        0x00000010
 535 #define TX4938_PCIC_PCICCFG_ICAEN       0x00000008
 536
 537 /* bits for P2GMnGBASE */
 538 #define TX4938_PCIC_P2GMnGBASE_TMEMEN   _CONST64(0x0000004000000000)
 539 #define TX4938_PCIC_P2GMnGBASE_TBSDIS   _CONST64(0x0000002000000000)
 540 #define TX4938_PCIC_P2GMnGBASE_TECHG    _CONST64(0x0000001000000000)
 541
 542 /* bits for P2GIOGBASE */
 543 #define TX4938_PCIC_P2GIOGBASE_TIOEN    _CONST64(0x0000004000000000)
 544 #define TX4938_PCIC_P2GIOGBASE_TBSDIS   _CONST64(0x0000002000000000)
 545 #define TX4938_PCIC_P2GIOGBASE_TECHG    _CONST64(0x0000001000000000)
 546
 547 #define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
 548 #define TX4938_PCIC_MAX_DEVNU   TX4938_PCIC_IDSEL_AD_TO_SLOT(32)
 549
 550 /* bits for PDMCFG */
 551 #define TX4938_PCIC_PDMCFG_RSTFIFO      0x00200000
 552 #define TX4938_PCIC_PDMCFG_EXFER        0x00100000
 553 #define TX4938_PCIC_PDMCFG_REQDLY_MASK  0x00003800
 554 #define TX4938_PCIC_PDMCFG_REQDLY_NONE  (0 << 11)
 555 #define TX4938_PCIC_PDMCFG_REQDLY_16    (1 << 11)
 556 #define TX4938_PCIC_PDMCFG_REQDLY_32    (2 << 11)
 557 #define TX4938_PCIC_PDMCFG_REQDLY_64    (3 << 11)
 558 #define TX4938_PCIC_PDMCFG_REQDLY_128   (4 << 11)
 559 #define TX4938_PCIC_PDMCFG_REQDLY_256   (5 << 11)
 560 #define TX4938_PCIC_PDMCFG_REQDLY_512   (6 << 11)
 561 #define TX4938_PCIC_PDMCFG_REQDLY_1024  (7 << 11)
 562 #define TX4938_PCIC_PDMCFG_ERRIE        0x00000400
 563 #define TX4938_PCIC_PDMCFG_NCCMPIE      0x00000200
 564 #define TX4938_PCIC_PDMCFG_NTCMPIE      0x00000100
 565 #define TX4938_PCIC_PDMCFG_CHNEN        0x00000080
 566 #define TX4938_PCIC_PDMCFG_XFRACT       0x00000040
 567 #define TX4938_PCIC_PDMCFG_BSWAP        0x00000020
 568 #define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
 569 #define TX4938_PCIC_PDMCFG_XFRSIZE_1DW  0x00000000
 570 #define TX4938_PCIC_PDMCFG_XFRSIZE_1QW  0x00000004
 571 #define TX4938_PCIC_PDMCFG_XFRSIZE_4QW  0x00000008
 572 #define TX4938_PCIC_PDMCFG_XFRDIRC      0x00000002
 573 #define TX4938_PCIC_PDMCFG_CHRST        0x00000001
 574
 575 /* bits for PDMSTS */
 576 #define TX4938_PCIC_PDMSTS_REQCNT_MASK  0x3f000000
 577 #define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
 578 #define TX4938_PCIC_PDMSTS_FIFOWP_MASK  0x000c0000
 579 #define TX4938_PCIC_PDMSTS_FIFORP_MASK  0x00030000
 580 #define TX4938_PCIC_PDMSTS_ERRINT       0x00000800
 581 #define TX4938_PCIC_PDMSTS_DONEINT      0x00000400
 582 #define TX4938_PCIC_PDMSTS_CHNEN        0x00000200
 583 #define TX4938_PCIC_PDMSTS_XFRACT       0x00000100
 584 #define TX4938_PCIC_PDMSTS_ACCMP        0x00000080
 585 #define TX4938_PCIC_PDMSTS_NCCMP        0x00000040
 586 #define TX4938_PCIC_PDMSTS_NTCMP        0x00000020
 587 #define TX4938_PCIC_PDMSTS_CFGERR       0x00000008
 588 #define TX4938_PCIC_PDMSTS_PCIERR       0x00000004
 589 #define TX4938_PCIC_PDMSTS_CHNERR       0x00000002
 590 #define TX4938_PCIC_PDMSTS_DATAERR      0x00000001
 591 #define TX4938_PCIC_PDMSTS_ALL_CMP      0x000000e0
 592 #define TX4938_PCIC_PDMSTS_ALL_ERR      0x0000000f
 593
 594 /*
 595  * DMA
 596  */
 597 /* bits for MCR */
 598 #define TX4938_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
 599 #define TX4938_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
 600 #define TX4938_DMA_MCR_RSFIF    0x00000080
 601 #define TX4938_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
 602 #define TX4938_DMA_MCR_RPRT     0x00000002
 603 #define TX4938_DMA_MCR_MSTEN    0x00000001
 604
 605 /* bits for CCRn */
 606 #define TX4938_DMA_CCR_IMMCHN   0x20000000
 607 #define TX4938_DMA_CCR_USEXFSZ  0x10000000
 608 #define TX4938_DMA_CCR_LE       0x08000000
 609 #define TX4938_DMA_CCR_DBINH    0x04000000
 610 #define TX4938_DMA_CCR_SBINH    0x02000000
 611 #define TX4938_DMA_CCR_CHRST    0x01000000
 612 #define TX4938_DMA_CCR_RVBYTE   0x00800000
 613 #define TX4938_DMA_CCR_ACKPOL   0x00400000
 614 #define TX4938_DMA_CCR_REQPL    0x00200000
 615 #define TX4938_DMA_CCR_EGREQ    0x00100000
 616 #define TX4938_DMA_CCR_CHDN     0x00080000
 617 #define TX4938_DMA_CCR_DNCTL    0x00060000
 618 #define TX4938_DMA_CCR_EXTRQ    0x00010000
 619 #define TX4938_DMA_CCR_INTRQD   0x0000e000
 620 #define TX4938_DMA_CCR_INTENE   0x00001000
 621 #define TX4938_DMA_CCR_INTENC   0x00000800
 622 #define TX4938_DMA_CCR_INTENT   0x00000400
 623 #define TX4938_DMA_CCR_CHNEN    0x00000200
 624 #define TX4938_DMA_CCR_XFACT    0x00000100
 625 #define TX4938_DMA_CCR_SMPCHN   0x00000020
 626 #define TX4938_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
 627 #define TX4938_DMA_CCR_XFSZ_1W  TX4938_DMA_CCR_XFSZ(2)
 628 #define TX4938_DMA_CCR_XFSZ_2W  TX4938_DMA_CCR_XFSZ(3)
 629 #define TX4938_DMA_CCR_XFSZ_4W  TX4938_DMA_CCR_XFSZ(4)
 630 #define TX4938_DMA_CCR_XFSZ_8W  TX4938_DMA_CCR_XFSZ(5)
 631 #define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
 632 #define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
 633 #define TX4938_DMA_CCR_MEMIO    0x00000002
 634 #define TX4938_DMA_CCR_SNGAD    0x00000001
 635
 636 /* bits for CSRn */
 637 #define TX4938_DMA_CSR_CHNEN    0x00000400
 638 #define TX4938_DMA_CSR_STLXFER  0x00000200
 639 #define TX4938_DMA_CSR_CHNACT   0x00000100
 640 #define TX4938_DMA_CSR_ABCHC    0x00000080
 641 #define TX4938_DMA_CSR_NCHNC    0x00000040
 642 #define TX4938_DMA_CSR_NTRNFC   0x00000020
 643 #define TX4938_DMA_CSR_EXTDN    0x00000010
 644 #define TX4938_DMA_CSR_CFERR    0x00000008
 645 #define TX4938_DMA_CSR_CHERR    0x00000004
 646 #define TX4938_DMA_CSR_DESERR   0x00000002
 647 #define TX4938_DMA_CSR_SORERR   0x00000001
 648
 649 /* TX4938 Interrupt Controller (32-bit registers) */
 650 #define TX4938_IRC_BASE                 0xf510
 651 #define TX4938_IRC_IRFLAG0              0xf510
 652 #define TX4938_IRC_IRFLAG1              0xf514
 653 #define TX4938_IRC_IRPOL                0xf518
 654 #define TX4938_IRC_IRRCNT               0xf51c
 655 #define TX4938_IRC_IRMASKINT            0xf520
 656 #define TX4938_IRC_IRMASKEXT            0xf524
 657 #define TX4938_IRC_IRDEN                0xf600
 658 #define TX4938_IRC_IRDM0                0xf604
 659 #define TX4938_IRC_IRDM1                0xf608
 660 #define TX4938_IRC_IRLVL0               0xf610
 661 #define TX4938_IRC_IRLVL1               0xf614
 662 #define TX4938_IRC_IRLVL2               0xf618
 663 #define TX4938_IRC_IRLVL3               0xf61c
 664 #define TX4938_IRC_IRLVL4               0xf620
 665 #define TX4938_IRC_IRLVL5               0xf624
 666 #define TX4938_IRC_IRLVL6               0xf628
 667 #define TX4938_IRC_IRLVL7               0xf62c
 668 #define TX4938_IRC_IRMSK                0xf640
 669 #define TX4938_IRC_IREDC                0xf660
 670 #define TX4938_IRC_IRPND                0xf680
 671 #define TX4938_IRC_IRCS                 0xf6a0
 672 #define TX4938_IRC_LIMIT                0xf6ff
 673
 674
 675 #ifndef __ASSEMBLY__
 676
 677 #define tx4938_sdramcptr        ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
 678 #define tx4938_ebuscptr         ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
 679 #define tx4938_dmaptr(ch)       ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
 680 #define tx4938_ndfmcptr         ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
 681 #define tx4938_ircptr           ((struct tx4938_irc_reg *)TX4938_IRC_REG)
 682 #define tx4938_pcicptr          ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
 683 #define tx4938_pcic1ptr         ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
 684 #define tx4938_ccfgptr          ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
 685 #define tx4938_tmrptr(ch)       ((struct tx4938_tmr_reg *)TX4938_TMR_REG(ch))
 686 #define tx4938_sioptr(ch)       ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
 687 #define tx4938_pioptr           ((struct tx4938_pio_reg *)TX4938_PIO_REG)
 688 #define tx4938_aclcptr          ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
 689 #define tx4938_spiptr           ((struct tx4938_spi_reg *)TX4938_SPI_REG)
 690 #define tx4938_sramcptr         ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
 691
 692
 693 #define TX4938_REV_MAJ_MIN()    ((unsigned long)tx4938_ccfgptr->crir & 0x00ff)
 694 #define TX4938_REV_PCODE()      ((unsigned long)tx4938_ccfgptr->crir >> 16)
 695
 696 #define TX4938_SDRAMC_BA(ch)    ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
 697 #define TX4938_SDRAMC_SIZE(ch)  (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
 698
 699 #define TX4938_EBUSC_BA(ch)     ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
 700 #define TX4938_EBUSC_SIZE(ch)   \
 701         (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
 702
 703
 704 #endif /* !__ASSEMBLY__ */
 705
 706 #endif