include/asm-sparc64/cpudata.h

   1 /* cpudata.h: Per-cpu parameters.
   2  *
   3  * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #ifndef _SPARC64_CPUDATA_H
   7 #define _SPARC64_CPUDATA_H
   8
   9 #include <asm/hypervisor.h>
  10 #include <asm/asi.h>
  11
  12 #ifndef __ASSEMBLY__
  13
  14 #include <linux/percpu.h>
  15 #include <linux/threads.h>
  16
  17 typedef struct {
  18         /* Dcache line 1 */
  19         unsigned int    __softirq_pending; /* must be 1st, see rtrap.S */
  20         unsigned int    multiplier;
  21         unsigned int    counter;
  22         unsigned int    __pad1;
  23         unsigned long   clock_tick;     /* %tick's per second */
  24         unsigned long   udelay_val;
  25
  26         /* Dcache line 2, rarely used */
  27         unsigned int    dcache_size;
  28         unsigned int    dcache_line_size;
  29         unsigned int    icache_size;
  30         unsigned int    icache_line_size;
  31         unsigned int    ecache_size;
  32         unsigned int    ecache_line_size;
  33         unsigned int    __pad3;
  34         unsigned int    __pad4;
  35 } cpuinfo_sparc;
  36
  37 DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
  38 #define cpu_data(__cpu)         per_cpu(__cpu_data, (__cpu))
  39 #define local_cpu_data()        __get_cpu_var(__cpu_data)
  40
  41 /* Trap handling code needs to get at a few critical values upon
  42  * trap entry and to process TSB misses.  These cannot be in the
  43  * per_cpu() area as we really need to lock them into the TLB and
  44  * thus make them part of the main kernel image.  As a result we
  45  * try to make this as small as possible.
  46  *
  47  * This is padded out and aligned to 64-bytes to avoid false sharing
  48  * on SMP.
  49  */
  50
  51 /* If you modify the size of this structure, please update
  52  * TRAP_BLOCK_SZ_SHIFT below.
  53  */
  54 struct thread_info;
  55 struct trap_per_cpu {
  56 /* D-cache line 1: Basic thread information, cpu and device mondo queues */
  57         struct thread_info      *thread;
  58         unsigned long           pgd_paddr;
  59         unsigned long           cpu_mondo_pa;
  60         unsigned long           dev_mondo_pa;
  61
  62 /* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
  63         unsigned long           resum_mondo_pa;
  64         unsigned long           resum_kernel_buf_pa;
  65         unsigned long           nonresum_mondo_pa;
  66         unsigned long           nonresum_kernel_buf_pa;
  67
  68 /* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
  69         struct hv_fault_status  fault_info;
  70
  71 /* Dcache line 7: Physical addresses of CPU send mondo block and CPU list.  */
  72         unsigned long           cpu_mondo_block_pa;
  73         unsigned long           cpu_list_pa;
  74         unsigned long           tsb_huge;
  75         unsigned long           tsb_huge_temp;
  76
  77 /* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size.  */
  78         unsigned int            irq_worklist;
  79         unsigned int            __pad1;
  80         unsigned long           __pad2[3];
  81 } __attribute__((aligned(64)));
  82 extern struct trap_per_cpu trap_block[NR_CPUS];
  83 extern void init_cur_cpu_trap(struct thread_info *);
  84 extern void setup_tba(void);
  85
  86 struct cpuid_patch_entry {
  87         unsigned int    addr;
  88         unsigned int    cheetah_safari[4];
  89         unsigned int    cheetah_jbus[4];
  90         unsigned int    starfire[4];
  91         unsigned int    sun4v[4];
  92 };
  93 extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
  94
  95 struct sun4v_1insn_patch_entry {
  96         unsigned int    addr;
  97         unsigned int    insn;
  98 };
  99 extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
 100         __sun4v_1insn_patch_end;
 101
 102 struct sun4v_2insn_patch_entry {
 103         unsigned int    addr;
 104         unsigned int    insns[2];
 105 };
 106 extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
 107         __sun4v_2insn_patch_end;
 108
 109 #endif /* !(__ASSEMBLY__) */
 110
 111 #define TRAP_PER_CPU_THREAD             0x00
 112 #define TRAP_PER_CPU_PGD_PADDR          0x08
 113 #define TRAP_PER_CPU_CPU_MONDO_PA       0x10
 114 #define TRAP_PER_CPU_DEV_MONDO_PA       0x18
 115 #define TRAP_PER_CPU_RESUM_MONDO_PA     0x20
 116 #define TRAP_PER_CPU_RESUM_KBUF_PA      0x28
 117 #define TRAP_PER_CPU_NONRESUM_MONDO_PA  0x30
 118 #define TRAP_PER_CPU_NONRESUM_KBUF_PA   0x38
 119 #define TRAP_PER_CPU_FAULT_INFO         0x40
 120 #define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
 121 #define TRAP_PER_CPU_CPU_LIST_PA        0xc8
 122 #define TRAP_PER_CPU_TSB_HUGE           0xd0
 123 #define TRAP_PER_CPU_TSB_HUGE_TEMP      0xd8
 124 #define TRAP_PER_CPU_IRQ_WORKLIST       0xe0
 125
 126 #define TRAP_BLOCK_SZ_SHIFT             8
 127
 128 #include <asm/scratchpad.h>
 129
 130 #define __GET_CPUID(REG)                                \
 131         /* Spitfire implementation (default). */        \
 132 661:    ldxa            [%g0] ASI_UPA_CONFIG, REG;      \
 133         srlx            REG, 17, REG;                   \
 134          and            REG, 0x1f, REG;                 \
 135         nop;                                            \
 136         .section        .cpuid_patch, "ax";             \
 137         /* Instruction location. */                     \
 138         .word           661b;                           \
 139         /* Cheetah Safari implementation. */            \
 140         ldxa            [%g0] ASI_SAFARI_CONFIG, REG;   \
 141         srlx            REG, 17, REG;                   \
 142         and             REG, 0x3ff, REG;                \
 143         nop;                                            \
 144         /* Cheetah JBUS implementation. */              \
 145         ldxa            [%g0] ASI_JBUS_CONFIG, REG;     \
 146         srlx            REG, 17, REG;                   \
 147         and             REG, 0x1f, REG;                 \
 148         nop;                                            \
 149         /* Starfire implementation. */                  \
 150         sethi           %hi(0x1fff40000d0 >> 9), REG;   \
 151         sllx            REG, 9, REG;                    \
 152         or              REG, 0xd0, REG;                 \
 153         lduwa           [REG] ASI_PHYS_BYPASS_EC_E, REG;\
 154         /* sun4v implementation. */                     \
 155         mov             SCRATCHPAD_CPUID, REG;          \
 156         ldxa            [REG] ASI_SCRATCHPAD, REG;      \
 157         nop;                                            \
 158         nop;                                            \
 159         .previous;
 160
 161 #ifdef CONFIG_SMP
 162
 163 #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 164         __GET_CPUID(TMP)                        \
 165         sethi   %hi(trap_block), DEST;          \
 166         sllx    TMP, TRAP_BLOCK_SZ_SHIFT, TMP;  \
 167         or      DEST, %lo(trap_block), DEST;    \
 168         add     DEST, TMP, DEST;                \
 169
 170 /* Clobbers TMP, current address space PGD phys address into DEST.  */
 171 #define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
 172         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 173         ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
 174
 175 /* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
 176 #define TRAP_LOAD_IRQ_WORK(DEST, TMP)           \
 177         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 178         add     DEST, TRAP_PER_CPU_IRQ_WORKLIST, DEST;
 179
 180 /* Clobbers TMP, loads DEST with current thread info pointer.  */
 181 #define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
 182         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 183         ldx     [DEST + TRAP_PER_CPU_THREAD], DEST;
 184
 185 /* Given the current thread info pointer in THR, load the per-cpu
 186  * area base of the current processor into DEST.  REG1, REG2, and REG3 are
 187  * clobbered.
 188  *
 189  * You absolutely cannot use DEST as a temporary in this code.  The
 190  * reason is that traps can happen during execution, and return from
 191  * trap will load the fully resolved DEST per-cpu base.  This can corrupt
 192  * the calculations done by the macro mid-stream.
 193  */
 194 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)  \
 195         ldub    [THR + TI_CPU], REG1;                   \
 196         sethi   %hi(__per_cpu_shift), REG3;             \
 197         sethi   %hi(__per_cpu_base), REG2;              \
 198         ldx     [REG3 + %lo(__per_cpu_shift)], REG3;    \
 199         ldx     [REG2 + %lo(__per_cpu_base)], REG2;     \
 200         sllx    REG1, REG3, REG3;                       \
 201         add     REG3, REG2, DEST;
 202
 203 #else
 204
 205 #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 206         sethi   %hi(trap_block), DEST;          \
 207         or      DEST, %lo(trap_block), DEST;    \
 208
 209 /* Uniprocessor versions, we know the cpuid is zero.  */
 210 #define TRAP_LOAD_PGD_PHYS(DEST, TMP)           \
 211         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 212         ldx     [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
 213
 214 /* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
 215 #define TRAP_LOAD_IRQ_WORK(DEST, TMP)           \
 216         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 217         add     DEST, TRAP_PER_CPU_IRQ_WORKLIST, DEST;
 218
 219 #define TRAP_LOAD_THREAD_REG(DEST, TMP)         \
 220         TRAP_LOAD_TRAP_BLOCK(DEST, TMP)         \
 221         ldx     [DEST + TRAP_PER_CPU_THREAD], DEST;
 222
 223 /* No per-cpu areas on uniprocessor, so no need to load DEST.  */
 224 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
 225
 226 #endif /* !(CONFIG_SMP) */
 227
 228 #endif /* _SPARC64_CPUDATA_H */